ISSDK
1.7
IoT Sensing Software Development Kit
boardkit
frdm-k22f
RTE_Device.h
Go to the documentation of this file.
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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/* Driver name mapping. */
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#define RTE_I2C0 1
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#define RTE_I2C0_DMA_EN 0
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#define RTE_I2C1 1
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#define RTE_I2C1_DMA_EN 0
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#define RTE_SPI0 0
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#define RTE_SPI0_DMA_EN 0
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#define RTE_SPI1 1
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#define RTE_SPI1_DMA_EN 0
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/* Use UART0 - UART2. */
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#define RTE_USART0 0
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#define RTE_USART0_DMA_EN 0
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#define RTE_USART1 1
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#define RTE_USART1_DMA_EN 0
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#define RTE_USART2 1
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#define RTE_USART2_DMA_EN 0
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/* Use LPUART0. */
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#define RTE_USART3 0
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#define RTE_USART3_DMA_EN 0
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/* UART configuration. */
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#define USART_RX_BUFFER_LEN 64
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#define USART1_RX_BUFFER_ENABLE 1
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#define USART2_RX_BUFFER_ENABLE 1
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/* DSPI configuration. */
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#define RTE_SPI0_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI0_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
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#define RTE_SPI0_DMA_TX_CH 0
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#define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx
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#define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_RX_CH 1
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#define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx
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#define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_LINK_DMA_BASE DMA0
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#define RTE_SPI0_DMA_LINK_CH 2
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#define RTE_SPI1_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI1_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
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#define RTE_SPI1_DMA_TX_CH 0
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#define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
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#define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI1_DMA_RX_CH 1
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#define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
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#define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI1_DMA_LINK_DMA_BASE DMA0
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#define RTE_SPI1_DMA_LINK_CH 2
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/*I2C configuration*/
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#define RTE_I2C0_Master_DMA_BASE DMA0
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#define RTE_I2C0_Master_DMA_CH 0
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#define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0
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#define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0
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#define RTE_I2C1_Master_DMA_BASE DMA0
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#define RTE_I2C1_Master_DMA_CH 1
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#define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0
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#define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1
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/* UART configuration. */
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#define RTE_USART0_DMA_TX_CH 0
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#define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx
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#define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_TX_DMA_BASE DMA0
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#define RTE_USART0_DMA_RX_CH 1
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#define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx
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#define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_RX_DMA_BASE DMA0
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#define RTE_USART1_DMA_TX_CH 0
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#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx
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#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_TX_DMA_BASE DMA0
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#define RTE_USART1_DMA_RX_CH 1
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#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx
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#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_RX_DMA_BASE DMA0
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#define RTE_USART2_DMA_TX_CH 0
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#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx
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#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART2_DMA_TX_DMA_BASE DMA0
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#define RTE_USART2_DMA_RX_CH 1
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#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx
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#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART2_DMA_RX_DMA_BASE DMA0
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#endif
/* __RTE_DEVICE_H */
© Freescale Semiconductor, Inc. 2016-2017. All Rights Reserved.
