ISSDK
1.7
IoT Sensing Software Development Kit
boardkit
frdm-kl27z
RTE_Device.h
Go to the documentation of this file.
1
/*
2
* The Clear BSD License
3
* Copyright (c) 2016, Freescale Semiconductor, Inc.
4
* Copyright 2016-2017 NXP
5
* All rights reserved.
6
*
7
* Redistribution and use in source and binary forms, with or without modification,
8
* are permitted (subject to the limitations in the disclaimer below) provided
9
* that the following conditions are met:
10
*
11
* o Redistributions of source code must retain the above copyright notice, this list
12
* of conditions and the following disclaimer.
13
*
14
* o Redistributions in binary form must reproduce the above copyright notice, this
15
* list of conditions and the following disclaimer in the documentation and/or
16
* other materials provided with the distribution.
17
*
18
* o Neither the name of the copyright holder nor the names of its
19
* contributors may be used to endorse or promote products derived from this
20
* software without specific prior written permission.
21
*
22
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
23
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
24
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
27
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
*/
34
#ifndef __RTE_DEVICE_H
35
#define __RTE_DEVICE_H
36
37
/*Driver name mapping*/
38
#define RTE_I2C0 1
39
#define RTE_I2C0_DMA_EN 0
40
#define RTE_I2C1 1
41
#define RTE_I2C1_DMA_EN 0
42
43
#define RTE_SPI0 1
44
#define RTE_SPI0_DMA_EN 0
45
#define RTE_SPI1 0
46
#define RTE_SPI1_DMA_EN 0
47
48
#define RTE_USART0 1
49
#define RTE_USART0_DMA_EN 0
50
#define RTE_USART1 0
51
#define RTE_USART1_DMA_EN 0
52
#define RTE_USART2 0
53
#define RTE_USART2_DMA_EN 0
54
55
/* UART configuration. */
56
#define USART_RX_BUFFER_LEN 64
57
#define USART0_RX_BUFFER_ENABLE 1
58
59
#define RTE_USART0_DMA_TX_CH 0
60
#define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx
61
#define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0
62
#define RTE_USART0_DMA_TX_DMA_BASE DMA0
63
#define RTE_USART0_DMA_RX_CH 1
64
#define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx
65
#define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0
66
#define RTE_USART0_DMA_RX_DMA_BASE DMA0
67
68
#define RTE_USART1_DMA_TX_CH 0
69
#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx
70
#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0
71
#define RTE_USART1_DMA_TX_DMA_BASE DMA0
72
#define RTE_USART1_DMA_RX_CH 1
73
#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx
74
#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0
75
#define RTE_USART1_DMA_RX_DMA_BASE DMA0
76
77
#define RTE_USART2_DMA_TX_CH 0
78
#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx
79
#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0
80
#define RTE_USART2_DMA_TX_DMA_BASE DMA0
81
#define RTE_USART2_DMA_RX_CH 1
82
#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx
83
#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0
84
#define RTE_USART2_DMA_RX_DMA_BASE DMA0
85
86
/* SPI configuration. */
87
#define RTE_SPI0_DMA_TX_CH 0
88
#define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx
89
#define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0
90
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
91
#define RTE_SPI0_DMA_RX_CH 1
92
#define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx
93
#define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0
94
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
95
96
#define RTE_SPI1_DMA_TX_CH 2
97
#define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx
98
#define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0
99
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
100
#define RTE_SPI1_DMA_RX_CH 3
101
#define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx
102
#define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0
103
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
104
105
/*I2C configuration*/
106
#define RTE_I2C0_Master_DMA_BASE DMA0
107
#define RTE_I2C0_Master_DMA_CH 0
108
#define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0
109
#define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0
110
111
#define RTE_I2C1_Master_DMA_BASE DMA0
112
#define RTE_I2C1_Master_DMA_CH 1
113
#define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0
114
#define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1
115
116
#endif
/* __RTE_DEVICE_H */
© Freescale Semiconductor, Inc. 2016-2017. All Rights Reserved.
