ISSDK  1.8
IoT Sensing Software Development Kit
pin_mux.c
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1 /*
2  * Copyright 2020 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 
13 /*
14  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15 !!GlobalInfo
16 product: Pins v9.0
17 processor: MIMXRT1176xxxxx
18 package_id: MIMXRT1176DVMAA
19 mcu_data: ksdk2_0
20 processor_version: 0.9.3
21  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
22  */
23 
24 #include "fsl_common.h"
25 #include "fsl_iomuxc.h"
26 #include "pin_mux.h"
27 
28 /* FUNCTION ************************************************************************************************************
29  *
30  * Function Name : BOARD_InitBootPins
31  * Description : Calls initialization functions.
32  *
33  * END ****************************************************************************************************************/
34 void BOARD_InitBootPins(void) {
35  BOARD_InitPins();
36 }
37 
38 /*
39  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
40 BOARD_InitPins:
41 - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
42 - pin_list:
43  - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
44  open_drain: Disable, drive_strength: High, slew_rate: Slow}
45  - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
46  open_drain: Disable, drive_strength: High, slew_rate: Slow}
47  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
48  */
49 
50 /* FUNCTION ************************************************************************************************************
51  *
52  * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
53  * Description : Configures pin routing and optionally pin electrical features.
54  *
55  * END ****************************************************************************************************************/
56 void BOARD_InitPins(void) {
57  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
58 
59  IOMUXC_SetPinMux(
60  IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
61  0U); /* Software Input On Field: Input Path is determined by functionality */
62  IOMUXC_SetPinMux(
63  IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
64  0U); /* Software Input On Field: Input Path is determined by functionality */
65  IOMUXC_SetPinConfig(
66  IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
67  0x02U); /* Slew Rate Field: Slow Slew Rate
68  Drive Strength Field: high drive strength
69  Pull / Keep Select Field: Pull Disable, Highz
70  Pull Up / Down Config. Field: Weak pull down
71  Open Drain Field: Disabled
72  Domain write protection: Both cores are allowed
73  Domain write protection lock: Neither of DWP bits is locked */
74  IOMUXC_SetPinConfig(
75  IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
76  0x02U); /* Slew Rate Field: Slow Slew Rate
77  Drive Strength Field: high drive strength
78  Pull / Keep Select Field: Pull Disable, Highz
79  Pull Up / Down Config. Field: Weak pull down
80  Open Drain Field: Disabled
81  Domain write protection: Both cores are allowed
82  Domain write protection lock: Neither of DWP bits is locked */
83 }
84 
85 
86 /*
87  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
88 LPI2C1_InitPins:
89 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
90 - pin_list:
91  - {pin_num: R15, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_08, software_input_on: Enable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
92  open_drain: Enable, drive_strength: Normal, slew_rate: Slow}
93  - {pin_num: R16, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_09, software_input_on: Enable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
94  open_drain: Enable, drive_strength: Normal, slew_rate: Slow}
95  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
96  */
97 
98 /* FUNCTION ************************************************************************************************************
99  *
100  * Function Name : LPI2C1_InitPins, assigned for the Cortex-M7F core.
101  * Description : Configures pin routing and optionally pin electrical features.
102  *
103  * END ****************************************************************************************************************/
104 void LPI2C1_InitPins(void) {
105  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
106 
107  IOMUXC_SetPinMux(
108  IOMUXC_GPIO_AD_08_LPI2C1_SCL, /* GPIO_AD_08 is configured as LPI2C1_SCL */
109  1U); /* Software Input On Field: Force input path of pad GPIO_AD_08 */
110  IOMUXC_SetPinMux(
111  IOMUXC_GPIO_AD_09_LPI2C1_SDA, /* GPIO_AD_09 is configured as LPI2C1_SDA */
112  1U); /* Software Input On Field: Force input path of pad GPIO_AD_09 */
113  IOMUXC_SetPinConfig(
114  IOMUXC_GPIO_AD_08_LPI2C1_SCL, /* GPIO_AD_08 PAD functional properties : */
115  0x10U); /* Slew Rate Field: Slow Slew Rate
116  Drive Strength Field: normal drive strength
117  Pull / Keep Select Field: Pull Disable, Highz
118  Pull Up / Down Config. Field: Weak pull down
119  Open Drain Field: Enabled
120  Domain write protection: Both cores are allowed
121  Domain write protection lock: Neither of DWP bits is locked */
122  IOMUXC_SetPinConfig(
123  IOMUXC_GPIO_AD_09_LPI2C1_SDA, /* GPIO_AD_09 PAD functional properties : */
124  0x10U); /* Slew Rate Field: Slow Slew Rate
125  Drive Strength Field: normal drive strength
126  Pull / Keep Select Field: Pull Disable, Highz
127  Pull Up / Down Config. Field: Weak pull down
128  Open Drain Field: Enabled
129  Domain write protection: Both cores are allowed
130  Domain write protection lock: Neither of DWP bits is locked */
131 }
132 
133 
134 /*
135  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
136 LPI2C1_DeinitPins:
137 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
138 - pin_list:
139  - {pin_num: R15, peripheral: GPIO3, signal: 'gpio_mux_io, 07', pin_signal: GPIO_AD_08, software_input_on: Disable}
140  - {pin_num: R16, peripheral: GPIO3, signal: 'gpio_mux_io, 08', pin_signal: GPIO_AD_09, software_input_on: Disable}
141  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
142  */
143 
144 /* FUNCTION ************************************************************************************************************
145  *
146  * Function Name : LPI2C1_DeinitPins, assigned for the Cortex-M7F core.
147  * Description : Configures pin routing and optionally pin electrical features.
148  *
149  * END ****************************************************************************************************************/
150 void LPI2C1_DeinitPins(void) {
151  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
152 
153  IOMUXC_SetPinMux(
154  IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07, /* GPIO_AD_08 is configured as GPIO_MUX3_IO07 */
155  0U); /* Software Input On Field: Input Path is determined by functionality */
156  IOMUXC_SetPinMux(
157  IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08, /* GPIO_AD_09 is configured as GPIO_MUX3_IO08 */
158  0U); /* Software Input On Field: Input Path is determined by functionality */
159  IOMUXC_GPR->GPR42 = ((IOMUXC_GPR->GPR42 &
160  (~(IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK))) /* Mask bits to zero which are setting */
161  | IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(0x00U) /* GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function: 0x00U */
162  );
163 }
164 
165 
166 /*
167  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
168 LPSPI1_InitPins:
169 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
170 - pin_list:
171  - {pin_num: M17, peripheral: LPSPI1, signal: PCS0, pin_signal: GPIO_AD_29, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
172  open_drain: Disable, drive_strength: High, slew_rate: Slow}
173  - {pin_num: L17, peripheral: LPSPI1, signal: SCK, pin_signal: GPIO_AD_28, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
174  open_drain: Disable, drive_strength: High, slew_rate: Slow}
175  - {pin_num: J17, peripheral: LPSPI1, signal: SIN, pin_signal: GPIO_AD_31, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
176  open_drain: Disable, drive_strength: High, slew_rate: Slow}
177  - {pin_num: K17, peripheral: LPSPI1, signal: SOUT, pin_signal: GPIO_AD_30, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
178  open_drain: Disable, drive_strength: High, slew_rate: Slow}
179  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
180  */
181 
182 /* FUNCTION ************************************************************************************************************
183  *
184  * Function Name : LPSPI1_InitPins, assigned for the Cortex-M7F core.
185  * Description : Configures pin routing and optionally pin electrical features.
186  *
187  * END ****************************************************************************************************************/
188 void LPSPI1_InitPins(void) {
189  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
190 
191  IOMUXC_SetPinMux(
192  IOMUXC_GPIO_AD_28_LPSPI1_SCK, /* GPIO_AD_28 is configured as LPSPI1_SCK */
193  0U); /* Software Input On Field: Input Path is determined by functionality */
194  IOMUXC_SetPinMux(
195  IOMUXC_GPIO_AD_29_LPSPI1_PCS0, /* GPIO_AD_29 is configured as LPSPI1_PCS0 */
196  0U); /* Software Input On Field: Input Path is determined by functionality */
197  IOMUXC_SetPinMux(
198  IOMUXC_GPIO_AD_30_LPSPI1_SOUT, /* GPIO_AD_30 is configured as LPSPI1_SOUT */
199  0U); /* Software Input On Field: Input Path is determined by functionality */
200  IOMUXC_SetPinMux(
201  IOMUXC_GPIO_AD_31_LPSPI1_SIN, /* GPIO_AD_31 is configured as LPSPI1_SIN */
202  0U); /* Software Input On Field: Input Path is determined by functionality */
203  IOMUXC_SetPinConfig(
204  IOMUXC_GPIO_AD_28_LPSPI1_SCK, /* GPIO_AD_28 PAD functional properties : */
205  0x02U); /* Slew Rate Field: Slow Slew Rate
206  Drive Strength Field: high drive strength
207  Pull / Keep Select Field: Pull Disable, Highz
208  Pull Up / Down Config. Field: Weak pull down
209  Open Drain Field: Disabled
210  Domain write protection: Both cores are allowed
211  Domain write protection lock: Neither of DWP bits is locked */
212  IOMUXC_SetPinConfig(
213  IOMUXC_GPIO_AD_29_LPSPI1_PCS0, /* GPIO_AD_29 PAD functional properties : */
214  0x02U); /* Slew Rate Field: Slow Slew Rate
215  Drive Strength Field: high drive strength
216  Pull / Keep Select Field: Pull Disable, Highz
217  Pull Up / Down Config. Field: Weak pull down
218  Open Drain Field: Disabled
219  Domain write protection: Both cores are allowed
220  Domain write protection lock: Neither of DWP bits is locked */
221  IOMUXC_SetPinConfig(
222  IOMUXC_GPIO_AD_30_LPSPI1_SOUT, /* GPIO_AD_30 PAD functional properties : */
223  0x02U); /* Slew Rate Field: Slow Slew Rate
224  Drive Strength Field: high drive strength
225  Pull / Keep Select Field: Pull Disable, Highz
226  Pull Up / Down Config. Field: Weak pull down
227  Open Drain Field: Disabled
228  Domain write protection: Both cores are allowed
229  Domain write protection lock: Neither of DWP bits is locked */
230  IOMUXC_SetPinConfig(
231  IOMUXC_GPIO_AD_31_LPSPI1_SIN, /* GPIO_AD_31 PAD functional properties : */
232  0x02U); /* Slew Rate Field: Slow Slew Rate
233  Drive Strength Field: high drive strength
234  Pull / Keep Select Field: Pull Disable, Highz
235  Pull Up / Down Config. Field: Weak pull down
236  Open Drain Field: Disabled
237  Domain write protection: Both cores are allowed
238  Domain write protection lock: Neither of DWP bits is locked */
239 }
240 
241 
242 /*
243  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
244 LPSPI1_DeinitPins:
245 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
246 - pin_list:
247  - {pin_num: M17, peripheral: GPIO3, signal: 'gpio_mux_io, 28', pin_signal: GPIO_AD_29}
248  - {pin_num: L17, peripheral: GPIO3, signal: 'gpio_mux_io, 27', pin_signal: GPIO_AD_28}
249  - {pin_num: J17, peripheral: GPIO3, signal: 'gpio_mux_io, 30', pin_signal: GPIO_AD_31}
250  - {pin_num: K17, peripheral: GPIO3, signal: 'gpio_mux_io, 29', pin_signal: GPIO_AD_30}
251  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
252  */
253 
254 /* FUNCTION ************************************************************************************************************
255  *
256  * Function Name : LPSPI1_DeinitPins, assigned for the Cortex-M7F core.
257  * Description : Configures pin routing and optionally pin electrical features.
258  *
259  * END ****************************************************************************************************************/
260 void LPSPI1_DeinitPins(void) {
261  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
262 
263  IOMUXC_SetPinMux(
264  IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27, /* GPIO_AD_28 is configured as GPIO_MUX3_IO27 */
265  0U); /* Software Input On Field: Input Path is determined by functionality */
266  IOMUXC_SetPinMux(
267  IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28, /* GPIO_AD_29 is configured as GPIO_MUX3_IO28 */
268  0U); /* Software Input On Field: Input Path is determined by functionality */
269  IOMUXC_SetPinMux(
270  IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29, /* GPIO_AD_30 is configured as GPIO_MUX3_IO29 */
271  0U); /* Software Input On Field: Input Path is determined by functionality */
272  IOMUXC_SetPinMux(
273  IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30, /* GPIO_AD_31 is configured as GPIO_MUX3_IO30 */
274  0U); /* Software Input On Field: Input Path is determined by functionality */
275  IOMUXC_GPR->GPR43 = ((IOMUXC_GPR->GPR43 &
276  (~(IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK))) /* Mask bits to zero which are setting */
277  | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(0x00U) /* GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function: 0x00U */
278  );
279 }
280 
281 
282 /*
283  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
284 LPUART1_InitPins:
285 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
286 - pin_list:
287  - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
288  slew_rate: Slow}
289  - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High,
290  slew_rate: Slow}
291  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
292  */
293 
294 /* FUNCTION ************************************************************************************************************
295  *
296  * Function Name : LPUART1_InitPins, assigned for the Cortex-M7F core.
297  * Description : Configures pin routing and optionally pin electrical features.
298  *
299  * END ****************************************************************************************************************/
300 void LPUART1_InitPins(void) {
301  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
302 
303  IOMUXC_SetPinMux(
304  IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
305  0U); /* Software Input On Field: Input Path is determined by functionality */
306  IOMUXC_SetPinMux(
307  IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
308  0U); /* Software Input On Field: Input Path is determined by functionality */
309  IOMUXC_SetPinConfig(
310  IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
311  0x02U); /* Slew Rate Field: Slow Slew Rate
312  Drive Strength Field: high drive strength
313  Pull / Keep Select Field: Pull Disable, Highz
314  Pull Up / Down Config. Field: Weak pull down
315  Open Drain Field: Disabled
316  Domain write protection: Both cores are allowed
317  Domain write protection lock: Neither of DWP bits is locked */
318  IOMUXC_SetPinConfig(
319  IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
320  0x02U); /* Slew Rate Field: Slow Slew Rate
321  Drive Strength Field: high drive strength
322  Pull / Keep Select Field: Pull Disable, Highz
323  Pull Up / Down Config. Field: Weak pull down
324  Open Drain Field: Disabled
325  Domain write protection: Both cores are allowed
326  Domain write protection lock: Neither of DWP bits is locked */
327 }
328 
329 
330 /*
331  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
332 LPUART1_DeinitPins:
333 - options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'}
334 - pin_list:
335  - {pin_num: M15, peripheral: GPIO3, signal: 'gpio_mux_io, 24', pin_signal: GPIO_AD_25}
336  - {pin_num: L13, peripheral: GPIO3, signal: 'gpio_mux_io, 23', pin_signal: GPIO_AD_24}
337  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
338  */
339 
340 /* FUNCTION ************************************************************************************************************
341  *
342  * Function Name : LPUART1_DeinitPins, assigned for the Cortex-M7F core.
343  * Description : Configures pin routing and optionally pin electrical features.
344  *
345  * END ****************************************************************************************************************/
346 void LPUART1_DeinitPins(void) {
347  CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
348 
349  IOMUXC_SetPinMux(
350  IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23, /* GPIO_AD_24 is configured as GPIO_MUX3_IO23 */
351  0U); /* Software Input On Field: Input Path is determined by functionality */
352  IOMUXC_SetPinMux(
353  IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24, /* GPIO_AD_25 is configured as GPIO_MUX3_IO24 */
354  0U); /* Software Input On Field: Input Path is determined by functionality */
355  IOMUXC_GPR->GPR43 = ((IOMUXC_GPR->GPR43 &
356  (~(IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK))) /* Mask bits to zero which are setting */
357  | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(0x00U) /* GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function: 0x00U */
358  );
359 }
360 
361 /***********************************************************************************************************************
362  * EOF
363  **********************************************************************************************************************/
LPUART1_InitPins
void LPUART1_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:387
LPI2C1_InitPins
void LPI2C1_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:311
LPSPI1_InitPins
void LPSPI1_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:440
LPUART1_DeinitPins
void LPUART1_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:421
LPSPI1_DeinitPins
void LPSPI1_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:469
BOARD_InitBootPins
void BOARD_InitBootPins(void)
Calls initialization functions.
Definition: pin_mux.c:36
LPI2C1_DeinitPins
void LPI2C1_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:351
BOARD_InitPins
void BOARD_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:47
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