ISSDK
1.8
IoT Sensing Software Development Kit
boardkit
frdm-k64f
RTE_Device.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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/*Driver name mapping*/
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#define RTE_I2C0 1
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#define RTE_I2C0_DMA_EN 0
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#define RTE_I2C1 1
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#define RTE_I2C1_DMA_EN 0
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#define RTE_SPI0 1
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#define RTE_SPI0_DMA_EN 0
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#define RTE_SPI1 0
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#define RTE_SPI1_DMA_EN 0
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#define RTE_USART0 1
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#define RTE_USART0_DMA_EN 0
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#define RTE_USART1 0
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#define RTE_USART1_DMA_EN 0
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#define RTE_USART2 0
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#define RTE_USART2_DMA_EN 0
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#define RTE_USART3 1
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#define RTE_USART3_DMA_EN 0
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/* UART configuration. */
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#define USART_RX_BUFFER_LEN 64
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#define USART0_RX_BUFFER_ENABLE 1
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#define USART3_RX_BUFFER_ENABLE 1
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/* I2C configuration */
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#define RTE_I2C0_Master_DMA_BASE DMA0
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#define RTE_I2C0_Master_DMA_CH 0
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#define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0
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#define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0
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#define RTE_I2C1_Master_DMA_BASE DMA0
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#define RTE_I2C1_Master_DMA_CH 1
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#define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0
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#define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1
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#define RTE_I2C2_Master_DMA_BASE DMA0
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#define RTE_I2C2_Master_DMA_CH 2
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#define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0
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#define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2
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/* DSPI configuration. */
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#define RTE_SPI0_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI0_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
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#define RTE_SPI0_DMA_TX_CH 0
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#define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx
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#define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_RX_CH 1
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#define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx
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#define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_LINK_DMA_BASE DMA0
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#define RTE_SPI0_DMA_LINK_CH 2
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#define RTE_SPI1_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI1_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
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#define RTE_SPI1_DMA_TX_CH 0
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#define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
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#define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI1_DMA_RX_CH 1
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#define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
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#define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI1_DMA_LINK_DMA_BASE DMA0
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#define RTE_SPI1_DMA_LINK_CH 2
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#define RTE_SPI2_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI2_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
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#define RTE_SPI2_DMA_TX_CH 0
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#define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2
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#define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI2_DMA_RX_CH 1
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#define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2
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#define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI2_DMA_LINK_DMA_BASE DMA0
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#define RTE_SPI2_DMA_LINK_CH 2
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/* UART configuration. */
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#define RTE_USART0_DMA_TX_CH 0
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#define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx
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#define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_TX_DMA_BASE DMA0
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#define RTE_USART0_DMA_RX_CH 1
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#define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx
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#define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_RX_DMA_BASE DMA0
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#define RTE_USART1_DMA_TX_CH 0
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#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx
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#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_TX_DMA_BASE DMA0
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#define RTE_USART1_DMA_RX_CH 1
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#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx
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#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_RX_DMA_BASE DMA0
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#define RTE_USART2_DMA_TX_CH 0
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#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx
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#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART2_DMA_TX_DMA_BASE DMA0
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#define RTE_USART2_DMA_RX_CH 1
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#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx
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#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART2_DMA_RX_DMA_BASE DMA0
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#define RTE_USART3_DMA_TX_CH 0
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#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx
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#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART3_DMA_TX_DMA_BASE DMA0
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#define RTE_USART3_DMA_RX_CH 1
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#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx
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#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART3_DMA_RX_DMA_BASE DMA0
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#define RTE_USART4_DMA_TX_CH 0
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#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4
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#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART4_DMA_TX_DMA_BASE DMA0
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#define RTE_USART4_DMA_RX_CH 1
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#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4
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#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART4_DMA_RX_DMA_BASE DMA0
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#define RTE_USART5_DMA_TX_CH 0
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#define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART5
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#define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART5_DMA_TX_DMA_BASE DMA0
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#define RTE_USART5_DMA_RX_CH 1
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#define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART5
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#define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART5_DMA_RX_DMA_BASE DMA0
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#endif
/* __RTE_DEVICE_H */
© Copyright 2016-2020 NXP. All Rights Reserved.
