ISSDK
1.8
IoT Sensing Software Development Kit
boardkit
lpcxpresso54114
RTE_Device.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2016, Freescale Semiconductor, Inc.
3
* Copyright 2016-2017 NXP
4
* All rights reserved.
5
*
6
* SPDX-License-Identifier: BSD-3-Clause
7
*/
8
#ifndef __RTE_DEVICE_H
9
#define __RTE_DEVICE_H
10
11
/*Driver name mapping*/
12
#define RTE_I2C4 1
13
#define RTE_I2C4_DMA_EN 0
14
#define RTE_I2C5 1
15
#define RTE_I2C5_DMA_EN 0
16
17
#define RTE_SPI3 0
18
#define RTE_SPI3_DMA_EN 0
19
#define RTE_SPI5 1
20
#define RTE_SPI5_DMA_EN 0
21
22
#define RTE_USART0 1
23
#define RTE_USART0_DMA_EN 0
24
25
/* UART configuration. */
26
#define USART_RX_BUFFER_LEN 64
27
#define USART0_RX_BUFFER_ENABLE 1
28
29
/* I2C configuration */
30
#define RTE_I2C4_Master_DMA_BASE DMA0
31
#define RTE_I2C4_Master_DMA_CH 9
32
33
#define RTE_I2C5_Master_DMA_BASE DMA0
34
#define RTE_I2C5_Master_DMA_CH 11
35
36
/* SPI configuration. */
37
#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
38
#define RTE_SPI0_DMA_TX_CH 1
39
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
40
#define RTE_SPI0_DMA_RX_CH 0
41
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
42
43
#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
44
#define RTE_SPI1_DMA_TX_CH 3
45
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
46
#define RTE_SPI1_DMA_RX_CH 2
47
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
48
49
#define RTE_SPI2_SSEL_NUM kSPI_Ssel0
50
#define RTE_SPI2_DMA_TX_CH 5
51
#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
52
#define RTE_SPI2_DMA_RX_CH 4
53
#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
54
55
#define RTE_SPI3_SSEL_NUM kSPI_Ssel2
56
#define RTE_SPI3_DMA_TX_CH 7
57
#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
58
#define RTE_SPI3_DMA_RX_CH 6
59
#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
60
61
#define RTE_SPI4_SSEL_NUM kSPI_Ssel0
62
#define RTE_SPI4_DMA_TX_CH 9
63
#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
64
#define RTE_SPI4_DMA_RX_CH 8
65
#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
66
67
#define RTE_SPI5_SSEL_NUM kSPI_Ssel2
68
#define RTE_SPI5_DMA_TX_CH 11
69
#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
70
#define RTE_SPI5_DMA_RX_CH 10
71
#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
72
73
#define RTE_SPI6_SSEL_NUM kSPI_Ssel0
74
#define RTE_SPI6_DMA_TX_CH 13
75
#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
76
#define RTE_SPI6_DMA_RX_CH 12
77
#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
78
79
#define RTE_SPI7_SSEL_NUM kSPI_Ssel0
80
#define RTE_SPI7_DMA_TX_CH 15
81
#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
82
#define RTE_SPI7_DMA_RX_CH 14
83
#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
84
85
/* USART configuration. */
86
#define RTE_USART0_DMA_TX_CH 1
87
#define RTE_USART0_DMA_TX_DMA_BASE DMA0
88
#define RTE_USART0_DMA_RX_CH 0
89
#define RTE_USART0_DMA_RX_DMA_BASE DMA0
90
91
#endif
/* __RTE_DEVICE_H */
© Copyright 2016-2020 NXP. All Rights Reserved.
