EVTG Peripheral and Driver Overview

Peripheral feature and how this peripheral works

The Event Generator module is designed to be integrated in conjuction with one or more inter-peripheral crossbar switch (XBAR) modules. A crossbar switch is typically used to select the 4 EVTG inputs from among available peripheral outputs and GPIO signals. The EVTG outputs are typically used as additional inputs to a second crossbar switch, adding to it the ability to connect to its outputs an arbitrary 4-input boolean function of its other inputs. The input/output signals are chip specific, user has to check the reference manual or data sheet for the information.

Features

• The EVTG(Event Generator) module mainly includes two parts.
  • Two AND/OR/INVERT (known simply as the AOI) modules and one configurable Flip-Flop. It supports the generation of a configurable number of EVENT signals.
  • The two AOI combinational expressions share the four associated EVTG inputs: An, Bn, Cn, and Dn.
  • The Flip-Flop can be configured to make the two expressions act as the Reset port, Set port or D port, CLK port or simply go through to EVTG output with FF(Flip-Flop) bypassed.
• Highly programmable module for creating combinational boolean events
  • Each EVTG has four inputs and two outputs.
    • Four inputs are from available peripheral outputs and GPIO signals.
    • Two outputs can operate as hardware trigger signals or for other purpose.
  • Each EVTG has two groups of AOI to generate two combinational expressions.
  • Each AOI evaluates a combinational boolean expression as the sum of four products where each product term includes all four selected input sources available as true or complement values.
• One flexible FF can be configured as RS, D-FF, T-FF, JK-FF, Latch.
• Programmable AOI output filter to remove AOI output glitch.
• All logics are synchronous in bus clk domain.

How this peripheral works

EVTG module inside implements different kinds of Flip-Flop for the generation of desired EVTG output. Specific functional differences can refer to reference manual. EVTG support sync to evtg inputs and filter function to AOI output. The application scenario for both are different. Input sync feature makes evtg input sync for two bus_clk cycles. Any glitch whose width is less than a bus clk period will be removed. But for Filter, though this module works in bus_clk and have the same function as the first one, it's designed for filter. Any signal whose width is less than Filter_Delay value will be filtered. Therefore, functions should be enabled depends on the actual user case.Each selected AOI input term in each product term can be configured to produce a logical 0 or 1 or pass the true or complement of the selected event input.

How this driver is designed to make this peripheral work

This driver provide multiple APIs to configure Event Generator module. The APIs this driver provides can be classified in 3 API groups:

• Initialization Interfaces
  • EVTG initial configuration covering all configurable fields.
• Force Init Flipflop Interfaces
  • The API in this function group can be used to force Flip-flop initial output value to be presented on flip-flop positive output.
• Input Interfaces
  • Configure each selected input term in each product term to produce a logical 0 or 1 or pass the true or complement of the selected event input.

How to use this driver

• To generate event output signals, invoke the EVTG_Init() function. It takes the argument in type of evtg_config_t, which contains all EVTG features.
• If needed, other API groups can be used to do individual EVTG configuration. invoke Force Init Flipflop Interface to force Flip-flop initial output value to be presented on flip-flop positive output. The functions in Input Interfaces can be used to configure each selected input term in each product term.

Typical Use Case

EVTG module inside implements different kinds of Flip-Flop for the generation of desired EVTG output. Here take Bypass mode and JK-FF Mode as examples.

• Bypass Mode:
  • Configure an EVTG to expected Bypass mode.
  • In this mode, filp-flop will be passed, The two AOI expressions "AOI_0" and "AOI_1" will be directly assigned to EVTG outputs. User can choose to enable or disable input sync logic and filter function.
  • Here disable both input sync logic and filter function. The event logical expression example:(A & ~B)|(~A & B). Obviously, AOI0 expression is (A & ~B) | (~A & B).

             evtg_config_t sConfig;
             EVTG_GetDefaultConfig(&sConfig,kEVTG_FFMode_Bypass); //select Bypass mode as default.
             // Term0 is "A & ~B".
             sConfig.sAOI0Config.sProductTerm0.eAInput = kEVTG_Input_DirectPass;
             sConfig.sAOI0Config.sProductTerm0.eBInput = kEVTG_Input_Complement;
             sConfig.sAOI0Config.sProductTerm0.eCInput = kEVTG_Input_LogicOne;
             sConfig.sAOI0Config.sProductTerm0.eDInput = kEVTG_Input_LogicOne;
             // Term1 is "~A & B".
             sConfig.sAOI0Config.sProductTerm1.eAInput = kEVTG_Input_Complement;
             sConfig.sAOI0Config.sProductTerm1.eBInput = kEVTG_Input_DirectPass;
             sConfig.sAOI0Config.sProductTerm1.eCInput = kEVTG_Input_LogicOne;
             sConfig.sAOI0Config.sProductTerm1.eDInput = kEVTG_Input_LogicOne;
    
             EVTG_Init(EVTG, kEVTG_Index0, &sConfig);
    *    

• JK-FF Mode:
  • In general, JK Flip-Flop have four input ports: J, K , Q and CLK. And the logical expression is J&~Q | ~K&Q .
  • Suppose we set EVTG input "An" as "J" port, "Cn" as "K" port, "Dn" as "CLK" port, and "Q" port of Flip-Flop feed back and override "Bn", According to the JK logic expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", AOI_1 expression will be "Dn".

             evtg_config_t sConfig;
             // The AOI_0 expression is "An&~Bn | Bn&~Cn", the AOI_1 expression is "Dn".
             EVTG_GetDefaultConfig(&sConfig, kEVTG_FFMode_JKFF); //select kEVTG_FFMode_JKFF mode as default.
    
             EVTG_Init(EVTG, kEVTG_Index0, &sConfig);
    *