eFlexPWM Peripheral and Driver Overview

Content including 1) peripheral features, work logic and work method; 2) driver design logic and use method; 3) typical use case. More...

Peripheral feature and how this peripheral works

The pulse width modulator (PWM) module contains 4 PWM submodules, each of which can set up to generate various switching patterns, including highly sophisticated waveforms. It can be used to control all known motor types and is ideal for controlling different Switched Mode Power Supplies (SMPS) topologies as well.

Features

• Support flexible PWM generator logic, include a 16 bit counter, register reload logic, VAL registers logic, force logic, dead time insertion logic , fractional delay logic and output logic.
  • The 16 bit counter support select input clock from multiple clock sources, and has multiple initial source. It only count in the up direction and then reset to the initial count register (INIT) value.
    • Input source can select between three clock signals: the IPBus clock, EXT_CLK (typically from external timer or an off-chip source), and AUX_CLK (can't be used in submodule 0 ).
      • The AUX_CLK signal is broadcast from submodule0 (after clock prescaler and run enable control) and can be selected as the clock source by other submodules.
    • 8 bit clock prescaler support to dividing the clock source by 1~128.
    • 16-bit initial count register, which will loaded into the submodule counter when the selected initialize signal triggers or a FORCE_OUT signal is asserted.
      • The initial signal can select between four signals : the local initial signal (VAL1 register compare), master reload signal (from submodule 0), master initial signal (from submodule 0), and PWM_EXT_SYNC signal (from on chip or off chip depending on the system architecture).
      • The master reload/initial signal should not be used in submodule 0 as it will force the INIT signal to logic 0.
      • Force output signal initialization is disabled by default. A enabled FORCE_OUT initialization will also assert the local reload if MCTRL[LDOK] is set.
  • The register reload control logic is used to determine when the outer set of registers for all double buffered register pairs will be transferred to the inner set of registers. The double buffered register include the prescaler bits, initial count register, and VALn registers. The reload signal can select from local reload signal or master reload signal (from submodule 0).
    • The master reload signal should not be used in submodule 0 as it will force the RELOAD signal to logic 0. The master reload signal actual is the submodule 0 local reload signal.
    • When choose local reload signal, it can assert when execute the software initialization command, or can reload immediately if MCTRL[LDOK] is set. The local reload also can select take effect at the next PWM reload if MCTRL[LDOK] is set. The next PWM reload means need to wait one or more reload opportunities.
      • Reload opportunities can be generated on a half compare event (VAL0 register compare) or/and a full compare event (VAL1 register compare).
      • The number of reload opportunities need to wait can choose from 1 to 16.
  • The VAL registers logic include 6 16-bit compare registers (VAL0 ~VAL5) and 3 PWM output (PwmX , Pwm23 and Pwm45).Each output use two compare registers, and one VAL register is used to control the turn-on edge, while another VAL register control the turn-off edge. Each VAL register compare event can be used to generate interrupt and output trigger.
    • The VALx register compare mode can choose "equal to" or "equal to or greater than", and both under unsigned mode. The compare mode bit can only be written one time after which it requires a reset to release the bit for writing again.
    • FORCE_OUT initialization can force PwmX and Pwm23/45 output, and the initial output value can select.
    • The PwmX use VAL0 (turn-on) and VAL1 (turn-off) registers. The VAL0 used to trigger a half compare event and the VAL1 used to trigger a full compare event. The PwmX output falling edge will assert local initial signal.
    • The Pwm23 use VAL2 (turn-on) and VAL3 (turn-off). The Pwm23 will transfer to force logic to do further processing.
    • The Pwm45 use VAL4 (turn-on) and VAL5 (turn-off). The Pwm45 will transfer to force logic to do further processing.
    • By set the initial count register value to be the 2's complement of the VAL1 value, the PWM generator can operates in "signed" mode. Just like set initial count value to 0xFF00, VAL0 to 0x0 and VAL1 to 0x00FF, (0x100 -1, because the change during the end to start of the PWM period requires a count time) then counter will count from 0xFF00 to 0xFFFF, then overflow to 0x0 and count to 0x00FF.
  • Support force logic to process the Pwm23 and Pwm45 signal from VAL registers logic, and it has two outputs. (Pwm23_force and Pwm45_force).
    • Each force logic output can select between 4 sources : RAW Pwm23/45 ( RAW signal from PWM generation logic) , invert Pwm23/45, software output (can select logic 0 or 1) and PWM_EXTA/B signal (alternate external control signals).
    • The selection of force logic output source are presented to the signal selection mux only when a selected FORCE_OUT signal assert. The FORCE_OUT signal support select from multiple signal sources.
      1. Local software force signal, will transfer to other submodules as master force signal.
      2. Master force signal form submodule 0. Should not be used in submodule 0 as it will hold the FORCE_OUT signal to logic 0.
      3. Local reload signal.
      4. Master reload signal form submodule 0. Should not be used in submodule 0 as it will hold the FORCE_OUT signal to logic 0.
      5. Local sync signal.
      6. Master sync signal form submodule 0. Should not be used in submodule 0 as it will hold the FORCE_OUT signal to logic 0.
      7. External force signal (EXT_FORCE) from outside the PWM module.
      8. External sync signal (EXT_SYNC) from outside the PWM module.
  • Support deadtime insertion logic, which can insert dead time in its input source, and make the deadtime insertion logic output (Pwm23_deadtime and Pwm45_deadtime) to be complementary state.
    • Deadtime insertion logic input 0/1 can choose source as two types:
      1. Input 0 be Pwm23_force and Input 1 Pwm45_force from force logic.
      2. Both input0/1 be double switching signal ("Pwm23_force XOR Pwm45_force" signal).
    • Deadtime insertion logic two output can select works as complementary mode or independent mode, and dead time insertion only takes effect in complementary mode.
      1. Complementary mode, the outputs become a pair of complementary signals.
         • The complementary signals source can select from Input 0 (Pwm23_force or double switching signal) or Input 1 (Pwm45_force or double switching signal).
         • The output complementary signals will be inserted a number of IPBus clock cycles of deadtime. The number can be different for each output.
         • The inserted number of IPBus clock cycles can be fractional if enable the fractional delay logic, the smallest unit is 1/32 IPBus clock cycle.
      2. Independent mode.
         • When the inputs are double switching signal, can enable SPLIT feature to causes Pwm23_deadtime output occurs when the Pwm23_force is 1 and the Pwm45_force is 0. The Pwm45_deadtime output occurs when the Pwm45_force is 1 and the Pwm23_force is 0.
  • Support fractional delay logic to support more resolution than a single IPBus clock period, it can be used to achieve fine resolution the rising and falling edges of the Pwm23_deadtime and Pwm45_deadtime, and fine resolution for the PwmX period. The fractional delay logic can only be used when the IPBus clock is running at 100 MHz.
    • Pwm23_deadtime and Pwm45_deadtime rising and falling edges fractional delay value can be different, range from 1/32 to 31/32 IPBus clock cycle.
    • PwmX only support add fractional delay on falling edges, if it is enabled, the largest value for the VAL1 register is 0xFFFE for "unsigned" usage or 0x7FFE for "signed" usage.
    • Each output fractional delay feature can be enabled/disabled independent. And module fractional delay circuit need waiting 25usec after first submodule fractional delay logic power up.
  • Support output logic to do flexibility control about fault disabling, polarity/mask control, and output enable. It process the PWM output form fractional delay logic (Pwm23_fractional_delay, Pwm45_fractional_delay and PwmX_fractional_delay) and output the final PWM signal (PWM_A , PWM_B and PWM_X). It also process the compare trigger output from PWM generation logic.
    • Final PWM output signal under no-fault status be processed follow the steps below:
      1. Select mask output (logic 0 before polarity select) or normal output.
      2. Select polarity as invert or not invert.
      3. Select enable or disable output (disable with tristated status).
    • Final PWM output signal under fault status (fault input signal mapping from fault protection channel) can be follow types:
      1. Output with low.
      2. Output with high.
      3. Output with tristated.
    • Final mux trigger output signal (PWM_MUX_TRIG0/1)can choose to use "VAL compare trigger signal" from VAL registers logic or "final PWM output". The "VAL compare trigger signal" based on the counter value matching the value in one or more of the VAL0-5 registers.
      • The VAL0, VAL2, and VAL4 matching can use to generate PWM_MUX_TRIG0, and VAL1, VAL3, and VAL5 matching can use to generate PWM_MUX_TRIG1.
      • VAL0-5 registers compare trigger signals can be enabled/disabled independent.
      • VAL0-5 registers compare trigger signals can be generator on every full compare cycle (every PWM period which count from INIT to VAL1) or on local reload opportunities (need wait one or more reload opportunities according to reload configure).
• Support enhanced capture (E-Capture) feature to measure both edges of an input signal. Each input signal has an independent E-Capture logic, which with two input capture circuits (Circuit 0/1). The submodule 16 bits counter are share for these input capture logic
  • The input signals are from PWM_A, PWM_B and PWM_X pins (default works as output and connect to PWM output signal). When enable input capture, the corresponding PWM output must be disabled.
  • The input capture circuit0/1 input source are "raw input signal" and the "output of the edge counter/compare circuitry".
    • When the input source is "raw input signal", the input capture circuit0/1 capture edge can be falling edges, rising edges and both edges.
    • When the input source is "output of the edge counter/compare circuitry", the capture edge selection will be ignored but it need to choose one edge mode to enable the circuit0/1.
    • The edge counter/compare circuitry will counts rising and falling edges on the raw input signal. And trigger a active edge to the input capture circuit0/1 when it counter value matching the value in 8 bit capture compare register.
  • The input capture circuit0/1 can be enabled/disabled independent, and they can work at one shot mode, which make both circuit0/1 works only once.
• Support fault protection channel logic, one PWM can contain one or more fault protection channels. The fault protection channel process the input fault pin signals and output the faults status to all PWM submodules. When the faults status are mapped on submodules, it can disables PWM outputs (the submodule PWM generator continues to run, only the output pins are forced to logic 0, logic 1, or tristated status). The fault protection is enabled even when the PWM module clock is disabled.
  • Each fault protection channel has 4 independent input fault pins. And the active logic level of the individual fault inputs can be logic 0 or logic 1. Each fault pin has a programmable filter that can be bypassed, and the fault inputs signal can combined with the the filtered and latched fault input signal to disable the PWM outputs.
  • Fault protection channel supports two different states (FFPIN and FFLAG).
    1. The FFPIN bits reflect the current state of the filtered FAULTx pins converted to high polarity. A logic 1 indicates a fault condition exists on the filtered FAULTx pin.
    2. The FFLAG bits are set within two CPU cycles after a transition to active on the FAULTx pin. FFLAG only can be cleared by writing a logic one to it.
  • Fault protection channel can select automatic or manual clearing mode to disable the PWM output. Each submodule PWM output (PwmA, PwmB and PwmX) can be disabled by each fault protection channel 4 fault input condition status independent.
    1. Manual fault clearing normal mode. The PWM output disable when FFLAG status set, and will not re-enable until FFLAG is clear at the start of a half cycle or full cycle without regard to the state of FFPIN.
    2. Manual fault clearing safe mode. The PWM output disable when FFLAG status set, and will not re-enable until FFLAG and FFPIN are clear at the start of a half cycle or full cycle.
    3. Automatic fault clearing. The PWM output disable when FFPIN status set, and will re-enable automatic base on FFPIN value at the start of a half cycle or full cycle.
• Supports Interrupts.
  • Submodule interrupt.
    1. Compare VAL0-5 interrupt.
    2. Capture A0/1, B0/1 and X0/1 interrupt.
    3. Reload interrupt.
    4. Reload error interrupt.
  • Fault protection channel interrupt.
    1. Each channel has 4 FAULT condition interrupt.
• Supports DMA.
  • Submodule DMA request.
    1. Independent capture A0/1, B0/1 and X0/1 will trigger DMA read requests for the Capture A0/1, B0/1 and X0/1 FIFO data. Will be selected as FIFO watermarks source for DMA read capture FIFOs request when enable. Can't works will capture interrupt.
    2. Reload will trigger DMA write requests for the VALx and FRACVALx registers.
    3. DMA read capture FIFOs request which the trigger source can select. The trigger source can be:
       • Exceeding a FIFO watermark sets the DMA read request. Need to enable at least one of the capture DMA request to decide use which capture FIFO. Multiple selected FIFO watermarks are OR'ed/AND'ed together.
       • A local initial (VAL1 matches counter) sets the read DMA request.
       • A local reload (STS[RF] being set) sets the read DMA request.

How this peripheral works

• PWM generation mode In this mode, the enhanced capture (E-Capture) logic is not used.
  1. Submodule start count up with input source rising edge until its value equals VAL1. This compare causes a rising edge to occur on the Local sync signal which is one of four possible sources used to cause the 16 bit counter to be initialized with INIT.
  2. During counting, the VAL0-5 registers compare make the corresponding output turn-on and turn-off, then the VAL registers logic output will process by force logic, deadtime insertion logic, fractional delay logic and output logic, final generate PWM output.
  3. Fault protection logic provide output faults status, which can mapping to disable submodule PWM output.
• Input capture mode In this mode, the enhanced capture (E-Capture) logic is used.
  1. Submodule start count up with input source rising edge until its value equals VAL1, This compare causes a rising edge to occur on the Local sync signal which is one of four possible sources used to cause the 16 bit counter to be initialized with INIT.
  2. Enable the PWM output pin capture feature to make it works as an input signal. The CVALx registers associated with that pin will record the counter values when capture occurs.

How this driver are designed to make this peripheral works

The PWM driver provides the structure pwm_config_t, which contain four submodule configure structure pointers and two fault protection channel configure structure pointers, only actually used submodule/fault channels need to assign a value to its structure pointer. This is want to save stack space. The channel configure structure pwm_sm_config_t which contain several sub-structures and other member to cover all feature of one PWM submodule. The PWM_Init() function takes the argument in type of pwm_config_t, and can complete the initialization of the PWM module. Since PWM is very flexible and has a very complex function configuration, use sub-structures to facilitate the understanding of the module and provide function APIs to take them as parameters. Base on the sub-structures and other behaviors of PWM submodule, the PWM driver can be divided into several function API groups.

• Initialization and De-initialization Interfaces. The APIs in this function group can be used to initialize or de-initialize the PWM module.
• Submodule PWM Generation Related Interfaces. The APIs in this function group can be used to configure submodule PWM generation related options. Include counter control, reload logic Control, force logic control, deadtime insert control, fractional delay feature control and final output control. Also provide a API to do the complete channel initialization.
• Submodule Input Capture Related Interfaces. The APIs in this function group can be used to configure submodule enhanced capture (E-Capture) logics.
• Fault Protection Channel Related Interfaces. The APIs in this function group can be used to configure fault protection channel.
• DMA Control Interfaces. The APIs in this function group can be used to set DMA features. Such as select DMA enable source select, enable/disable DMA.
• Interrupt Control Interfaces. The APIs in this function group can be used to enable/disable submodule or fault protection channnel interrupts.
• Status Flag Interfaces. The APIs in this function group can be used to get or clear the status flag of the PWM submodules and fault protection channels.

How to use this driver

• Steps shall be done outside PWM driver
  • Initialize the pin or/and XBAR with expected features configured. PWM input signal (fault input or input capture) can from chip pin or other peripheral output, and PWM output signal can connect to chip pin or other peripheral input.
  • SoC level interrupt controller configuration shall be configured / enabled in application codes if PWM is expected to generator interrupt on submodule compare event, submodule input capture event, submodule reload event or fault protection channel fault status event.
  • Interrupt entry function shall be added in the application codes and interrupt handler function shall be placed in the entry function to make sure the implemented interrupt handling codes will be invoked on a generation of interrupt.
  • Enable DMA and configure DMA channel trigger source in application codes if PWM submodule is expected to generator DMA request on input capture event or submodule reload/sync event.
• Sets the PWM work mode by invoking PWM_Init()
  • [Optional] Invokes PWM_GetSMDefaultConfig() function to get the submodule default configuration.
  • [Optional] Invokes PWM_GetFaultProtectionDefaultConfig() function to get the fault protection channel default configuration.
  • [Optional] Invokes PWM_GetValueConfig() function to get the VALn registers configuration.
  • Set the member of submodule configure structure pwm_sm_config_t to get expected PWM submodule feature.
  • Set the member of fault protection channel configure structure pwm_fault_protection_config_t to get expected fault protection channel feature.
  • Set the pointer member of pwm_config_t with the address of "submodule"/"fault protection channel" configure structure.
  • Invokes PWM_Init() to set PWM configuration.
    • Submodule counter will start directly when channel configure variable member enableRun is true.
• [Optional] Invokes PWM_EnableCounters() to start submodule counter.
• [Optional] Invokes function API to get status or do flexible control.

Typical Use Case

1. Generate PWM_A/B output with different pulse width and enable fault disable for PWM_A output. In this typical use case, the PWM submodule will count the rising edges of the IP bus clock divider by 1. The PWM_A output will be u16PwmPulse/u16PwmPeriod duty cycle PWM, and PWM_B duty cycle be the half of PWM_A. The PWM_A output will be disabled when the fault pins 0 of the fault protection channel 0 is activated (active level be logic 0).

   *        pwm_config_t sPwmConfig = {0};
   *        pwm_sm_config_t sSubmoduleConfig;
   *        pwm_fault_protection_config_t sFaultConfig;
   *        uint16_t u16PwmPeriod, u16PwmPulse;
   *        sPwmConfig.psPwmSubmoduleConfig[0] = &sSubmoduleConfig;
   *        sPwmConfig.psFaultProtectionConfig[0] = &sFaultConfig;
   *        PWM_GetSMDefaultConfig(&sSubmoduleConfig);
   *        PWM_GetFaultProtectionDefaultConfig(&sFaultConfig);
   *        PWM_GetValueConfig(&sSubmoduleConfig.sValRegisterConfig, kPWM_SignedCenterAligned, u16PwmPeriod,
   *                                    u16PwmPulse, (u16PwmPulse / 2));
   *        sPwmSm0Config.sPwmAFaultInputMapping.bFaultInput0Mapping = true;
   *        PWM_Init(PWM, &sPwmConfig);
   *        PWM_EnableCounters(PWM, kPWM_SubModule0Enable);
   *    

2. Generate a pair of center aligned complementary PWM (PWM_B is inverted PWM_A) signals (with dead time insert). In this typical use case, the PWM submodule 0 will count the rising edges of the IP bus clock divider by 1. The PWM_A output will be u16PwmPulse/u16PwmPeriod duty cycle PWM, and PWM_B be the inverted of PWM_A. The dead time can be inserted before the rising edge of PWM_A/B. The inserted value is in the unit of IP clock cycle and PWM_A/B can choose to insert different values.

   *        pwm_config_t sPwmConfig = {0};
   *        pwm_sm_config_t sSubmoduleConfig;
   *        uint16_t u16PwmPeriod, u16PwmPulse, u16DeadTime;
   *        sPwmConfig.psPwmSubmoduleConfig[0] = &sSubmoduleConfig;
   *        PWM_GetSMDefaultConfig(&sSubmoduleConfig);
   *        PWM_GetValueConfig(&sSubmoduleConfig.sValRegisterConfig, kPWM_SignedCenterAligned, u16PwmPeriod,
   *                                    u16PwmPulse, u16PwmPulse);
   *        sSubmoduleConfig.sDeadTimeConfig.eMode = kPWM_ComplementaryWithPwmA;
   *        sSubmoduleConfig.sDeadTimeConfig.sDeadTimeValue0.bitsIntegerCycles = u16DeadTime;
   *        sSubmoduleConfig.sDeadTimeConfig.sDeadTimeValue1.bitsIntegerCycles = u16DeadTime;
   *        PWM_Init(PWM, &sPwmConfig);
   *        PWM_EnableCounters(PWM, kPWM_SubModule0Enable);
   *    

3. Generate phase shifted PWMs In this typical use case, the PWM submodule 0 will start count the rising edges of the IP bus clock divider by 1. Submodule 1 count on same clock with submodule 0. And the PWM_A output of submodules 1 be delayed from the output of submodule 0 with same PWM period and same PWM pulse width.

   *        pwm_config_t sPwmConfig = {0};
   *        pwm_sm_config_t sSubmoduleConfig0, sSubmoduleConfig1;
   *        uint16_t u16PwmPeriod, u16PwmPulse, u16PhaseDelay;
   *        sPwmConfig.psPwmSubmoduleConfig[0] = &sSubmoduleConfig0;
   *        sPwmConfig.psPwmSubmoduleConfig[0] = &sSubmoduleConfig1;
   *        PWM_GetSMDefaultConfig(&sSubmoduleConfig0);
   *        PWM_GetSMDefaultConfig(&sSubmoduleConfig1);
   *        PWM_GetValueConfig(&sSubmoduleConfig.sValRegisterConfig, kPWM_SignedCenterAligned, u16PwmPeriod,
   *                                    u16PwmPulse, u16PwmPulse);
   *        sSubmoduleConfig1.sCounterConfig.eCountClockSource = kPWM_ClockSrcSubmodule0Clock;
   *        sSubmoduleConfig1.sCounterConfig.eCountInitSource = kPWM_InitOnMasterSync;
   *        sSubmoduleConfig1.sCounterConfig.u16PhaseDelayValue = u16PhaseDelay;
   *        PWM_Init(PWM, &sPwmConfig);
   *        PWM_EnableCounters(PWM, kPWM_SubModule0Enable | kPWM_SubModule1Enable);
   *