MCUXpresso SDK Changelog
ADC
[2.0.4]
Bug Fixes
Fixed violation of MISRA C-2012 rule 10.4.
[2.0.3]
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.1 10.4 10.7 17.7.
[2.0.2]
Improvements
Used conversion control feature macro instead of that in IO map.
[2.0.1]
New Features
Added a control macro to enable/disable CLOCK code in current driver.
[2.0.0]
Initial version.
ADC_ETC
[2.3.0]
Improvements
Added blocking way to implement SW trigger.
[2.2.1]
Improvements
Moditied macro “ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK” to “ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK” based on the updates of header file.
[2.2.0]
Improvements
Defined two macros to support some devices that do not equipped with TSC trigger.
[2.1.1]
Bug Fixes
Fixed the violation of MISRA-2012 rule.
[2.1.0]
New Features
Supported independent IRQ enable bit in ADC-ETC chain configuration registers.
Supported trigger n DONE3 interrupt operations.
Bug Fixes
Fixed the violation of MISRA-2012 rules:
Rule 10.1 10.3 10.7 15.5 16.1 16.3 16.4 17.7
[2.0.1]
New Features
Added a control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
AIPSTZ
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.0]
Initial version.
AOI
[2.0.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8, 2.2.
[2.0.0]
Initial version.
BEE
[2.0.2]
Bug Fixes
Fix MISRA issue.
[2.0.1]
Bug Fixes
Fixed bug in key user key loading sequence. BEE must be enabled during loading of user key.
Fixed typos in comments.
New Features
Added configuration setting for endian swap, access permission and region security level.
Improvements
Setting of AES nonce was moved from BEE_SetRegionKey() into separate BEE_SetRegionNonce() function.
Changed handling of region settings. Both regions are configured simultaneously by BEE_SetConfig() function. Configuration of FAC start and end address using IOMUXC_GPRs was moved to application.
Default value for region address offset was changed to 0.
[2.0.0]
Initial version.
CACHE ARMv7-M7
[2.0.4]
Bug Fixes
Fixed doxygen issue.
[2.0.3]
Improvements
Deleted redundancy code about calculating cache clean/invalidate size and address aligns.
[2.0.2]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.1, 10.3 and 10.4.
[2.0.1]
Bug Fixes
Fixed cache size issue in L2CACHE_GetDefaultConfig API.
[2.0.0]
Initial version.
CLOCK
[2.5.3]
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.7.
[2.5.2]
Bug Fixes
Fixed issues in CLOCK_GetSysPfdFreq() and CLOCK_GetUsb1PfdFreq() which produce incorrect result.
[2.5.1]
Improvements
Added enumeration clock_div_value_t.
[2.5.0]
New features
Added CLOCK_IsUsb1PfdEnabled and CLOCK_IsSysPfdEnabled to get the clock source status.
[2.4.1]
Improvements
Placed function internal constants into initialized data segment.
[2.4.0]
New Features
Added clock output related APIs and data structures.
Added one function CLOCK_GetClockRootFreq to get the frequency of each clock root.
[2.3.2]
Bug Fixes
Fixed MISRA C-2012 rule 20.7 rule 8.6 rule 10.3 and rule 10.1.
Fixed IAR warning Pa082 for the clock driver.
[2.3.1]
Improvements
Added new macro in case that the CCM has CAN clock affect issue.
[2.3.0]
New feature:
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.2.0]
New feature
Adding new API CLOCK_DelayAtLeastUs() implemented by DWT to allow users set delay in unit of microsecond.
[2.1.6]
Bug Fix:
Fix build issue with GCC compiler when include header from C++ file.
[2.1.5]
Bug Fix:
Add initialization of the fractional mode and spread spectrum mode in CLOCK_InitSysPll().
[2.1.4]
Optimization:
Add PerClk in clock_name_t and CLOCK_GetFreq.
Add APIs to get the frequency of AHB clock and SEMC, IPG clock and PER clock.
[2.1.3]
Use double instead of uint64_t to achieve better performance with double precision FPU.
[2.1.2]
some minor fixes.
[2.0.0]
initial version.
CMP
[2.0.3]
Improvements
Updated to clear CMP settings in DeInit function.
[2.0.2]
Bug Fixes
Fixed the violations of MISRA 2012 rules:
Rule 10.3
[2.0.1]
Bug Fixes
Fixed MISRA-2012 rules.
Rule 14.4, rule 10.3, rule 10.1, rule 10.4 and rule 17.7.
[2.0.0]
Initial version.
COMMON
[2.5.0]
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]
New Features
Added NETC into status group.
[2.3.2]
Improvements
Make driver aarch64 compatible
[2.3.1]
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]
Other Change
Added MECC status group definition.
[2.2.6]
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]
New Features
Added OTFAD into status group.
[2.1.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]
Initial version.
DCDC
[2.3.0]
Improvements
REG3[MISC_DELAY_TIMING], REG2[LOOPCTRL_DC_R], and REG2[LOOPCTRL_DC_C] are reserved in the latest RM, deleted corresponding functions.
[2.2.1]
Improvements
Fixed the doxygen warning.
[2.2.0]
New Features
Added supports for i.MXRT1170 series.
Bug Fixes
Fixed the warning that the DCDC_ConvertByteArrayToWord function defined but not used.
Improvements
Updated rcscale to reduce the ripple when booting into DCM.
[2.1.0]
Improvements
Divided the DCDC_AdjustTargetVoltage() into two APIs for two different modes.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.1, 10.4, 16.4, 17.7.
[2.0.0]
Initial version.
DCP
[2.1.7]
Bug Fix
Reduce optimization level for critical functions working with SRF.
[2.1.6]
Bug Fix
MISRA C-2012 issue fix.
[2.1.5]
Improvements
Added support when DCACHE enabled. Input and output buffers should be in non-cached memory or handled properly (DCACHE Clean and Invalidate).
[2.1.4]
Bug Fix
Fix CRC-32 computation issue on the code’s block boundary size.
[2.1.3]
Bug Fix
MISRA C-2012 issue fixed: rule 10.1, 10.3, 10.4, 11.9, 14.4, 16.4 and 17.7.
[2.1.2]
Bug Fix
Fix sign-compare warning in dcp_reverse_and_copy.
[2.1.1]
Improvements
Added DCP status clearing when channel operation is complete.
[2.1.0]
New Features
Added byte/word swap feature for key, input, and output data.
[2.0.0]
Initial version.
DMAMUX
[2.1.1]
Improvements
Add macro FSL_FEATURE_DMAMUX_CHANNEL_NEEDS_ENDIAN_CONVERT and DMAMUX_CHANNEL_ENDIAN_CONVERTn do channel endian convert.
[2.1.0]
Improvements
Modify the type of parameter source from uint32_t to int32_t in the DMAMUX_SetSource.
[2.0.5]
Improvements
Added feature FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH for the difference of CHCFG register width.
[2.0.4]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.0.3]
Bug Fixes
Fixed the issue for MISRA-2012 check.
Fixed rule 10.4 and rule 10.3.
[2.0.2]
New Features
Added an always-on enable feature to a DMA channel for ULP1 DMAMUX support.
[2.0.1]
Bug Fixes
Fixed the build warning issue by changing the type of parameter source from uint8_t to uint32_t when setting DMA request source in DMAMUX_SetSourceChange.
[2.0.0]
Initial version.
EDMA
[2.4.5]
Bug Fixes
Fixed memory convert would convert NULL as zero address issue.
[2.4.4]
Bug Fixes
Fixed comments by replacing STCD with TCD
Fixed the TCD overwrite issue when submit transfer request in the callback if there is a active TCD in hardware.
Fixed violations of MISRA C-2012 rule 10.8,5.6.
[2.4.3]
Improvements
Added FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET to convert the address between system mapped address and dma quick access address.
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt for the non scatter gather case.
[2.4.2]
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt by correct the initial value of the header.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.4.1]
Bug Fixes
Added clear CITER and BITER registers in EDMA_AbortTransfer to make sure the TCD registers in a correct state for next calling of EDMA_SubmitTransfer.
Removed the clear DONE status for ESG not enabled case to aovid DONE bit cleared unexpectedly.
[2.4.0]
Improvements
Added api EDMA_EnableContinuousChannelLinkMode to support continuous link mode.
Added apis EDMA_SetMajorOffsetConfig/EDMA_TcdSetMajorOffsetConfig to support major loop address offset feature.
Added api EDMA_EnableChannelMinorLoopMapping for minor loop offset feature.
Removed the reduntant IRQ Handler in edma driver.
[2.3.2]
Improvements
Fixed HIS ccm issue in function EDMA_PrepareTransferConfig.
Fixed violations of MISRA C-2012 rule 11.6, 10.7, 10.3, 18.1.
Bug Fixes
Added ACTIVE & BITER & CITER bitfields to determine the channel status to fixed the issue of the transfer request cannot submit by function EDMA_SubmitTransfer when channel is idle.
[2.3.1]
Improvements
Added source/destination address alignment check.
Added driver IRQ handler support for multi DMA instance in one SOC.
[2.3.0]
Improvements
Added new api EDMA_PrepareTransferConfig to allow different configurations of width and offset.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4, 10.1.
Fixed the Coverity issue regarding out-of-bounds write.
[2.2.0]
Improvements
Added peripheral-to-peripheral support in EDMA driver.
[2.1.9]
Bug Fixes
Fixed MISRA issue: Rule 10.7 and 10.8 in function EDMA_DisableChannelInterrupts and EDMA_SubmitTransfer.
Fixed MISRA issue: Rule 10.7 in function EDMA_EnableAsyncRequest.
[2.1.8]
Bug Fixes
Fixed incorrect channel preemption base address used in EDMA_SetChannelPreemptionConfig API which causes incorrect configuration of the channel preemption register.
[2.1.7]
Bug Fixes
Fixed incorrect transfer size setting.
Added 8 bytes transfer configuration and feature for RT series;
Added feature to support 16 bytes transfer for Kinetis.
Fixed the issue that EDMA_HandleIRQ would go to incorrect branch when TCD was not used and callback function not registered.
[2.1.6]
Bug Fixes
Fixed KW3X MISRA Issue.
Rule 14.4, 10.8, 10.4, 10.7, 10.1, 10.3, 13.5, and 13.2.
Improvements
Cleared the IRQ handler unavailable for specific platform with macro FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET.
[2.1.5]
Improvements
Improved EDMA IRQ handler to support half interrupt feature.
[2.1.4]
Bug Fixes
Cleared enabled request, status during EDMA_Init for the case that EDMA is halted before reinitialization.
[2.1.3]
Bug Fixes
Added clear DONE bit in IRQ handler to avoid overwrite TCD issue.
Optimized above solution for the case that transfer request occurs in callback.
[2.1.2]
Improvements
Added interface to get next TCD address.
Added interface to get the unused TCD number.
[2.1.1]
Improvements
Added documentation for eDMA data flow when scatter/gather is implemented for the EDMA_HandleIRQ API.
Updated and corrected some related comments in the EDMA_HandleIRQ API and edma_handle_t struct.
[2.1.0]
Improvements
Changed the EDMA_GetRemainingBytes API into EDMA_GetRemainingMajorLoopCount due to eDMA IP limitation (see API comments/note for further details).
[2.0.5]
Improvements
Added pubweak DriverIRQHandler for K32H844P (16 channels shared).
[2.0.4]
Improvements
Added support for SoCs with multiple eDMA instances.
Added pubweak DriverIRQHandler for KL28T DMA1 and MCIMX7U5_M4.
[2.0.3]
Bug Fixes
Fixed the incorrect pubweak IRQHandler name issue, which caused re-definition build errors when client set his/her own IRQHandler, by changing the 32-channel IRQHandler name to DriverIRQHandler.
[2.0.2]
Bug Fixes
Fixed incorrect minorLoopBytes type definition in _edma_transfer_config struct, and defined minorLoopBytes as uint32_t instead of uint16_t.
[2.0.1]
Bug Fixes
Fixed the eDMA callback issue (which did not check valid status) in EDMA_HandleIRQ API.
[2.0.0]
Initial version.
ENC
[2.2.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.0]
New Features
Supported input filter prescaler.
[2.1.0]
Improvements
Supported period measurement function.
[2.0.2]
Improvements
Added feature macro for CTRL2[SABIE] and CTRL2[SABIRQ] bits.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 17.7.
[2.0.0]
Initial version.
ENET
[2.9.2]
Bug Fixes
RGMII mode is (temporarily) disabled before selecting between 10/100-Mbit/s and 1000-Mbit/s modes of operation. The bit RGMII_EN of RCR register must not be set while changing ECR register’s speed bit, otherwise there is a possibility of ENET IP ending in an incorrect state.
[2.9.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.4.
[2.9.0]
Bug Fixes
Enabled collection of transfer statistics, so the function ENET_GetStatistics does not always return zeroes.
New Features
Added new function ENET_EnableStatistics to enable/disable collection of transfer statistics.
Added new function ENET_ResetStatistics to reset transfer statistics.
Improvements
Renamed the function ENET_ResetHareware to ENET_ResetHardware.
[2.8.0]
New Features
Added the function to reset hardware on certain devices.
[2.7.1]
Bug Fixes
Fixed the issue that free wrong buffer address when one frame stores in multiple buffers and memory pool is not enough to allocate these buffers to receive one complete frame.
[2.7.0]
Improvements
Deleted deprecated zero copy Tx/Rx functions and set callback function which can be configured in ENET_Init.
Moved the Rx zero copy buffer allocation to Rx BD initialization function to reduce unnecessary looping code.
Bug Fixes
Fixed the issue that predefined Rx buffers which should not be used when enabling Rx zero copy are still be handled by cache operation, it causes hardfault on some platforms.
Fixed the issue that zero-copy Rx function doesn’t check Rx length of 0 in the BD with EMPTY bit is 0, it may occur in the corner case reported by customer. Not sure how it turns out, consider it as an ENET IP issue and drop this abnormal BD.
[2.6.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 11.6.
[2.6.2]
Improvements
Changed ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler/ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler to ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler/ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler which represent ring 1 and ring 2.
[2.6.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 10.7, 11.6, 11.8.
[2.6.0]
Improvements
Added MDIO access wrapper APIs for ease of use.
Fixed the build warning introduced by 64-bit compatibility patch.
[2.5.4]
Improvements
Made the driver compatible with 64-bit platforms.
[2.5.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 11.6.
[2.5.2]
Improvements
Updated the TXIC/RXIC register handling code according to the new header file.
[2.5.1]
Bug Fixes
Fixed document typo.
[2.5.0]
Bug Fixes
Fixed the SendFrame/SendFrameZeroCopy functions issue with scattered buffers.
Updated the formula of MDC calculation.
Used a feature macro to distinguish the old IP design from the new design, because old IP design always reads a value zero from ATCR->CAPTURE bit. For old IP, driver caculates and wait the necessary delay cycles after setting ATCR->CAPTURE then gets the timestamp value.
New Features
Added new zero copy Tx/Rx function.
New zero copy Tx function combines scattered and contiguous Tx buffer in one API, it also supports more Tx featrues which buffer descriptor supports but previous Tx function doesn’t support.
New zero copy Rx function use dynamic buffer mechanism and simpler interface.
Improvements
Corrected the interrupt handler for PTP timestamp IRQ and PTP1588 event IRQ since platform difference.
Added missing IRQ handlers for PTP1588 events on some platforms.
Corrected the max Tx frame length verification, it will not depend on a fixed macro. The ENET_FRAME_MAX_FRAMELEN is only an default value for driver, application can configure it. Driver caculates the limitation with the max frame length in register which may takes extended 4 or 8 bytes VLAN tag if VLAN/SVLAN enables.
Deleted deprecated Clause 45 read/write legacy APIs.
[2.4.3]
Improvements
Aligned the IRQ handler name with header file.
[2.4.2]
Bug Fixes
Fixed the MISRA issue of speculative out-of-bounds access.
[2.4.1]
Bug Fixes
Fixed the PTP time capture issue.
[2.4.0]
Improvements
Exposed API ENET_ReclaimTxDescriptor for user application to relaim tx descriptors in their application.
Added counter to record multicast hash conflict in struct _enet_handle, improved the situation that one multicast group could be left by other conflict multicast address left operation.
Improved concurrent usage of relaim and send frame operation.
[2.3.4]
Bug Fixes
Fixed the issue that interrupt handler only checks the interrupt event flag but not checks interrupt mask flag.
[2.3.3]
Bug Fixes
Fixed the issue that some compilers may choose the memcpy with 4-bit aligned address limitation due to the type of address pointer is ‘unsigned int *’, the data address doesn’t have to be 4-bit aligned.
[2.3.2]
New Features
Added the feature that ENET driver can be used in the platform which integrates both 10/100M and 1G ENET IP.
Deleted duplicated code about ARM errata 838869 in first/second level IRQ handler.
[2.3.1]
Improvements
Added function pointer checking in IRQ handler to make sure code can be used even it runs into the interrupt when the second level interupt handler is NULL.
[2.3.0]
Bug Fixes
Fixed the issue that clause 45 MDIO read/write API doesn’t check the transmission over status between two transmissions.
Fixed violations of the MISRA C-2012 rules 2.2,10.3,10.4,10.7,11.6,11.8,13.5,14.4,15.7,17.7.
New Features
Added APIs to support send/receive frame with Zero-Copy.
Improvements
Separated the clock configuration from module configuration when init and deinit.
Added functions to set second level interrupt handler.
Provided new function to get 1588 timer count without disabling interrupt.
Improved timestamp controlling, deleted all old timestamp management APIs and data structures.
Merged the single/multiple ring(s) APIs, now these APIs can handle both.
Used base and index to control buffer descriptor, aligned with qos and lpc enet driver.
[2.2.6]
Bug Fixes
Updated MII speed formula referring to the manual.
[2.2.5]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.7, 11.6, 11.9, 13.5, 14.4, 16.4, 17.7, 21.15, 3.1, 8.4.
Changed to use ARRAY_SIZE(s_enetBases) as the array size for s_ENETHandle, fixed the hardfault issue for using some ENET instance when ARRAY_SIZE(s_enetBases) is not same as FSL_FEATURE_SOC_ENET_COUNT.
[2.2.4]
Improvements
Added call to Data Synchronization Barrier instruction before activating Tx/Rx buffer descriptor to ensure previous data update is completed.
Improved ENET_TransmitIRQHandler to store timestamps for multiple transmit buffer descriptors.
Bug Fixes
Fixed the issue that ENET_Ptp1588GetTimer did not handle the timer wrap situation.
[2.2.3]
Improvements
Improved data buffer cache maintenance in the ENET driver.
[2.2.2]
New Features
Added APIs for extended multi-ring support.
Added the AVB configure API for extended AVB feature support.
[2.2.1]
Improvements
Changed the input data pointer attribute to const in ENET_SendFrame().
[2.1.1]
New Features
Added the extended MDIO IEEE802.3 Clause 45 MDIO format SMI command APIs.
Added the extended interrupt coalescing feature.
Improvements
Combined all storage operations in the ENET_Init to ENET_SetHandler API.
[2.0.1]
Bug Fixes
Used direct transmit busy check when doing data transmit.
Miscellaneous Changes
Updated IRQ handler work flow.
Changed the TX/RX interrupt macro from kENET_RxByteInterrupt to kENET_RxBufferInterrupt, from kENET_TxByteInterrupt to kENET_TxBufferInterrupt.
Deleted unnecessary parameters in ENET handler.
[2.0.0]
Initial version.
EWM
[2.0.3]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.1, 10.3.
[2.0.2]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.3, 10.4.
[2.0.1]
Bug Fixes
Fixed the hard fault in EWM_Deinit.
[2.0.0]
Initial version.
FLEXCAN
[2.13.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
Improvements
Support payload endianness selection feature.
[2.12.0]
Improvements
Support automatic Remote Response feature.
Add API FLEXCAN_SetRemoteResponseMbConfig() to configure automatic Remote Response mailbox.
[2.11.8]
Improvements
Synchronize flexcan driver update on s32z platform.
[2.11.7]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compatibility with edma5.
[2.11.6]
Bug Fixes
Fixed ERRATA_9595 FLEXCAN_EnterFreezeMode() may result to bus fault on some platform.
[2.11.5]
Bug Fixes
Fixed flexcan_memset() crash under high optimization compilation.
[2.11.4]
Improvements
Update CANFD max bitrate to 10Mbps on MCXNx3x and MCXNx4x.
Release peripheral from reset if necessary in init function.
[2.11.3]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compile error with DMA3.
[2.11.2]
Bug Fixes
Fixed bug that timestamp in flexcan_handle_t not updated when RX overflow happens.
[2.11.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
[2.11.0]
Bug Fixes
Fixed wrong base address argument in FLEXCAN2 IRQ Handler.
Improvements
Add API to determine if the instance supports CAN FD mode at run time.
[2.10.1]
Bug Fixes
Fixed HIS CCM issue.
Fixed RTOS issue by adding protection to read-modify-write operations on interrupt enable/disable API.
[2.10.0]
Improvements
Update driver to make it able to support devices which has more than 64 8bytes MBs.
Update CAN FD transfer APIs to make them set/get edl bit according to frame content, which can make them compatible with classic CAN.
[2.9.2]
Bug Fixes
Fixed the issue that FLEXCAN_CheckUnhandleInterruptEvents() can’t detecting the exist enhanced RX FIFO interrupt status.
Fixed the issue that FLEXCAN_ReadPNWakeUpMB() does not return fail even no existing valid wake-up frame.
Fixed the issue that FLEXCAN_ReadEnhancedRxFifo() may clear bits other than the data available bit.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8.
Improvements
Return kStatus_FLEXCAN_RxFifoDisabled instead of kStatus_Fail when read FIFO fail during IRQ handler.
Remove unreachable code from timing calculates APIs.
Update Enhanced Rx FIFO handler to make it deal with underflow/overflow status first.
[2.9.1]
Bug Fixes
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoBlocking() API clearing Fifo data available flag more than once.
Fixed the issue that entering FLEXCAN_SubHandlerForEhancedRxFifo() even if Enhanced Rx fifo interrupts are not enabled.
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoEDMA() update handle even if previous Rx FIFO receive not finished.
Fixed the issue that FLEXCAN_SetEnhancedRxFifoConfig() not configure the ERFCR[NFE] bits to the correct value.
Fixed the issue that FLEXCAN_ReceiveFifoEDMACallback() can’t differentiate between Rx fifo and enhanced rx fifo.
Fixed the issue that FLEXCAN_TransferHandleIRQ() can’t report Legacy Rx FIFO warning status.
[2.9.0]
Improvements
Add public set bit rate API to make driver easier to use.
Update Legacy Rx FIFO transfer APIs to make it support received multiple frames during one API call.
Optimized FLEXCAN_SubHandlerForDataTransfered() API in interrupt handling to reduce the probability of packet loss.
[2.8.7]
Improvements
Initialized the EDMA configuration structure in the FLEXCAN EDMA driver.
[2.8.6]
Bug Fixes
Fix Coverity overrun issues in fsl_flexcan_edma driver.
[2.8.5]
Improvements
Make driver aarch64 compatible.
[2.8.4]
Bug Fixes
Fixed FlexCan_Errata_6032 to disable all interrupts.
[2.8.3]
Bug Fixes
Fixed an issue with the FLEXCAN_EnableInterrupts and FLEXCAN_DisableInterrupts interrupt enable bits in the CTRL1 register.
[2.8.2]
Bug Fixes
Fixed errors in timing calculations and simplify the calculation process.
Fixed issue of CBT and FDCBT register may write failure.
[2.8.1]
Bug Fixes
Fixed the issue of CAN FD three sampling points.
Added macro to support the devices that no MCR[SUPV] bit.
Remove unnecessary clear WMB operations.
[2.8.0]
Improvements
Update config configuration.
Added enableSupervisorMode member to support enable/disable Supervisor mode.
Simplified the algorithm in CAN FD improved timing APIs.
[2.7.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.7.
[2.7.0]
Improvements
Update config configuration.
Added enablePretendedeNetworking member to support enable/disable Pretended Networking feature.
Added enableTransceiverDelayMeasure member to support enable/disable Transceiver Delay MeasurementPretended feature.
Added bitRate/bitRateFD member to work as baudRate/baudRateFD member union.
Rename all “baud” in code or comments to “bit” to align with the CAN spec.
Added Pretended Networking mode related APIs.
FLEXCAN_SetPNConfig
FLEXCAN_GetPNMatchCount
FLEXCAN_ReadPNWakeUpMB
Added support for Enhanced Rx FIFO.
Removed independent memory error interrupt/status APIs and put all interrupt/status control operation into FLEXCAN_EnableInterrupts/FLEXCAN_DisableInterrupts and FLEXCAN_GetStatusFlags/FLEXCAN_ClearStatusFlags APIs.
Update improved timing APIs to make it calculate improved timing according to CiA doc recommended.
FLEXCAN_CalculateImprovedTimingValues.
FLEXCAN_FDCalculateImprovedTimingValues.
Update FLEXCAN_SetBitRate/FLEXCAN_SetFDBitRate to added the use of enhanced timing registers.
[2.6.2]
Improvements
Add CANFD frame data length enumeration.
[2.6.1]
Bug Fixes
Fixed the issue of not fully initializing memory in FLEXCAN_Reset() API.
[2.6.0]
Improvements
Enable CANFD ISO mode in FLEXCAN_FDInit API.
Enable the transceiver delay compensation feature when enable FD operation and set bitrate switch.
Implementation memory error control in FLEXCAN_Init API.
Improve FLEXCAN_FDCalculateImprovedTimingValues API to get same value for FPRESDIV and PRESDIV.
Added memory error configuration for user.
enableMemoryErrorControl
enableNonCorrectableErrorEnterFreeze
Added memory error related APIs.
FLEXCAN_GetMemoryErrorReportStatus
FLEXCAN_GetMemoryErrorStatusFlags
FLEXCAN_ClearMemoryErrorStatusFlags
FLEXCAN_EnableMemoryErrorInterrupts
FLEXCAN_DisableMemoryErrorInterrupts
Bug Fixes
Fixed the issue of sent duff CAN frame after call FLEXCAN_FDInit() API.
[2.5.2]
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
The bit field in CTRL1 register couldn’t calculate higher ideal SP, we set it as the lowest one(75%)
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
Fixed MISRA-C 2012 Rule 17.7 and 14.4.
Improvements
Pass EsrStatus to callback function when kStatus_FLEXCAN_ErrorStatus is comming.
[2.5.1]
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
[2.5.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-11.8, rule-12.2, rule-13.4, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-16.4, rule-17.3, rule-5.8, rule-8.3, rule-8.5.
Fixed the issue that API FLEXCAN_SetFDRxMbConfig lacks inactive message buff.
Fixed the issue of Pa082 warning.
Fixed the issue of dead lock in the function of interruption handler.
Fixed the issue of Legacy Rx Fifo EDMA transfer data fail in evkmimxrt1060 and evkmimxrt1064.
Fixed the issue of setting CANFD Bit Rate Switch.
Fixed the issue of operating unknown pointer risk.
when used the pointer “handle->mbFrameBuf[mbIdx]” to update the timestamp in a short-live TX frame, the frame pointer became as unknown, the action of operating it would result in program stack destroyed.
Added assert to check current CAN clock source affected by other clock gates in current device.
In some chips, CAN clock sources could be selected by CCM. But for some clock sources affected by other clock gates, if user insisted on using that clock source, they had to open these gates at the same time. However, they should take into consideration the power consumption issue at system level. In RT10xx chips, CAN clock source 2 was affected by the clock gate of lpuart1. ERRATA ID: (ERR050235 in CCM).
Improvements
Implementation for new FLEXCAN with ECC feature able to exit Freeze mode.
Optimized the function of interruption handler.
Added two APIs for FLEXCAN EDMA driver.
FLEXCAN_PrepareTransfConfiguration
FLEXCAN_StartTransferDatafromRxFIFO
Added new API for FLEXCAN driver.
FLEXCAN_GetTimeStamp
For TX non-blocking API, we wrote the frame into mailbox only, so no need to register TX frame address to the pointer, and the timestamp could be updated into the new global variable handle->timestamp[mbIdx], the FLEXCAN driver provided a new API for user to get it by handle and index number after TX DONE Success.
FLEXCAN_EnterFreezeMode
FLEXCAN_ExitFreezeMode
Added new configuration for user.
disableSelfReception
enableListenOnlyMode
Renamed the two clock source enum macros based on CLKSRC bit field value directly.
The CLKSRC bit value had no property about Oscillator or Peripheral type in lots of devices, it acted as two different clock input source only, but the legacy enum macros name contained such property, that misled user to select incorrect CAN clock source.
Created two new enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrc0
kFLEXCAN_ClkSrc1
Deprecated two legacy enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrcOsc
kFLEXCAN_ClkSrcPeri
Changed the process flow for Remote request frame response..
Created a new enum macro for the FLEXCAN driver.
kStatus_FLEXCAN_RxRemote
Changed the process flow for kFLEXCAN_StateRxRemote state in the interrupt handler.
Should the TX frame not register to the pointer of frame handle, interrupt handler would not be able to read the remote response frame from the mail box to ram, so user should read the frame by manual from mail box after a complete remote frame transfer.
[2.4.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-12.1, rule-17.7, rule-16.4, rule-11.9, rule-8.4, rule-14.4, rule-10.8, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-8.3, rule-12.2 and rule-16.1.
Fixed the issue that CANFD transfer data fail when bus baudrate is 30Khz.
Fixed the issue that ERR009595 does not folllow the ERRATA document.
Fixed code error for ERR006032 work around solution.
Fixed the Coverity issue of BAD_SHIFT in FLEXCAN.
Fixed the Repo build warning issue for variable without initial.
Improvements
Fixed the run fail issue of FlexCAN RemoteRequest UT Case.
Implementation all TX and RX transfering Timestamp used in FlexCAN demos.
Fixed the issue of UT Test Fail for CANFD payload size changed from 64BperMB to 8PerMB.
Implementation for improved timing API by baud rate.
[2.3.2]
Improvements
Implementation for ERR005959.
Implementation for ERR005829.
Implementation for ERR006032.
[2.3.1]
Bug Fixes
Added correct handle when kStatus_FLEXCAN_TxSwitchToRx is comming.
[2.3.0]
Improvements
Added self-wakeup support for STOP mode in the interrupt handling.
[2.2.3]
Bug Fixes
Fixed the issue of CANFD data phase’s bit rate not set as expected.
[2.2.2]
Improvements
Added a time stamp feature and enable it in the interrupt_transfer example.
[2.2.1]
Improvements
Separated CANFD initialization API.
In the interrupt handling, fix the issue that the user cannot use the normal CAN API when with an FD.
[2.2.0]
Improvements
Added FSL_FEATURE_FLEXCAN_HAS_SUPPORT_ENGINE_CLK_SEL_REMOVE feature to support SoCs without CAN Engine Clock selection in FlexCAN module.
Added FlexCAN Serial Clock Operation to support i.MX SoCs.
[2.1.0]
Bug Fixes
Corrected the spelling error in the function name FLEXCAN_XXX().
Moved Freeze Enable/Disable setting from FLEXCAN_Enter/ExitFreezeMode() to FLEXCAN_Init().
Corrected wrong helper macro values.
Improvements
Hid FLEXCAN_Reset() from user.
Used NDEBUG macro to wrap FLEXCAN_IsMbOccupied() function instead of DEBUG macro.
[2.0.0]
Initial version.
FLEXIO
[2.3.0]
Improvements
Supported platforms which don’t have DOZE mode control.
Added more pin control functions.
[2.2.3]
Improvements
Adapter the FLEXIO driver to platforms which don’t have system level interrupt controller, such as NVIC.
[2.2.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]
Improvements
Added doxygen index parameter comment in FLEXIO_SetClockMode.
[2.2.0]
New Features
Added new APIs to support FlexIO pin register.
[2.1.0]
Improvements
Added API FLEXIO_SetClockMode to set flexio channel counter and source clock.
[2.0.4]
Bug Fixes
Fixed MISRA 8.4 issues.
[2.0.3]
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.2]
Improvements
Split FLEXIO component which combines all flexio/flexio_uart/flexio_i2c/flexio_i2s drivers into several components: FlexIO component, flexio_uart component, flexio_i2c_master component, and flexio_i2s component.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.0.1]
Bug Fixes
Fixed the dozen mode configuration error in FLEXIO_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
FLEXIO_I2C
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Split some functions, fixed CCM problem in file fsl_flexio_i2c_master.c.
[2.4.0]
Improvements
Added delay of 1 clock cycle in FLEXIO_I2C_MasterTransferRunStateMachine to ensure that bus would be idle before next transfer if master is nacked.
Fixed issue that the restart setup time is less than the time in I2C spec by adding delay of 1 clock cycle before restart signal.
[2.3.0]
Improvements
Used 3 timers instead of 2 to support transfer which is more than 14 bytes in single transfer.
Improved FLEXIO_I2C_MasterTransferGetCount so that the API can check whether the transfer is still in progress.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Added an API for checking bus pin status.
Bug Fixes
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
Added codes in FLEXIO_I2C_MasterTransferCreateHandle to clear pending NVIC IRQ, disable internal IRQs before enabling NVIC IRQ.
Modified code so that during master’s nonblocking transfer the start and slave address are sent after interrupts being enabled, in order to avoid potential issue of sending the start and slave address twice.
[2.1.7]
Bug Fixes
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking did not wait for STOP bit sent.
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed the issue that I2C master did not check whether bus was busy before transfer.
[2.1.6]
Bug Fixes
Fixed the issue that I2C Master transfer APIs(blocking/non-blocking) did not support the situation of master transfer with subaddress and transfer data size being zero, which means no data followed the subaddress.
[2.1.5]
Improvements
Unified component full name to FLEXIO I2C Driver.
[2.1.4]
Bug Fixes
The following modifications support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.3]
Improvements
Changed the prototype of FLEXIO_I2C_MasterInit to return kStatus_Success if initialized successfully or to return kStatus_InvalidArgument if “(srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1” exceeds 0xFFU.
[2.1.2]
Bug Fixes
Fixed the FLEXIO I2C issue where the master could not receive data from I2C slave in high baudrate.
Fixed the FLEXIO I2C issue where the master could not receive NAK when master sent non-existent addr.
Fixed the FLEXIO I2C issue where the master could not get transfer count successfully.
Fixed the FLEXIO I2C issue where the master could not receive data successfully when sending data first.
Fixed the Dozen mode configuration error in FLEXIO_I2C_MasterInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking API called FLEXIO_I2C_MasterTransferCreateHandle, which lead to the s_flexioHandle/s_flexioIsr/s_flexioType variable being written. Then, if calling FLEXIO_I2C_MasterTransferBlocking API multiple times, the s_flexioHandle/s_flexioIsr/s_flexioType variable would not be written any more due to it being out of range. This lead to the following situation: NonBlocking transfer APIs could not work due to the fail of register IRQ.
[2.1.1]
Bug Fixes
Implemented the FLEXIO_I2C_MasterTransferBlocking API which is defined in header file but has no implementation in the C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S
[2.2.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed violations of the MISRA C-2012 rules 10.4, 14.4, 11.8, 11.9, 10.1, 17.7, 11.6, 10.3, 10.7.
[2.1.6]
Bug Fixes
Added reset flexio before flexio i2s init to make sure flexio status is normal.
[2.1.5]
Bug Fixes
Fixed the issue that I2S driver used hard code for bitwidth setting.
[2.1.4]
Improvements
Unified component’s full name to FLEXIO I2S (DMA/EDMA) driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
New Features
Added configure items for all pin polarity and data valid polarity.
Added default configure for pin polarity and data valid polarity.
[2.1.1]
Bug Fixes
Fixed FlexIO I2S RX data read error and eDMA address error.
Fixed FlexIO I2S slave timer compare setting error.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S_EDMA
[2.1.8]
Improvements
Applied EDMA ERRATA 51327.
FLEXIO_SPI
[2.4.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.3.5]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.4]
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.3]
Bugfixes
Fixed cs-continuous mode.
[2.3.2]
Improvements
Changed FLEXIO_SPI_DUMMYDATA to 0x00.
[2.3.1]
Bugfixes
Fixed IRQ SHIFTBUF overrun issue when one FLEXIO instance used as multiple SPIs.
[2.3.0]
New Features
Supported FLEXIO_SPI slave transfer with continuous master CS signal and CPHA=0.
Supported FLEXIO_SPI master transfer with continuous CS signal.
Support 32 bit transfer width.
Bug Fixes
Fixed wrong timer compare configuration for dma/edma transfer.
Fixed wrong byte order of rx data if transfer width is 16 bit, since the we use shifter buffer bit swapped/byte swapped register to read in received data, so the high byte should be read from the high bits of the register when MSB.
[2.2.1]
Bug Fixes
Fixed bug in FLEXIO_SPI_MasterTransferAbortEDMA that when aborting EDMA transfer EDMA_AbortTransfer should be used rather than EDMA_StopTransfer.
[2.2.0]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
Added codes in FLEXIO_SPI_MasterTransferCreateHandle and FLEXIO_SPI_SlaveTransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.1.3]
Improvements
Unified component full name to FLEXIO SPI(DMA/EDMA) Driver.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.2]
Bug Fixes
The following modification support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.1]
Bug Fixes
Fixed bug where FLEXIO SPI transfer data is in 16 bit per frame mode with eDMA.
Fixed bug when FLEXIO SPI works in eDMA and interrupt mode with 16-bit per frame and Lsbfirst.
Fixed the Dozen mode configuration error in FLEXIO_SPI_MasterInit/FLEXIO_SPI_SlaveInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Improvements
Added #ifndef/#endif to allow users to change the default TX value at compile time.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
Bug Fixes
Fixed the error register address return for 16-bit data write in FLEXIO_SPI_GetTxDataRegisterAddress.
Provided independent IRQHandler/transfer APIs for Master and slave to fix the baudrate limit issue.
FLEXIO_UART
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Added API FLEXIO_UART_FlushShifters to flush UART fifo.
[2.4.0]
Improvements
Use separate data for TX and RX in flexio_uart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling FLEXIO_UART_TransferReceiveNonBlocking, the received data count returned by FLEXIO_UART_TransferGetReceiveCount is wrong.
[2.3.0]
Improvements
Added check for baud rate’s accuracy that returns kStatus_FLEXIO_UART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
Bug Fixes
Added codes in FLEXIO_UART_TransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.2.0]
Improvements
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.1.6]
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.5]
Improvements
Triggered user callback after all the data in ringbuffer were received in FLEXIO_UART_TransferReceiveNonBlocking.
[2.1.4]
Improvements
Unified component full name to FLEXIO UART(DMA/EDMA) Driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
Bug Fixes
Fixed the transfer count calculation issue in FLEXIO_UART_TransferGetReceiveCount, FLEXIO_UART_TransferGetSendCount, FLEXIO_UART_TransferGetReceiveCountDMA, FLEXIO_UART_TransferGetSendCountDMA, FLEXIO_UART_TransferGetReceiveCountEDMA and FLEXIO_UART_TransferGetSendCountEDMA.
Fixed the Dozen mode configuration error in FLEXIO_UART_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Added code to report errors if the user sets a too-low-baudrate which FLEXIO cannot reach.
Disabled FLEXIO_UART receive interrupt instead of all NVICs when reading data from ring buffer. If ring buffer is used, receive nonblocking will disable all NVIC interrupts to protect the ring buffer. This had negative effects on other IPs using interrupt.
[2.1.1]
Bug Fixes
Changed the API name FLEXIO_UART_StopRingBuffer to FLEXIO_UART_TransferStopRingBuffer to align with the definition in C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added txSize/rxSize in handle structure to record the transfer size.
Bug Fixes
Added an error handle to handle the situation that data count is zero or data buffer is NULL.
FLEXIO_UART_EDMA
[2.3.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.3.0]
Refer FLEXIO_UART driver change log to 2.3.0
FLEXRAM
[2.3.0]
New Features
Supported platforms which have ECC but no ECC error injection.
[2.2.0]
New Features
Supported flexram ECC error injection function.
[2.1.0]
New Features
Supported flexram ECC function.
[2.0.7]
Bug Fixes
Fixed doxygen issue.
[2.0.6]
New Features
Updated bank configuration and TCM size with GPR16/GPR17/GPR18 into SOC level for different SOC.
[2.0.5]
New Features
Added the magic address feature for OCRAM, DTCM and ITCM.
[2.0.4]
Bug Fixes
Fixed FlexRAM driver’s missing extern C around functions in header file.
Removed magic address feature from driver.
[2.0.3]
Bug Fixes
Fixed the issue that TCM size configuration was wrong when TCM bank number was not a value power of 2.
[2.0.2]
Bug Fixes
Updated driver due to Reference Manual update.
[2.0.1]
Bug Fixes
Fixed MISRA issue.
[2.0.0]
Initial version.
FLEXSPI
[2.6.3]
Bug Fixes
Fixed an issue which cause IPCR1[IPAREN] cleared by mistake.
[2.6.2]
Bug Fixes
Wait Bus IDLE before operation of FLEXSPI_SoftwareReset(), FLEXSPI_TransferBlocking() and FLEXSPI_TransferNonBlocking().
[2.6.1]
Bug Fixes
Updated code of reset peripheral.
Updated FLEXSPI_UpdateLUT() to check if input lut address is not in Flexspi AMBA region.
Updated FLEXSPI_Init() to check if input AHB buffer size exceeded maximum AHB size.
[2.6.0]
New Features
Added new API to set AHB memory-mapped flash base address.
Added support of DLLxCR[REFPHASEGAP] bit field, it is recommended to set it as 0x2 if DLL calibration is enabled.
[2.5.1]
Bugfixes
Fixed handling of W1C bits in the INTR register
Removed FIFO resets from FLEXSPI_CheckAndClearError
FLEXSPI_TransferBlocking is observing IPCMDDONE and then fetches the final status of the transfer
Fixed issue that FLEXSPI2_DriverIRQHandler not defined.
[2.5.0]
Improvements
Supported word un-aligned access for write/read blocking/non-blocking API functions.
Fixed dead loop issue in DLL update function when using FRO clock source.
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.4.0]
Improvements
Isolated IP command parallel mode and AHB command parallel mode using feature MACRO.
Supported new column address shift feature for external memory.
[2.3.5]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.2.
[2.3.4]
Bug Fixes
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_CONBINATION.
[2.3.3]
Bug Fixes
Removed feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS for DLL delay setting. Changed to use feature FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN to set slave delay target as 0 for DLL enable and clock frequency higher than 100MHz.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 8.4, 8.5, 10.1, 10.3, 10.4, 11.6 and 14.4.
[2.3.1]
Bug Fixes
Wait for bus to be idle before using it as access to external flash with new setting in FLEXSPI_SetFlashConfig() API.
Fixed the potential buffer overread and Tx FIFO overwrite issue in FLEXSPI_WriteBlocking.
[2.3.0]
New Features
Added new API FLEXSPI_UpdateDllValue for users to update DLL value after updating flexspi root clock.
Corrected grammatical issues for comments.
Added support for new feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS in DLL configuration.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3 and 10.4.
Updated _flexspi_command from named enumerator into anonymous enumerator.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8, 11.9, 14.4, 15.7, 16.4, 17.7, 7.3.
Fixed IAR build warning Pe167.
Fixed the potential buffer overwrite and Rx FIFO overread issue in FLEXSPI_ReadBlocking.
[2.2.0]
Bug Fixes
Fixed flag name typos: kFLEXSPI_IpTxFifoWatermarkEmpltyFlag to kFLEXSPI_IpTxFifoWatermarkEmptyFlag; kFLEXSPI_IpCommandExcutionDoneFlag to kFLEXSPI_IpCommandExecutionDoneFlag.
Fixed comments typos such as sequencen->sequence, levle->level.
Fixed FLSHCR2[ARDSEQID] field clean issue.
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN and FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN.
Updated flexspi_flags_t structure to support new feature FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN.
[2.1.1]
Improvements
Defaulted enable prefetch for AHB RX buffer configuration in FLEXSPI_GetDefaultConfig, which is align with the reset value in AHBRXBUFxCR0.
Added software workaround for ERR011377 in FLEXSPI_SetFlashConfig; added some delay after DLL lock status set to ensure correct data read/write.
[2.1.0]
New Features
Added new API FLEXSPI_UpdateRxSampleClock for users to update read sample clock source after initialization.
Added reset peripheral operation in FLEXSPI_Init if required.
[2.0.5]
Bug Fixes
Fixed FLEXSPI_UpdateLUT cannot do partial update issue.
[2.0.4]
Bug Fixes
Reset flash size to zero for all ports in FLEXSPI_Init; fixed the possible out-of-range flash access with no error reported.
[2.0.3]
Bug Fixes
Fixed AHB receive buffer size configuration issue. The FLEXSPI_AHBRXBUFCR0_BUFSZ field should configure 64 bits size, and currently the AHB receive buffer size is in bytes which means 8-bit, so the correct configuration should be config->ahbConfig.buffer[i].bufferSize / 8.
[2.0.2]
New Features
Supported DQS write mask enable/disable feature during set FLEXSPI configuration.
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
Bug Fixes
Fixed invalid operation of FLEXSPI_Init to enable AHB bus Read Access to IP RX FIFO.
Fixed incorrect operation of FLEXSPI_Init to configure IP TX FIFO watermark.
[2.0.1]
Bug Fixes
Fixed the flag clear issue and AHB read Command index configuration issue in FLEXSPI_SetFlashConfig.
Updated FLEXSPI_UpdateLUT function to update LUT table from any index instead of previous command index.
Added bus idle wait in FLEXSPI_SetFlashConfig and FLEXSPI_UpdateLUT to ensure bus is idle before any change to FlexSPI controller.
Updated interrupt API FLEXSPI_TransferNonBlocking and interrupt handle flow FLEXSPI_TransferHandleIRQ.
Updated eDMA API FLEXSPI_TransferEDMA.
[2.0.0]
Initial version.
FLEXSPI EDMA Driver
[2.3.3]
Bug Fixes
Fixed FLEXSPI_TransferEDMA bug that, the DMA channel not configured correctly when using kFLEXSPI_Read.
[2.3.2]
Bug Fixes
Fixed the bug that internal variable s_edmaPrivateHandle overflows when using FlexSPI2.
[2.0.2]
New Features
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
[2.0.0]
Initial version.
GPC
[2.1.1]
Bug Fixes
Moved the assert sentence that irq register number has to be greater than 0 to platforms which irq 0-31 is not available.
Fixed the violations of MISRA C-2012 rules:
Rule 10.7 12.2.
[2.1.0]
Improvements
Updated driver for IMXRT.
[2.0.0]
Initial version.
GPIO
[2.0.6]
Bug Fixes
Fixed compile warning: ‘GPIO_GetInstance’ defined but not used when macro FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is defined.
[2.0.5]
Bug Fixes
Fixed MISRA C-2012 issue: rule-17.7.
[2.0.4]
Improvements
Updated the GPIO_PinWrite to use atomic operation if possible.
Bug Fixes
Fixed GPIO_PortToggle bug with platforms don’t have register DR_TOGGLE.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rules, containing: rule-10.3, rule-14.4, and rule-15.5.
[2.0.2]
Bug Fixes
Fixed the bug of enabling wrong GPIO clock gate in initial API. Since some GPIO instances may not have a clock gate enabled, it checks the clock gate number and makes sure the clock gate is valid.
[2.0.1]
Improvements
API interface changes:
Refined naming of the API while keeping all original APIs, marking them as deprecated. Original APIs will be removed in next release. The main change is to update the API with prefix of _PinXXX() and _PortXXX().
[2.0.0]
Initial version.
GPT
[2.0.5]
Improvements
Support workaround for ERR003777. This workaround helps switching the clock sources.
[2.0.4]
Bug Fixes
Fixed compiler warning when built with FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL flag enabled.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 5.3 by customizing function parameter.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.8, 17.7.
[2.0.0]
Initial version.
IOMUXC
[2.0.1]
Doxygen improvement.
[2.0.0]
initial version.
KPP
[2.0.1]
Bug Fixes
Fixed the violations of MISRA 2012 rules:
Rule 10.3 10.4 10.6 14.4 17.7
[2.0.0]
Initial version.
LPI2C
[2.5.7]
Improvements
Added support for separated IRQ handlers.
[2.5.6]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.5]
Bug Fixes
Fixed LPI2C_SlaveInit() - allow to disable SDA/SCL glitch filter.
[2.5.4]
Bug Fixes
Fixed LPI2C_MasterTransferBlocking() - the return value was sometime affected by call of LPI2C_MasterStop().
[2.5.3]
Improvements
Added handler for LPI2C7 and LPI2C8.
[2.5.2]
Bug Fixes
Fixed ERR051119 to ignore the nak flag when IGNACK=1 in LPI2C_MasterCheckAndClearError.
[2.5.1]
Bug Fixes
Added bus stop incase of bus stall in LPI2C_MasterTransferBlocking.
Improvements
Release peripheral from reset if necessary in init function.
[2.5.0]
New Features
Added new function LPI2C_SlaveEnableAckStall to enable or disable ACKSTALL.
[2.4.1]
Improvements
Before master transfer with transactional APIs, enable master function while disable slave function and vise versa for slave transfer to avoid the one affecting the other.
[2.4.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpi2c.c.
Bug Fixes
Fixed bug in LPI2C_MasterInit that the MCFGR2’s value set in LPI2C_MasterSetBaudRate may be overwritten by mistake.
[2.3.2]
Improvements
Initialized the EDMA configuration structure in the LPI2C EDMA driver.
[2.3.1]
Improvements
Updated LPI2C_GetCyclesForWidth to add the parameter of minimum cycle, because for master SDA/SCL filter, master bus idle/pin low timeout and slave SDA/SCL filter configuration, 0 means disabling the feature and cannot be used.
Bug Fixes
Fixed bug in LPI2C_SlaveTransferHandleIRQ that when restart detect event happens the transfer structure should not be cleared.
Fixed bug in LPI2C_RunTransferStateMachine, that when only slave address is transferred or there is still data remaining in tx FIFO the last byte’s nack cannot be ignored.
Fixed bug in slave filter doze enable, that when FILTDZ is set it means disable rather than enable.
Fixed bug in the usage of LPI2C_GetCyclesForWidth. First its return value cannot be used directly to configure the slave FILTSDA, FILTSCL, DATAVD or CLKHOLD, because the real cycle width for them should be FILTSDA+3, FILTSCL+3, FILTSCL+DATAVD+3 and CLKHOLD+3. Second when cycle period is not affected by the prescaler value, prescaler value should be passed as 0 rather than 1.
Fixed wrong default setting for LPI2C slave. If enabling the slave tx SCL stall, then the default clock hold time should be set to 250ns according to I2C spec for 100kHz standard mode baudrate.
Fixed bug that before pushing command to the tx FIFO the FIFO occupation should be checked first in case FIFO overflow.
[2.3.0]
New Features
Supported reading more than 256 bytes of data in one transfer as master.
Added API LPI2C_GetInstance.
Bug Fixes
Fixed bug in LPI2C_MasterTransferAbortEDMA, LPI2C_MasterTransferAbort and LPI2C_MasterTransferHandleIRQ that before sending stop signal whether master is active and whether stop signal has been sent should be checked, to make sure no FIFO error or bus error will be caused.
Fixed bug in LPI2C master EDMA transactional layer that the bus error cannot be caught and returned by user callback, by monitoring bus error events in interrupt handler.
Fixed bug in LPI2C_GetCyclesForWidth that the parameter used to calculate clock cycle should be 2^prescaler rather than prescaler.
Fixed bug in LPI2C_MasterInit that timeout value should be configured after baudrate, since the timeout calculation needs prescaler as parameter which is changed during baudrate configuration.
Fixed bug in LPI2C_MasterTransferHandleIRQ and LPI2C_RunTransferStateMachine that when master writes with no stop signal, need to first make sure no data remains in the tx FIFO before finishes the transfer.
[2.2.0]
Bug Fixes
Fixed issue that the SCL high time, start hold time and stop setup time do not meet I2C specification, by changing the configuration of data valid delay, setup hold delay, clock high and low parameters.
MISRA C-2012 issue fixed.
Fixed rule 8.4, 13.5, 17.7, 20.8.
[2.1.12]
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.1.11]
Bug Fixes
Fixed the bug that, during master non-blocking transfer, after the last byte is sent/received, the kLPI2C_MasterNackDetectFlag is expected, so master should not check and clear kLPI2C_MasterNackDetectFlag when remainingBytes is zero, in case FIFO is emptied when stop command has not been sent yet.
Fixed the bug that, during non-blocking transfer slave may nack master while master is busy filling tx FIFO, and NDF may not be handled properly.
[2.1.10]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rule 10.3, 14.4, 15.5.
Fixed unaligned access issue in LPI2C_RunTransferStateMachine.
Fixed uninitialized variable issue in LPI2C_MasterTransferHandleIRQ.
Used linked TCD to disable tx and enable rx in read operation to fix the issue that for platform sharing the same DMA request with tx and rx, during LPI2C read operation if interrupt with higher priority happened exactly after command was sent and before tx disabled, potentially both tx and rx could trigger dma and cause trouble.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 11.6, 11.9, 14.4, 17.7.
Fixed the waitTimes variable not re-assignment issue for each byte read.
New Features
Added the IRQHandler for LPI2C5 and LPI2C6 instances.
Improvements
Updated the LPI2C_WAIT_TIMEOUT macro to unified name I2C_RETRY_TIMES.
[2.1.9]
Bug Fixes
Fixed Coverity issue of unchecked return value in I2C_RTOS_Transfer.
Fixed Coverity issue of operands did not affect the result in LPI2C_SlaveReceive and LPI2C_SlaveSend.
Removed STOP signal wait when NAK detected.
Cleared slave repeat start flag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved repeat start flag. This caused the next slave to send a break, and the master was always in the receive data status, but could not receive data.
[2.1.8]
Bug Fixes
Fixed the transfer issue with LPI2C_MasterTransferNonBlocking, kLPI2C_TransferNoStopFlag, with the wait transfer done through callback in a way of not doing a blocking transfer.
Fixed the issue that STOP signal did not appear in the bus when NAK event occurred.
[2.1.7]
Bug Fixes
Cleared the stopflag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved stop flag and caused the next slave to send a break, and the master always stayed in the receive data status but could not receive data.
[2.1.6]
Bug Fixes
Fixed driver MISRA build error and C++ build error in LPI2C_MasterSend and LPI2C_SlaveSend.
Reset FIFO in LPI2C Master Transfer functions to avoid any byte still remaining in FIFO during last transfer.
Fixed the issue that LPI2C_MasterStop did not return the correct NAK status in the bus for second transfer to the non-existing slave address.
[2.1.5]
Bug Fixes
Extended the Driver IRQ handler to support LPI2C4.
Changed to use ARRAY_SIZE(kLpi2cBases) instead of FEATURE COUNT to decide the array size for handle pointer array.
[2.1.4]
Bug Fixes
Fixed the LPI2C_MasterTransferEDMA receive issue when LPI2C shared same request source with TX/RX DMA request. Previously, the API used scatter-gather method, which handled the command transfer first, then the linked TCD which was pre-set with the receive data transfer. The issue was that the TX DMA request and the RX DMA request were both enabled, so when the DMA finished the first command TCD transfer and handled the receive data TCD, the TX DMA request still happened due to empty TX FIFO. The result was that the RX DMA transfer would start without waiting on the expected RX DMA request.
Fixed the issue by enabling IntMajor interrupt for the command TCD and checking if there was a linked TCD to disable the TX DMA request in LPI2C_MasterEDMACallback API.
[2.1.3]
Improvements
Added LPI2C_WATI_TIMEOUT macro to allow the user to specify the timeout times for waiting flags in functional API and blocking transfer API.
Added LPI2C_MasterTransferBlocking API.
[2.1.2]
Bug Fixes
In LPI2C_SlaveTransferHandleIRQ, reset the slave status to idle when stop flag was detected.
[2.1.1]
Bug Fixes
Disabled the auto-stop feature in eDMA driver. Previously, the auto-stop feature was enabled at transfer when transferring with stop flag. Since transfer was without stop flag and the auto-stop feature was enabled, when starting a new transfer with stop flag, the stop flag would be sent before the new transfer started, causing unsuccesful sending of the start flag, so the transfer could not start.
Changed default slave configuration with address stall false.
[2.1.0]
Improvements
API name changed:
LPI2C_MasterTransferCreateHandle -> LPI2C_MasterCreateHandle.
LPI2C_MasterTransferGetCount -> LPI2C_MasterGetTransferCount.
LPI2C_MasterTransferAbort -> LPI2C_MasterAbortTransfer.
LPI2C_MasterTransferHandleIRQ -> LPI2C_MasterHandleInterrupt.
LPI2C_SlaveTransferCreateHandle -> LPI2C_SlaveCreateHandle.
LPI2C_SlaveTransferGetCount -> LPI2C_SlaveGetTransferCount.
LPI2C_SlaveTransferAbort -> LPI2C_SlaveAbortTransfer.
LPI2C_SlaveTransferHandleIRQ -> LPI2C_SlaveHandleInterrupt.
[2.0.0]
Initial version.
LPI2C_EDMA
[2.4.3]
Improvements
Added support for separated IRQ handlers.
[2.4.2]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.1]
Refer LPI2C driver change log 2.0.0 to 2.4.1
LPSPI
[2.6.10]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.6.9]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.6.8]
Bug Fixes
Fixed build error when SPI_RETRY_TIMES is defined to non-zero value.
[2.6.7]
Bug Fixes
Fixed the txData from void * to const void * in transmit API _lpspi_master_handle and _lpspi_slave_handle.
[2.6.6]
Bug Fixes
Added LPSPI register init in LPSPI_MasterInit incase of LPSPI register exist.
[2.6.5]
Improvements
Introduced FSL_FEATURE_LPSPI_HAS_NO_PCSCFG and FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH for conditional compile.
Release peripheral from reset if necessary in init function.
[2.6.4]
Bug Fixes
Added LPSPI6_DriverIRQHandler for LPSPI6 instance.
[2.6.3]
Hot Fixes
Added macro switch in function LPSPI_Enable about ERRATA051472.
[2.6.2]
Bug Fixes
Disabled lpspi before LPSPI_MasterSetBaudRate incase of LPSPI opened.
[2.6.1]
Bug Fixes
Fixed return value while calling LPSPI_WaitTxFifoEmpty in function LPSPI_MasterTransferNonBlocking.
[2.6.0]
Feature
Added the new feature of multi-IO SPI .
[2.5.3]
Bug Fixes
Fixed 3-wire txmask of handle vaule reentrant issue.
[2.5.2]
Bug Fixes
Workaround for errata ERR051588 by clearing FIFO after transmit underrun occurs.
[2.5.1]
Bug Fixes
Workaround for errata ERR050456 by resetting the entire module using LPSPIn_CR[RST] bit.
[2.5.0]
Bug Fixes
Workaround for errata ERR011097 to wait the TX FIFO to go empty when writing TCR register and TCR[TXMSK] value is 1.
Added API LPSPI_WaitTxFifoEmpty for wait the txfifo to go empty.
[2.4.7]
Bug Fixes
Fixed bug that the SR[REF] would assert if software disabled or enabled the LPSPI module in LPSPI_Enable.
[2.4.6]
Improvements
Moved the configuration of registers for the 3-wire lpspi mode to the LPSPI_MasterInit and LPSPI_SlaveInit function.
[2.4.5]
Improvements
Improved LPSPI_MasterTransferBlocking send performance when frame size is 1-byte.
[2.4.4]
Bug Fixes
Fixed LPSPI_MasterGetDefaultConfig incorrect default inter-transfer delay calculation.
[2.4.3]
Bug Fixes
Fixed bug that the ISR response speed is too slow on some platforms, resulting in the first transmission of overflow, Set proper RX watermarks to reduce the ISR response times.
[2.4.2]
Bug Fixes
Fixed bug that LPSPI_MasterTransferBlocking will modify the parameter txbuff and rxbuff pointer.
[2.4.1]
Bug Fixes
Fixed bug that LPSPI_SlaveTransferNonBlocking can’t detect RX error.
[2.4.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpspi.c.
[2.3.1]
Improvements
Initialized the EDMA configuration structure in the LPSPI EDMA driver.
Bug Fixes
Fixed bug that function LPSPI_MasterTransferBlocking should return after the transfer complete flag is set to make sure the PCS is re-asserted.
[2.3.0]
New Features
Supported the master configuration of sampling the input data using a delayed clock to improve slave setup time.
[2.2.1]
Bug Fixes
Fixed bug in LPSPI_SetPCSContinous when disabling PCS continous mode.
[2.2.0]
Bug Fixes
Fixed bug in 3-wire polling and interrupt transfer that the received data is not correct and the PCS continous mode is not working.
[2.1.0]
Improvements
Improved LPSPI_SlaveTransferHandleIRQ to fill up TX FIFO instead of write one data to TX register which improves the slave transmit performance.
Added new functional APIs LPSPI_SelectTransferPCS and LPSPI_SetPCSContinous to support changing PCS selection and PCS continous mode.
Bug Fixes
Fixed bug in non-blocking and EDMA transfer APIs that kStatus_InvalidArgument is returned if user configures 3-wire mode and full-duplex transfer at the same time, but transfer state is already set to kLPSPI_Busy by mistake causing following transfer can not start.
Fixed bug when LPSPI slave using EDMA way to transfer, tx should be masked when tx data is null, otherwise in 3-wire mode which tx/rx use the same pin, the received data will be interfered.
[2.0.5]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed the bug that LPSPI can not transfer large data using EDMA.
Fixed MISRA 17.7 issues.
Fixed variable overflow issue introduced by MISRA fix.
Fixed issue that rxFifoMaxBytes should be calculated according to transfer width rather than FIFO width.
Fixed issue that completion flag was not cleared after transfer completed.
[2.0.4]
Bug Fixes
Fixed in LPSPI_MasterTransferBlocking that master rxfifo may overflow in stall condition.
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.6, 11.9, 14.2, 14.4, 15.7, 17.7.
[2.0.3]
Bug Fixes
Removed LPSPI_Reset from LPSPI_MasterInit and LPSPI_SlaveInit, because this API may glitch the slave select line. If needed, call this function manually.
[2.0.2]
New Features
Added dummy data set up API to allow users to configure the dummy data to be transferred.
Enabled the 3-wire mode, SIN and SOUT pins can be configured as input/output pin.
[2.0.1]
Bug Fixes
Fixed the bug that the clock source should be divided by the PRESCALE setting in LPSPI_MasterSetDelayTimes function.
Fixed the bug that LPSPI_MasterTransferBlocking function would hang in some corner cases.
Optimization
Added #ifndef/#endif to allow user to change the default TX value at compile time.
[2.0.0]
Initial version.
LPSPI_EDMA
[2.4.6]
Improvements
Increased transmit FIFO watermark to ensure whole transmit FIFO will be used during data transfer.
[2.4.5]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.4.4]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.3]
Improvements
Supported 32K bytes transmit in DMA, improve the max datasize in LPSPI_MasterTransferEDMALite.
[2.4.2]
Improvements
Added callback status in EDMA_LpspiMasterCallback and EDMA_LpspiSlaveCallback to check transferDone.
[2.4.1]
Improvements
Add the TXMSK wait after TCR setting.
[2.4.0]
Improvements
Separated LPSPI_MasterTransferEDMA functions to LPSPI_MasterTransferPrepareEDMA and LPSPI_MasterTransferEDMALite to optimize the process of transfer.
LPUART
[2.9.0]
New Feature
Added support for swap TXD and RXD pins.
[2.8.3]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.8.2]
Bug Fix
Fixed the bug that LPUART_TransferEnable16Bit controled by wrong feature macro.
[2.8.1]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-5.3, rule-5.8, rule-10.4, rule-11.3, rule-11.8.
[2.8.0]
Improvements
Added support of DATA register for 9bit or 10bit data transmit in write and read API. Such as: LPUART_WriteBlocking16bit, LPUART_ReadBlocking16bit, LPUART_TransferEnable16Bit LPUART_WriteNonBlocking16bit, LPUART_ReadNonBlocking16bit.
[2.7.7]
Bug Fixes
Fixed the bug that baud rate calculation overflow when srcClock_Hz is 528MHz.
[2.7.6]
Bug Fixes
Fixed LPUART_EnableInterrupts and LPUART_DisableInterrupts bug that blocks if the LPUART address doesn’t support exclusive access.
[2.7.5]
Improvements
Release peripheral from reset if necessary in init function.
[2.7.4]
Improvements
Added support for atomic register accessing in LPUART_EnableInterrupts and LPUART_DisableInterrupts.
[2.7.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 15.7.
[2.7.2]
Bug Fix
Fixed the bug that the OSR calculation error when lupart init and lpuart set baud rate.
[2.7.1]
Improvements
Added support for LPUART_BASE_PTRS_NS in security mode in file fsl_lpuart.c.
[2.7.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpuart.c.
[2.6.0]
Bug Fixes
Fixed bug that when there are multiple lpuart instance, unable to support different ISR.
[2.5.3]
Bug Fixes
Fixed comments by replacing unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag with kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag.
[2.5.2]
Bug Fixes
Fixed bug that when setting watermark for TX or RX FIFO, the value may exceed the maximum limit.
Improvements
Added check in LPUART_TransferDMAHandleIRQ and LPUART_TransferEdmaHandleIRQ to ensure if user enables any interrupts other than transfer complete interrupt, the dma transfer is not terminated by mistake.
[2.5.1]
Improvements
Use separate data for TX and RX in lpuart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling LPUART_TransferReceiveNonBlocking, the received data count returned by LPUART_TransferGetReceiveCount is wrong.
[2.5.0]
Bug Fixes
Added missing interrupt enable masks kLPUART_Match1InterruptEnable and kLPUART_Match2InterruptEnable.
Fixed bug in LPUART_EnableInterrupts, LPUART_DisableInterrupts and LPUART_GetEnabledInterrupts that the BAUD[LBKDIE] bit field should be soc specific.
Fixed bug in LPUART_TransferHandleIRQ that idle line interrupt should be disabled when rx data size is zero.
Deleted unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag, since firstly their function are the same as kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag, secondly to obtain them one data word must be read out thus interfering with the receiving process.
Fixed bug in LPUART_GetStatusFlags that the STAT[LBKDIF], STAT[MA1F] and STAT[MA2F] should be soc specific.
Fixed bug in LPUART_ClearStatusFlags that tx/rx FIFO is reset by mistake when clearing flags.
Fixed bug in LPUART_TransferHandleIRQ that while clearing idle line flag the other bits should be masked in case other status bits be cleared by accident.
Fixed bug of race condition during LPUART transfer using transactional APIs, by disabling and re-enabling the global interrupt before and after critical operations on interrupt enable register.
Fixed DMA/eDMA transfer blocking issue by enabling tx idle interrupt after DMA/eDMA transmission finishes.
New Features
Added APIs LPUART_GetRxFifoCount/LPUART_GetTxFifoCount to get rx/tx FIFO data count.
Added APIs LPUART_SetRxFifoWatermark/LPUART_SetTxFifoWatermark to set rx/tx FIFO water mark.
[2.4.1]
Bug Fixes
Fixed MISRA advisory 17.7 issues.
[2.4.0]
New Features
Added APIs to configure 9-bit data mode, set slave address and send address.
[2.3.1]
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.3.0]
Improvements
Modified LPUART_TransferHandleIRQ so that txState will be set to idle only when all data has been sent out to bus.
Modified LPUART_TransferGetSendCount so that this API returns the real byte count that LPUART has sent out rather than the software buffer status.
Added timeout mechanism when waiting for certain states in transfer driver.
[2.2.8]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-10.3, rule-14.4, rule-15.5.
Eliminated Pa082 warnings by assigning volatile variables to local variables and using local variables instead.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.8, 14.4, 11.6, 17.7.
Improvements
Added check for kLPUART_TransmissionCompleteFlag in LPUART_WriteBlocking, LPUART_TransferHandleIRQ, LPUART_TransferSendDMACallback and LPUART_SendEDMACallback to ensure all the data would be sent out to bus.
Rounded up the calculated sbr value in LPUART_SetBaudRate and LPUART_Init to achieve more acurate baudrate setting. Changed osr from uint32_t to uint8_t since osr’s bigest value is 31.
Modified LPUART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.
[2.2.7]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-12.1, rule-17.7, rule-14.4, rule-13.3, rule-14.4, rule-10.4, rule-10.8, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-13.2, rule-8.3.
[2.2.6]
Bug Fixes
Fixed the issue of register’s being in repeated reading status while dealing with the IRQ routine.
[2.2.5]
Bug Fixes
Do not set or clear the TIE/RIE bits when using LPUART_EnableTxDMA and LPUART_EnableRxDMA.
[2.2.4]
Improvements
Added hardware flow control function support.
Added idle-line-detecting feature in LPUART_TransferNonBlocking function. If an idle line is detected, a callback is triggered with status kStatus_LPUART_IdleLineDetected returned. This feature may be useful when the received Bytes is less than the expected received data size. Before triggering the callback, data in the FIFO (if has FIFO) is read out, and no interrupt will be disabled, except for that the receive data size reaches 0.
Enabled the RX FIFO watermark function. With the idle-line-detecting feature enabled, users can set the watermark value to whatever you want (should be less than the RX FIFO size). Data is received and a callback will be triggered when data receive ends.
[2.2.3]
Improvements
Changed parameter type in LPUART_RTOS_Init struct from rtos_lpuart_config to lpuart_rtos_config_t.
Bug Fixes
Disabled LPUART receive interrupt instead of all NVICs when reading data from ring buffer. Otherwise when the ring buffer is used, receive nonblocking method will disable all NVICs to protect the ring buffer. This may has a negative effect on other IPs that are using the interrupt.
[2.2.2]
Improvements
Added software reset feature support.
Added software reset API in LPUART_Init.
[2.2.1]
Improvements
Added separate RX/TX IRQ number support.
[2.2.0]
Improvements
Added support of 7 data bits and MSB.
[2.1.1]
Improvements
Removed unnecessary check of event flags and assert in LPUART_RTOS_Receive.
Added code to always wait for RX event flag in LPUART_RTOS_Receive.
[2.1.0]
Improvements
Update transactional APIs.
LPUART_EDMA
[2.4.0]
Refer LPUART driver change log 2.1.0 to 2.4.0
OCOTP
[2.1.4]
Bug fixes
Fixed the bug that OCOTP_ReadFuseShadowRegisterExt can’t read more than one word.
[2.1.3]
Bug fixes
Fixed MISRA 2012 issue: 8.4, 10.3, 10.4, 14.3.
Fixed doxygen warning.
[2.1.2]
Improvements
Updated for new MIMXRT117X header file.
[2.1.1]
Improvements
Updated OCOTP_ReloadShadowRegister to return error status.
Added functions OCOTP_ReadFuseShadowRegisterExt and OCOTP_WriteFuseShadowRegisterWithLock.
Bug fixes
Fixed MISRA 2012 rule 10.3 issue.
[2.0.1]
Bug Fixes
Fixed doxygen issues.
[2.0.0]
Initial version.
PIT
[2.1.0]
New Features
Support RTI (Real Time Interrupt) timer.
[2.0.5]
Improvements
Support workaround for ERR007914. This workaround guarantee the write to MCR register is not ignored.
[2.0.4]
Bug Fixes
Fixed PIT_SetTimerPeriod implementation, the load value trigger should be PIT clock cycles minus 1.
[2.0.3]
Bug Fixes
Clear all status bits for all channels to make sure the status of all TCTRL registers is clean.
[2.0.2]
Bug Fixes
Fixed MISRA-2012 issues.
Rule 10.1.
[2.0.1]
Bug Fixes
Cleared timer enable bit for all channels in function PIT_Init() to make sure all channels stay in disable status before setting other configurations.
Fixed MISRA-2012 rules.
Rule 14.4, rule 10.4.
[2.0.0]
Initial version.
PMU
[2.1.1]
Bug Fixes
Fixed the violations of MISRA 2012 rules: Rule 10.1 10.4
[2.1.0]
Improvements
Added feature macros for low power control APIs to support conditional compile.
Renamed “PMU_2P1EnablePullDown” to “PMU_2P5EnablePullDown”.
[2.0.0]
Initial version.
PWM
[2.9.0]
Improvements
Support PWMX channel output for edge aligned PWM.
Forbid submodule 0 counter initialize with master sync and master reload mode.
[2.8.4]
Improvements
Support workaround for ERR051989. This function helps realize no phase delay between submodule 0 and other submodule.
[2.8.3]
Bug Fixes
Fixed MISRA C-2012 Rule 15.7
[2.8.2]
Bug Fixes
Fixed warning conversion from ‘int’ to ‘uint16_t’ on API PWM_Init.
Fixed warning unused variable ‘reg’ on API PWM_SetPwmForceOutputToZero.
[2.8.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.8.0]
Improvements
Added API PWM_UpdatePwmPeriodAndDutycycle to update the PWM signal’s period and dutycycle for a PWM submodule.
Added API PWM_SetPeriodRegister and PWM_SetDutycycleRegister to merge duplicate code in API PWM_SetupPwm, PWM_UpdatePwmDutycycleHighAccuracy and PWM_UpdatePwmPeriodAndDutycycle
[2.7.1]
Improvements
Supported UPDATE_MASK bit in MASK register.
[2.7.0]
Improvements
Supported platforms which don’t have Capture feature with channel A and B.
Supported platforms which don’t have Submodule 3.
Added assert function in API PWM_SetPhaseDelay to prevent wrong argument.
[2.6.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3.
[2.6.0]
Improvements
Added API PWM_SetPhaseDelay to set the phase delay from the master sync signal of submodule 0.
Added API PWM_SetFilterSampleCountthe to set number of consecutive samples that must agree prior to the input filter.
Added API PWM_SetFilterSamplePeriod to set set the sampling period of the fault pin input filter.
[2.5.1]
Bug Fixes
Fixed MISRA C-2012 rules: 10.1, 10.3, 10.4 , 10.6 and 10.8.
Fixed the issue that PWM_UpdatePwmDutycycle() can’t update duty cycle status value correct.
[2.5.0]
Improvements
Added API PWM_SetOouputToIdle to set pwm channel output to idle.
Added API PWM_GetPwmChannelState to get the pwm channel output duty cycle value.
Added API PWM_SetPwmForceOutputToZero to set the pwm channel output to zero logic.
Added API PWM_SetChannelOutput to set the pwm channel output state.
Added API PWM_SetClockMode to set the value of the clock prescaler.
Added API PWM_SetupPwmPhaseShift to set PWM which a special phase shift and 50% duty cycle.
Added API PWM_SetVALxValue/PWM_GetVALxValue to set/get PWM VALs registers values directly.
[2.4.0]
Improvements
Supported the PWM which can’t work in wait mode.
[2.3.0]
Improvements
Add PWM output enable&disbale API for SDK.
Bug Fixes
Fixed changing channel B configuration when parameter is kPWM_PWMX and PWMX configuration is not supported yet.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3, 10.4.
Bug Fixes
Fixed the issue that PWM drivers computed VAL1 improperly.
Improvements
Updated calculation accuracy of reloadValue in dutyCycleToReloadValue function.
[2.2.0]
Improvements
Added new enumeration and two APIs to support enabling and disabling one or more PWM output triggers.
Added a new function to make the most of 16-bit resolution PWM.
Added one API to support updating fault status of PWM output.
Added one API to support PWM DMA write request.
Added three APIs to support PWM DMA capture read request.
Added one API to support get default fault config of PWM.
Added one API to support setting PWM fault disable mapping.
[2.1.0]
Improvements
Moved the configuration of fault input filter into a new API to avoid be initialized multiple times.
Bug Fixes
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.2, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-14.4, rule-16.4.
[2.0.1]
Bug Fixes
Fixed the issue that PWM submodule may be initialized twice in function PWM_SetupPwm().
[2.0.0]
Initial version.
QTMR
[2.2.2]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.8.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.8.
[2.2.0]
Improvements
Added API QTMR_SetPwmOutputToIdle to set the generated pwm signal to the configured idle value.
Added API QTMR_GetPwmOutputStatus to return the output status of the generated pwm signal.
Added API QTMR_GetPwmChannelStatus to return the channel dutycycle value.
Added API QTMR_SetPwmClockMode to set clock mode change peripheral clock frequency.
Bug Fixes
Fixed the issue that pwm duty cycle could not be 0 and 100.
[2.1.0]
Bug Fixes
Fixed the issue QTMR_SetTimerPeriod needs to decrement down count by 1, and added new APIs to configure the LOAD register, COMP register.
[2.0.2]
Bug Fixes
Fixed the issue introduced by previous code correction for improving the output signal accuracy.
[2.0.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.3, 11.5, 11.9.
Improvements
Improved the output signal accuracy.
[2.0.0]
Initial version.
ROMAPI
[1.1.0]
New feature:
Add update lut command for ROMAPI.
Improvements
Update the comments of “clear cache” function.
[1.0.0]
initial version.
RTWDOG
[2.1.4]
Bug Fixes
Fixed CERT INT30-C, INT31-C issue.
Make API RTWDOG_CountToMesec return 0 if result overflow.
[2.1.3]
Improvements
Waited the over status after CS register operation in case next CS operation causes problem.
[2.1.2]
Bug Fixes
Fixed doxygen issue.
[2.1.1]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rules, containing: rule-10.3, rule-10.8, rule-11.9, rule-14.4, rule-15.5.
[2.1.0]
Improvements
Added an API to enable or disable the window mode.
Added an API to convert a raw count value to millisecond.
Used AT_QUICKACCESS_SECTION_CODE macro to decorate RTWDOG_Init, and copied this function from flash to QUICKACCESS section.
[2.0.1]
Bug Fixes
Fixed bug in the RTWDOG_Init; added check for register’s unlock status when configuring the RTWDOG in RTWDOG_init.
[2.0.0]
Initial version.
SAI
[2.4.4]
Bug Fixes
Fixed enumeration sai_fifo_combine_t - add RX configuration.
[2.4.3]
Bug Fixes
Fixed enumeration sai_fifo_combine_t value configuration issue.
[2.4.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.4.1]
Bug Fixes
Fixed bitWidth incorrectly assigned issue.
[2.4.0]
Improvements
Removed deprecated APIs.
[2.3.8]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.3.7]
Improvements
Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.
Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function
[2.3.6]
Bug Fixes
Fixed violations of MISRA C-2012 rule 5.6.
[2.3.5]
Improvements
Make driver to be aarch64 compatible.
[2.3.4]
Bug Fixes
Corrected the fifo combine feature macro used in driver.
[2.3.3]
Bug Fixes
Added bit clock polarity configuration when sai act as slave.
Fixed out of bound access coverity issue.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.3.2]
Bug Fixes
Corrected the frame sync configuration when sai act as slave.
[2.3.1]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
Fixed violations of MISRA C-2012 rule 17.7.
[2.3.0]
Bug Fixes
Fixed the build error caused by the SOC has no fifo feature.
[2.2.3]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
[2.2.2]
Bug Fixes
Fixed the issue of MISRA 2004 rule 9.3.
Fixed sign-compare warning.
Fixed the PA082 build warning.
Fixed sign-compare warning.
Fixed violations of MISRA C-2012 rule 10.3,17.7,10.4,8.4,10.7,10.8,14.4,17.7,11.6,10.1,10.6,8.4,14.3,16.4,18.4.
Allow to reset Rx or Tx FIFO pointers only when Rx or Tx is disabled.
Improvements
Added 24bit raw audio data width support in sai sdma driver.
Disabled the interrupt/DMA request in the SAI_Init to avoid generates unexpected sai FIFO requests.
[2.2.1]
Improvements
Added mclk post divider support in function SAI_SetMasterClockDivider.
Removed useless configuration code in SAI_RxSetSerialDataConfig.
Bug Fixes
Fixed the SAI SDMA driver build issue caused by the wrong structure member name used in the function SAI_TransferRxSetConfigSDMA/SAI_TransferTxSetConfigSDMA.
Fixed BAD BIT SHIFT OPERATION issue caused by the FSL_FEATURE_SAI_CHANNEL_COUNTn.
Applied ERR05144: not set FCONT = 1 when TMR > 0, otherwise the TX may not work.
[2.2.0]
Improvements
Added new APIs for parameters collection and simplified user interfaces:
SAI_Init
SAI_SetMasterClockConfig
SAI_TxSetBitClockRate
SAI_TxSetSerialDataConfig
SAI_TxSetFrameSyncConfig
SAI_TxSetFifoConfig
SAI_TxSetBitclockConfig
SAI_TxSetConfig
SAI_TxSetTransferConfig
SAI_RxSetBitClockRate
SAI_RxSetSerialDataConfig
SAI_RxSetFrameSyncConfig
SAI_RxSetFifoConfig
SAI_RxSetBitclockConfig
SAI_RXSetConfig
SAI_RxSetTransferConfig
SAI_GetClassicI2SConfig
SAI_GetLeftJustifiedConfig
SAI_GetRightJustifiedConfig
SAI_GetTDMConfig
[2.1.9]
Improvements
Improved SAI driver comment for clock polarity.
Added enumeration for SAI for sample inputs on different edges.
Changed FSL_FEATURE_SAI_CHANNEL_COUNT to FSL_FEATURE_SAI_CHANNEL_COUNTn(base) for the difference between the different SAI instances.
Added new APIs:
SAI_TxSetBitClockDirection
SAI_RxSetBitClockDirection
SAI_RxSetFrameSyncDirection
SAI_TxSetFrameSyncDirection
[2.1.8]
Improvements
Added feature macro test for the sync mode2 and mode 3.
Added feature macro test for masterClockHz in sai_transfer_format_t.
[2.1.7]
Improvements
Added feature macro test for the mclkSource member in sai_config_t.
Changed “FSL_FEATURE_SAI5_SAI6_SHARE_IRQ” to “FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ”.
Added #ifndef #endif check for SAI_XFER_QUEUE_SIZE to allow redefinition.
Bug Fixes
Fixed build error caused by feature macro test for mclkSource.
[2.1.6]
Improvements
Added feature macro test for mclkSourceClockHz check.
Added bit clock source name for general devices.
Bug Fixes
Fixed incorrect channel numbers setting while calling RX/TX set format together.
[2.1.5]
Bug Fixes
Corrected SAI3 driver IRQ handler name.
Added I2S4/5/6 IRQ handler.
Added base in handler structure to support different instances sharing one IRQ number.
New Features
Updated SAI driver for MCR bit MICS.
Added 192 KHZ/384 KHZ in the sample rate enumeration.
Added multi FIFO interrupt/SDMA transfer support for TX/RX.
Added an API to read/write multi FIFO data in a blocking method.
Added bclk bypass support when bclk is same with mclk.
[2.1.4]
New Features
Added an API to enable/disable auto FIFO error recovery in platforms that support this feature.
Added an API to set data packing feature in platforms which support this feature.
[2.1.3]
New Features
Added feature to make I2S frame sync length configurable according to bitWidth.
[2.1.2]
Bug Fixes
Added 24-bit support for SAI eDMA transfer. All data shall be 32 bits for send/receive, as eDMA cannot directly handle 3-Byte transfer.
[2.1.1]
Improvements
Reduced code size while not using transactional API.
[2.1.0]
Improvements
API name changes:
SAI_GetSendRemainingBytes -> SAI_GetSentCount.
SAI_GetReceiveRemainingBytes -> SAI_GetReceivedCount.
All names of transactional APIs were added with “Transfer” prefix.
All transactional APIs use base and handle as input parameter.
Unified the parameter names.
Bug Fixes
Fixed WLC bug while reading TCSR/RCSR registers.
Fixed MOE enable flow issue. Moved MOE enable after MICS settings in SAI_TxInit/SAI_RxInit.
[2.0.0]
Initial version.
SAI_EDMA
[2.7.1]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.7.0]
Improvements
Updated api SAI_TransferReceiveEDMA to support voice channel block interleave transfer.
Updated api SAI_TransferSendEDMA to support voice channel block interleave transfer.
Added new api SAI_TransferSetInterleaveType to support channel interleave type configurations.
[2.6.0]
Improvements
Removed deprecated APIs.
[2.5.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 20.7.
[2.5.0]
Improvements
Added new api SAI_TransferSendLoopEDMA/SAI_TransferReceiveLoopEDMA to support loop transfer.
Added multi sai channel transfer support.
[2.4.0]
Improvements
Added new api SAI_TransferGetValidTransferSlotsEDMA which can be used to get valid transfer slot count in the sai edma transfer queue.
Deprecated the api SAI_TransferRxSetFormatEDMA and SAI_TransferTxSetFormatEDMA.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3,10.4.
[2.3.2]
Refer SAI driver change log 2.1.0 to 2.3.2
SEMC
[2.7.1]
Bug Fixes
Fixed the wrong write operation to INTR register. The INTR register is a W1C register, so the right write operation is write directly to it to clear.
[2.7.0]
Improvements
Add new autofreshTimes parameter in semc_sdram_config_t.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.6.0]
Bug Fixes
Fixed the SEMC SRAM function bug that some configuration options can’t be set.
Correct legacy SEMC SRAM function feature macros.
Improvements
Add new SEMC SRAM function feature macros.
[2.5.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.3.
Fixed SEMC_ConfigureDBI bug that RDX not set correctly.
[2.5.0]
Bug Fixes
Fixed definitions of bitfields of BMCR0 and BMCR1 - wrong field order and incorrect semantical naming
The fix alters the driver API regarding configuration of AXI bus queue reordering
[2.4.3]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 5.6.
[2.4.2]
Improvements
Deleted meaningless parameter in memory size conversion function.
[2.4.1]
Bug Fixes
Fixed PSRAM A8 configuration issue, which should be 0x06U for PSRAM while pix mux bit width is 0x04U, based on different pix mux bit width.
[2.4.0]
Improvements
Improved nor and sram timing configuration on sync mode.
[2.3.1]
Bug Fixes
Updated refresh timer period(RT) timing setting, which updated into (RT+1)*(Prescaler period) for SDRAM.
Supported new DBI control register 2 to configure CSX interval time(CEITV).
Fixed violations of the MISRA C-2012 Rule 10.8.
Fixed doxygen warning.
[2.3.0]
New Features
Limited burst length as 1 according to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller’s burst length is greater than 1.
Supported 8 bits column address for SDRAM.
[2.2.1]
New Features
Added queue weight control, which can control queue a/b is working or not.
Updated NAND FLASH configuration API which disables and enables SEMC between configure control registers.
Added ONFI parameter Integrity CRC check for SEMC flash component.
[2.2.0]
New Features
Supported up to 4 PSRAM CS.
Added programmable delay line for DQS.
Added ready/wait feature for SRAM in asynchronous mode.
[2.1.0]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
Updated parameter type from uint16_t into uint32_t for send IP command API.
[2.0.4]
Bug Fixes
Fixed the SEMC queueA and queueB weight configuration issue.
Fixed the wrong configuration of DBICR1 register in SEMC_ConfigureDBI.
[2.0.3]
Bug Fixes
Added feature macro to control WDS&WDH bit setting for NOR synchronous transfer.
[2.0.2]
Bug Fixes
Changed SEMC NAND configuration structure and verify SEMC NAND related APIs.
Added extended SEMC clock enable.
[2.0.1]
Bug Fixes
Fixed data size mask configure in SEMC_ConfigureIPCommand API.
Updated the command mode in IP command type.
[2.0.0]
Initial version.
SNVS_HP
[2.3.2]
Make SNVS_HP_RTC_Init()/SNVS_HP_RTC_Deinit more transparent. Use function SNVS_HP_Init()/SNVS_HP_Deinit() instead of copy of this code in SNVS_HP_RTC_XXX() function.
[2.3.1]
Fixed problem in SNVS_HP_RTC_Init(), which is clearing bits that should stay intact.
[2.3.0]
Re-map Security Violation for RT11xx specific violations.
[2.2.0]
Fixed doxygen issues.
Add SNVS HP Set locks.
[2.1.4]
Fix MISRA issues.
[2.1.3]
Fixed IAR Pa082 warnings.
[2.1.2]
Fixed problem with initialization of the periodic interrupt frequency.
Fixed problem with SNVS entering into fail state when HAB enters closed mode.
[2.1.1]
Added APIs for HP security violation status flags.
[2.1.0]
Added APIs for High Assurance Counter (HAC), Zeroizable Master Key (ZMK) and Software Security Violation.
[2.0.0]
Initial version.
SNVS_LP
[2.4.6]
Fix a bug in SNVS_LP_EnableRxActiveTamper() where assignments to base->LPATRC2R were done wrongly to LPATRC1R.
[2.4.5]
Fix a bug in SNVS_LP_EnableRxActiveTamper() where assignments to base->LPATRC1R would overwrite previously set bits.
[2.4.4]
Make SNVS_LP_SRTC_Init()/SNVS_LP_SRTC_Deinit more transparent. Use function SNVS_LP_Init()/SNVS_LP_Deinit() instead of copy of this code in SNVS_LP_SRTC_XXX() function.
[2.4.3]
Fixed problem in SNVS_LP_SRTC_Init(), which is clearing bits that should stay intact.
[2.4.2]
Updated driver to match with new device header files.
[2.4.1]
Fixed MISRA issues.
[2.4.0]
Fix backward compatibility with version 2.2.x.
[2.3.0]
Add active pin, clock, voltage and temperature tamper features.
[2.2.0]
Fixed doxygen issues.
Add Transition SNVS SSM state to Trusted/Non-secure from Check state.
[2.1.2]
Fix MISRA issues.
[2.1.1]
Fix IAR Pa082 warning.
[2.1.0]
Added APIs for Zeroizable Master Key (ZMK) and Monotonic Counter (MC).
[2.0.0]
Initial version.
SPDIF
[2.0.7]
Improvements
Add feature macro FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER to handle nonexistent SIC register.
[2.0.6]
Bug Fixes
Fixed the Q/U channel interrupt enabled unexpectly while Q/U transfer pointer is NULL.
[2.0.5]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.3.
[2.0.4]
Bug Fixes
Added udata/qdata buffer address validation in driver IRQ handler to ensure that NULL pointer dereferences do not occur.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.2]
Bug Fixes
Corrected operator used for size value assertion in SPDIF_ReadBlocking/SPDIF_WriteBlocking.
[2.0.1]
Bug Fixes
Corrected the feature macro name used to define s_edmaPrivateHandle.
[2.0.0]
Initial version.
SPDIF DMA Driver
[2.0.8]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.0.7]
Bug Fixes
Fixed the incompatibility issue with edma4 driver.
[2.0.6]
Bug Fixes
Add feature macro to determine whether to use the API MEMORY_ConvertMemoryMapAddress to translate TCD addresses for DLAST_SGA.
[2.0.5]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.3.
[2.0.4]
Bug Fixes
Added udata/qdata buffer address validation in driver IRQ handler to ensure that NULL pointer dereferences do not occur.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.2]
Bug Fixes
Corrected operator used for size value assertion in SPDIF_ReadBlocking/SPDIF_WriteBlocking.
[2.0.1]
Bug Fixes
Corrected the feature macro name used to define s_edmaPrivateHandle.
[2.0.0]
Initial version.
SRC
[2.0.1]
Improvements
Updated SRC driver for adding SRC_SRSR_JTAG_SW_RST enumeration.
[2.0.0]
Initial version.
TEMPMON
[2.2.0]
Bug Fixes
Fixed the issue of inconsistency between data width and RM.
[2.1.1]
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.3 10.4.
[2.1.0]
Bug Fixes
Supported minus value for alarm temperature setting.
Fixed wrong temperature calculation equation.
[2.0.3]
Improvements
Added temperature threshold check for high/low/panic to avoid temperature overflow.
[2.0.2]
Bug Fixes
Fixed wrong alarm value setting API, it need to clear it firstly and set a new value into it.
[2.0.1]
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.1 10.3 10.4 10.8 17.7.
[2.0.0]
Initial version.
TRNG
[2.0.18]
Bug fix:
TRNG health checks now done in software on RT5xx and RT6xx.
[2.0.17]
New features:
Add support for RT700.
[2.0.16]
Improvements:
Added support for Dual oscillator mode.
[2.0.15]
Other changes:
Changed TRNG_USER_CONFIG_DEFAULT_XXX values according to latest reccomended by design team.
[2.0.14]
New features:
Add support for RW610 and RW612.
[2.0.13]
Bug fix:
After deepsleep it might return error, added clearing bits in TRNG_GetRandomData() and generating new entropy.
Modified reloading entropy in TRNG_GetRandomData(), for some data length it doesn’t reloading entropy correctly.
[2.0.12]
Bug fix:
For KW34A4_SERIES, KW35A4_SERIES, KW36A4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8.
[2.0.11]
Bug fix:
Add clearing pending errors in TRNG_Init().
[2.0.10]
Bug Fix:
Fixed doxygen issues.
[2.0.9]
Bug Fix:
Fix HIS_CCM metrics issues.
[2.0.8]
Bug fix:
For K32L2A41A_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv4.
[2.0.7]
Bug fix:
Fix MISRA 2004 issue rule 12.5.
[2.0.6]
Bug fix:
For KW35Z4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8.
[2.0.5]
Improvements:
For FRQMIN, FRQMAX and OSCDIV, add possibility to use device specific preprocessor macro to define default value in TRNG user configuration structure.
[2.0.4]
Bug Fix:
Fix MISRA-2012 issues.
Rule 10.1, rule 10.3, rule 13.5, rule 16.1.
[2.0.3]
Improvements:
update TRNG_Init to restart new entropy generation.
[2.0.2]
Improvements:
fix MISRA issues
Rule 14.4.
[2.0.1]
New features:
Set default OSCDIV for Kinetis devices KL8x and KL28Z.
Other changes:
Changed default OSCDIV for K81 to divide by 2.
[2.0.0]
Initial version.
USDHC
[2.8.4]
Improvements
Add feature macro FSL_FEATURE_USDHC_HAS_NO_VS18.
[2.8.3]
Improvements
Improved api USDHC_EnableAutoTuningForCmdAndData to adapt to new bit field name for USDHC_VEND_SPEC2 register.
[2.8.2]
Improvements
Added feature macro FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT.
[2.8.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9.
[2.8.0]
Improvements
Fixed the mmc boot transfer failed issue which is caused by the Dma complete interrupt not enabled.
Marked api USDHC_AdjustDelayForManualTuning as deprecated and added new api USDHC_SetTuingDelay/USDHC_GetTuningDelayStatus.
Improved the manual tuning flow accroding to specification.
Added memory address conversion to support buffers which could only be accessed using alias address by non-core masters.
Fixed violations of MISRA C-2012 rule 10.4.
[2.7.0]
Improvements
Added api USDHC_TransferScatterGatherADMANonBlocking to support scatter gather transfer.
Added feature FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER for re-tuning time counter field in HOST_CTRL_CAP register.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 10.1, 10.3, 10.4, 8.4.
[2.6.0]
Improvements
Added api USDHC_SetStandardTuningCounter to support adjust tuning counter of Standard tuning.
[2.5.1]
Improvements
Used different status code for command and data interrupt callback.
Added cache line invalidate for receive buffer in driver IRQ handler to fix CM7 speculative access issue.
[2.5.0]
Improvements
Added new api USDHC_SetStrobeDllOverride for HS400 strobe dll override mode delay taps configurations.
Corrected the STROBE DLL configurations sequence.
[2.4.0]
Improvements
Added feature macro for read/write burst length.
Disabled redundant interrupt per different transfer request.
Disabled interrupt and reset command/data pointer in handle when transfer completes.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3.
Fixed PA082 build warning.
Fixed logically dead code Coverity issue.
[2.3.0]
Improvements
Added USDHC_SetDataConfig API to support manual tuning.
Removed the limitaion that source clock must be bigger than the target in function USDHC_SetSdClock by using source clock frequency as target directly.
Added peripheral reset in USDHC_Init function.
Added tuning reset support in function USDHC_Reset function.
[2.2.8]
Bug Fixes
Fixed out-of bounds write in function USDHC_ReceiveCommandResponse.
[2.2.7]
Improvements
Added API USDHC_GetEnabledInterruptStatusFlags and used in USDHC_TransferHandleIRQ.
Removed useless member interruptFlags in usdhc_handle_t.
[2.2.6]
Improvements
Added address align check for ADMA descriptor table address.
Changed USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY to (65536-4096) to make sure the data address is 4KB align for a transfer which need more than one ADMA1 descriptor.
[2.2.5]
Bug Fixes
Fixed MDK 66-D warning.
[2.2.4]
Bug Fixes
Fixed issue that real clock frequency wss mismatched with target clock frequency, which was caused by an incorrect prescaler calculation.
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.2.3]
Bug Fixes
Fixed issue where AMDA did not disable with DMAEN clear.
Improvements
Improved set clock function to check the output frequency range.
Dynamic set SDCLKFS during DDR enable or disable.
[2.2.2]
Improvements
Improved read transfer cache maintain operation, combined clean, and invalidated them into one function.
[2.2.1]
Bug Fixes
Disabled the invalidate cache operation for tuning.
[2.2.0]
Improvements
Improved USDHC to support MMC boot feature.
[2.1.3]
Bug Fixes
Fixed MISRA issue.
[2.1.2]
Bug Fixes
Fixed Coverity issue.
Added base address and userData parameter for all callback functions.
[2.1.1]
Improvements
Added cache maintain operation.
Added timeout status check for the DATA transfer which ignore error.
Added feature macro for SDR50/SDR104 mode.
Removed useless IRQ handler from different platforms.
[2.1.0]
Improvements
Integrated tuning into transfer function.
Added strobe DLL feature.
Added enableAutoCommand23 in data structure.
Removed enable card clock function because the controller would handle the clock on/off.
[2.0.0]
Initial version.
WDOG
[2.2.0]
Bug Fixes
Fixed the wrong behavior of workMode.enableWait, workMode.enableStop, workMode.enableDebug in configuration structure wdog_config_t. When set the items to true, WDOG will continues working in those modes.
[2.1.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.1, 10.3, 10.4, 10.6, 10.7 and 11.9.
Fixed the issue of the inseparable process interrupted by other interrupt source.
WDOG_Init
WDOG_Refresh
[2.1.0]
New Features
Added new API “WDOG_TriggerSystemSoftwareReset()” to allow users to reset the system by software.
Added new API “WDOG_TriggerSoftwareSignal()” to allow users to trigger a WDOG_B signal by software.
Removed the parameter “softwareAssertion” and “softwareResetSignal” out of the wdog_config_t structure.
Added new parameter “enableTimeOutAssert” to the wdog_config_t structure. With this parameter enabled, when the WDOG timeout occurs, a WDOG_B signal will be asserted. This signal can be routed to external pin of the chip. Note that WDOG_B signal remains asserted until a power-on reset (POR) occurs.
[2.0.1]
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
XBARA
[2.0.6]
Bug Fixes
Fixed typo in kXBARA_RequestInterruptEnalbe item.
[2.0.5]
Bug Fixes
Fixed IAR build warning Pa082.
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.7, 10.8, 12.1, 18.1, 20.7.
[2.0.4]
Improvements
Optimized XBARA_SetOutputSignalConfig.
[2.0.3]
Bug Fixes
Corrected configuration for function XBAR_SetOutputSignalConfig.
[2.0.2]
Other Changes
Changed array clock name.
[2.0.1]
Bug Fixes
Fixed w1c bits for XBARA_SetOutputSignalConfig function.
[2.0.0]
Initial version.
XBARB
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 12.2, 10.7
[2.0.1]
Bug Fixes
Corrected XBARB_SetSignalsConnection function.
Other Changes
Changed array clock name.
[2.0.0]
Initial version.