MCUXpresso SDK Changelog
ACMP
[2.3.0]
Improvements
Expose C0 register FILTER_CNT bitfield and FPR bitfield to the user.
[2.2.0]
Improvements
Updated feature macros for roundrobin mode, window mode, filter mode, and 3V domain removes.
[2.1.0]
New Feature
Supported the plateforms which don’t have hysteresis mode.
[2.0.6]
Bug Fixes
Fixed the wrong comments, the DAC value should range from 0 to 255.
[2.0.5]
Bug Fixes
Fixed the out-of-bounds error of Coverity caused by missing an assert sentence to avoid the return value of ACMP_GetInstance() exceeding the array bounds.
Fixed the violations of MISRA C-2012 rules:
Rule 10.1, 14.4, 16.4, 17.7.
[2.0.4]
Bug Fixes
Avoided changing w1c bit in ACMP_SetRoundRobinPreState().
[2.0.3]
New Features
Added feature functions for usage of different power domains(1.8 V and 3 V). These functions are first enabled in ULP1. They are about:
ACMP_EnableLinkToDAC()
ACMP_SetDiscreteModeConfig()
ACMP_GetDefaultDiscreteModeConfig()
[2.0.2]
Other Changes
Changed coding style of peripheral base address from “s_acmpBases” to “s_acmpBase”.
[2.0.1]
Bug Fixes
Fixed bug regarding the function “ACMP_SetRoundRobinConfig”. It will not continue execution but returns directly after disabling round robin mode.
AOI
[2.0.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8, 2.2.
[2.0.0]
Initial version.
ASRC
[2.1.3]
Bug Fixes
Fixed function did not match the specified channel pair issue.
[2.1.2]
Improvements
Correct feature name in source file by changing FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM to FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASRPM.
Removed the asrc_clock_source_t from driver header file, as SOC header file will provide detail definition.
Bug Fixes
Fixed the ASRC_SetChannelPairConfig/ASRC_ChannelPairEnable functions missing functionality when using channel pair B/C.
Fixed violations of the MISRA C-2012 rules 10.7.
[2.1.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1，10.4, 12.2.
[2.1.0]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 10.1, 17.7, 11.9, 8.6, 12.2, 11.6.
[2.0.1]
Improvements
Added feature macro FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM for ASRC parameter register.
Bug Fixes
Fixed the unused build warning in asrc edma driver.
[2.0.0]
Initial version.
ASRC EDMA Driver
[2.2.0]
Bug Fixes
Fixed the “watermark” and “channel” was defined in struct asrc_p2p_edma_config_t but never used issue.
[2.1.0]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 10.1, 17.7, 11.9, 8.6, 12.2, 11.6.
[2.0.1]
Improvements
Added feature macro FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM for ASRC parameter register.
Bug Fixes
Fixed the unused build warning in asrc edma driver.
[2.0.0]
Initial version.
BBNSM
[2.0.0]
Initial version.
CACHE XCACHE
[2.0.2]
Bug Fixes
Updated XCACHE_InvalidateCacheByRange(), XCACHE_CleanCacheByRange(), XCACHE_CleanInvalidateCacheByRange() in case of startAddr equal to endAddr.
[2.0.1]
Improvements
Check input parameter “size_byte” must be larger than 0.
[2.0.0]
Initial version.
CACHE ARMv7-M7
[2.0.4]
Bug Fixes
Fixed doxygen issue.
[2.0.3]
Improvements
Deleted redundancy code about calculating cache clean/invalidate size and address aligns.
[2.0.2]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.1, 10.3 and 10.4.
[2.0.1]
Bug Fixes
Fixed cache size issue in L2CACHE_GetDefaultConfig API.
[2.0.0]
Initial version.
CLOCK
[2.1.5]
Improvements
update OSC_RC_400M STAT registers to read only.
[2.1.4]
Bug Fixes
Fix edma base ptrs and edma clocks did not match issue.
[2.1.3]
Improvements
Move s_clockSourceName array to c from header.
[2.1.2]
Comment improvements for CLOCK_InitPfd()
[2.1.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 8.6, 10.3.
Fixed potential infinite loop in CLOCK_GetCoreSysClkFreq() function.
[2.1.0]
Improvements
Added CLOCK_GetFreqFromObs() function.
Bug Fixes
Fixed bug in CLOCK_InitArmPll() function.
Fixed bug in CLOCK_InitSysPll1() function.
[2.0.0]
Initial version.
COMMON
[2.5.0]
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]
New Features
Added NETC into status group.
[2.3.2]
Improvements
Make driver aarch64 compatible
[2.3.1]
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]
Other Change
Added MECC status group definition.
[2.2.6]
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]
New Features
Added OTFAD into status group.
[2.1.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]
Initial version.
DAC12
[2.1.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.0]
Improvements
Defined the macro “FSL_FEATURE_HAS_NO_ITRM_REGISTER” to distinguish different scenes that ITRM register may not equipped one some devices.
[2.0.1]
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.8, 17.7.
[2.0.0]
Initial version.
DCDC
[2.0.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 8.6.
[2.0.0]
Initial version.
ECAT
[2.0.0]
Initial version.
EDMA
[2.10.5]
Bug Fixes
Fixed memory convert would convert NULL as zero address issue.
[2.10.4]
Improvements
Add new MP register macros to ensure compatibility with different devices.
Add macro DMA_CHANNEL_ARRAY_STEPn to adapt to complex addressing of edma tcd registers.
[2.10.3]
Bug Fixes
Clear interrupt status flags in EDMA_CreateHandle to avoid triggering interrupt by mistake.
[2.10.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.10.1]
Bug Fixes
Fixed EDMA_GetRemainingMajorLoopCount may return wrong value issue.
Fixed violations of the MISRA C-2012 rules 13.5, 10.4.
[2.10.0]
Improvements
Modify the structures edma_core_mp_t, edma_core_channel_t, edma_core_tcd_t to adapt to edma5.
Add TCD register macro to facilitate confirmation of tcd type.
Modfiy the mask macro to a fixed value.
Add EDMA_TCD_TYPE macro to determine edma tcd type.
Add extension API to the following API to determine edma tcd type.
EDMA_ConfigChannelSoftwareTCD -> EDMA_ConfigChannelSoftwareTCDExt
EDMA_TcdReset -> EDMA_TcdResetExt
EDMA_TcdSetTransferConfig -> EDMA_TcdSetTransferConfigExt
EDMA_TcdSetMinorOffsetConfig -> EDMA_TcdSetMinorOffsetConfigExt
EDMA_TcdSetChannelLink -> EDMA_TcdSetChannelLinkExt
EDMA_TcdSetBandWidth -> EDMA_TcdSetBandWidthExt
EDMA_TcdSetModulo -> EDMA_TcdSetModuloExt
EDMA_TcdEnableAutoStopRequest -> EDMA_TcdEnableAutoStopRequestExt
EDMA_TcdEnableInterrupts -> EDMA_TcdEnableInterruptsExt
EDMA_TcdDisableInterrupts -> EDMA_TcdDisableInterruptsExt
EDMA_TcdSetMajorOffsetConfig -> EDMA_TcdSetMajorOffsetConfigExt
[2.9.2]
Improvements
Remove tcd alignment check in API that is low level and does not necessarily use scather/gather mode.
[2.9.1]
Bug Fixes
Deinit channel request source before set channel mux.
[2.9.0]
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed the variable type definition error issue.
Fixed doxygen warning.
Fixed violations of MISRA C-2012 rule 18.1.
[2.8.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3
[2.8.0]
Improvements
Added feature FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC to separate DMA without SEC bitfield.
[2.7.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, 10.4, 11.6, 11.8, 14.3,.
[2.7.0]
Improvements
Use more accurate DMA instance based feature macros.
New Features
Add new APIs EDMA_PrepareTransferTCD and EDMA_SubmitTransferTCD, which support EDMA transfer using TCD.
[2.6.0]
Improvements
Modify the type of parameter channelRequestSource from dma_request_source_t to int32_t in the EDMA_SetChannelMux.
[2.5.3]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, 10.4, 11.6, 20.7, 12.2, 20.9, 5.3, 10.8, 8.4, 9.3.
[2.5.2]
Improvements
Applied ERRATA 51327.
[2.5.1]
Bug Fixes
Fixed the EDMA_ResetChannel function cannot reset channel DONE/ERROR status.
[2.5.0]
Improvements
Added feature FSL_FEATURE_EDMA_HAS_NO_SBR_ATTR_BIT to separate DMA without ATTR bitfield.
Added api EDMA_GetChannelSystemBusInformation to gets the channel identification and attribute information on the system bus interface.
Bug Fixes
Fixed the ESG bit not set in scatter gather mode issue.
Fixed the DREQ bit configuration missed in single transfer issue.
Cleared the interrupt status before invoke callback to avoid miss interrupt issue.
Removed disableRequestAfterMajorLoopComplete from edma_transfer_config_t structure as driver will handle it.
Fixed the channel mux configuration not compatible issue.
Fixed the out of bound access in function EDMA_DriverIRQHandler.
[2.4.4]
Bug Fixes
Fixed comments by replacing STCD with TCD
Fixed the TCD overwrite issue when submit transfer request in the callback if there is a active TCD in hardware.
[2.4.3]
Improvements
Added FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET to convert the address between system mapped address and dma quick access address.
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt for the non scatter gather case.
[2.4.2]
Bug Fixes
Fixed the wrong tcd done count calculated in first TCD interrupt by correct the initial value of the header.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.4.1]
Bug Fixes
Added clear CITER and BITER registers in EDMA_AbortTransfer to make sure the TCD registers in a correct state for next calling of EDMA_SubmitTransfer.
Removed the clear DONE status for ESG not enabled case to aovid DONE bit cleared unexpectedly.
[2.4.0]
Improvements
Added api EDMA_EnableContinuousChannelLinkMode to support continuous link mode.
Added apis EDMA_SetMajorOffsetConfig/EDMA_TcdSetMajorOffsetConfig to support major loop address offset feature.
Added api EDMA_EnableChannelMinorLoopMapping for minor loop offset feature.
Removed the reduntant IRQ Handler in edma driver.
[2.3.2]
Improvements
Fixed HIS ccm issue in function EDMA_PrepareTransferConfig.
Fixed violations of MISRA C-2012 rule 11.6, 10.7, 10.3, 18.1.
Bug Fixes
Added ACTIVE & BITER & CITER bitfields to determine the channel status to fixed the issue of the transfer request cannot submit by function EDMA_SubmitTransfer when channel is idle.
[2.3.1]
Improvements
Added source/destination address alignment check.
Added driver IRQ handler support for multi DMA instance in one SOC.
[2.3.0]
Improvements
Added new api EDMA_PrepareTransferConfig to allow different configurations of width and offset.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4, 10.1.
Fixed the Coverity issue regarding out-of-bounds write.
[2.2.0]
Improvements
Added peripheral-to-peripheral support in EDMA driver.
[2.1.9]
Bug Fixes
Fixed MISRA issue: Rule 10.7 and 10.8 in function EDMA_DisableChannelInterrupts and EDMA_SubmitTransfer.
Fixed MISRA issue: Rule 10.7 in function EDMA_EnableAsyncRequest.
[2.1.8]
Bug Fixes
Fixed incorrect channel preemption base address used in EDMA_SetChannelPreemptionConfig API which causes incorrect configuration of the channel preemption register.
[2.1.7]
Bug Fixes
Fixed incorrect transfer size setting.
Added 8 bytes transfer configuration and feature for RT series;
Added feature to support 16 bytes transfer for Kinetis.
Fixed the issue that EDMA_HandleIRQ would go to incorrect branch when TCD was not used and callback function not registered.
[2.1.6]
Bug Fixes
Fixed KW3X MISRA Issue.
Rule 14.4, 10.8, 10.4, 10.7, 10.1, 10.3, 13.5, and 13.2.
Improvements
Cleared the IRQ handler unavailable for specific platform with macro FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET.
[2.1.5]
Improvements
Improved EDMA IRQ handler to support half interrupt feature.
[2.1.4]
Bug Fixes
Cleared enabled request, status during EDMA_Init for the case that EDMA is halted before reinitialization.
[2.1.3]
Bug Fixes
Added clear DONE bit in IRQ handler to avoid overwrite TCD issue.
Optimized above solution for the case that transfer request occurs in callback.
[2.1.2]
Improvements
Added interface to get next TCD address.
Added interface to get the unused TCD number.
[2.1.1]
Improvements
Added documentation for eDMA data flow when scatter/gather is implemented for the EDMA_HandleIRQ API.
Updated and corrected some related comments in the EDMA_HandleIRQ API and edma_handle_t struct.
[2.1.0]
Improvements
Changed the EDMA_GetRemainingBytes API into EDMA_GetRemainingMajorLoopCount due to eDMA IP limitation (see API comments/note for further details).
[2.0.5]
Improvements
Added pubweak DriverIRQHandler for K32H844P (16 channels shared).
[2.0.4]
Improvements
Added support for SoCs with multiple eDMA instances.
Added pubweak DriverIRQHandler for KL28T DMA1 and MCIMX7U5_M4.
[2.0.3]
Bug Fixes
Fixed the incorrect pubweak IRQHandler name issue, which caused re-definition build errors when client set his/her own IRQHandler, by changing the 32-channel IRQHandler name to DriverIRQHandler.
[2.0.2]
Bug Fixes
Fixed incorrect minorLoopBytes type definition in _edma_transfer_config struct, and defined minorLoopBytes as uint32_t instead of uint16_t.
[2.0.1]
Bug Fixes
Fixed the eDMA callback issue (which did not check valid status) in EDMA_HandleIRQ API.
[2.0.0]
Initial version.
ELE_BASE_API
[1.0.0]
initial version.
EQDC
[2.3.1]
Bug Fix
Fixed CTRL2[CMODE] field overwritten in API EQDC_Init.
[2.3.0]
Improvements
Add feature macro to support platforms which do not have compare interrupt.
[2.2.3]
Bug Fix
Clear Revolution Counter Register(REV) in init function to prevent its value not equal to zero after reset.
[2.2.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]
Bug Fix
Fixed violations of the MISRA C-2012 rules 20.9.
[2.2.0]
New features
Supported the feature that the position counter to be initialized by Index Event Edge Mark.
[2.1.0]
Bug Fix
Fixed typo in interrupt enumeration values.
Improvements
Supported Count Direct Change interrupt.
Removed unused parameter in user configuration.
Supported ERRATA_051383 check, the CTRL[DMAEN] can’t be cleared.
[2.0.1]
Bug Fix
Fixed violations of the MISRA C-2012 rules 10.3, 10.6, 10.8, 14.4, 16.4.
[2.0.0]
Initial version.
EWM
[2.0.3]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.1, 10.3.
[2.0.2]
Bug Fixes
Fixed violation of MISRA C-2012 rules: 10.3, 10.4.
[2.0.1]
Bug Fixes
Fixed the hard fault in EWM_Deinit.
[2.0.0]
Initial version.
FLEXCAN
[2.13.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
Improvements
Support payload endianness selection feature.
[2.12.0]
Improvements
Support automatic Remote Response feature.
Add API FLEXCAN_SetRemoteResponseMbConfig() to configure automatic Remote Response mailbox.
[2.11.8]
Improvements
Synchronize flexcan driver update on s32z platform.
[2.11.7]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compatibility with edma5.
[2.11.6]
Bug Fixes
Fixed ERRATA_9595 FLEXCAN_EnterFreezeMode() may result to bus fault on some platform.
[2.11.5]
Bug Fixes
Fixed flexcan_memset() crash under high optimization compilation.
[2.11.4]
Improvements
Update CANFD max bitrate to 10Mbps on MCXNx3x and MCXNx4x.
Release peripheral from reset if necessary in init function.
[2.11.3]
Bug Fixes
Fixed FLEXCAN_TransferReceiveEnhancedFifoEDMA() compile error with DMA3.
[2.11.2]
Bug Fixes
Fixed bug that timestamp in flexcan_handle_t not updated when RX overflow happens.
[2.11.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
[2.11.0]
Bug Fixes
Fixed wrong base address argument in FLEXCAN2 IRQ Handler.
Improvements
Add API to determine if the instance supports CAN FD mode at run time.
[2.10.1]
Bug Fixes
Fixed HIS CCM issue.
Fixed RTOS issue by adding protection to read-modify-write operations on interrupt enable/disable API.
[2.10.0]
Improvements
Update driver to make it able to support devices which has more than 64 8bytes MBs.
Update CAN FD transfer APIs to make them set/get edl bit according to frame content, which can make them compatible with classic CAN.
[2.9.2]
Bug Fixes
Fixed the issue that FLEXCAN_CheckUnhandleInterruptEvents() can’t detecting the exist enhanced RX FIFO interrupt status.
Fixed the issue that FLEXCAN_ReadPNWakeUpMB() does not return fail even no existing valid wake-up frame.
Fixed the issue that FLEXCAN_ReadEnhancedRxFifo() may clear bits other than the data available bit.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8.
Improvements
Return kStatus_FLEXCAN_RxFifoDisabled instead of kStatus_Fail when read FIFO fail during IRQ handler.
Remove unreachable code from timing calculates APIs.
Update Enhanced Rx FIFO handler to make it deal with underflow/overflow status first.
[2.9.1]
Bug Fixes
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoBlocking() API clearing Fifo data available flag more than once.
Fixed the issue that entering FLEXCAN_SubHandlerForEhancedRxFifo() even if Enhanced Rx fifo interrupts are not enabled.
Fixed the issue that FLEXCAN_TransferReceiveEnhancedFifoEDMA() update handle even if previous Rx FIFO receive not finished.
Fixed the issue that FLEXCAN_SetEnhancedRxFifoConfig() not configure the ERFCR[NFE] bits to the correct value.
Fixed the issue that FLEXCAN_ReceiveFifoEDMACallback() can’t differentiate between Rx fifo and enhanced rx fifo.
Fixed the issue that FLEXCAN_TransferHandleIRQ() can’t report Legacy Rx FIFO warning status.
[2.9.0]
Improvements
Add public set bit rate API to make driver easier to use.
Update Legacy Rx FIFO transfer APIs to make it support received multiple frames during one API call.
Optimized FLEXCAN_SubHandlerForDataTransfered() API in interrupt handling to reduce the probability of packet loss.
[2.8.7]
Improvements
Initialized the EDMA configuration structure in the FLEXCAN EDMA driver.
[2.8.6]
Bug Fixes
Fix Coverity overrun issues in fsl_flexcan_edma driver.
[2.8.5]
Improvements
Make driver aarch64 compatible.
[2.8.4]
Bug Fixes
Fixed FlexCan_Errata_6032 to disable all interrupts.
[2.8.3]
Bug Fixes
Fixed an issue with the FLEXCAN_EnableInterrupts and FLEXCAN_DisableInterrupts interrupt enable bits in the CTRL1 register.
[2.8.2]
Bug Fixes
Fixed errors in timing calculations and simplify the calculation process.
Fixed issue of CBT and FDCBT register may write failure.
[2.8.1]
Bug Fixes
Fixed the issue of CAN FD three sampling points.
Added macro to support the devices that no MCR[SUPV] bit.
Remove unnecessary clear WMB operations.
[2.8.0]
Improvements
Update config configuration.
Added enableSupervisorMode member to support enable/disable Supervisor mode.
Simplified the algorithm in CAN FD improved timing APIs.
[2.7.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.7.
[2.7.0]
Improvements
Update config configuration.
Added enablePretendedeNetworking member to support enable/disable Pretended Networking feature.
Added enableTransceiverDelayMeasure member to support enable/disable Transceiver Delay MeasurementPretended feature.
Added bitRate/bitRateFD member to work as baudRate/baudRateFD member union.
Rename all “baud” in code or comments to “bit” to align with the CAN spec.
Added Pretended Networking mode related APIs.
FLEXCAN_SetPNConfig
FLEXCAN_GetPNMatchCount
FLEXCAN_ReadPNWakeUpMB
Added support for Enhanced Rx FIFO.
Removed independent memory error interrupt/status APIs and put all interrupt/status control operation into FLEXCAN_EnableInterrupts/FLEXCAN_DisableInterrupts and FLEXCAN_GetStatusFlags/FLEXCAN_ClearStatusFlags APIs.
Update improved timing APIs to make it calculate improved timing according to CiA doc recommended.
FLEXCAN_CalculateImprovedTimingValues.
FLEXCAN_FDCalculateImprovedTimingValues.
Update FLEXCAN_SetBitRate/FLEXCAN_SetFDBitRate to added the use of enhanced timing registers.
[2.6.2]
Improvements
Add CANFD frame data length enumeration.
[2.6.1]
Bug Fixes
Fixed the issue of not fully initializing memory in FLEXCAN_Reset() API.
[2.6.0]
Improvements
Enable CANFD ISO mode in FLEXCAN_FDInit API.
Enable the transceiver delay compensation feature when enable FD operation and set bitrate switch.
Implementation memory error control in FLEXCAN_Init API.
Improve FLEXCAN_FDCalculateImprovedTimingValues API to get same value for FPRESDIV and PRESDIV.
Added memory error configuration for user.
enableMemoryErrorControl
enableNonCorrectableErrorEnterFreeze
Added memory error related APIs.
FLEXCAN_GetMemoryErrorReportStatus
FLEXCAN_GetMemoryErrorStatusFlags
FLEXCAN_ClearMemoryErrorStatusFlags
FLEXCAN_EnableMemoryErrorInterrupts
FLEXCAN_DisableMemoryErrorInterrupts
Bug Fixes
Fixed the issue of sent duff CAN frame after call FLEXCAN_FDInit() API.
[2.5.2]
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
The bit field in CTRL1 register couldn’t calculate higher ideal SP, we set it as the lowest one(75%)
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
Fixed MISRA-C 2012 Rule 17.7 and 14.4.
Improvements
Pass EsrStatus to callback function when kStatus_FLEXCAN_ErrorStatus is comming.
[2.5.1]
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
FLEXCAN_CalculateImprovedTimingValues
FLEXCAN_FDCalculateImprovedTimingValues
[2.5.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-11.8, rule-12.2, rule-13.4, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-16.4, rule-17.3, rule-5.8, rule-8.3, rule-8.5.
Fixed the issue that API FLEXCAN_SetFDRxMbConfig lacks inactive message buff.
Fixed the issue of Pa082 warning.
Fixed the issue of dead lock in the function of interruption handler.
Fixed the issue of Legacy Rx Fifo EDMA transfer data fail in evkmimxrt1060 and evkmimxrt1064.
Fixed the issue of setting CANFD Bit Rate Switch.
Fixed the issue of operating unknown pointer risk.
when used the pointer “handle->mbFrameBuf[mbIdx]” to update the timestamp in a short-live TX frame, the frame pointer became as unknown, the action of operating it would result in program stack destroyed.
Added assert to check current CAN clock source affected by other clock gates in current device.
In some chips, CAN clock sources could be selected by CCM. But for some clock sources affected by other clock gates, if user insisted on using that clock source, they had to open these gates at the same time. However, they should take into consideration the power consumption issue at system level. In RT10xx chips, CAN clock source 2 was affected by the clock gate of lpuart1. ERRATA ID: (ERR050235 in CCM).
Improvements
Implementation for new FLEXCAN with ECC feature able to exit Freeze mode.
Optimized the function of interruption handler.
Added two APIs for FLEXCAN EDMA driver.
FLEXCAN_PrepareTransfConfiguration
FLEXCAN_StartTransferDatafromRxFIFO
Added new API for FLEXCAN driver.
FLEXCAN_GetTimeStamp
For TX non-blocking API, we wrote the frame into mailbox only, so no need to register TX frame address to the pointer, and the timestamp could be updated into the new global variable handle->timestamp[mbIdx], the FLEXCAN driver provided a new API for user to get it by handle and index number after TX DONE Success.
FLEXCAN_EnterFreezeMode
FLEXCAN_ExitFreezeMode
Added new configuration for user.
disableSelfReception
enableListenOnlyMode
Renamed the two clock source enum macros based on CLKSRC bit field value directly.
The CLKSRC bit value had no property about Oscillator or Peripheral type in lots of devices, it acted as two different clock input source only, but the legacy enum macros name contained such property, that misled user to select incorrect CAN clock source.
Created two new enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrc0
kFLEXCAN_ClkSrc1
Deprecated two legacy enum macros for the FLEXCAN driver.
kFLEXCAN_ClkSrcOsc
kFLEXCAN_ClkSrcPeri
Changed the process flow for Remote request frame response..
Created a new enum macro for the FLEXCAN driver.
kStatus_FLEXCAN_RxRemote
Changed the process flow for kFLEXCAN_StateRxRemote state in the interrupt handler.
Should the TX frame not register to the pointer of frame handle, interrupt handler would not be able to read the remote response frame from the mail box to ram, so user should read the frame by manual from mail box after a complete remote frame transfer.
[2.4.0]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-12.1, rule-17.7, rule-16.4, rule-11.9, rule-8.4, rule-14.4, rule-10.8, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-8.3, rule-12.2 and rule-16.1.
Fixed the issue that CANFD transfer data fail when bus baudrate is 30Khz.
Fixed the issue that ERR009595 does not folllow the ERRATA document.
Fixed code error for ERR006032 work around solution.
Fixed the Coverity issue of BAD_SHIFT in FLEXCAN.
Fixed the Repo build warning issue for variable without initial.
Improvements
Fixed the run fail issue of FlexCAN RemoteRequest UT Case.
Implementation all TX and RX transfering Timestamp used in FlexCAN demos.
Fixed the issue of UT Test Fail for CANFD payload size changed from 64BperMB to 8PerMB.
Implementation for improved timing API by baud rate.
[2.3.2]
Improvements
Implementation for ERR005959.
Implementation for ERR005829.
Implementation for ERR006032.
[2.3.1]
Bug Fixes
Added correct handle when kStatus_FLEXCAN_TxSwitchToRx is comming.
[2.3.0]
Improvements
Added self-wakeup support for STOP mode in the interrupt handling.
[2.2.3]
Bug Fixes
Fixed the issue of CANFD data phase’s bit rate not set as expected.
[2.2.2]
Improvements
Added a time stamp feature and enable it in the interrupt_transfer example.
[2.2.1]
Improvements
Separated CANFD initialization API.
In the interrupt handling, fix the issue that the user cannot use the normal CAN API when with an FD.
[2.2.0]
Improvements
Added FSL_FEATURE_FLEXCAN_HAS_SUPPORT_ENGINE_CLK_SEL_REMOVE feature to support SoCs without CAN Engine Clock selection in FlexCAN module.
Added FlexCAN Serial Clock Operation to support i.MX SoCs.
[2.1.0]
Bug Fixes
Corrected the spelling error in the function name FLEXCAN_XXX().
Moved Freeze Enable/Disable setting from FLEXCAN_Enter/ExitFreezeMode() to FLEXCAN_Init().
Corrected wrong helper macro values.
Improvements
Hid FLEXCAN_Reset() from user.
Used NDEBUG macro to wrap FLEXCAN_IsMbOccupied() function instead of DEBUG macro.
[2.0.0]
Initial version.
FLEXIO
[2.3.0]
Improvements
Supported platforms which don’t have DOZE mode control.
Added more pin control functions.
[2.2.3]
Improvements
Adapter the FLEXIO driver to platforms which don’t have system level interrupt controller, such as NVIC.
[2.2.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.1]
Improvements
Added doxygen index parameter comment in FLEXIO_SetClockMode.
[2.2.0]
New Features
Added new APIs to support FlexIO pin register.
[2.1.0]
Improvements
Added API FLEXIO_SetClockMode to set flexio channel counter and source clock.
[2.0.4]
Bug Fixes
Fixed MISRA 8.4 issues.
[2.0.3]
Bug Fixes
Fixed MISRA 10.4 issues.
[2.0.2]
Improvements
Split FLEXIO component which combines all flexio/flexio_uart/flexio_i2c/flexio_i2s drivers into several components: FlexIO component, flexio_uart component, flexio_i2c_master component, and flexio_i2s component.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.0.1]
Bug Fixes
Fixed the dozen mode configuration error in FLEXIO_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
FLEXIO_I2C
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Split some functions, fixed CCM problem in file fsl_flexio_i2c_master.c.
[2.4.0]
Improvements
Added delay of 1 clock cycle in FLEXIO_I2C_MasterTransferRunStateMachine to ensure that bus would be idle before next transfer if master is nacked.
Fixed issue that the restart setup time is less than the time in I2C spec by adding delay of 1 clock cycle before restart signal.
[2.3.0]
Improvements
Used 3 timers instead of 2 to support transfer which is more than 14 bytes in single transfer.
Improved FLEXIO_I2C_MasterTransferGetCount so that the API can check whether the transfer is still in progress.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Added an API for checking bus pin status.
Bug Fixes
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
Added codes in FLEXIO_I2C_MasterTransferCreateHandle to clear pending NVIC IRQ, disable internal IRQs before enabling NVIC IRQ.
Modified code so that during master’s nonblocking transfer the start and slave address are sent after interrupts being enabled, in order to avoid potential issue of sending the start and slave address twice.
[2.1.7]
Bug Fixes
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking did not wait for STOP bit sent.
Fixed COVERITY issue of useless call in FLEXIO_I2C_MasterTransferRunStateMachine.
Fixed the issue that I2C master did not check whether bus was busy before transfer.
[2.1.6]
Bug Fixes
Fixed the issue that I2C Master transfer APIs(blocking/non-blocking) did not support the situation of master transfer with subaddress and transfer data size being zero, which means no data followed the subaddress.
[2.1.5]
Improvements
Unified component full name to FLEXIO I2C Driver.
[2.1.4]
Bug Fixes
The following modifications support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.3]
Improvements
Changed the prototype of FLEXIO_I2C_MasterInit to return kStatus_Success if initialized successfully or to return kStatus_InvalidArgument if “(srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1” exceeds 0xFFU.
[2.1.2]
Bug Fixes
Fixed the FLEXIO I2C issue where the master could not receive data from I2C slave in high baudrate.
Fixed the FLEXIO I2C issue where the master could not receive NAK when master sent non-existent addr.
Fixed the FLEXIO I2C issue where the master could not get transfer count successfully.
Fixed the FLEXIO I2C issue where the master could not receive data successfully when sending data first.
Fixed the Dozen mode configuration error in FLEXIO_I2C_MasterInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Fixed the issue that FLEXIO_I2C_MasterTransferBlocking API called FLEXIO_I2C_MasterTransferCreateHandle, which lead to the s_flexioHandle/s_flexioIsr/s_flexioType variable being written. Then, if calling FLEXIO_I2C_MasterTransferBlocking API multiple times, the s_flexioHandle/s_flexioIsr/s_flexioType variable would not be written any more due to it being out of range. This lead to the following situation: NonBlocking transfer APIs could not work due to the fail of register IRQ.
[2.1.1]
Bug Fixes
Implemented the FLEXIO_I2C_MasterTransferBlocking API which is defined in header file but has no implementation in the C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S
[2.2.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.2.0]
New Features
Added timeout mechanism when waiting certain state in transfer API.
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed violations of the MISRA C-2012 rules 10.4, 14.4, 11.8, 11.9, 10.1, 17.7, 11.6, 10.3, 10.7.
[2.1.6]
Bug Fixes
Added reset flexio before flexio i2s init to make sure flexio status is normal.
[2.1.5]
Bug Fixes
Fixed the issue that I2S driver used hard code for bitwidth setting.
[2.1.4]
Improvements
Unified component’s full name to FLEXIO I2S (DMA/EDMA) driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
New Features
Added configure items for all pin polarity and data valid polarity.
Added default configure for pin polarity and data valid polarity.
[2.1.1]
Bug Fixes
Fixed FlexIO I2S RX data read error and eDMA address error.
Fixed FlexIO I2S slave timer compare setting error.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
FLEXIO_I2S_EDMA
[2.1.8]
Improvements
Applied EDMA ERRATA 51327.
FLEXIO_SPI
[2.4.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.3.5]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.4]
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.3]
Bugfixes
Fixed cs-continuous mode.
[2.3.2]
Improvements
Changed FLEXIO_SPI_DUMMYDATA to 0x00.
[2.3.1]
Bugfixes
Fixed IRQ SHIFTBUF overrun issue when one FLEXIO instance used as multiple SPIs.
[2.3.0]
New Features
Supported FLEXIO_SPI slave transfer with continuous master CS signal and CPHA=0.
Supported FLEXIO_SPI master transfer with continuous CS signal.
Support 32 bit transfer width.
Bug Fixes
Fixed wrong timer compare configuration for dma/edma transfer.
Fixed wrong byte order of rx data if transfer width is 16 bit, since the we use shifter buffer bit swapped/byte swapped register to read in received data, so the high byte should be read from the high bits of the register when MSB.
[2.2.1]
Bug Fixes
Fixed bug in FLEXIO_SPI_MasterTransferAbortEDMA that when aborting EDMA transfer EDMA_AbortTransfer should be used rather than EDMA_StopTransfer.
[2.2.0]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
Added codes in FLEXIO_SPI_MasterTransferCreateHandle and FLEXIO_SPI_SlaveTransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.1.3]
Improvements
Unified component full name to FLEXIO SPI(DMA/EDMA) Driver.
Bug Fixes
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.2]
Bug Fixes
The following modification support FlexIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer config instead of disabling module/clock.
Updated module Enable APIs to only support enable operation.
[2.1.1]
Bug Fixes
Fixed bug where FLEXIO SPI transfer data is in 16 bit per frame mode with eDMA.
Fixed bug when FLEXIO SPI works in eDMA and interrupt mode with 16-bit per frame and Lsbfirst.
Fixed the Dozen mode configuration error in FLEXIO_SPI_MasterInit/FLEXIO_SPI_SlaveInit API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Improvements
Added #ifndef/#endif to allow users to change the default TX value at compile time.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added transferSize in handle structure to record the transfer size.
Bug Fixes
Fixed the error register address return for 16-bit data write in FLEXIO_SPI_GetTxDataRegisterAddress.
Provided independent IRQHandler/transfer APIs for Master and slave to fix the baudrate limit issue.
FLEXIO_UART
[2.6.0]
Improvements
Supported platforms which don’t have DOZE mode control.
[2.5.1]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.0]
Improvements
Added API FLEXIO_UART_FlushShifters to flush UART fifo.
[2.4.0]
Improvements
Use separate data for TX and RX in flexio_uart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling FLEXIO_UART_TransferReceiveNonBlocking, the received data count returned by FLEXIO_UART_TransferGetReceiveCount is wrong.
[2.3.0]
Improvements
Added check for baud rate’s accuracy that returns kStatus_FLEXIO_UART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
Bug Fixes
Added codes in FLEXIO_UART_TransferCreateHandle to clear pending NVIC IRQ before enabling NVIC IRQ, to fix issue of pending IRQ interfering the on-going process.
[2.2.0]
Improvements
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.4 issues.
[2.1.6]
Bug Fixes
Fixed IAR Pa082 warnings.
Fixed MISRA issues
Fixed rules 10.1, 10.3, 10.4, 10.7, 11.6, 11.9, 14.4, 17.7.
[2.1.5]
Improvements
Triggered user callback after all the data in ringbuffer were received in FLEXIO_UART_TransferReceiveNonBlocking.
[2.1.4]
Improvements
Unified component full name to FLEXIO UART(DMA/EDMA) Driver.
[2.1.3]
Bug Fixes
The following modifications support FLEXIO using multiple instances:
Removed FLEXIO_Reset API in module Init APIs.
Updated module Deinit APIs to reset the shifter/timer configuration instead of disabling module and clock.
Updated module Enable APIs to only support enable operation.
[2.1.2]
Bug Fixes
Fixed the transfer count calculation issue in FLEXIO_UART_TransferGetReceiveCount, FLEXIO_UART_TransferGetSendCount, FLEXIO_UART_TransferGetReceiveCountDMA, FLEXIO_UART_TransferGetSendCountDMA, FLEXIO_UART_TransferGetReceiveCountEDMA and FLEXIO_UART_TransferGetSendCountEDMA.
Fixed the Dozen mode configuration error in FLEXIO_UART_Init API. For enableInDoze = true, the configuration should be 0; for enableInDoze = false, the configuration should be 1.
Added code to report errors if the user sets a too-low-baudrate which FLEXIO cannot reach.
Disabled FLEXIO_UART receive interrupt instead of all NVICs when reading data from ring buffer. If ring buffer is used, receive nonblocking will disable all NVIC interrupts to protect the ring buffer. This had negative effects on other IPs using interrupt.
[2.1.1]
Bug Fixes
Changed the API name FLEXIO_UART_StopRingBuffer to FLEXIO_UART_TransferStopRingBuffer to align with the definition in C file.
[2.1.0]
New Features
Added Transfer prefix in transactional APIs.
Added txSize/rxSize in handle structure to record the transfer size.
Bug Fixes
Added an error handle to handle the situation that data count is zero or data buffer is NULL.
FLEXIO_UART_EDMA
[2.3.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.3.0]
Refer FLEXIO_UART driver change log to 2.3.0
FLEXSPI
[2.6.3]
Bug Fixes
Fixed an issue which cause IPCR1[IPAREN] cleared by mistake.
[2.6.2]
Bug Fixes
Wait Bus IDLE before operation of FLEXSPI_SoftwareReset(), FLEXSPI_TransferBlocking() and FLEXSPI_TransferNonBlocking().
[2.6.1]
Bug Fixes
Updated code of reset peripheral.
Updated FLEXSPI_UpdateLUT() to check if input lut address is not in Flexspi AMBA region.
Updated FLEXSPI_Init() to check if input AHB buffer size exceeded maximum AHB size.
[2.6.0]
New Features
Added new API to set AHB memory-mapped flash base address.
Added support of DLLxCR[REFPHASEGAP] bit field, it is recommended to set it as 0x2 if DLL calibration is enabled.
[2.5.1]
Bugfixes
Fixed handling of W1C bits in the INTR register
Removed FIFO resets from FLEXSPI_CheckAndClearError
FLEXSPI_TransferBlocking is observing IPCMDDONE and then fetches the final status of the transfer
Fixed issue that FLEXSPI2_DriverIRQHandler not defined.
[2.5.0]
Improvements
Supported word un-aligned access for write/read blocking/non-blocking API functions.
Fixed dead loop issue in DLL update function when using FRO clock source.
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.4.0]
Improvements
Isolated IP command parallel mode and AHB command parallel mode using feature MACRO.
Supported new column address shift feature for external memory.
[2.3.5]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.2.
[2.3.4]
Bug Fixes
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_CONBINATION.
[2.3.3]
Bug Fixes
Removed feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS for DLL delay setting. Changed to use feature FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN to set slave delay target as 0 for DLL enable and clock frequency higher than 100MHz.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 8.4, 8.5, 10.1, 10.3, 10.4, 11.6 and 14.4.
[2.3.1]
Bug Fixes
Wait for bus to be idle before using it as access to external flash with new setting in FLEXSPI_SetFlashConfig() API.
Fixed the potential buffer overread and Tx FIFO overwrite issue in FLEXSPI_WriteBlocking.
[2.3.0]
New Features
Added new API FLEXSPI_UpdateDllValue for users to update DLL value after updating flexspi root clock.
Corrected grammatical issues for comments.
Added support for new feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS in DLL configuration.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3 and 10.4.
Updated _flexspi_command from named enumerator into anonymous enumerator.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8, 11.9, 14.4, 15.7, 16.4, 17.7, 7.3.
Fixed IAR build warning Pe167.
Fixed the potential buffer overwrite and Rx FIFO overread issue in FLEXSPI_ReadBlocking.
[2.2.0]
Bug Fixes
Fixed flag name typos: kFLEXSPI_IpTxFifoWatermarkEmpltyFlag to kFLEXSPI_IpTxFifoWatermarkEmptyFlag; kFLEXSPI_IpCommandExcutionDoneFlag to kFLEXSPI_IpCommandExecutionDoneFlag.
Fixed comments typos such as sequencen->sequence, levle->level.
Fixed FLSHCR2[ARDSEQID] field clean issue.
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN and FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN.
Updated flexspi_flags_t structure to support new feature FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN.
[2.1.1]
Improvements
Defaulted enable prefetch for AHB RX buffer configuration in FLEXSPI_GetDefaultConfig, which is align with the reset value in AHBRXBUFxCR0.
Added software workaround for ERR011377 in FLEXSPI_SetFlashConfig; added some delay after DLL lock status set to ensure correct data read/write.
[2.1.0]
New Features
Added new API FLEXSPI_UpdateRxSampleClock for users to update read sample clock source after initialization.
Added reset peripheral operation in FLEXSPI_Init if required.
[2.0.5]
Bug Fixes
Fixed FLEXSPI_UpdateLUT cannot do partial update issue.
[2.0.4]
Bug Fixes
Reset flash size to zero for all ports in FLEXSPI_Init; fixed the possible out-of-range flash access with no error reported.
[2.0.3]
Bug Fixes
Fixed AHB receive buffer size configuration issue. The FLEXSPI_AHBRXBUFCR0_BUFSZ field should configure 64 bits size, and currently the AHB receive buffer size is in bytes which means 8-bit, so the correct configuration should be config->ahbConfig.buffer[i].bufferSize / 8.
[2.0.2]
New Features
Supported DQS write mask enable/disable feature during set FLEXSPI configuration.
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
Bug Fixes
Fixed invalid operation of FLEXSPI_Init to enable AHB bus Read Access to IP RX FIFO.
Fixed incorrect operation of FLEXSPI_Init to configure IP TX FIFO watermark.
[2.0.1]
Bug Fixes
Fixed the flag clear issue and AHB read Command index configuration issue in FLEXSPI_SetFlashConfig.
Updated FLEXSPI_UpdateLUT function to update LUT table from any index instead of previous command index.
Added bus idle wait in FLEXSPI_SetFlashConfig and FLEXSPI_UpdateLUT to ensure bus is idle before any change to FlexSPI controller.
Updated interrupt API FLEXSPI_TransferNonBlocking and interrupt handle flow FLEXSPI_TransferHandleIRQ.
Updated eDMA API FLEXSPI_TransferEDMA.
[2.0.0]
Initial version.
FLEXSPI EDMA Driver
[2.3.3]
Bug Fixes
Fixed FLEXSPI_TransferEDMA bug that, the DMA channel not configured correctly when using kFLEXSPI_Read.
[2.3.2]
Bug Fixes
Fixed the bug that internal variable s_edmaPrivateHandle overflows when using FlexSPI2.
[2.0.2]
New Features
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
[2.0.0]
Initial version.
FLEXSPI_FLR
[1.0.0]
Initial version.
GPC
[2.1.0]
Improvements
Added GPC_SS_SoftwareTriggerPMICStandby() function.
Added GPC_SS_SystemSleepTriggerPMICStandby() function.
[2.0.0]
Initial version.
GPT
[2.0.5]
Improvements
Support workaround for ERR003777. This workaround helps switching the clock sources.
[2.0.4]
Bug Fixes
Fixed compiler warning when built with FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL flag enabled.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 5.3 by customizing function parameter.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.8, 17.7.
[2.0.0]
Initial version.
I3C
[2.13.1]
Bug Fixes
Disabled Rx auto-termination in repeated start interrupt event while transfer API doesn’t enable it.
Waited the completion event after loading all Tx data in Tx FIFO.
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
New features
Added the hot-join support for I3C bus initialization API.
Bug Fixes
Set read termination with START at the same time in case unknown issue.
Set MCTRL[TYPE] as 0 for DDR force exit.
Improvements
Added the API to reset device count assigned by ENTDAA.
Provided the method to set global macro I3C_MAX_DEVCNT to determine how many device addresses ENTDAA can allocate at one time.
Initialized target management static array based on instance number for the case that multiple instances are used at the same time.
[2.12.0]
Improvements
Added the slow clock parameter for Controller initialization function to calculate accurate timeout.
Bug Fixes
Fixed the issue that BAMATCH field can’t be 0. BAMATCH should be 1 for 1MHz slow clock.
[2.11.1]
Bug Fixes
Fixed the issue that interrupt API transmits extra byte when subaddress and data size are null.
Fixed the slow clock calculation issue.
[2.11.0]
New features
Added the START/ReSTART SCL delay setting for the Soc which supports this feature.
Bug Fixes
Fixed the issue that ENTDAA process waits Rx pending flag which causes problem when Rx watermark isn’t 0. Just check the Rx FIFO count.
[2.10.8]
Improvements
Support more instances.
[2.10.7]
Improvements
Fixed the potential compile warning.
[2.10.6]
New features
Added the I3C private read/write with 0x7E address as start.
[2.10.5]
New features
Added I3C HDR-DDR transfer support.
[2.10.4]
Improvements
Added one more option for master to not set RDTERM when doing I3C Common Command Code transfer.
[2.10.3]
Improvements
Masked the slave IBI/MR/HJ request functions with feature macro.
[2.10.2]
Bug Fixes
Added workaround for errata ERR051617: I3C working with I2C mode creates the unintended Repeated START before actual STOP on some platforms.
[2.10.1]
Bug Fixes
Fixed the issue that DAA function doesn’t wait until all Rx data is read out from FIFO after master control done flag is set.
Fixed the issue that DAA function could return directly although the disabled interrupts are not enabled back.
[2.10.0]
New features
Added I3C extended IBI data support.
[2.9.0]
Improvements
Added adaptive termination for master blocking transfer. Set termination with start signal when receiving bytes less than 256.
[2.8.2]
Improvements
Fixed the build warning due to armgcc strict check.
[2.8.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.8.0]
Improvements
Added API I3C_MasterProcessDAASpecifiedBaudrate for temporary baud rate adjustment when I3C master assigns dynamic address.
[2.7.1]
Bug Fixes
Fixed the issue that I3C slave handle STOP event before finishing data transmission.
[2.7.0]
Fixed the CCM problem in file fsl_i3c.c.
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in I3C_GetDefaultConfig and I3C_Init.
[2.6.0]
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in fsl_i3c.h.
Changed some static functions in fsl_i3c.c as non-static and define the functions in fsl_i3c.h to make I3C DMA driver reuse:
I3C_GetIBIType
I3C_GetIBIAddress
I3C_SlaveCheckAndClearError
Changed the handle pointer parameter in IRQ related funtions to void * type to make it reuse in I3C DMA driver.
Added new API I3C_SlaveRequestIBIWithSingleData for slave to request single data byte, this API could be used regardless slave is working in non-blocking interrupt or non-blocking dma.
Added new API I3C_MasterGetDeviceListAfterDAA for master application to get the device information list built up in DAA process.
[2.5.4]
Improved I3C driver to avoid setting state twice in the SendCommandState of I3C_RunTransferStateMachine.
Fixed MISRA violation of rule 20.9.
Fixed the issue that I3C_MasterEmitRequest did not use Type I3C SDR.
[2.5.3]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH and FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND.
[2.5.2]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM.
Fixed the issue that call to I3C_MasterTransferBlocking API did not generate STOP signal when NAK status was returned.
[2.5.1]
Improved the receive terminate size setting for interrupt transfer read, now it’s set at beginning of transfer if the receive size is less than 256 bytes.
[2.5.0]
Added new API I3C_MasterRepeatedStartWithRxSize to send repeated start signal with receive terminate size specified.
Fixed the status used in I3C_RunTransferStateMachine, changed to use pending interrupts as status to be handled in the state machine.
Fixed MISRA 2012 violation of rule 10.3, 10.7.
[2.4.0]
Bug Fixes
Fixed kI3C_SlaveMatchedFlag interrupt is not properly handled in I3C_SlaveTransferHandleIRQ when it comes together with interrupt kI3C_SlaveBusStartFlag.
Fixed the inaccurate I2C baudrate calculation in I3C_MasterSetBaudRate.
Added new API I3C_MasterGetIBIRules to get registered IBI rules.
Added new variable isReadTerm in struct _i3c_master_handle for transfer state routine to check if MCTRL.RDTERM is configured for read transfer.
Changed to emit Auto IBI in transfer state routine for slave start flag assertion.
Fixed the slave maxWriteLength and maxReadLength does not be configured into SMAXLIMITS register issue.
Fixed incorrect state for IBI in I3C master interrupt transfer IRQ handle routine.
Added isHotJoin in i3c_slave_config_t to request hot-join event during slave init.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 17.7.
Fixed incorrect HotJoin event index in I3C_GetIBIType.
[2.3.1]
Bug Fixes
Fixed the issue that call of I3C_MasterTransferBlocking/I3C_MasterTransferNonBlocking fails for the case which receive length 1 byte of data.
Fixed the issue that STOP signal is not sent when NAK status is detected during execution of I3C_MasterTransferBlocking function.
[2.3.0]
Improvements
Added I3C common driver APIs to initialize I3C with both master and slave configuration.
Updated I3C master transfer callback to function set structure to include callback invoke for IBI event and slave2master event.
Updated I3C master non-blocking transfer model and always enable the interrupts to be able to re-act to the slave start event and handle slave IBI.
[2.2.0]
Bug Fixes
Fixed the issue that I3C transfer size limit to 255 bytes.
[2.1.2]
Bug Fixes
Reset default hkeep value to kI3C_MasterHighKeeperNone in I3C_MasterGetDefaultConfig
[2.1.1]
Bug Fixes
Fixed incorrect FIFO reset operation in I3C Master Transfer APIs.
Fixed i3c slave IRQ handler issue, slave transmit could be underrun because tx FIFO is not filled in time right after start flag detected.
[2.1.0]
Added definitions and APIs for I3C slave functionality, updated previous I3C APIs to support I3C functionality.
[2.0.0]
Initial version.
I3C_EDMA
[2.2.9]
Bug Fixes
Fixed MISRA issue rule 11.3.
Added the master control done flag waiting code after STOP in case the bus is not idle when transfer function finishes.
[2.2.8]
Improvements
Removed I3C IRQ handler calling in the EDMA callback. Previously driver doesn’t use the END byte which can trigger the STOP interrupt for controller sending and receiving, now let I3C event handler deal with all I3C events.
Bug Fixes
Fixed the bug that the END type Tx register is not used when command length or data length is one byte.
[2.2.7]
Bug Fixes
Fixed MISRA issue rule 11.6.
[2.2.6]
New features
Added the I3C private read/write with 0x7E address as start.
[2.2.5]
Improvements
Added the workaround for RT1180 I3C EDMA issue ERR052086.
[2.2.4]
Bug Fixes
Fixed the issue that I3C master sends the last byte data without using the END type register.
[2.2.3]
Bug Fixes
Fixed issue that slave polulates the last byte when Tx FIFO may be full.
[2.2.2]
Bug Fixes
Fixed I3C MISRA issue rule 10.4, 11.3.
[2.2.1]
Bug Fixes
Fixed the issue that I3C slave send the last byte data without using the END type register.
Improvements
There’s no need to reserve two bytes FIFO for DMA transfer which is for IP issue workaround.
[2.2.0]
Improvements
Deleted legacy IBI data request code.
[2.1.0]
Bug Fixes
Fixed MISRA issue rule 8.4, 8.6, 11.8.
[2.0.1]
Bug Fixes
Fixed MISRA issue rule 9.1.
[2.0.0]
Initial version.
IEE
[2.1.1]
Fixed MISRA issues.
[2.1.0]
Add region lock function IEE_LockRegionConfig() and driver clock control.
[2.0.0]
Initial version.
IEE_APC
[2.0.2]
Updated to newer version of implementation in HW.
[2.0.1]
Fixed MISRA issues.
[2.0.0]
Initial version.
IOMUXC
[2.0.1]
Doxygen improvement.
[2.0.0]
Initial version.
KPP
[2.0.1]
Bug Fixes
Fixed the violations of MISRA 2012 rules:
Rule 10.3 10.4 10.6 14.4 17.7
[2.0.0]
Initial version.
LPADC
[2.9.1]
Bug Fixes
Fixed incorrect channel B FIFO selection logic.
[2.9.0]
Bug Fixes
Add code to handle the case where GCC[GAIN_CAL] is a signed number.
Split LPADC_FinishAutoCalibration function into two functions.
Improved LPADC driver.
[2.8.4]
Bug Fixes
Remove function ‘LPADC_SetOffsetValue’ assert statement, this statement may cause runtime errors in existing code.
[2.8.3]
Bug Fixes
Fixed SDK lpadc driver examples compile issue, move condition ‘commandId < ADC_CV_COUNT’ to a more appropriate location.
[2.8.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rule 18.1, 10.3, 10.1 and 10.4.
[2.8.1]
Bug Fixes
Fixed LPADC sample mode enum name mistake.
[2.8.0]
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed function LPADC_GetConvResult() issue.
Fixed function LPADC_SetConvCommandConfig() bugs.
[2.7.2]
Improvements
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.1]
Improvements
Corrected descriptions of several functions.
Improved function LPADC_GetOffsetValue and LPADC_SetOffsetValue.
Revert changes of feature macros for lpadc.
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.8.
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.0]
Improvements
Added supports of CFG2 register.
Removed some useless macros.
[2.6.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rules.
Fixed LPADC driver code compile error issue.
[2.6.1]
Improvements
Updated the use of macros in the driver code.
[2.6.0]
Improvements
Added the API LPADC_SetOffset12BitValue() to configure 12bit ADC conversion offset trim value manually.
Added the API LPADC_SetOffset16BitValue() to configure 16bit ADC conversion offset trim value manually.
Added API to set offset calibration mode.
Added configuration of alternate channel.
Updated auto calibration API and added calibration value conversion API.
New feature
Added API LPADC_EnableHardwareTriggerCommandSelection() to enable trigger commands controlled by ADC_ETC.
Updated LPADC_DoAutoCalibration() to allow doing something else before the ADC inititialization to be totally complete. Enhance initialization duration time of the ADC.
Added two new APIs to get/set calibration value.
[2.5.2]
Improvements
Added while loop, LPADC_GetConvResult() will return only when the FIFO will not be empty.
[2.5.1]
Bug Fixes
Fixed some typos in Lpadc driver comments.
[2.5.0]
Improvements
Added missing items to enable trigger interrupts.
[2.4.0]
New features
Added APIs to get/clear trigger status flags.
[2.3.0]
Improvements
Removed LPADC_MeasureTemperature() function for the LPADC supports different temperature sensor calculation equations.
[2.2.1]
Improvements
Optimized LPADC_MeasureTemperature() function to support the specific series with flash solidified calibration value.
Clean doxygen warnings.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, rule 10.8 and rule 17.7.
[2.2.0]
New Feature
Added API LPADC_MeasureTemperature() to get correct temperature from the internal sensor.
Improvements
Separated lpadc_conversion_resolution_mode_t with related feature macro.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.3, 10.4, 10.6, 10.7 and 17.7.
[2.1.1]
Improvements
Updated the gain calibration formula.
Used feature to segregate the new item kLPADC_TriggerPriorityPreemptSubsequently.
[2.1.0]
New Features
Added the API LPADC_SetOffsetValue() to support configure offset trim value manually.
Added the API LPADC_DoOffsetCalibration() to do offset calibration independently.
Improvements
Improved the usage of macros and removed invalid macros.
[2.0.2]
Improvements
Added support for platforms with 2 FIFOs and different calibration measures.
[2.0.1]
Bug Fixes
Ensured the API LPADC_SetConvCommandConfig configure related registers correctly.
[2.0.0]
Initial version.
LPI2C
[2.5.7]
Improvements
Added support for separated IRQ handlers.
[2.5.6]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.5.5]
Bug Fixes
Fixed LPI2C_SlaveInit() - allow to disable SDA/SCL glitch filter.
[2.5.4]
Bug Fixes
Fixed LPI2C_MasterTransferBlocking() - the return value was sometime affected by call of LPI2C_MasterStop().
[2.5.3]
Improvements
Added handler for LPI2C7 and LPI2C8.
[2.5.2]
Bug Fixes
Fixed ERR051119 to ignore the nak flag when IGNACK=1 in LPI2C_MasterCheckAndClearError.
[2.5.1]
Bug Fixes
Added bus stop incase of bus stall in LPI2C_MasterTransferBlocking.
Improvements
Release peripheral from reset if necessary in init function.
[2.5.0]
New Features
Added new function LPI2C_SlaveEnableAckStall to enable or disable ACKSTALL.
[2.4.1]
Improvements
Before master transfer with transactional APIs, enable master function while disable slave function and vise versa for slave transfer to avoid the one affecting the other.
[2.4.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpi2c.c.
Bug Fixes
Fixed bug in LPI2C_MasterInit that the MCFGR2’s value set in LPI2C_MasterSetBaudRate may be overwritten by mistake.
[2.3.2]
Improvements
Initialized the EDMA configuration structure in the LPI2C EDMA driver.
[2.3.1]
Improvements
Updated LPI2C_GetCyclesForWidth to add the parameter of minimum cycle, because for master SDA/SCL filter, master bus idle/pin low timeout and slave SDA/SCL filter configuration, 0 means disabling the feature and cannot be used.
Bug Fixes
Fixed bug in LPI2C_SlaveTransferHandleIRQ that when restart detect event happens the transfer structure should not be cleared.
Fixed bug in LPI2C_RunTransferStateMachine, that when only slave address is transferred or there is still data remaining in tx FIFO the last byte’s nack cannot be ignored.
Fixed bug in slave filter doze enable, that when FILTDZ is set it means disable rather than enable.
Fixed bug in the usage of LPI2C_GetCyclesForWidth. First its return value cannot be used directly to configure the slave FILTSDA, FILTSCL, DATAVD or CLKHOLD, because the real cycle width for them should be FILTSDA+3, FILTSCL+3, FILTSCL+DATAVD+3 and CLKHOLD+3. Second when cycle period is not affected by the prescaler value, prescaler value should be passed as 0 rather than 1.
Fixed wrong default setting for LPI2C slave. If enabling the slave tx SCL stall, then the default clock hold time should be set to 250ns according to I2C spec for 100kHz standard mode baudrate.
Fixed bug that before pushing command to the tx FIFO the FIFO occupation should be checked first in case FIFO overflow.
[2.3.0]
New Features
Supported reading more than 256 bytes of data in one transfer as master.
Added API LPI2C_GetInstance.
Bug Fixes
Fixed bug in LPI2C_MasterTransferAbortEDMA, LPI2C_MasterTransferAbort and LPI2C_MasterTransferHandleIRQ that before sending stop signal whether master is active and whether stop signal has been sent should be checked, to make sure no FIFO error or bus error will be caused.
Fixed bug in LPI2C master EDMA transactional layer that the bus error cannot be caught and returned by user callback, by monitoring bus error events in interrupt handler.
Fixed bug in LPI2C_GetCyclesForWidth that the parameter used to calculate clock cycle should be 2^prescaler rather than prescaler.
Fixed bug in LPI2C_MasterInit that timeout value should be configured after baudrate, since the timeout calculation needs prescaler as parameter which is changed during baudrate configuration.
Fixed bug in LPI2C_MasterTransferHandleIRQ and LPI2C_RunTransferStateMachine that when master writes with no stop signal, need to first make sure no data remains in the tx FIFO before finishes the transfer.
[2.2.0]
Bug Fixes
Fixed issue that the SCL high time, start hold time and stop setup time do not meet I2C specification, by changing the configuration of data valid delay, setup hold delay, clock high and low parameters.
MISRA C-2012 issue fixed.
Fixed rule 8.4, 13.5, 17.7, 20.8.
[2.1.12]
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.1.11]
Bug Fixes
Fixed the bug that, during master non-blocking transfer, after the last byte is sent/received, the kLPI2C_MasterNackDetectFlag is expected, so master should not check and clear kLPI2C_MasterNackDetectFlag when remainingBytes is zero, in case FIFO is emptied when stop command has not been sent yet.
Fixed the bug that, during non-blocking transfer slave may nack master while master is busy filling tx FIFO, and NDF may not be handled properly.
[2.1.10]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rule 10.3, 14.4, 15.5.
Fixed unaligned access issue in LPI2C_RunTransferStateMachine.
Fixed uninitialized variable issue in LPI2C_MasterTransferHandleIRQ.
Used linked TCD to disable tx and enable rx in read operation to fix the issue that for platform sharing the same DMA request with tx and rx, during LPI2C read operation if interrupt with higher priority happened exactly after command was sent and before tx disabled, potentially both tx and rx could trigger dma and cause trouble.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 11.6, 11.9, 14.4, 17.7.
Fixed the waitTimes variable not re-assignment issue for each byte read.
New Features
Added the IRQHandler for LPI2C5 and LPI2C6 instances.
Improvements
Updated the LPI2C_WAIT_TIMEOUT macro to unified name I2C_RETRY_TIMES.
[2.1.9]
Bug Fixes
Fixed Coverity issue of unchecked return value in I2C_RTOS_Transfer.
Fixed Coverity issue of operands did not affect the result in LPI2C_SlaveReceive and LPI2C_SlaveSend.
Removed STOP signal wait when NAK detected.
Cleared slave repeat start flag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved repeat start flag. This caused the next slave to send a break, and the master was always in the receive data status, but could not receive data.
[2.1.8]
Bug Fixes
Fixed the transfer issue with LPI2C_MasterTransferNonBlocking, kLPI2C_TransferNoStopFlag, with the wait transfer done through callback in a way of not doing a blocking transfer.
Fixed the issue that STOP signal did not appear in the bus when NAK event occurred.
[2.1.7]
Bug Fixes
Cleared the stopflag before transmission started in LPI2C_SlaveSend/LPI2C_SlaveReceive. The issue was that LPI2C_SlaveSend/LPI2C_SlaveReceive did not handle with the reserved stop flag and caused the next slave to send a break, and the master always stayed in the receive data status but could not receive data.
[2.1.6]
Bug Fixes
Fixed driver MISRA build error and C++ build error in LPI2C_MasterSend and LPI2C_SlaveSend.
Reset FIFO in LPI2C Master Transfer functions to avoid any byte still remaining in FIFO during last transfer.
Fixed the issue that LPI2C_MasterStop did not return the correct NAK status in the bus for second transfer to the non-existing slave address.
[2.1.5]
Bug Fixes
Extended the Driver IRQ handler to support LPI2C4.
Changed to use ARRAY_SIZE(kLpi2cBases) instead of FEATURE COUNT to decide the array size for handle pointer array.
[2.1.4]
Bug Fixes
Fixed the LPI2C_MasterTransferEDMA receive issue when LPI2C shared same request source with TX/RX DMA request. Previously, the API used scatter-gather method, which handled the command transfer first, then the linked TCD which was pre-set with the receive data transfer. The issue was that the TX DMA request and the RX DMA request were both enabled, so when the DMA finished the first command TCD transfer and handled the receive data TCD, the TX DMA request still happened due to empty TX FIFO. The result was that the RX DMA transfer would start without waiting on the expected RX DMA request.
Fixed the issue by enabling IntMajor interrupt for the command TCD and checking if there was a linked TCD to disable the TX DMA request in LPI2C_MasterEDMACallback API.
[2.1.3]
Improvements
Added LPI2C_WATI_TIMEOUT macro to allow the user to specify the timeout times for waiting flags in functional API and blocking transfer API.
Added LPI2C_MasterTransferBlocking API.
[2.1.2]
Bug Fixes
In LPI2C_SlaveTransferHandleIRQ, reset the slave status to idle when stop flag was detected.
[2.1.1]
Bug Fixes
Disabled the auto-stop feature in eDMA driver. Previously, the auto-stop feature was enabled at transfer when transferring with stop flag. Since transfer was without stop flag and the auto-stop feature was enabled, when starting a new transfer with stop flag, the stop flag would be sent before the new transfer started, causing unsuccesful sending of the start flag, so the transfer could not start.
Changed default slave configuration with address stall false.
[2.1.0]
Improvements
API name changed:
LPI2C_MasterTransferCreateHandle -> LPI2C_MasterCreateHandle.
LPI2C_MasterTransferGetCount -> LPI2C_MasterGetTransferCount.
LPI2C_MasterTransferAbort -> LPI2C_MasterAbortTransfer.
LPI2C_MasterTransferHandleIRQ -> LPI2C_MasterHandleInterrupt.
LPI2C_SlaveTransferCreateHandle -> LPI2C_SlaveCreateHandle.
LPI2C_SlaveTransferGetCount -> LPI2C_SlaveGetTransferCount.
LPI2C_SlaveTransferAbort -> LPI2C_SlaveAbortTransfer.
LPI2C_SlaveTransferHandleIRQ -> LPI2C_SlaveHandleInterrupt.
[2.0.0]
Initial version.
LPI2C_EDMA
[2.4.3]
Improvements
Added support for separated IRQ handlers.
[2.4.2]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.1]
Refer LPI2C driver change log 2.0.0 to 2.4.1
LPIT
[2.1.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.0]
Improvements
Add new function LPIT_SetTimerValue to set timeout period.
[2.0.2]
Improvements
Improved LPIT_SetTimerPeriod implementation, configure timeout value with LPIT ticks minus 1 generate more correct interval.
Added timeout value configuration check for LPIT_SetTimerPeriod, at least input 3 ticks for calling LPIT_SetTimerPeriod.
Bug Fixes
Fixed MISRA C-2012 rule 17.7 violations.
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rules, containing: rule-10.3, rule-14.4, rule-15.5.
[2.0.0]
Initial version.
LPSPI
[2.6.10]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.6.9]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.6.8]
Bug Fixes
Fixed build error when SPI_RETRY_TIMES is defined to non-zero value.
[2.6.7]
Bug Fixes
Fixed the txData from void * to const void * in transmit API _lpspi_master_handle and _lpspi_slave_handle.
[2.6.6]
Bug Fixes
Added LPSPI register init in LPSPI_MasterInit incase of LPSPI register exist.
[2.6.5]
Improvements
Introduced FSL_FEATURE_LPSPI_HAS_NO_PCSCFG and FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH for conditional compile.
Release peripheral from reset if necessary in init function.
[2.6.4]
Bug Fixes
Added LPSPI6_DriverIRQHandler for LPSPI6 instance.
[2.6.3]
Hot Fixes
Added macro switch in function LPSPI_Enable about ERRATA051472.
[2.6.2]
Bug Fixes
Disabled lpspi before LPSPI_MasterSetBaudRate incase of LPSPI opened.
[2.6.1]
Bug Fixes
Fixed return value while calling LPSPI_WaitTxFifoEmpty in function LPSPI_MasterTransferNonBlocking.
[2.6.0]
Feature
Added the new feature of multi-IO SPI .
[2.5.3]
Bug Fixes
Fixed 3-wire txmask of handle vaule reentrant issue.
[2.5.2]
Bug Fixes
Workaround for errata ERR051588 by clearing FIFO after transmit underrun occurs.
[2.5.1]
Bug Fixes
Workaround for errata ERR050456 by resetting the entire module using LPSPIn_CR[RST] bit.
[2.5.0]
Bug Fixes
Workaround for errata ERR011097 to wait the TX FIFO to go empty when writing TCR register and TCR[TXMSK] value is 1.
Added API LPSPI_WaitTxFifoEmpty for wait the txfifo to go empty.
[2.4.7]
Bug Fixes
Fixed bug that the SR[REF] would assert if software disabled or enabled the LPSPI module in LPSPI_Enable.
[2.4.6]
Improvements
Moved the configuration of registers for the 3-wire lpspi mode to the LPSPI_MasterInit and LPSPI_SlaveInit function.
[2.4.5]
Improvements
Improved LPSPI_MasterTransferBlocking send performance when frame size is 1-byte.
[2.4.4]
Bug Fixes
Fixed LPSPI_MasterGetDefaultConfig incorrect default inter-transfer delay calculation.
[2.4.3]
Bug Fixes
Fixed bug that the ISR response speed is too slow on some platforms, resulting in the first transmission of overflow, Set proper RX watermarks to reduce the ISR response times.
[2.4.2]
Bug Fixes
Fixed bug that LPSPI_MasterTransferBlocking will modify the parameter txbuff and rxbuff pointer.
[2.4.1]
Bug Fixes
Fixed bug that LPSPI_SlaveTransferNonBlocking can’t detect RX error.
[2.4.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpspi.c.
[2.3.1]
Improvements
Initialized the EDMA configuration structure in the LPSPI EDMA driver.
Bug Fixes
Fixed bug that function LPSPI_MasterTransferBlocking should return after the transfer complete flag is set to make sure the PCS is re-asserted.
[2.3.0]
New Features
Supported the master configuration of sampling the input data using a delayed clock to improve slave setup time.
[2.2.1]
Bug Fixes
Fixed bug in LPSPI_SetPCSContinous when disabling PCS continous mode.
[2.2.0]
Bug Fixes
Fixed bug in 3-wire polling and interrupt transfer that the received data is not correct and the PCS continous mode is not working.
[2.1.0]
Improvements
Improved LPSPI_SlaveTransferHandleIRQ to fill up TX FIFO instead of write one data to TX register which improves the slave transmit performance.
Added new functional APIs LPSPI_SelectTransferPCS and LPSPI_SetPCSContinous to support changing PCS selection and PCS continous mode.
Bug Fixes
Fixed bug in non-blocking and EDMA transfer APIs that kStatus_InvalidArgument is returned if user configures 3-wire mode and full-duplex transfer at the same time, but transfer state is already set to kLPSPI_Busy by mistake causing following transfer can not start.
Fixed bug when LPSPI slave using EDMA way to transfer, tx should be masked when tx data is null, otherwise in 3-wire mode which tx/rx use the same pin, the received data will be interfered.
[2.0.5]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed the bug that LPSPI can not transfer large data using EDMA.
Fixed MISRA 17.7 issues.
Fixed variable overflow issue introduced by MISRA fix.
Fixed issue that rxFifoMaxBytes should be calculated according to transfer width rather than FIFO width.
Fixed issue that completion flag was not cleared after transfer completed.
[2.0.4]
Bug Fixes
Fixed in LPSPI_MasterTransferBlocking that master rxfifo may overflow in stall condition.
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.6, 11.9, 14.2, 14.4, 15.7, 17.7.
[2.0.3]
Bug Fixes
Removed LPSPI_Reset from LPSPI_MasterInit and LPSPI_SlaveInit, because this API may glitch the slave select line. If needed, call this function manually.
[2.0.2]
New Features
Added dummy data set up API to allow users to configure the dummy data to be transferred.
Enabled the 3-wire mode, SIN and SOUT pins can be configured as input/output pin.
[2.0.1]
Bug Fixes
Fixed the bug that the clock source should be divided by the PRESCALE setting in LPSPI_MasterSetDelayTimes function.
Fixed the bug that LPSPI_MasterTransferBlocking function would hang in some corner cases.
Optimization
Added #ifndef/#endif to allow user to change the default TX value at compile time.
[2.0.0]
Initial version.
LPSPI_EDMA
[2.4.6]
Improvements
Increased transmit FIFO watermark to ensure whole transmit FIFO will be used during data transfer.
[2.4.5]
Bug Fixes
Fixed reading of TCR register
Workaround for errata ERR050606
[2.4.4]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.4.3]
Improvements
Supported 32K bytes transmit in DMA, improve the max datasize in LPSPI_MasterTransferEDMALite.
[2.4.2]
Improvements
Added callback status in EDMA_LpspiMasterCallback and EDMA_LpspiSlaveCallback to check transferDone.
[2.4.1]
Improvements
Add the TXMSK wait after TCR setting.
[2.4.0]
Improvements
Separated LPSPI_MasterTransferEDMA functions to LPSPI_MasterTransferPrepareEDMA and LPSPI_MasterTransferEDMALite to optimize the process of transfer.
LPTMR
[2.2.0]
Improvements
Updated lptmr_prescaler_clock_select_t, only define the valid options.
[2.1.1]
Improvements
Updated the characters from “PTMR” to “LPTMR” in “FSL_FEATURE_PTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT” feature definition.
[2.1.0]
Improvements
Implement for some special devices’ not supporting for all clock sources.
Bug Fixes
Fixed issue when accessing CMR register.
[2.0.2]
Bug Fixes
Fixed MISRA-2012 issues.
Rule 10.1.
[2.0.1]
Improvements
Updated the LPTMR driver to support 32-bit CNR and CMR registers in some devices.
[2.0.0]
Initial version.
LPUART
[2.9.0]
New Feature
Added support for swap TXD and RXD pins.
[2.8.3]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.8.2]
Bug Fix
Fixed the bug that LPUART_TransferEnable16Bit controled by wrong feature macro.
[2.8.1]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-5.3, rule-5.8, rule-10.4, rule-11.3, rule-11.8.
[2.8.0]
Improvements
Added support of DATA register for 9bit or 10bit data transmit in write and read API. Such as: LPUART_WriteBlocking16bit, LPUART_ReadBlocking16bit, LPUART_TransferEnable16Bit LPUART_WriteNonBlocking16bit, LPUART_ReadNonBlocking16bit.
[2.7.7]
Bug Fixes
Fixed the bug that baud rate calculation overflow when srcClock_Hz is 528MHz.
[2.7.6]
Bug Fixes
Fixed LPUART_EnableInterrupts and LPUART_DisableInterrupts bug that blocks if the LPUART address doesn’t support exclusive access.
[2.7.5]
Improvements
Release peripheral from reset if necessary in init function.
[2.7.4]
Improvements
Added support for atomic register accessing in LPUART_EnableInterrupts and LPUART_DisableInterrupts.
[2.7.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 15.7.
[2.7.2]
Bug Fix
Fixed the bug that the OSR calculation error when lupart init and lpuart set baud rate.
[2.7.1]
Improvements
Added support for LPUART_BASE_PTRS_NS in security mode in file fsl_lpuart.c.
[2.7.0]
Improvements
Split some functions, fixed CCM problem in file fsl_lpuart.c.
[2.6.0]
Bug Fixes
Fixed bug that when there are multiple lpuart instance, unable to support different ISR.
[2.5.3]
Bug Fixes
Fixed comments by replacing unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag with kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag.
[2.5.2]
Bug Fixes
Fixed bug that when setting watermark for TX or RX FIFO, the value may exceed the maximum limit.
Improvements
Added check in LPUART_TransferDMAHandleIRQ and LPUART_TransferEdmaHandleIRQ to ensure if user enables any interrupts other than transfer complete interrupt, the dma transfer is not terminated by mistake.
[2.5.1]
Improvements
Use separate data for TX and RX in lpuart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling LPUART_TransferReceiveNonBlocking, the received data count returned by LPUART_TransferGetReceiveCount is wrong.
[2.5.0]
Bug Fixes
Added missing interrupt enable masks kLPUART_Match1InterruptEnable and kLPUART_Match2InterruptEnable.
Fixed bug in LPUART_EnableInterrupts, LPUART_DisableInterrupts and LPUART_GetEnabledInterrupts that the BAUD[LBKDIE] bit field should be soc specific.
Fixed bug in LPUART_TransferHandleIRQ that idle line interrupt should be disabled when rx data size is zero.
Deleted unused status flags kLPUART_NoiseErrorInRxDataRegFlag and kLPUART_ParityErrorInRxDataRegFlag, since firstly their function are the same as kLPUART_NoiseErrorFlag and kLPUART_ParityErrorFlag, secondly to obtain them one data word must be read out thus interfering with the receiving process.
Fixed bug in LPUART_GetStatusFlags that the STAT[LBKDIF], STAT[MA1F] and STAT[MA2F] should be soc specific.
Fixed bug in LPUART_ClearStatusFlags that tx/rx FIFO is reset by mistake when clearing flags.
Fixed bug in LPUART_TransferHandleIRQ that while clearing idle line flag the other bits should be masked in case other status bits be cleared by accident.
Fixed bug of race condition during LPUART transfer using transactional APIs, by disabling and re-enabling the global interrupt before and after critical operations on interrupt enable register.
Fixed DMA/eDMA transfer blocking issue by enabling tx idle interrupt after DMA/eDMA transmission finishes.
New Features
Added APIs LPUART_GetRxFifoCount/LPUART_GetTxFifoCount to get rx/tx FIFO data count.
Added APIs LPUART_SetRxFifoWatermark/LPUART_SetTxFifoWatermark to set rx/tx FIFO water mark.
[2.4.1]
Bug Fixes
Fixed MISRA advisory 17.7 issues.
[2.4.0]
New Features
Added APIs to configure 9-bit data mode, set slave address and send address.
[2.3.1]
Bug Fixes
Fixed MISRA advisory 15.5 issues.
[2.3.0]
Improvements
Modified LPUART_TransferHandleIRQ so that txState will be set to idle only when all data has been sent out to bus.
Modified LPUART_TransferGetSendCount so that this API returns the real byte count that LPUART has sent out rather than the software buffer status.
Added timeout mechanism when waiting for certain states in transfer driver.
[2.2.8]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-10.3, rule-14.4, rule-15.5.
Eliminated Pa082 warnings by assigning volatile variables to local variables and using local variables instead.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.8, 14.4, 11.6, 17.7.
Improvements
Added check for kLPUART_TransmissionCompleteFlag in LPUART_WriteBlocking, LPUART_TransferHandleIRQ, LPUART_TransferSendDMACallback and LPUART_SendEDMACallback to ensure all the data would be sent out to bus.
Rounded up the calculated sbr value in LPUART_SetBaudRate and LPUART_Init to achieve more acurate baudrate setting. Changed osr from uint32_t to uint8_t since osr’s bigest value is 31.
Modified LPUART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.
[2.2.7]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule-12.1, rule-17.7, rule-14.4, rule-13.3, rule-14.4, rule-10.4, rule-10.8, rule-10.3, rule-10.7, rule-10.1, rule-11.6, rule-13.5, rule-11.3, rule-13.2, rule-8.3.
[2.2.6]
Bug Fixes
Fixed the issue of register’s being in repeated reading status while dealing with the IRQ routine.
[2.2.5]
Bug Fixes
Do not set or clear the TIE/RIE bits when using LPUART_EnableTxDMA and LPUART_EnableRxDMA.
[2.2.4]
Improvements
Added hardware flow control function support.
Added idle-line-detecting feature in LPUART_TransferNonBlocking function. If an idle line is detected, a callback is triggered with status kStatus_LPUART_IdleLineDetected returned. This feature may be useful when the received Bytes is less than the expected received data size. Before triggering the callback, data in the FIFO (if has FIFO) is read out, and no interrupt will be disabled, except for that the receive data size reaches 0.
Enabled the RX FIFO watermark function. With the idle-line-detecting feature enabled, users can set the watermark value to whatever you want (should be less than the RX FIFO size). Data is received and a callback will be triggered when data receive ends.
[2.2.3]
Improvements
Changed parameter type in LPUART_RTOS_Init struct from rtos_lpuart_config to lpuart_rtos_config_t.
Bug Fixes
Disabled LPUART receive interrupt instead of all NVICs when reading data from ring buffer. Otherwise when the ring buffer is used, receive nonblocking method will disable all NVICs to protect the ring buffer. This may has a negative effect on other IPs that are using the interrupt.
[2.2.2]
Improvements
Added software reset feature support.
Added software reset API in LPUART_Init.
[2.2.1]
Improvements
Added separate RX/TX IRQ number support.
[2.2.0]
Improvements
Added support of 7 data bits and MSB.
[2.1.1]
Improvements
Removed unnecessary check of event flags and assert in LPUART_RTOS_Receive.
Added code to always wait for RX event flag in LPUART_RTOS_Receive.
[2.1.0]
Improvements
Update transactional APIs.
LPUART_EDMA
[2.4.0]
Refer LPUART driver change log 2.1.0 to 2.4.0
MECC
[2.1.1]
Bug fixes:
Add volatile to variable counter to fix armgcc 13.2.1 -Os optimization issue.
[2.1.0]
Bug fixes:
Removed Ocram1StartAddress, Ocram1EndAddress, Ocram2StartAddress, Ocram2EndAddress in mecc_config_t structure. Use startAddress and endAddress as instead.
Removed static function MECC_GetInstance().
New Features:
Added new function MECC_GetPendingFlags().
Added new members: enableReadDataWait, enableReadAddrPipeline, enableWriteDataPipeline, enableWriteAddrPipeline in mecc_config_t structure to support pipeline features.
[2.0.2]
Bug fixes:
Fixed MISRA 2012 issue: 10.3, 10.4.
[2.0.1]
Bug fixes:
Fixed MISRA 2012 issue: 10.1, 10.3, 10.4, 10.6.
[2.0.0]
Initial version.
MEMORY
[2.1.0]
Bug Fixes
Provide correct address translation based on TCM_SIZE config.
[2.0.0]
Initial version.
MSGINTR
[2.0.2]
Improvements
Conditional compile IRQ handlers.
[2.0.1]
Bug Fixes
Fixed MISRA issue rule 8.4, 11.9, 17.7.
[2.0.0]
Initial version.
MU
[2.7.0]
New Features
Added API MU_GetRxStatusFlags.
[2.6.0]
New Features
Added API MU_GetInterruptsPending.
[2.5.1]
Bug Fixes
Fixed the bug that MU_TriggerGeneralPurposeInterrupts and MU_TriggerInterrupts may trigger previous triggered general purpose interrupts again by mistake.
[2.5.0]
New Features
Supported more than 4 general purpose interrupts.
Added seperate APIs for general purpose interrupts.
[2.4.0]
Improvements
Supported the case that some features only avaiable with specific instances. These features include Hardware Reset, Boot Peer Core, Hold Reset. When using the features with instances which don’t support them, driver will report error.
[2.3.3]
Improvements
Release peripheral from reset if necessary in init function.
[2.3.2]
Improvements
Supported platforms which don’t have CCR0[RSTH], CCR0[CLKE], CCR0[HR], CCR0[HRM].
[2.3.1]
Bug Fixes
Fixed build error for platforms which have CCR0[RSTH], but no CCR0[NMI].
[2.3.0]
New features
Added support for i.MX RT7xx.
[2.2.1]
Bug Fixes
Fixed issue that MU_GetInstance() is defined but never used.
[2.2.0]
New features
Added support for i.MX RT118x.
Bug Fixes
Fixed general purpose interrupt bug.
Other Changes
Change _mu_interrupt_trigger item value.
[2.1.2]
Bug Fixes
Fixed bug that general purpose interrupt can’t be configured.
[2.1.1]
Bug Fixes
Fixed MISRA C-2012 issues.
[2.1.0]
Improvements
Added new enum mu_msg_reg_index_t.
[2.0.0]
Initial version.
NETC
[2.8.2]
Bug Fixes
Fixed ingress port filter table frame attribute flags mask field issue.
[2.8.1]
Bug Fixes
Fixed MAC/VLAN filter operations through VSI-PSI message.
Fixed NETC_PortConfigTxIpgPreamble compile.
Improvements
Enabled standard VLAN EtherTypes for i.MX95 VSIs for VLAN support.
Added netc_timer_exttrig_index_t definition for i.MX95.
Updated default BPCR[STAMVD] value setting to align the register reset value.
[2.8.0]
Bug Fixes
Fixed ERRATA 052024.
Fixed ERRATA 052129.
Fixed ERRATA 052134.
Fixed ERRATA 052031.
Fixed ERRATA 051994.
Fixed ERRATA 051936.
New Features
Added interface to reset the mark frame red parameter.
Added support for FRER sequence generation reset.
Added NETC Switch Tag support.
Added the Tx offload feature support.
Improvements
Simplify NETC_TimerGetFreeRunningTime. Hardware synchronizes reads from high/low registers for the free running time. No need to do it in software.
[2.7.2]
Bug Fixes
Fixed MISRA issue rule 4.10, 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 16.1, 16.4, 17.7.
[2.7.1]
Bug Fixes
Fixed Coverity issue with array out of bounds access.
[2.7.0]
New Features
Added VSI-PSI messaging driver.
Bug Fixes
Fixed the issue that EP/SWT_ReceiveFrame don’t return error status when some errors occur.
[2.6.1]
Bug Fixes
Updated the MAC loopback configuration as Reference Manual.
[2.6.0]
New Features
Added API to get transmit max SDU for specified port Traffic Class.
Added API to query entry from the Rate Policing table.
Added API to retrieve maximum rate policer entries.
Added API to set switch port default VID separately.
Added API to set max frame size separately.
Added API to query FRER resource.
Bug Fixes
Fixed the issue that stream gate query functions don’t check return status.
Fixed the ISF table query function operation issue.
Fixed the wrong configuration of Tx max SDU check.
Fixed ERRATA 051524.
Fixed ERRATA 051649.
Fixed ERRATA 051707.
Fixed ERRATA 051710.
Fixed ERRATA 051711.
Improvements
Factorized qbv basetime workaround code, and stop using synchronized time for the workaround code. Synchronized time functionality should be reserved for gPTP operation.
[2.5.1]
Improvements
Conditional compile NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN register.
[2.5.0]
New Features
Added PHY WRAPPER driver.
Added C45 support for internal MDIO.
Added 10G support.
Bug Fixes
Fixed ERRATA 051130.
Fixed master bus and memory access.
Improvements
Moved platform specific code to soc driver.
Split switch code.
[2.4.0]
New Features
Added the interrupt control functions for port MAC module.
Added setting parameters including half-duplex back pressure, port timestamp capture point, RGMII Tx clock stop state during low power idle, ports default traffic class gating states and timer atomic writing setting.
Added NETC_TimerInitHandle() to initialize a timer handle without modifying hardware state. Required to be able to read timer from another CPU.
Added NETC_TimerGetFreeRunningTime() to be able to read free running timer.
Added support for ingress stream gate query.
Improvements
Added necessary default settings in the GetDefaultConfig functions in case some features can’t work after initialization.
Updated loopback function according to new bit field in CRR.
Deleted the useless error check for ERRATA051243.
Updated NETC_TimerGetCurrentTime() to avoid using synchronized time and be able to read the time from different threads/cpus without locking.
Deleted the useless priority check in NETC_PortConfigTcCBS().
Bug Fixes
Fixed typo in NETC_PortConfig.
[2.3.2]
Bug Fixes
Added workaround for ERRATA051587.
[2.3.1]
Bug Fixes
Fixed MISRA issue rule 10.3, 10.4, 10.8, 11.6, 11.7.
[2.3.0]
Bug Fixes
Added SWT_PortStop() API for ERRATA051398.
Fixed the build error by add feature macro for port FCS Error Action feature.
Removed duplicate code from NETC_PortEthMacGracefulStop() API.
Fixed MISRA issue rule 8.6, 10.4, 11.9, 14.4.
[2.2.2]
Bug Fixes
Fixed the issue that NETC_PortSetSpeed() would overwrite the full PCR register.
[2.2.1]
Improvements
Fixed cpp build warning.
[2.2.0]
Bug Fixes
Fixed the issue that NETC_ConfigTGSAdminList() doesn’t clear the previous command response data status filed.
Fixed the issue that EP_ReceiveFrameCopy(&handle, 0, NULL, 0, NULL) can’t drop error frame.
Fixed the issue that SWT_GetTimestampRefResp can’t get Switch Tx TS Resp with no MgmtRxBdRing.
Fixed the issue that RGMII Half Duplex mode misconfigured.
Fixed the issue that missing workaround for ERR050679, ERR051246 and ERR051254.
Fixed the issue that missing feature macro for ERR051130, ERR051202, ERR051260.
Fixed the issue that ep/swt_tx_opt struct use wrong vlan tag tpid value.
Fixed MISRA issue rule 5.8, 8.3, 8.12, 10.1, 10.3, 10.4, 10.6, 10.7, 10.8, 11.6, 11.8, 12.2, 14.4, 15.5, 15.6, 16.1, 16.3, 16.4, 17.7.
Fixed the issue that internal MDIO read function uses wrong register.
Fixed the issue that SWT_TxPortTGSEnable()/EP_TxPortTGSEnable() still uses the default timer after enabling the 1588 timer.
Remove the resetCount parameter from get port discard statistic APIs because the registers required by this function have been removed from hardware design.
Fixed the issue that SWT/EP_ReclaimTxDesc() can’t call reclaim callback for each full frame.
Fixed the issue in NETC_TimerAdjustFreq().
New Features
Added the support for 1588 One-Step timestamp when chip doesn’t have ERR051255.
Added APIs to get dynamic table remaining available entry numbers.
Added APIs to get static table number of entries.
Improvements
Return detail error status instead of kStatus_Fail in NTMP APIs.
Rename feature macros and move them into the feature file.
Optimize the implementation of the NETC_TimerAddOffset() function to avoid change the TMR_CNT_L/H registers, and add required procedure for call NETC_TimerAddOffset() API in the comments.
Update the SWT_FMDUpdateTableEntry()/SWT_FMDQueryTableEntry() APIs to make them use internel table buffer.
Update SWT_TxPortTGSEnable()/EP_TxPortTGSEnable() to make it can config the default administration gate control list gates’ state.
Use TMR_SRT_L/H instead of TMR_CUR_TIMER when want to get current 1588 timer value.
[2.1.0]
Bug Fixes
Fixed the issue that EP_RxL2MFInit doesn’t set the multicast promiscuous correctly.
Fixed the timer add offset issue.
Fixed the issue that all ENETC/Switch PCIe functions must be enabled firstly before triggering EP/SWT NTMP access and MSIX messages.
Fixed RT1180 NETC errata 051202: Configure Tx MAC to wait until 32 bytes of data are built up in the transmit FIFO before beginning transmission on the link.
Added workaround for RT1180 NETC errata 051130: C Egress time gate scheduling can get corrupted when functional level reset is applied or when time gating is disabled.
Fixed bugs in statistic APIs.
New Features
Added the support for EP VSI transmission and PSI-VSI message exchanging.
Added EP receive regular frame zero-copy support.
Integrated EMDIO support in NETC MDIO driver for accessing PHY when EP/Switch function isn’t enabled.
Added Timer and Switch MSIX table configuration support.
Added update entry APIs for IPF/VF/FDB/L2MCF/IS/ISF/SGI/RP/FM/ET/ISEQG tables, and search entry APIs for FDB/L2MCF table.
Added Ingress buffer pool table config APIs.
Added MAC Tx padding and Rx min/max frame size configuration to support Tx/Rx frames smaller than 64 bytes.
Added API to do graceful Stop for ETH MAC.
Improvements
Used Rx buffer address array provided by application instead of buffer start address with contiguous memory to make the Rx buffer setup more flexible.
Added ring and userData parameter in the Tx reclaim callback.
Updated NETC hardware layer folder name from ‘hw’ to ‘netc_hw’.
Stored necessary EP and SWT configurations constant in handle structure instead of storing pointer which forces appliction to keep static configuration structure data.
Updated NETC_MsixXxx to EP_MsixXxx to differentiate with corresponding SWT/Timer MSIX configuration APIs.
Aligned TGSL/SGCL API with enet_qos high-level driver.
Updated EP/Switch config structure to include all port related config.
Updated Switch transfer API only send management frame (Direct enqueue and Switch Port Masquerading) and only receive Host Reason no-zero frames.
Updated EP transfer API only send/receive regular frames.
Updated Switch/EP handle to make them use independent cache maintain, alloc/free memory and reclaimCallback functions.
[2.0.0]
Initial version.
OTFAD
[2.1.4]
Bug fixes
Fixed MISRA 2012 issue: 10.1.
[2.1.3]
Bug fixes
Fixed the error that waiting for both FLEXSPI AHB idle and SEQ idle.
[2.1.2]
Bug fixes
Fixed MISRA 2012 issue: 10.4.
[2.1.1]
Improvements:
Hided some bits in CR and SR registers for selected platforms.
Fixed doxygen issues.
[2.1.0]
Improvements:
Used boolean type to define 1-bit field concepts.
[2.0.0]
Initial version.
PDM
[2.9.1]
Bug Fixes
Fixed the issue that the driver still enters the interrupt after disabling clock.
[2.9.0]
Improvements
Added feature FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS to config CTRL_2[DEC_BYPASS] field.
Modify code to make the OSR value is not limited to 16.
[2.8.1]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_DOZEN to handle nonexistent CTRL_1[DOZEN] field.
[2.8.0]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_HWVAD to remove the support of hadware voice activity detector.
Added feature FSL_FEATURE_PDM_HAS_NO_FILTER_BUFFER to remove the support of FIR_RDY bitfield in STAT register.
[2.7.4]
Bug Fixes
Fixed driver can not determine the specific float number of clock divider.
Fixed PDM_ValidateSrcClockRate calculates PDM channel in wrong method issue.
[2.7.3]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_VADEF to remove the support of VADEF bitfield in VAD0_STAT register.
[2.7.2]
Improvements
Added feature FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV to decide whether the minimum clock frequency division is required.
[2.7.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.3, 10.1, 10.4, 14.4
[2.7.0]
Improvements
Added api PDM_EnableHwvadInterruptCallback to support handle hwvad IRQ in PDM driver.
Corrected the sample rate configuration for non high quality mode.
Added api PDM_SetChannelGain to support adjust the channel gain.
[2.6.0]
Improvements
Added new features FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ/FSL_FEATURE_PDM_HAS_DC_OUT_CTRL/FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED.
[2.5.0]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 16.5, 10.4, 10.3, 10.1, 11.9, 17.7, 10.6, 14.4, 11.8, 11.6.
[2.4.1]
Bug Fixes
Fixed MDK 66-D warning in pdm driver.
[2.4.0]
Improvements
Added api PDM_TransferSetChannelConfig/PDM_ReadFifo to support read different width data.
Added feature FSL_FEATURE_PDM_HAS_RANGE_CTRL and api PDM_ClearRangeStatus/PDM_GetRangeStatus for range register.
Bug Fixes
Fixed violation of MISRA C-2012 Rule 14.4, 10.3, 10.4.
[2.3.0]
Improvements
Enabled envelope/energy voice detect mode by adding apis PDM_SetHwvadInEnvelopeBasedMode/PDM_SetHwvadInEnergyBasedMode.
Added feature FSL_FEATURE_PDM_CHANNEL_NUM for different SOC.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.6, 10.7, 11.3, 11.8, 14.4, 17.7, 18.4.
Added medium quality mode support in function PDM_SetSampleRateConfig.
[2.2.0]
Improvements
Added api PDM_SetSampleRateConfig to improve user experience and marked api PDM_SetSampleRate as deprecated.
[2.1.1]
Improvements
Used new SDMA API SDMA_SetDoneConfig instead of SDMA_EnableSwDone for PDM SDMA driver.
[2.1.0]
Improvements
Added software buffer queue for transactional API.
[2.0.1]
Improvements
Improved HWVAD feature.
[2.0.0]
Initial version.
PDM_EDMA
[2.6.3]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.6.2]
Improvements
Add macro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL to let the user decide whether to enable it when calling PDM_TransferReceiveEDMA.
[2.6.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 10.3, 10.4.
[2.6.0]
Improvements
Updated api PDM_TransferReceiveEDMA to support channel block interleave transfer.
Added new api PDM_TransferSetMultiChannelInterleaveType to support channel interleave type configurations.
[2.5.0]
Refer PDM driver change log 2.1.0 to 2.5.0
PMU
[2.1.2]
Bug Fixes
Updated PMU_StaticEnablePllLdo() with disabling LDO current limit after LDO is stable to minimize ARM PLL jitter in cold temperature.
[2.1.1]
Bug Fixes
Fixed bugs in FBB configuration.
[2.1.0]
Improvements
Added PMU_EnableFBB() function.
Added PMU_EnableFBBStandbyMode() function.
Added PMU_EnableLdoStandbyMode() function.
[2.0.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 8.4.
[2.0.0]
Initial version.
PWM
[2.9.0]
Improvements
Support PWMX channel output for edge aligned PWM.
Forbid submodule 0 counter initialize with master sync and master reload mode.
[2.8.4]
Improvements
Support workaround for ERR051989. This function helps realize no phase delay between submodule 0 and other submodule.
[2.8.3]
Bug Fixes
Fixed MISRA C-2012 Rule 15.7
[2.8.2]
Bug Fixes
Fixed warning conversion from ‘int’ to ‘uint16_t’ on API PWM_Init.
Fixed warning unused variable ‘reg’ on API PWM_SetPwmForceOutputToZero.
[2.8.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.8.0]
Improvements
Added API PWM_UpdatePwmPeriodAndDutycycle to update the PWM signal’s period and dutycycle for a PWM submodule.
Added API PWM_SetPeriodRegister and PWM_SetDutycycleRegister to merge duplicate code in API PWM_SetupPwm, PWM_UpdatePwmDutycycleHighAccuracy and PWM_UpdatePwmPeriodAndDutycycle
[2.7.1]
Improvements
Supported UPDATE_MASK bit in MASK register.
[2.7.0]
Improvements
Supported platforms which don’t have Capture feature with channel A and B.
Supported platforms which don’t have Submodule 3.
Added assert function in API PWM_SetPhaseDelay to prevent wrong argument.
[2.6.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3.
[2.6.0]
Improvements
Added API PWM_SetPhaseDelay to set the phase delay from the master sync signal of submodule 0.
Added API PWM_SetFilterSampleCountthe to set number of consecutive samples that must agree prior to the input filter.
Added API PWM_SetFilterSamplePeriod to set set the sampling period of the fault pin input filter.
[2.5.1]
Bug Fixes
Fixed MISRA C-2012 rules: 10.1, 10.3, 10.4 , 10.6 and 10.8.
Fixed the issue that PWM_UpdatePwmDutycycle() can’t update duty cycle status value correct.
[2.5.0]
Improvements
Added API PWM_SetOouputToIdle to set pwm channel output to idle.
Added API PWM_GetPwmChannelState to get the pwm channel output duty cycle value.
Added API PWM_SetPwmForceOutputToZero to set the pwm channel output to zero logic.
Added API PWM_SetChannelOutput to set the pwm channel output state.
Added API PWM_SetClockMode to set the value of the clock prescaler.
Added API PWM_SetupPwmPhaseShift to set PWM which a special phase shift and 50% duty cycle.
Added API PWM_SetVALxValue/PWM_GetVALxValue to set/get PWM VALs registers values directly.
[2.4.0]
Improvements
Supported the PWM which can’t work in wait mode.
[2.3.0]
Improvements
Add PWM output enable&disbale API for SDK.
Bug Fixes
Fixed changing channel B configuration when parameter is kPWM_PWMX and PWMX configuration is not supported yet.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3, 10.4.
Bug Fixes
Fixed the issue that PWM drivers computed VAL1 improperly.
Improvements
Updated calculation accuracy of reloadValue in dutyCycleToReloadValue function.
[2.2.0]
Improvements
Added new enumeration and two APIs to support enabling and disabling one or more PWM output triggers.
Added a new function to make the most of 16-bit resolution PWM.
Added one API to support updating fault status of PWM output.
Added one API to support PWM DMA write request.
Added three APIs to support PWM DMA capture read request.
Added one API to support get default fault config of PWM.
Added one API to support setting PWM fault disable mapping.
[2.1.0]
Improvements
Moved the configuration of fault input filter into a new API to avoid be initialized multiple times.
Bug Fixes
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.2, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-14.4, rule-16.4.
[2.0.1]
Bug Fixes
Fixed the issue that PWM submodule may be initialized twice in function PWM_SetupPwm().
[2.0.0]
Initial version.
QTMR
[2.2.2]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.8.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.8.
[2.2.0]
Improvements
Added API QTMR_SetPwmOutputToIdle to set the generated pwm signal to the configured idle value.
Added API QTMR_GetPwmOutputStatus to return the output status of the generated pwm signal.
Added API QTMR_GetPwmChannelStatus to return the channel dutycycle value.
Added API QTMR_SetPwmClockMode to set clock mode change peripheral clock frequency.
Bug Fixes
Fixed the issue that pwm duty cycle could not be 0 and 100.
[2.1.0]
Bug Fixes
Fixed the issue QTMR_SetTimerPeriod needs to decrement down count by 1, and added new APIs to configure the LOAD register, COMP register.
[2.0.2]
Bug Fixes
Fixed the issue introduced by previous code correction for improving the output signal accuracy.
[2.0.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.1, 10.3, 11.5, 11.9.
Improvements
Improved the output signal accuracy.
[2.0.0]
Initial version.
RGPIO
[2.1.0]
New feature:
Added API RGPIO_EnablePortInput()
Added API RGPIO_SetPinInterruptConfig()
Added API RGPIO_GetPinsInterruptFlags()
Added API RGPIO_ClearPinsInterruptFlags()
[2.0.3]
Improvements:
Enhanced FGPIO_PinInit to enable clock internally.
[2.0.2]
Bug fix
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.3, rule-14.4, rule-15.5.
[2.0.1]
API Interface Change:
Refined naming of API while keep all original APIs with marking them as deprecated. The original API will be removed in the next release. The main change is to update API with prefix of _PinXXX() and _PortXXX().
[2.0.0]
Initial version.
ROMAPI
[1.1.2]
Improvements
Fix Misra issues
[1.1.1]
Improvements
Update the comments of “clear cache” function.
[1.1.0]
New features
Support B0 silicon
[1.0.0]
initial version.
RTWDOG
[2.1.4]
Bug Fixes
Fixed CERT INT30-C, INT31-C issue.
Make API RTWDOG_CountToMesec return 0 if result overflow.
[2.1.3]
Improvements
Waited the over status after CS register operation in case next CS operation causes problem.
[2.1.2]
Bug Fixes
Fixed doxygen issue.
[2.1.1]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed rules, containing: rule-10.3, rule-10.8, rule-11.9, rule-14.4, rule-15.5.
[2.1.0]
Improvements
Added an API to enable or disable the window mode.
Added an API to convert a raw count value to millisecond.
Used AT_QUICKACCESS_SECTION_CODE macro to decorate RTWDOG_Init, and copied this function from flash to QUICKACCESS section.
[2.0.1]
Bug Fixes
Fixed bug in the RTWDOG_Init; added check for register’s unlock status when configuring the RTWDOG in RTWDOG_init.
[2.0.0]
Initial version.
S3MU
2.0.1 Update kStatusGroup_SNT to kStatusGroup_ELEMU.
2.0.0 Initial version of S3MU driver.
SAI
[2.4.4]
Bug Fixes
Fixed enumeration sai_fifo_combine_t - add RX configuration.
[2.4.3]
Bug Fixes
Fixed enumeration sai_fifo_combine_t value configuration issue.
[2.4.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.4.1]
Bug Fixes
Fixed bitWidth incorrectly assigned issue.
[2.4.0]
Improvements
Removed deprecated APIs.
[2.3.8]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.3.7]
Improvements
Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.
Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function
[2.3.6]
Bug Fixes
Fixed violations of MISRA C-2012 rule 5.6.
[2.3.5]
Improvements
Make driver to be aarch64 compatible.
[2.3.4]
Bug Fixes
Corrected the fifo combine feature macro used in driver.
[2.3.3]
Bug Fixes
Added bit clock polarity configuration when sai act as slave.
Fixed out of bound access coverity issue.
Fixed violations of MISRA C-2012 rule 10.3, 10.4.
[2.3.2]
Bug Fixes
Corrected the frame sync configuration when sai act as slave.
[2.3.1]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
Fixed violations of MISRA C-2012 rule 17.7.
[2.3.0]
Bug Fixes
Fixed the build error caused by the SOC has no fifo feature.
[2.2.3]
Bug Fixes
Corrected the peripheral name in function SAI0_DriverIRQHandler.
[2.2.2]
Bug Fixes
Fixed the issue of MISRA 2004 rule 9.3.
Fixed sign-compare warning.
Fixed the PA082 build warning.
Fixed sign-compare warning.
Fixed violations of MISRA C-2012 rule 10.3,17.7,10.4,8.4,10.7,10.8,14.4,17.7,11.6,10.1,10.6,8.4,14.3,16.4,18.4.
Allow to reset Rx or Tx FIFO pointers only when Rx or Tx is disabled.
Improvements
Added 24bit raw audio data width support in sai sdma driver.
Disabled the interrupt/DMA request in the SAI_Init to avoid generates unexpected sai FIFO requests.
[2.2.1]
Improvements
Added mclk post divider support in function SAI_SetMasterClockDivider.
Removed useless configuration code in SAI_RxSetSerialDataConfig.
Bug Fixes
Fixed the SAI SDMA driver build issue caused by the wrong structure member name used in the function SAI_TransferRxSetConfigSDMA/SAI_TransferTxSetConfigSDMA.
Fixed BAD BIT SHIFT OPERATION issue caused by the FSL_FEATURE_SAI_CHANNEL_COUNTn.
Applied ERR05144: not set FCONT = 1 when TMR > 0, otherwise the TX may not work.
[2.2.0]
Improvements
Added new APIs for parameters collection and simplified user interfaces:
SAI_Init
SAI_SetMasterClockConfig
SAI_TxSetBitClockRate
SAI_TxSetSerialDataConfig
SAI_TxSetFrameSyncConfig
SAI_TxSetFifoConfig
SAI_TxSetBitclockConfig
SAI_TxSetConfig
SAI_TxSetTransferConfig
SAI_RxSetBitClockRate
SAI_RxSetSerialDataConfig
SAI_RxSetFrameSyncConfig
SAI_RxSetFifoConfig
SAI_RxSetBitclockConfig
SAI_RXSetConfig
SAI_RxSetTransferConfig
SAI_GetClassicI2SConfig
SAI_GetLeftJustifiedConfig
SAI_GetRightJustifiedConfig
SAI_GetTDMConfig
[2.1.9]
Improvements
Improved SAI driver comment for clock polarity.
Added enumeration for SAI for sample inputs on different edges.
Changed FSL_FEATURE_SAI_CHANNEL_COUNT to FSL_FEATURE_SAI_CHANNEL_COUNTn(base) for the difference between the different SAI instances.
Added new APIs:
SAI_TxSetBitClockDirection
SAI_RxSetBitClockDirection
SAI_RxSetFrameSyncDirection
SAI_TxSetFrameSyncDirection
[2.1.8]
Improvements
Added feature macro test for the sync mode2 and mode 3.
Added feature macro test for masterClockHz in sai_transfer_format_t.
[2.1.7]
Improvements
Added feature macro test for the mclkSource member in sai_config_t.
Changed “FSL_FEATURE_SAI5_SAI6_SHARE_IRQ” to “FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ”.
Added #ifndef #endif check for SAI_XFER_QUEUE_SIZE to allow redefinition.
Bug Fixes
Fixed build error caused by feature macro test for mclkSource.
[2.1.6]
Improvements
Added feature macro test for mclkSourceClockHz check.
Added bit clock source name for general devices.
Bug Fixes
Fixed incorrect channel numbers setting while calling RX/TX set format together.
[2.1.5]
Bug Fixes
Corrected SAI3 driver IRQ handler name.
Added I2S4/5/6 IRQ handler.
Added base in handler structure to support different instances sharing one IRQ number.
New Features
Updated SAI driver for MCR bit MICS.
Added 192 KHZ/384 KHZ in the sample rate enumeration.
Added multi FIFO interrupt/SDMA transfer support for TX/RX.
Added an API to read/write multi FIFO data in a blocking method.
Added bclk bypass support when bclk is same with mclk.
[2.1.4]
New Features
Added an API to enable/disable auto FIFO error recovery in platforms that support this feature.
Added an API to set data packing feature in platforms which support this feature.
[2.1.3]
New Features
Added feature to make I2S frame sync length configurable according to bitWidth.
[2.1.2]
Bug Fixes
Added 24-bit support for SAI eDMA transfer. All data shall be 32 bits for send/receive, as eDMA cannot directly handle 3-Byte transfer.
[2.1.1]
Improvements
Reduced code size while not using transactional API.
[2.1.0]
Improvements
API name changes:
SAI_GetSendRemainingBytes -> SAI_GetSentCount.
SAI_GetReceiveRemainingBytes -> SAI_GetReceivedCount.
All names of transactional APIs were added with “Transfer” prefix.
All transactional APIs use base and handle as input parameter.
Unified the parameter names.
Bug Fixes
Fixed WLC bug while reading TCSR/RCSR registers.
Fixed MOE enable flow issue. Moved MOE enable after MICS settings in SAI_TxInit/SAI_RxInit.
[2.0.0]
Initial version.
SAI_EDMA
[2.7.1]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.7.0]
Improvements
Updated api SAI_TransferReceiveEDMA to support voice channel block interleave transfer.
Updated api SAI_TransferSendEDMA to support voice channel block interleave transfer.
Added new api SAI_TransferSetInterleaveType to support channel interleave type configurations.
[2.6.0]
Improvements
Removed deprecated APIs.
[2.5.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 20.7.
[2.5.0]
Improvements
Added new api SAI_TransferSendLoopEDMA/SAI_TransferReceiveLoopEDMA to support loop transfer.
Added multi sai channel transfer support.
[2.4.0]
Improvements
Added new api SAI_TransferGetValidTransferSlotsEDMA which can be used to get valid transfer slot count in the sai edma transfer queue.
Deprecated the api SAI_TransferRxSetFormatEDMA and SAI_TransferTxSetFormatEDMA.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3,10.4.
[2.3.2]
Refer SAI driver change log 2.1.0 to 2.3.2
SEMA42
[2.0.4]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]
Improvements
Changed to implement SEMA42_Lock base on SEMA42_TryLock.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 14.4, 18.1.
[2.0.0]
Initial version.
SEMC
[2.7.1]
Bug Fixes
Fixed the wrong write operation to INTR register. The INTR register is a W1C register, so the right write operation is write directly to it to clear.
[2.7.0]
Improvements
Add new autofreshTimes parameter in semc_sdram_config_t.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.6.0]
Bug Fixes
Fixed the SEMC SRAM function bug that some configuration options can’t be set.
Correct legacy SEMC SRAM function feature macros.
Improvements
Add new SEMC SRAM function feature macros.
[2.5.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.3.
Fixed SEMC_ConfigureDBI bug that RDX not set correctly.
[2.5.0]
Bug Fixes
Fixed definitions of bitfields of BMCR0 and BMCR1 - wrong field order and incorrect semantical naming
The fix alters the driver API regarding configuration of AXI bus queue reordering
[2.4.3]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 5.6.
[2.4.2]
Improvements
Deleted meaningless parameter in memory size conversion function.
[2.4.1]
Bug Fixes
Fixed PSRAM A8 configuration issue, which should be 0x06U for PSRAM while pix mux bit width is 0x04U, based on different pix mux bit width.
[2.4.0]
Improvements
Improved nor and sram timing configuration on sync mode.
[2.3.1]
Bug Fixes
Updated refresh timer period(RT) timing setting, which updated into (RT+1)*(Prescaler period) for SDRAM.
Supported new DBI control register 2 to configure CSX interval time(CEITV).
Fixed violations of the MISRA C-2012 Rule 10.8.
Fixed doxygen warning.
[2.3.0]
New Features
Limited burst length as 1 according to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller’s burst length is greater than 1.
Supported 8 bits column address for SDRAM.
[2.2.1]
New Features
Added queue weight control, which can control queue a/b is working or not.
Updated NAND FLASH configuration API which disables and enables SEMC between configure control registers.
Added ONFI parameter Integrity CRC check for SEMC flash component.
[2.2.0]
New Features
Supported up to 4 PSRAM CS.
Added programmable delay line for DQS.
Added ready/wait feature for SRAM in asynchronous mode.
[2.1.0]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
Updated parameter type from uint16_t into uint32_t for send IP command API.
[2.0.4]
Bug Fixes
Fixed the SEMC queueA and queueB weight configuration issue.
Fixed the wrong configuration of DBICR1 register in SEMC_ConfigureDBI.
[2.0.3]
Bug Fixes
Added feature macro to control WDS&WDH bit setting for NOR synchronous transfer.
[2.0.2]
Bug Fixes
Changed SEMC NAND configuration structure and verify SEMC NAND related APIs.
Added extended SEMC clock enable.
[2.0.1]
Bug Fixes
Fixed data size mask configure in SEMC_ConfigureIPCommand API.
Updated the command mode in IP command type.
[2.0.0]
Initial version.
SINC
[2.1.5]
Bug Fixes
Fixed building warning.
[2.1.4]
Bug Fixes
Fixed building issue.
[2.1.3]
Bug Fixes
Fixed function ‘SINC_SetChannelProtectionOption’ logic operation error.
[2.1.2]
Bug Fixes
Fixed the typo issue of missing character ‘U’ in the feature macro ‘FSL_FEATRE_SINC_CACFR_HAS_NO_PTMUX’.
[2.1.1]
Bug Fixes
Fixed MISRA C-2012 rule 10.4 and 10.8 issues.
[2.1.0]
Improvements
Added support for chips that each instance equipped with 5 channels.
[2.0.2]
Improvements
Added comments for over sample ratio.
[2.0.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 15.6, 10.4, 10.1, 10.3 and 10.7.
[2.0.0]
Initial version.
SPDIF
[2.0.7]
Improvements
Add feature macro FSL_FEATURE_SPDIF_HAS_NO_SIC_REGISTER to handle nonexistent SIC register.
[2.0.6]
Bug Fixes
Fixed the Q/U channel interrupt enabled unexpectly while Q/U transfer pointer is NULL.
[2.0.5]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.3.
[2.0.4]
Bug Fixes
Added udata/qdata buffer address validation in driver IRQ handler to ensure that NULL pointer dereferences do not occur.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.2]
Bug Fixes
Corrected operator used for size value assertion in SPDIF_ReadBlocking/SPDIF_WriteBlocking.
[2.0.1]
Bug Fixes
Corrected the feature macro name used to define s_edmaPrivateHandle.
[2.0.0]
Initial version.
SPDIF DMA Driver
[2.0.8]
Improvements
Add EDMA ext API to accommodate more types of EDMA.
[2.0.7]
Bug Fixes
Fixed the incompatibility issue with edma4 driver.
[2.0.6]
Bug Fixes
Add feature macro to determine whether to use the API MEMORY_ConvertMemoryMapAddress to translate TCD addresses for DLAST_SGA.
[2.0.5]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.3.
[2.0.4]
Bug Fixes
Added udata/qdata buffer address validation in driver IRQ handler to ensure that NULL pointer dereferences do not occur.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, and 14.4.
[2.0.2]
Bug Fixes
Corrected operator used for size value assertion in SPDIF_ReadBlocking/SPDIF_WriteBlocking.
[2.0.1]
Bug Fixes
Corrected the feature macro name used to define s_edmaPrivateHandle.
[2.0.0]
Initial version.
SYSCTR
[2.0.1]
Bug Fixes
Fixed MISRA issue 10.4.
[2.0.0]
Initial version.
SYSPM
[2.3.0]
New Features
Supported instruction counter.
[2.2.0]
New Features
Supported platforms which only have one monitor.
Supported platforms whose instrction counter can’t be cleared.
Supported platforms whose counter can’t be disabled.
[2.1.0]
New Features
Added new APIs SYSPM_Init and SYSPM_Deinit.
[2.0.0]
Initial version.
TEMPSENSOR
[2.1.2]
Bug Fixes
Fixed the bug of incorrect default value of temperature sensor registers in initialization state.
[2.1.1]
Improvements
CTRL0 register fields are not needed for customer, they are trim registers for the IP that are determined during calibration.
[2.1.0]
Improvements
Supported directly access to TEMPSENSOR registers.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8.
[2.0.2]
Bug Fixes
Fixed bug that FINISH flag not cleared after temperature read out.
[2.0.1]
Improvements
Updated temperature calculation formula, to get more accurate result with high or low temperature..
[2.0.0]
Initial version.
TPM
[2.3.3]
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.3.2]
Bug Fixes
Fixed ERR008085 TPM writing the TPMx_MOD or TPMx_CnV registers more than once may fail when the timer is disabled.
[2.3.1]
Bug Fixes
Fixed compilation error when macro FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is 1.
[2.3.0]
Improvements
Create callback feature for TPM match and timer overflow interrupts.
[2.2.4]
Improvements
Add feature macros(FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN, FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC).
[2.2.3]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.2]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.2.1]
Bug Fixes
Fixed CCM issue by splitting function from TPM_SetupPwm() function to reduce function complexity.
Fixed violations of MISRA C-2012 rule 17.7.
[2.2.0]
Improvements
Added TPM_SetChannelPolarity to support select channel input/output polarity.
Added TPM_EnableChannelExtTrigger to support enable external trigger input to be used by channel.
Added TPM_CalculateCounterClkDiv to help calculates the counter clock prescaler.
Added TPM_GetChannelValue to support get TPM channel value.
Added new TPM configuration.
syncGlobalTimeBase
extTriggerPolarity
chnlPolarity
Added new PWM signal configuration.
secPauseLevel
Bug Fixes
Fixed TPM_SetupPwm can’t configure 0% combined PWM issues.
[2.1.1]
Improvements
Add feature macro for PWM pause level select feature.
[2.1.0]
Improvements
Added TPM_EnableChannel and TPM_DisableChannel APIs.
Added new PWM signal configuration.
pauseLevel - Support select output level when counter first enabled or paused.
enableComplementary - Support enable/disable generate complementary PWM signal.
deadTimeValue - Support deadtime insertion for each pair of channels in combined PWM mode.
Bug Fixes
Fixed issues about channel MSnB:MSnA and ELSnB:ELSnA bit fields and CnV register change request acknowledgement. Writes to these bits are ignored when the interval between successive writes is less than the TPM clock period.
[2.0.8]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, 10.4 ,10.7 and 14.4.
[2.0.7]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4 and 17.7.
[2.0.6]
Bug Fixes
Fixed Out-of-bounds issue.
[2.0.5]
Bug Fixes
Fixed MISRA-2012 rules.
Rule 10.6, 10.7
[2.0.4]
Bug Fixes
Fixed ERR050050 in functions TPM_SetupPwm/TPM_UpdatePwmDutycycle. When TPM was configured in EPWM mode as PS = 0, the compare event was missed on the first reload/overflow after writing 1 to the CnV register.
[2.0.3]
Bug Fixes
MISRA-2012 issue fixed.
Fixed rules: rule-12.1, rule-17.7, rule-16.3, rule-14.4, rule-1.3, rule-10.4, rule-10.3, rule-10.7, rule-10.1, rule-10.6, and rule-18.1.
[2.0.2]
Bug Fixes
Fixed issues in functions TPM_SetupPwm/TPM_UpdateChnlEdgeLevelSelect /TPM_SetupInputCapture/TPM_SetupOutputCompare/TPM_SetupDualEdgeCapture, wait acknowledgement when the channel is disabled.
[2.0.1]
Bug Fixes
Fixed TPM_UpdateChnIEdgeLevelSelect ACK wait issue.
Fixed the issue that TPM_SetupdualEdgeCapture could not set FILTER register.
Fixed TPM_UpdateChnEdgeLevelSelect ACK wait issue.
[2.0.0]
Initial version.
TRDC
[2.3.0]
New Features
Added API TRDC_EnableProcessorDomainAssignment to disable/enable DAC.
Bug Fixes
Fixed MISRA violation of missing function declaration.
Fixed wrong operation of domain mask in TRDC_MbcNseClearAll and TRDC_MrcDomainNseClear.
[2.2.1]
Bug Fixes
Fixed MISRA violations of rule 10.3.
[2.2.0]
New Features
Added new APIs to support SoC with more than one processor core.
[2.1.1]
Bug Fixes
Fixed MISRA violations of rule 10.3, 10.6, 10.7 and 18.1.
[2.1.0]
Improvements
Modified some of the addressing method according to the device header file’s update.
Modified flash address configuration structure and default setting.
New Features
Added API to set flash logic window array address.
Bug Fixes
Fixed wrong return value of TRDC_GetFlashLogicalWindowPbase.
Fixed bug in TRDC_GetAndClearFirstSpecificDomainError that the error status is cleared by mistake before obtained by software.
Fixed MISRA violations of rule 10.3, 10.4, 10.6 and 10.8.
[2.0.0]
Initial version.
TSTMR
[2.0.2]
Improvements
Support 24MHz clock source.
Bugfix
Fix MISRA C-2012 Rule 10.4 issue.
Read of TSTMR HIGH must follow TSTMR LOW atomically: require masking interrupt around 2 LSB / MSB accesses.
[2.0.1]
Bugfix
Restrict to read with 32-bit accesses only.
Restrict that TSTMR LOW read occurs first, followed by the TSTMR HIGH read.
[2.0.0]
Initial version.
USDHC
[2.8.4]
Improvements
Add feature macro FSL_FEATURE_USDHC_HAS_NO_VS18.
[2.8.3]
Improvements
Improved api USDHC_EnableAutoTuningForCmdAndData to adapt to new bit field name for USDHC_VEND_SPEC2 register.
[2.8.2]
Improvements
Added feature macro FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT.
[2.8.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9.
[2.8.0]
Improvements
Fixed the mmc boot transfer failed issue which is caused by the Dma complete interrupt not enabled.
Marked api USDHC_AdjustDelayForManualTuning as deprecated and added new api USDHC_SetTuingDelay/USDHC_GetTuningDelayStatus.
Improved the manual tuning flow accroding to specification.
Added memory address conversion to support buffers which could only be accessed using alias address by non-core masters.
Fixed violations of MISRA C-2012 rule 10.4.
[2.7.0]
Improvements
Added api USDHC_TransferScatterGatherADMANonBlocking to support scatter gather transfer.
Added feature FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER for re-tuning time counter field in HOST_CTRL_CAP register.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 10.1, 10.3, 10.4, 8.4.
[2.6.0]
Improvements
Added api USDHC_SetStandardTuningCounter to support adjust tuning counter of Standard tuning.
[2.5.1]
Improvements
Used different status code for command and data interrupt callback.
Added cache line invalidate for receive buffer in driver IRQ handler to fix CM7 speculative access issue.
[2.5.0]
Improvements
Added new api USDHC_SetStrobeDllOverride for HS400 strobe dll override mode delay taps configurations.
Corrected the STROBE DLL configurations sequence.
[2.4.0]
Improvements
Added feature macro for read/write burst length.
Disabled redundant interrupt per different transfer request.
Disabled interrupt and reset command/data pointer in handle when transfer completes.
Bug Fixes
Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3.
Fixed PA082 build warning.
Fixed logically dead code Coverity issue.
[2.3.0]
Improvements
Added USDHC_SetDataConfig API to support manual tuning.
Removed the limitaion that source clock must be bigger than the target in function USDHC_SetSdClock by using source clock frequency as target directly.
Added peripheral reset in USDHC_Init function.
Added tuning reset support in function USDHC_Reset function.
[2.2.8]
Bug Fixes
Fixed out-of bounds write in function USDHC_ReceiveCommandResponse.
[2.2.7]
Improvements
Added API USDHC_GetEnabledInterruptStatusFlags and used in USDHC_TransferHandleIRQ.
Removed useless member interruptFlags in usdhc_handle_t.
[2.2.6]
Improvements
Added address align check for ADMA descriptor table address.
Changed USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY to (65536-4096) to make sure the data address is 4KB align for a transfer which need more than one ADMA1 descriptor.
[2.2.5]
Bug Fixes
Fixed MDK 66-D warning.
[2.2.4]
Bug Fixes
Fixed issue that real clock frequency wss mismatched with target clock frequency, which was caused by an incorrect prescaler calculation.
New Features
Added control macro to enable/disable the CLOCK code in current driver.
[2.2.3]
Bug Fixes
Fixed issue where AMDA did not disable with DMAEN clear.
Improvements
Improved set clock function to check the output frequency range.
Dynamic set SDCLKFS during DDR enable or disable.
[2.2.2]
Improvements
Improved read transfer cache maintain operation, combined clean, and invalidated them into one function.
[2.2.1]
Bug Fixes
Disabled the invalidate cache operation for tuning.
[2.2.0]
Improvements
Improved USDHC to support MMC boot feature.
[2.1.3]
Bug Fixes
Fixed MISRA issue.
[2.1.2]
Bug Fixes
Fixed Coverity issue.
Added base address and userData parameter for all callback functions.
[2.1.1]
Improvements
Added cache maintain operation.
Added timeout status check for the DATA transfer which ignore error.
Added feature macro for SDR50/SDR104 mode.
Removed useless IRQ handler from different platforms.
[2.1.0]
Improvements
Integrated tuning into transfer function.
Added strobe DLL feature.
Added enableAutoCommand23 in data structure.
Removed enable card clock function because the controller would handle the clock on/off.
[2.0.0]
Initial version.
VREF
[2.4.0]
Improvements
Support TEST_UNLOCK and TRIM0 registers read and write.
[2.3.0]
Improvements
Add feature macros for compatibility with some platforms that don’t have CSR[LPBG_BUF_EN] and UTRIM[TRIM2V1].
[2.2.2]
Bug Fixes
Fixed typo in vref_buffer_mode_t enumerator.
[2.2.1]
Improvements
Updated VREF driver code to reduce code redundancy.
[2.2.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
[2.1.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
Bug Fixes
Fix issue which progeam stuck in VREF_Init
[2.0.0]
Initial version.
XBAR
[2.1.2]
Correct bits of SEL registers
[2.1.1]
Fix wrong offset of ctrl registers
[2.1.0]
unify bit fields width for xbar instance index and xbar input/output signal index.
[2.0.4]
Improvements
Rename feature macro name.
[2.0.3]
Improvements
Improved to support 32-bit width peripheral.
[2.0.2]
Bug Fixes
Fixed MISRA C-2012 violations.
[2.0.1]
Bug Fixes
Fixed the xbar instance base offset error.
[2.0.0]
Initial version.