MCUXpresso SDK Changelog

CACHE LMEM

[2.0.6]

• Bug Fixes

  • Fixed doxygen issue.

[2.0.5]

• Improvements

  • Updated the cache enable function, don’t enable again when it is already enabled.

[2.0.4]

• Bug Fixes

  • Updated full name for lmem driver.

  • Fixed doxygen issue.

[2.0.3]

• Bug Fixes

  • Fixed violation of MISRA C-2012 Rule 10.4 and 14.4.

[2.0.2]

• Improvements

  • Moved CLCR register configuration out of the while loop, it’s unnecessary to repeat this operation.

[2.0.1]

• Bug Fixes

  • Fixed the over-4KB-size maintenance issue in invalidate/clean/clean&invalidate by range APIs.

[2.0.0]

• Initial version.

---

COMMON

[2.5.0]

• New Features

  • Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.

[2.4.3]

• Improvements

  • Enable irqs that mount under irqsteer interrupt extender.

[2.4.2]

• Improvements

  • Add the macros to convert peripheral address to secure address or non-secure address.

[2.4.1]

• Improvements

  • Improve for the macro redefinition error when integrated with zephyr.

[2.4.0]

• New Features

  • Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.

  • Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.

[2.3.3]

• New Features

  • Added NETC into status group.

[2.3.2]

• Improvements

  • Make driver aarch64 compatible

[2.3.1]

• Bug Fixes

  • Fixed MAKE_VERSION overflow on 16-bit platforms.

[2.3.0]

• Improvements

  • Split the driver to common part and CPU architecture related part.

[2.2.10]

• Bug Fixes

  • Fixed the ATOMIC macros build error in cpp files.

[2.2.9]

• Bug Fixes

  • Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.

  • Fixed SDK_Malloc issue that not allocate memory with required size.

[2.2.8]

• Improvements

  • Included stddef.h header file for MDK tool chain.

• New Features:

  • Added atomic modification macros.

[2.2.7]

• Other Change

  • Added MECC status group definition.

[2.2.6]

• Other Change

  • Added more status group definition.

• Bug Fixes

  • Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h

[2.2.5]

• Bug Fixes

  • Fixed MISRA C-2012 rule-15.5.

[2.2.4]

• Bug Fixes

  • Fixed MISRA C-2012 rule-10.4.

[2.2.3]

• New Features

  • Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.

  • Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.

[2.2.2]

• New Features

  • Added include RTE_Components.h for CMSIS pack RTE.

[2.2.1]

• Bug Fixes

  • Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.

[2.2.0]

• New Features

  • Moved SDK_DelayAtLeastUs function from clock driver to common driver.

[2.1.4]

• New Features

  • Added OTFAD into status group.

[2.1.3]

• Bug Fixes

  • MISRA C-2012 issue fixed.

    • Fixed the rule: rule-10.3.

[2.1.2]

• Improvements

  • Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.

[2.1.1]

• Bug Fixes

  • Deleted and optimized repeated macro.

[2.1.0]

• New Features

  • Added IRQ operation for XCC toolchain.

  • Added group IDs for newly supported drivers.

[2.0.2]

• Bug Fixes

  • MISRA C-2012 issue fixed.

    • Fixed the rule: rule-10.4.

[2.0.1]

• Improvements

  • Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.

  • Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.

  • Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.

[2.0.0]

• Initial version.

---

ECSPI

[2.3.3]

• Bug Fixes

  • Fixed the txData from void * to const void * in transmit API

[2.3.2]

• Improvements

  • Changed ECSPI_DUMMYDATA to 0x00.

[2.3.1]

• Bug Fixes

  • Fixed ECSPI_GetInstance potential issue that return wrong instance number.

[2.3.0]

• Bug Fixes

  • Fixed burst length issue,the burst length range shall range from 1-4096 bits, so the width shall be uint8_t rather than uint16_t.

[2.2.0]

• Bug Fixes

  • Removed the useless channel configuration of waveform, since the waveform can not be configured when not using the exchange bit(ECSPIx_CONREG[XCH]) for the transfer.

  • Fixed violations of MISRA C-2012 rules: 10.1, 11.9, 8.4.

[2.1.1]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rules: 10.1, 10.3, 10.4, 11.9, 14.4, 15.7, 17.7.

[2.1.0]

• Improvements

  • Added timeout mechanism when waiting certain states in transfer driver.

[2.0.2]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rules: 10.1, 10.3, 10.4

[2.0.1]

• Bug Fixes

  • Memset local variable SDMA transfer configuration structure to make sure unused members in structure are cleared.

  • Fixed sign-compare warning in ECSPI_SendTransfer.

[2.0.0]

• Initial version.

---

GPIO

[2.0.6]

• Bug Fixes

  • Fixed compile warning: ‘GPIO_GetInstance’ defined but not used when macro FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is defined.

[2.0.5]

• Bug Fixes

  • Fixed MISRA C-2012 issue: rule-17.7.

[2.0.4]

• Improvements

  • Updated the GPIO_PinWrite to use atomic operation if possible.

• Bug Fixes

  • Fixed GPIO_PortToggle bug with platforms don’t have register DR_TOGGLE.

[2.0.3]

• Bug Fixes

  • MISRA C-2012 issue fixed.

    • Fixed rules, containing: rule-10.3, rule-14.4, and rule-15.5.

[2.0.2]

• Bug Fixes

  • Fixed the bug of enabling wrong GPIO clock gate in initial API. Since some GPIO instances may not have a clock gate enabled, it checks the clock gate number and makes sure the clock gate is valid.

[2.0.1]

• Improvements

  • API interface changes:

    • Refined naming of the API while keeping all original APIs, marking them as deprecated. Original APIs will be removed in next release. The main change is to update the API with prefix of _PinXXX() and _PortXXX().

[2.0.0]

• Initial version.

---

GPT

[2.0.5]

• Improvements

  • Support workaround for ERR003777. This workaround helps switching the clock sources.

[2.0.4]

• Bug Fixes

  • Fixed compiler warning when built with FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL flag enabled.

[2.0.3]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 5.3 by customizing function parameter.

[2.0.2]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 17.7.

[2.0.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 10.8, 17.7.

[2.0.0]

• Initial version.

---

I2C

[2.0.7]

• Bug Fixes

  • Fixed MISRA issues.

    • Fixed rules 8.4, 8.5.

[2.0.6]

• Bug Fixes

  • Fixed the bug that, in I2C_MasterStop after the stop command is issued, the IBB flag should be cleared rather than set.

  • Fixed the bug that to clear kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag, their bits should be written ‘0’ rather than ‘1’.

[2.0.5]

• Bug Fixes

  • Fixed Coverity issue of unchecked return value in I2C_RTOS_Transfer.

  • Fixed MISRA issues.

    • Fixed rules 10.1, 10.3, 10.4, 11.9, 14.4, 15.7, 16.4, 17.7.

• Improvements

  • Updated the I2C_WAIT_TIMEOUT macro to unified name I2C_RETRY_TIMES.

[2.0.4]

• Bug Fixes

  • Fixed the issue that I2C Master transfer APIs(blocking/non-blocking) did not support the situation that master transfer with subaddress and transfer data size being zero, which means no data followed by the subaddress.

[2.0.3]

• Improvements

  • Improved code readability, added new static API I2C_WaitForStatusReady for the status flag wait, and changed to call I2C_WaitForStatusReady instead of polling flags with reading register.

[2.0.2]

• Improvements

  • Added I2C_WATI_TIMEOUT macro to allow users to specify the timeout times for waiting flags in functional API and blocking transfer API.

[2.0.1]

• Bug Fixes

  • Added a proper handle for transfer config flag kI2C_TransferNoStartFlag to support transmit with kI2C_TransferNoStartFlag flag. Only supports write only or write+read with no start flag; does not support read only with no start flag.

[2.0.0]

• Initial version.

---

MCM

[2.2.0]

• Improvements

  • Support platforms with less features.

[2.1.0]

• Others

  • Remove byteID from mcm_lmem_fault_attribute_t for document update.

[2.0.0]

• Initial version.

---

MU

[2.2.0]

• New Features

  • Added API MU_GetRxStatusFlags.

[2.1.3]

• Improvements

  • Release peripheral from reset if necessary in init function.

[2.1.2]

• Bug Fixes

  • Fixed issue that MU_GetInstance() is defined but never used.

[2.1.1]

• Bug Fixes

  • Fixed general interrupt comment typo.

[2.1.0]

• Improvements

  • Added new enum mu_msg_reg_index_t.

[2.0.7]

• Bug Fixes

  • Fixed MU_GetInterruptsPending bug that can not get general interrupt status.

[2.0.6]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 17.7.

[2.0.5]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 14.4, 15.5.

[2.0.4]

• Improvements

  • Improved for the platforms which don’t support reset assert interrupt and get the other core power mode.

[2.0.3]

• Bug fixes

  • MISRA C-2012 issue fixed.

    • Fixed rules, containing: rule-10.3, rule-14.4, rule-15.5.

[2.0.2]

• Improvements

  • Added support for MIMX8MQx.

[2.0.1]

• Improvements

  • Added support for MCIMX7Ux_M4.

[2.0.0]

• Initial version.

---

PWM

[2.0.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 17.7.

[2.0.0]

• Initial version.

---

QSPI

[2.2.5]

• Bug Fixes

  • Fixed the txData from void * to const void * in transmit API.

[2.2.4]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 10.3.

[2.2.3]

• Bug Fixes

  • Cleared buffer generic configuration when do software reset.

[2.2.2]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 10.1 and 11.9.

[2.2.1]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 10.1, 10.3, 10.4, 10.6, 10.8, 11.3, 11.6, 11.8, 11.9, 14.4, 16.1, 16.4, 17.7.

[2.2.0]

• New Features

  • Added new API QSPI_ClearCache to clear cache for new IP feature FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC.

• Bug Fixes

  • Fixed the QSPI_WriteBlocking API programming issue for low watermark, caused by previous improvement change of using TX watermark signal to fill the TX FIFO. Reverted change to previous implementation to use TX FIFO full flag for filling the FIFO. Improved previous API by accessing TX data register directly.

  • Fixed the issue that QSPI_SetIPCommandSize incorrectly triggered a transaction.

  • Fixed clock divider accurate issue when using internal QSPI internal divider.

  • Fixed build fail issue for some devices’ not supporting API QSPI_SetDqsConfig for DQS configuration.

[2.1.0]

• New Features

  • Added new API QSPI_SetDqsConfig for DQS configuration.

• Improvements

  • Updated the QSPI_WriteBlocking API to fill the TX FIFO once there are bytes of TX watermark room in the FIFO. This will improve the performance of filling TX FIFO when watermark is high.

[2.0.2]

• Improvements

  • New Macro function:

    • Added QSPI_LUT_SEQ() function for users to set LUT table easily.

    • Added LUT command macros for users to easy use.

  • Comment update:

    • Added the comments for the limitation of QSPI_ReadBlocking and QSPI_TransferReceiveBlocking.

[2.0.1]

• Improvements

  • New API:

    • QSPI_SetReadArea to set the read area.

• Bug Fixes

  • Fixed the issue that QSPI_UpdateLUT function only updated first LUT.

  • Fixed issue that some function that hardcode QSPI0 as base.

[2.0.0]

• Initial version.

---

RDC

[2.2.0]

• New Features

  • Added APIs to get memory region or peripheral access policy for specific domain.

[2.1.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.6.

[2.1.0]

• Improvements

  • Enhanced to support memory region larger than 32-bit address.

[2.0.2]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 11.3, 11.8, 17.7.

[2.0.1]

• Bug Fixes:

  • Added __DSB after new configuration is set to ensure the new configuration takes effect.

[2.0.0]

• Initial version.

---

RDC_SEMA42

[2.0.4]

• Improvements

  • Changed to implement RDC_SEMAPHORE_Lock base on RDC_SEMAPHORE_TryLock.

[2.0.3]

• Improvements:

  • Supported the RDC_SEMAPHORE_Type structure whose gate registers are defined as an array.

[2.0.2]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 10.8, 14.3, 14.4, 18.1.

[2.0.1]

• Improvements:

  • Added support for the platforms that don’t have dedicated RDC_SEMA42 clock gate.

[2.0.0]

• Initial version.

---

SAI

[2.4.4]

• Bug Fixes

  • Fixed enumeration sai_fifo_combine_t - add RX configuration.

[2.4.3]

• Bug Fixes

  • Fixed enumeration sai_fifo_combine_t value configuration issue.

[2.4.2]

• Improvements

  • Release peripheral from reset if necessary in init function.

[2.4.1]

• Bug Fixes

  • Fixed bitWidth incorrectly assigned issue.

[2.4.0]

• Improvements

  • Removed deprecated APIs.

[2.3.8]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 10.4.

[2.3.7]

• Improvements

  • Change feature “FSL_FEATURE_SAI_FIFO_COUNT” to “FSL_FEATURE_SAI_HAS_FIFO”.

  • Added feature “FSL_FEATURE_SAI_FIFO_COUNTn(x)” to align SAI fifo count function with IP in function

[2.3.6]

• Bug Fixes

  • Fixed violations of MISRA C-2012 rule 5.6.

[2.3.5]

• Improvements

  • Make driver to be aarch64 compatible.

[2.3.4]

• Bug Fixes

  • Corrected the fifo combine feature macro used in driver.

[2.3.3]

• Bug Fixes

  • Added bit clock polarity configuration when sai act as slave.

  • Fixed out of bound access coverity issue.

  • Fixed violations of MISRA C-2012 rule 10.3, 10.4.

[2.3.2]

• Bug Fixes

  • Corrected the frame sync configuration when sai act as slave.

[2.3.1]

• Bug Fixes

  • Corrected the peripheral name in function SAI0_DriverIRQHandler.

  • Fixed violations of MISRA C-2012 rule 17.7.

[2.3.0]

• Bug Fixes

  • Fixed the build error caused by the SOC has no fifo feature.

[2.2.3]

• Bug Fixes

  • Corrected the peripheral name in function SAI0_DriverIRQHandler.

[2.2.2]

• Bug Fixes

  • Fixed the issue of MISRA 2004 rule 9.3.

  • Fixed sign-compare warning.

  • Fixed the PA082 build warning.

  • Fixed sign-compare warning.

  • Fixed violations of MISRA C-2012 rule 10.3,17.7,10.4,8.4,10.7,10.8,14.4,17.7,11.6,10.1,10.6,8.4,14.3,16.4,18.4.

  • Allow to reset Rx or Tx FIFO pointers only when Rx or Tx is disabled.

• Improvements

  • Added 24bit raw audio data width support in sai sdma driver.

  • Disabled the interrupt/DMA request in the SAI_Init to avoid generates unexpected sai FIFO requests.

[2.2.1]

• Improvements

  • Added mclk post divider support in function SAI_SetMasterClockDivider.

  • Removed useless configuration code in SAI_RxSetSerialDataConfig.

• Bug Fixes

  • Fixed the SAI SDMA driver build issue caused by the wrong structure member name used in the function SAI_TransferRxSetConfigSDMA/SAI_TransferTxSetConfigSDMA.

  • Fixed BAD BIT SHIFT OPERATION issue caused by the FSL_FEATURE_SAI_CHANNEL_COUNTn.

  • Applied ERR05144: not set FCONT = 1 when TMR > 0, otherwise the TX may not work.

[2.2.0]

• Improvements

  • Added new APIs for parameters collection and simplified user interfaces:

    • SAI_Init

    • SAI_SetMasterClockConfig

    • SAI_TxSetBitClockRate

    • SAI_TxSetSerialDataConfig

    • SAI_TxSetFrameSyncConfig

    • SAI_TxSetFifoConfig

    • SAI_TxSetBitclockConfig

    • SAI_TxSetConfig

    • SAI_TxSetTransferConfig

    • SAI_RxSetBitClockRate

    • SAI_RxSetSerialDataConfig

    • SAI_RxSetFrameSyncConfig

    • SAI_RxSetFifoConfig

    • SAI_RxSetBitclockConfig

    • SAI_RXSetConfig

    • SAI_RxSetTransferConfig

    • SAI_GetClassicI2SConfig

    • SAI_GetLeftJustifiedConfig

    • SAI_GetRightJustifiedConfig

    • SAI_GetTDMConfig

[2.1.9]

• Improvements

  • Improved SAI driver comment for clock polarity.

  • Added enumeration for SAI for sample inputs on different edges.

  • Changed FSL_FEATURE_SAI_CHANNEL_COUNT to FSL_FEATURE_SAI_CHANNEL_COUNTn(base) for the difference between the different SAI instances.

• Added new APIs:

  • SAI_TxSetBitClockDirection

  • SAI_RxSetBitClockDirection

  • SAI_RxSetFrameSyncDirection

  • SAI_TxSetFrameSyncDirection

[2.1.8]

• Improvements

  • Added feature macro test for the sync mode2 and mode 3.

  • Added feature macro test for masterClockHz in sai_transfer_format_t.

[2.1.7]

• Improvements

  • Added feature macro test for the mclkSource member in sai_config_t.

  • Changed “FSL_FEATURE_SAI5_SAI6_SHARE_IRQ” to “FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ”.

  • Added #ifndef #endif check for SAI_XFER_QUEUE_SIZE to allow redefinition.

• Bug Fixes

  • Fixed build error caused by feature macro test for mclkSource.

[2.1.6]

• Improvements

  • Added feature macro test for mclkSourceClockHz check.

  • Added bit clock source name for general devices.

• Bug Fixes

  • Fixed incorrect channel numbers setting while calling RX/TX set format together.

[2.1.5]

• Bug Fixes

  • Corrected SAI3 driver IRQ handler name.

  • Added I2S4/5/6 IRQ handler.

  • Added base in handler structure to support different instances sharing one IRQ number.

• New Features

  • Updated SAI driver for MCR bit MICS.

  • Added 192 KHZ/384 KHZ in the sample rate enumeration.

  • Added multi FIFO interrupt/SDMA transfer support for TX/RX.

  • Added an API to read/write multi FIFO data in a blocking method.

  • Added bclk bypass support when bclk is same with mclk.

[2.1.4]

• New Features

  • Added an API to enable/disable auto FIFO error recovery in platforms that support this feature.

  • Added an API to set data packing feature in platforms which support this feature.

[2.1.3]

• New Features

  • Added feature to make I2S frame sync length configurable according to bitWidth.

[2.1.2]

• Bug Fixes

  • Added 24-bit support for SAI eDMA transfer. All data shall be 32 bits for send/receive, as eDMA cannot directly handle 3-Byte transfer.

[2.1.1]

• Improvements

  • Reduced code size while not using transactional API.

[2.1.0]

• Improvements

  • API name changes:

    • SAI_GetSendRemainingBytes -> SAI_GetSentCount.

    • SAI_GetReceiveRemainingBytes -> SAI_GetReceivedCount.

    • All names of transactional APIs were added with “Transfer” prefix.

    • All transactional APIs use base and handle as input parameter.

    • Unified the parameter names.

• Bug Fixes

  • Fixed WLC bug while reading TCSR/RCSR registers.

  • Fixed MOE enable flow issue. Moved MOE enable after MICS settings in SAI_TxInit/SAI_RxInit.

[2.0.0]

• Initial version.

---

SEMA4

[2.0.3]

• Improvements

  • Changed to implement SEMA4_Lock base on SEMA4_TryLock.

[2.0.2]

• Improvements:

  • Supported the SEMA4_Type structure whose gate registers are defined as an array.

[2.0.1]

• Bug Fixes

  • Fixed violations of the MISRA C-2012 rules 10.3, 10.4, 15.5, 18.1, 18.4.

[2.0.0]

• Initial version.

---

SNVS_HP

[2.3.2]

• Make SNVS_HP_RTC_Init()/SNVS_HP_RTC_Deinit more transparent. Use function SNVS_HP_Init()/SNVS_HP_Deinit() instead of copy of this code in SNVS_HP_RTC_XXX() function.

[2.3.1]

• Fixed problem in SNVS_HP_RTC_Init(), which is clearing bits that should stay intact.

[2.3.0]

• Re-map Security Violation for RT11xx specific violations.

[2.2.0]

• Fixed doxygen issues.

• Add SNVS HP Set locks.

[2.1.4]

• Fix MISRA issues.

[2.1.3]

• Fixed IAR Pa082 warnings.

[2.1.2]

• Fixed problem with initialization of the periodic interrupt frequency.

• Fixed problem with SNVS entering into fail state when HAB enters closed mode.

[2.1.1]

• Added APIs for HP security violation status flags.

[2.1.0]

• Added APIs for High Assurance Counter (HAC), Zeroizable Master Key (ZMK) and Software Security Violation.

[2.0.0]

• Initial version.

---

SNVS_LP

[2.4.6]

• Fix a bug in SNVS_LP_EnableRxActiveTamper() where assignments to base->LPATRC2R were done wrongly to LPATRC1R.

[2.4.5]

• Fix a bug in SNVS_LP_EnableRxActiveTamper() where assignments to base->LPATRC1R would overwrite previously set bits.

[2.4.4]

• Make SNVS_LP_SRTC_Init()/SNVS_LP_SRTC_Deinit more transparent. Use function SNVS_LP_Init()/SNVS_LP_Deinit() instead of copy of this code in SNVS_LP_SRTC_XXX() function.

[2.4.3]

• Fixed problem in SNVS_LP_SRTC_Init(), which is clearing bits that should stay intact.

[2.4.2]

• Updated driver to match with new device header files.

[2.4.1]

• Fixed MISRA issues.

[2.4.0]

• Fix backward compatibility with version 2.2.x.

[2.3.0]

• Add active pin, clock, voltage and temperature tamper features.

[2.2.0]

• Fixed doxygen issues.

• Add Transition SNVS SSM state to Trusted/Non-secure from Check state.

[2.1.2]

• Fix MISRA issues.

[2.1.1]

• Fix IAR Pa082 warning.

[2.1.0]

• Added APIs for Zeroizable Master Key (ZMK) and Monotonic Counter (MC).

[2.0.0]

• Initial version.

---

TMU

[2.0.3]

• Bug Fixes

  • Fixed the violations of MISRA 2012 rules:

    • Rule 10.1 10.3 10.4 17.7.

[2.0.2]

• Bug Fixes

  • Fixed missing right pair definition for extern C.

[2.0.1]

• New Features

  • Added control macro to enable/disable the CLOCK code in current driver.

[2.0.0]

• Initial version.

• This module was first developed on i.MX 8MQuad.

---

UART

[2.3.2]

• Improvements

  • Make driver aarch64 compatible

[2.3.1]

• Improvements

  • Use separate data for TX and RX in uart_transfer_t.

• Bug Fixes

  • Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling UART_TransferReceiveNonBlocking, the received data count returned by UART_TransferGetReceiveCount is wrong.

[2.3.0]

• Bug Fixes

  • Fixed DMA transfer blocking issue by enabling tx idle interrupt after DMA transmission finishes.

[2.2.1]

• Bug Fixes

  • Fixed MISRA 2012 rule 10.4 violation.

[2.2.0]

• New Features

  • Modified uart_config_t, UART_Init and UART_GetDefaultConfig APIs so that the RTS and CTS used for hardware flow control can be enabled during module initialization.

  • Added API UART_SetRxRTSWatermark so that the water mark level of RTS deassertion can be configured.

[2.1.1]

• Bug Fixes

  • Fixed MISRA 8.5 violation.

[2.1.0]

• Improvements

  • Added timeout mechanism when waiting for certain states in transfer driver.

[2.0.2]

• Improvements

  • Added check for transmission complete in UART_WriteBlocking, UART_TransferHandleIRQ and UART_SendSDMACallback to ensure all the data would be sent out to bus.

  • Modified UART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.

• Bug Fixes

  • Fixed MISRA issues.

    • Fixed rules 10.1, 10.3, 10.4, 10.6, 10.7, 10.8, 11.9, 14.4.

[2.0.1]

• Bug Fixes

  • Memset local variable SDMA transfer configuration structure to make sure unused members in structure are cleared.

[2.0.0]

• Initial version.

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WDOG

[2.2.0]

• Bug Fixes

  • Fixed the wrong behavior of workMode.enableWait, workMode.enableStop, workMode.enableDebug in configuration structure wdog_config_t. When set the items to true, WDOG will continues working in those modes.

[2.1.1]

• Bug Fixes

  • MISRA C-2012 issue fixed: rule 10.1, 10.3, 10.4, 10.6, 10.7 and 11.9.

  • Fixed the issue of the inseparable process interrupted by other interrupt source.

    • WDOG_Init

    • WDOG_Refresh

[2.1.0]

• New Features

  • Added new API “WDOG_TriggerSystemSoftwareReset()” to allow users to reset the system by software.

  • Added new API “WDOG_TriggerSoftwareSignal()” to allow users to trigger a WDOG_B signal by software.

  • Removed the parameter “softwareAssertion” and “softwareResetSignal” out of the wdog_config_t structure.

  • Added new parameter “enableTimeOutAssert” to the wdog_config_t structure. With this parameter enabled, when the WDOG timeout occurs, a WDOG_B signal will be asserted. This signal can be routed to external pin of the chip. Note that WDOG_B signal remains asserted until a power-on reset (POR) occurs.

[2.0.1]

• New Features

  • Added control macro to enable/disable the CLOCK code in current driver.

[2.0.0]

• Initial version.

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