MIMX94398

MIMX94398#

AOI: Crossbar AND/OR/INVERT Driver#

void AOI_Init(AOI_Type *base)

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Index of the event which will be set of type aoi_event_t.
config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Event which will be configured of type aoi_event_t.
eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION: Version 2.0.2.

enum _aoi_input_config

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero: Forces the input to logical zero.

enumerator kAOI_InputSignal: Passes the input signal.

enumerator kAOI_InvInputSignal: Inverts the input signal.

enumerator kAOI_LogicOne: Forces the input to logical one.

enum _aoi_event

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0: Event 0 index

enumerator kAOI_Event1: Event 1 index

enumerator kAOI_Event2: Event 2 index

enumerator kAOI_Event3: Event 3 index

typedef enum _aoi_input_config aoi_input_config_t

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t: AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI: AOI peripheral address

struct _aoi_event_config

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC: Product term 0 input A

aoi_input_config_t PT0BC: Product term 0 input B

aoi_input_config_t PT0CC: Product term 0 input C

aoi_input_config_t PT0DC: Product term 0 input D

aoi_input_config_t PT1AC: Product term 1 input A

aoi_input_config_t PT1BC: Product term 1 input B

aoi_input_config_t PT1CC: Product term 1 input C

aoi_input_config_t PT1DC: Product term 1 input D

aoi_input_config_t PT2AC: Product term 2 input A

aoi_input_config_t PT2BC: Product term 2 input B

aoi_input_config_t PT2CC: Product term 2 input C

aoi_input_config_t PT2DC: Product term 2 input D

aoi_input_config_t PT3AC: Product term 3 input A

aoi_input_config_t PT3BC: Product term 3 input B

aoi_input_config_t PT3CC: Product term 3 input C

aoi_input_config_t PT3DC: Product term 3 input D

Battery-Backed Non-Secure Module#

void BBNSM_Init(BBNSM_Type *base)

Init the BBNSM section.

Parameters:

base – BBNSM peripheral base address

void BBNSM_Deinit(BBNSM_Type *base)

Deinit the BBNSM section.

Parameters:

base – BBNSM peripheral base address

FSL_BBNSM_DRIVER_VERSION: Version 2.0.0

enum _bbnsm_interrupts

List of BBNSM interrupts.

Values:

enumerator kBBNSM_RTC_AlarmInterrupt: RTC time alarm interrupt

enumerator kBBNSM_RTC_RolloverInterrupt: RTC rollover interrupt

enum _bbnsm_status_flags

List of BBNSM flags.

Values:

enumerator kBBNSM_RTC_AlarmInterruptFlag: RTC time alarm interrupt flag

enumerator kBBNSM_RTC_RolloverInterruptFlag: RTC rollover interrupt flag

enumerator kBBNSM_PWR_ON_InterruptFlag: power on interrupt flag

enumerator kBBNSM_PWR_OFF_InterruptFlag: power off interrupt flag

enumerator kBBNSM_EMG_OFF_InterruptFlag: emergency power off interrupt flag

typedef enum _bbnsm_interrupts bbnsm_interrupts_t: List of BBNSM interrupts.

typedef enum _bbnsm_status_flags bbnsm_status_flags_t: List of BBNSM flags.

typedef struct _bbnsm_rtc_config bbnsm_rtc_config_t

BBNSM config structure.

This structure holds the configuration settings for the BBNSM peripheral. To initialize this structure to reasonable defaults, call the BBNSM_RTC_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

void BBNSM_RTC_Init(BBNSM_Type *base, const bbnsm_rtc_config_t *config)

Ungates the BBNSM clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the BBNSM driver.

Parameters:

base – BBNSM peripheral base address
config – Pointer to the user’s BBNSM rtc configuration structure.

void BBNSM_RTC_Deinit(BBNSM_Type *base)

Stops the RTC timer.

Parameters:

base – BBNSM peripheral base address

void BBNSM_RTC_GetDefaultConfig(bbnsm_rtc_config_t *config)

Fills in the BBNSM RTC config struct with the default settings.

The default values are as follows.

config->rtccalenable = false;
config->rtccalvalue = 0U;

Parameters:

config – Pointer to the user’s BBNSM configuration structure.

status_t BBNSM_RTC_SetAlarm(BBNSM_Type *base, uint32_t alarmSeconds)

Sets the BBNSM RTC alarm time.

The function sets the RTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error. Please note, that RTC alarm has limited resolution because only 32 most significant bits of RTC counter are compared to RTC Alarm register. If the alarm time is beyond RTC resolution, the function does not set the alarm and returns an error.

Parameters:

base – BBNSM peripheral base address
alarmSeconds –

Returns:

kStatus_Success: success in setting the BBNSM RTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed or is beyond resolution

uint32_t BBNSM_RTC_GetAlarm(BBNSM_Type *base)

Returns the BBNSM RTC alarm time.

Parameters:

base – BBNSM peripheral base address

struct _bbnsm_rtc_config

#include <fsl_bbnsm.h>

BBNSM config structure.

The config struct can be made const so it resides in flash

Public Members

bool rtcCalEnable: true: RTC calibration mechanism is enabled; false: No calibration is used

uint32_t rtcCalValue: Defines signed calibration value for RTC; This is a 5-bit 2’s complement value, range from -16 to +15

BiSS: BiSS Interface#

FSL_BISS_DRIVER_VERSION: Version 1.0.2

BISS_CTRLCOMM2_CMD_MASK

BISS_CTRLCOMM2_CMD_SHIFT

BISS_CTRLCOMM2_CMD(x)

BISS_CTRLCOMM2_IDA_TEST_MASK

BISS_CTRLCOMM2_IDA_TEST_SHIFT

BISS_CTRLCOMM2_IDA_TEST(x)

BISS_MASTER_COUNT

BISS_MAX_SLAVE_COUNT

BISS_MAX_CHAN_COUNT

BISS_IDS_VALID_MASK

BISS_STATUS1_SVALID_MASK(slvID)

BISS_MIN_MA_FREQ

BISS_MAX_SYS_CLK_FREQ

BISS_INSTR_CDM_0

BISS_INSTR_CDM_1

BISS_INSTR_CDM_NOT

BISS_INSTR_CTRL_FRAME

BISS_INSTR_REDUCE_CTRL_FRAME

BISS_AGS_ENABLE

BISS_AGS_DISABLE

enum _biss_channel_flags_t

Defines the BiSS channel flag.

Values:

enumerator BISS_UseCurrentChannel

enumerator BISS_UsePhyChannel1

enumerator BISS_UseNextChannel

enum _biss_prot_type_t

Defines the BiSS Master protocol type.

Values:

enumerator PROTOCOL_BISS_B

enumerator PROTOCOL_BISS_C

enumerator PROTOCOL_SSI

enumerator PROTOCOL_NOT_USED

enum _biss_align_type_t

Defines the SCD align type.

Values:

enumerator BISS_RightAlign

enumerator BISS_LeftAlign

enum _biss_trigger_mode_t

Defines trigger mode.

BISS_INSTR_TRIGGER - Data acquisition will be triggered by software BISS_AGS_TRIGGER - Data acquisition will automatically by setting repetion time BISS_PIN_TRIGGER - Data acquistion will be triggered by a pin GETSENS

Values:

enumerator BISS_INSTR_TRIGGER

enumerator BISS_AGS_TRIGGER

enumerator BISS_TIMEOUT_TRIGGER

enumerator BISS_PIN_TRIGGER

enum _biss_slave_role_t

BiSS slave role type.

Values:

enumerator BISS_Actuator

enumerator BISS_BusCoupler

enumerator BISS_TempSensor

enumerator BISS_RotaryEncoder

enumerator BISS_LinearEncoder

enumerator BISS_UnknowRole

enum _biss_encoder_type_t

Values:

enumerator BISS_SENSOR_ROTARY

enumerator BISS_SENSOE_LINEAR

enum _biss_data_type_t

Values:

enumerator BISS_DATA_SENSOR

enumerator BISS_DATA_ACTUATOR

typedef enum _biss_channel_flags_t biss_chan_flag_t: Defines the BiSS channel flag.

typedef enum _biss_prot_type_t biss_prot_type_t: Defines the BiSS Master protocol type.

typedef enum _biss_align_type_t biss_align_type_t: Defines the SCD align type.

typedef enum _biss_trigger_mode_t biss_trigger_mode_t

Defines trigger mode.

typedef enum _biss_slave_role_t biss_slave_role_t: BiSS slave role type.

typedef enum _biss_encoder_type_t biss_encoder_type_t

typedef enum _biss_data_type_t biss_data_type_t

typedef struct _biss_slave_info_t biss_slave_info_t: BiSS slave information.

typedef struct _biss_master_t biss_master_t: BiSS Master information.

biss_master_t *BISS_GetMaster(BISS_Type *base)

Get BiSS master handle pointer.

Parameters:

base – base BiSS peripheral address.

biss_master_t *BISS_MasterInit(BISS_Type *base, uint32_t srcClk_Hz, uint32_t ma_Hz, uint32_t ags_Hz)

Initialize the BiSS master. This function configures the BISS module with the input parameters. User should call this function before any BISS operations.

Parameters:

base – BiSS peripheral base address.
srcClk_Hz – BiSS sys clock frequency.
ma_Hz – BiSS MA clock frequency.
ags_Hz – BiSS AGS frequency.

Returns:

The BiSS master handle pointer.

int BISS_CalculateMADiv(biss_master_t *master, uint32_t srcClk_Hz, uint32_t ma_Hz)

Calculate BiSS MA master clock division valule.

Parameters:

master – BiSS master handle pointer.
srcClk_Hz – BiSS sys clock frequency.
ma_Hz – BiSS MA clock frequency.

Returns:

The division value. A negative number indicates an incorrect input.

int BISS_CalculateAGSDiv(biss_master_t *master, uint32_t srcClk_Hz, uint32_t AGSfre_Hz)

Calculate BiSS frame repetition rate division valule.

Parameters:

master – BiSS master handle pointer.
srcClk_Hz – BiSS sys clock frequency.
AGSfre_Hz – BiSS frame repetition frequency.

Returns:

The division value. A negative number indicates an incorrect input.

void BISS_SetFREQS(biss_master_t *master, uint8_t MADiv)

Set BiSS master MA clock division valule.

Parameters:

master – BiSS master handle pointer.
Div – MA clock frequency division value.

void BISS_SetFREQAGS(biss_master_t *master, uint8_t AGSDiv)

Set BiSS frame repetition rate.

Parameters:

master – BiSS master handle pointer.
Div – frame repetition rate division valule.

void BISS_SetFREQR(biss_master_t *master, uint8_t FREQRDiv)

Set BiSS Register data clock frequency.

Parameters:

master – BiSS master handle pointer.
Div – FREQR division value.

void BISS_SetNOCRC(biss_master_t *master, bool NoCRC)

Enable/disable CRC check.

Parameters:

master – BiSS master handle pointer.
NoCRC – true - not stroe CRC, false - store CRC.

void BISS_SetSingleRAMBank(biss_master_t *master, bool SingleBank)

Enable/disable single Bank.

Parameters:

master – BiSS master handle pointer.
SingleBank – true - use one RAM bank, false - use two RAM banks.

void BISS_SetProtocol(biss_master_t *master, biss_prot_type_t protType)

Set BiSS master protocol.

Parameters:

master – BiSS master handle pointer.
protType – BiSS protocol type.

void BISS_SetHoldCDM(biss_master_t *master, bool holdcdm)

set hold cmd after timeout.

Parameters:

master – BiSS master handle pointer.
holdcmd – true - hold cdm, false - not hold cdm.

void BISS_SetChannel(biss_master_t *master, int channel)

set default channel ID.

Parameters:

master – BiSS master handle pointer.
channel – channel ID 1 - 8.

void BISS_SetMOBusy(biss_master_t *master, uint8_t busy)

set processing time by the delay of the start bit at MO

Parameters:

master – BiSS master handle pointer.
busy – MO busy time.

void BISS_SetENMO(biss_master_t *master, bool enmo)

Enable/disable MO signal.

Parameters:

master – BiSS master handle pointer.
enmo – true - enable MO signal, false - disable MO signal.

void BISS_SetHoldBank(biss_master_t *master, bool holdbank)

Hold ram bank.

Parameters:

master – BiSS master handle pointer.
holdbank – true - hold bank, false - not hold bank.

void BISS_InitBissStatus(biss_master_t *master)

Initialize BiSS-C status.

Parameters:

master – BiSS master handle pointer.

void BISS_AbortTrans(biss_master_t *master)

Abort data transmission.

Parameters:

master – BiSS master handle pointer.

uint32_t BISS_GetStatus(biss_master_t *master)

Get BiSS master status1 register.

Parameters:

master – BiSS master handle pointer.

Returns:

BiSS master status1 register value.

void BISS_DisableAGS(biss_master_t *master)

Disable Automatic Get Sensor Data.

Parameters:

master – BiSS master handle pointer.

void BISS_EnableAGS(biss_master_t *master)

Enable Automatic Get Sensor Data.

Parameters:

master – BiSS master handle pointer.

uint32_t BISS_GetStepVal(biss_master_t *master, uint8_t slvID)

Get step value of BiSS slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

step value.

uint8_t BISS_GetLineDelay(biss_master_t *master)

Get line delay.

Parameters:

master – BiSS master handle pointer.

Returns:

line delay.

biss_trigger_mode_t BISS_GetTriggerMode(biss_master_t *master)

Get BiSS trigger mode.

Parameters:

master – BiSS master handle pointer.

Returns:

BiSS trigger mode.

void BISS_ChangeTriggerMode(biss_master_t *master, biss_trigger_mode_t triggerMode)

Change BiSS trigger mode.

Parameters:

master – BiSS master handle pointer.
triggerMode – BiSS trigger mode.

void BISS_InitBissSequence(biss_master_t *master)

Initialize BiSS sequence.

Parameters:

master – BiSS master handle pointer.

void BISS_InstrSend(biss_master_t *master, int instr, int ags)

send out instruction.

Parameters:

master – BiSS master handle pointer.
instr – BiSS instruction
ags – automatic get sensor data

void BISS_InstrWait(biss_master_t *master)

Wait for instruction to be processed.

Parameters:

master – BiSS master handle pointer.

void BISS_InstrSendandWait(biss_master_t *master, int instr, int ags)

Send out instruction and wait for it to be processed.

Parameters:

master – BiSS master handle pointer.
instr – BiSS instruction
ags – automatic get sensor data

status_t BISS_CMDProcess(biss_master_t *master, uint8_t IDS, uint8_t cmd)

BiSS command process.

Parameters:

master – BiSS master handle pointer.
IDS – slave device ID set.
cmd – BiSS command.

Returns:

kStatus_Success Successfully process command.

Returns:

kStatus_Fail failed to process command.

status_t BISS_ActivateAllSLV(biss_master_t *master)

Activate all slave devices.

Parameters:

master – BiSS master handle pointer.

Returns:

kStatus_Success Successfully activate all slave devices.

Returns:

kStatus_Fail failed to activate

biss_slave_info_t *BISS_SLVGet(biss_master_t *master, uint8_t slvID)

Return pointer of BiSS slave device.

Parameters:

master – BiSS master handle pointer.
slvID – Biss slave device ID 0 - 7.

Returns:

pointer of BiSS slave device.

status_t BISS_SLVWriteRegister(biss_master_t *master, uint8_t slvID, uint8_t regAddr, uint8_t regNum, uint8_t *buffer)

Write BiSS slave device’s registers.

Parameters:

master – BiSS master handle pointer.
slvID – Biss slave device ID 0 - 7.
regAddr – start register address.
regNum – Register number.
buffer – Data buffer.

Returns:

kStatus_Success Successfully write to register

Returns:

kStatus_Fail failed to write register

status_t BISS_SLVReadRegister(biss_master_t *master, uint8_t slvID, uint8_t regAddr, uint8_t regNum, uint8_t *buffer)

Read BiSS slave device’s registers.

Parameters:

master – BiSS master handle pointer.
slvID – Biss slave device ID 0 - 7.
regAddr – start register address.
regNum – Register number.
buffer – Data buffer.

Returns:

kStatus_Success Successfully read from register

Returns:

kStatus_Fail failed to read register

void BISS_SLVSetSCDEN(biss_master_t *master, uint8_t slvID, bool enable)

Enable/disable SCD of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
enable – true - SCD is available, false - SCD not available.

void BISS_SLVSetSCDLen(biss_master_t *master, uint8_t slvID, int SCDLen)

Set SCD length of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
SCDLen – SCD length.

void BISS_SLVSetCRCLen(biss_master_t *master, uint8_t slvID, int CRCLen)

Set CRC length of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
CRCLen – CRC length.

void BISS_SLVSetSCD(biss_master_t *master, uint8_t slvID, int SCDLen, int CRCLen)

Set SCD length and CRC length of the slave device.

Parameters:

master – BiSS master handle pointer.
slvid – slave device ID 0 - 7.
SCDLen – SCD length.
CRCLen – CRC length.

void BISS_SLVSetCRCPoly(biss_master_t *master, uint8_t slvID, int CRCPoly)

Set CRC polynomial of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
CRCPoly – CRC polynomial.

void BISS_SLVSetCRCStart(biss_master_t *master, uint8_t slvID, uint32_t CRCStart)

Set CRC start value of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
CRCStart – CRC start value.

void BISS_SLVSetLStop(biss_master_t *master, uint8_t slvID, bool enable)

Set leading stop bit of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
align – with/without leading stop bit on actuator data.

void BISS_SLVSetDataType(biss_master_t *master, uint8_t slvID, biss_data_type_t dataType)

Set data type of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
dataType – data type - sensor or actuator.

status_t BISS_SLVGetEDSBank(biss_master_t *master, uint8_t slvID, uint8_t *bank)

Get EDS bank number of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
bank – EDS bank number.

Returns:

kStatus_Success Successfully get EDS bank number.

Returns:

kStatus_Fail failed to get EDS bank number.

status_t BISS_SLVSelectBank(biss_master_t *master, uint8_t slvID, uint8_t bank)

Slect Ram bank of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
bank – bank number.

Returns:

kStatus_Success Successfully set bank number.

Returns:

kStatus_Fail failed to set bank number.

status_t BISS_SLVGetProfile(biss_master_t *master, uint8_t slvID, uint16_t *profile)

Get profile of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
profile – profile value.

Returns:

kStatus_Success Successfully get profile.

Returns:

kStatus_Fail failed to get profile.

status_t BISS_SLVGetSerialNum(biss_master_t *master, uint8_t slvID, uint32_t *serialNum)

Get serial number of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
serialNum – serial number.

Returns:

kStatus_Success Successfully get serial number.

Returns:

kStatus_Fail failed to get serial number.

status_t BISS_SLVGetManufacturerID(biss_master_t *master, uint8_t slvID, uint16_t *mfrID)

Get manufacturer ID of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
mfrID – device ID.

Returns:

kStatus_Success Successfully get manufacturer ID.

Returns:

kStatus_Fail failed to get manufacturer ID.

status_t BISS_SLVGetDeviceID(biss_master_t *master, uint8_t slaveID, uint8_t *devID)

Get device ID of the slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
devID – device ID.

Returns:

kStatus_Success Successfully get device ID.

Returns:

kStatus_Fail failed to get device ID.

status_t BISS_SLVUpdateWithProfile(biss_master_t *master, uint8_t slvID)

Update slave device information via Profile.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success Successfully update device information.

Returns:

kStatus_Fail failed to update device information.

status_t BISS_SLVUpdatewithCommonEDS(biss_master_t *master, uint8_t slvID)

Update slave device information via Common EDS.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success Successfully update device information.

Returns:

kStatus_Fail failed to update device information.

status_t BISS_SLVUpdatewithProfileEDS(biss_master_t *master, uint8_t slvID)

Update slave device information via ProfileEDS.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success Successfully update device information.

Returns:

kStatus_Fail failed to update device information.

status_t BISS_SLVScan(biss_master_t *master)

scan slave device in the BiSS bus.

Parameters:

master – BiSS master handle pointer.

Returns:

kStatus_Success Successfully scan slave devices.

Returns:

kStatus_Fail failed to scan slave devices.

status_t BISS_SLVDeactivate(biss_master_t *master, uint8_t slvID)

Deactivate slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success Successfully deactivate slave device.

Returns:

kStatus_Fail failed to deactivate slave device.

status_t BISS_SLVActivate(biss_master_t *master, uint8_t slvID)

Activate slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success Successfully activate slave device.

Returns:

kStatus_Fail failed to activate slave device.

uint8_t BISS_SLVGetCnt(biss_master_t *master)

Get slave device count.

Parameters:

master – BiSS master handle pointer.

Returns:

slave device count.

void BISS_SLVSetup(biss_master_t *master, uint8_t slvID)

setup slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

uint64_t BISS_SLVGetSCDRawData(biss_master_t *master, uint8_t slvID)

Get SCD data of a slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

SCD data.

status_t BISS_SLVCheckSVALID(biss_master_t *master, uint8_t slvID)

Check if SCD data is valid.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

kStatus_Success SCD is valid.

Returns:

kStatus_Fail SCD is invalid.

void BISS_SLVResetSVALID(biss_master_t *master, uint8_t slvID)

Reset SVALID bit.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

status_t BISS_SLVGetSCD(biss_master_t *master, uint8_t slvID, uint64_t *SCData)

Get SCD data of a slave device.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.
SCData – SCD data.

Returns:

kStatus_Success SCD is valid.

Returns:

kStatus_Fail SCD is invalid.

int BISS_SCDGetnWarning(biss_master_t *master, uint8_t slvID, uint64_t SCData)

Get warning status from SCDdata.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

warning status.

int BISS_SCDGetnERR(biss_master_t *master, uint8_t slvID, uint64_t SCData)

Get error status from SCDdata.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

error status.

uint64_t BISS_SCDGetLinear(biss_master_t *master, uint8_t slvID, uint64_t SCData)

Get linear data from SCDdata.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

linear data.

uint64_t BISS_SCDGetMtVal(biss_master_t *master, uint8_t slvID, uint64_t SCData)

Get multiple turn data from SCDdata.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

multiple turn data.

uint64_t BISS_SLVGetStVal(biss_master_t *master, uint8_t slvID, uint64_t SCData)

Get single turn data from SCDdata.

Parameters:

master – BiSS master handle pointer.
slvID – slave device ID 0 - 7.

Returns:

single turn data.

BISS_FREQS_DEFAULT: BiSS default MA clock 100KHZ.

BISS_FREQR_DEFAULT

BISS_AGS_MIN

BISS_AGS_INFINITE

BISS_CMD_IDS_BOARDCAST

BISS_CMD_IDS_FRM_SLV(slvID)

BISS_CFGCH_MASK(x)

BISS_CFGCH_SEL(x, y)

BISS_CHSEL(x)

BISS_CHANNEL1

BISS_CMD_BOARDCAST_ALL_DEACTIVATED

BISS_CMD_BOARDCAST_CTRL_ACTIVATED

BISS_CMD_BOARDCAST_DEACTIVATED_BUS

BISS_CMD_BOARDCAST_RESERVED

BISS_CMD_ADDRESSED_ACTIVATED

BISS_CMD_ADDRESSED_DEACTIVATED

BISS_CMD_ADDRESSED_ACTIVATE_BUS

BISS_CMD_ADDRESSED_FREE

BISS_CTRL_CMD

BISS_REG_ACCESS

BISS_MAX_RDATA_COUNT

BISS_REG_ACCESS_READ

BISS_REG_ACCESS_WRITE

BISS_REGVERS_B

BISS_REGVERS_C

BISS_INIT_PROC

BISS_EN_MO_DISABLE

BISS_EN_MO_ENABLE

BISS_DEV_REG_LEN_1: BiSS slave device register.

BISS_DEV_REG_LEN_2

BISS_DEV_REG_LEN_3

BISS_DEV_REG_LEN_4

BISS_DEV_BANK_SEL_ADDR

BISS_DEV_EDS_BANK_NUM_ADDR

BISS_DEV_PROFILE_ADDR

BISS_DEV_PROFILE_LEN

BISS_DEV_SN_ADDR

BISS_DEV_SN_LEN

BISS_DEV_ID_ADDR

BISS_DEV_ID_LEN

BISS_DEV_MFR_ID_ADDR

BISS_DEV_MFR_ID_LEN

BISS_EDS_VER_ADDR: BiSS slave device EDS Commo register.

BISS_EDS_LEN_ADDR

BISS_EDS_USR_STA_ADDR

BISS_EDS_USR_END_ADDR

BISS_EDS_TMA_ADDR

BISS_EDS_TO_MIN_ADDR

BISS_EDS_TO_MAX_ADDR

BISS_EDS_TOS_MIN_ADDR

BISS_EDS_TOS_MAX_ADDR

BISS_EDS_TCLK_MIN_ADDR

BISS_EDS_TCLK_MAX_ADDR

BISS_EDS_TCYC_ADDR

BISS_EDS_TBUSY_MAX_ADDR

BISS_EDS_BUSY_S_ADDR

BISS_EDS_PON_DLY_ADDR

BISS_EDS_PON_DLY_LEN

BISS_EDS_DC_NUM_ADDR

BISS_EDS_SL_NUM_ADDR

BISS_EDS_SL_OFF_ADDR

BISS_EDS_BANK1_ADDR

BISS_EDS_DLEN1_ADDR

BISS_EDS_FORMAT1_ADDR

BISS_EDS_CPOLY1_ADDR

BISS_EDS_BANK_CHAN_BASE

BISS_EDS_CHAN_OFFSET

BISS_EDS_BANK_CHAN_ADDR(channel)

BISS_EDS_DLEN_CHAN_BASE

BISS_EDS_DLEN_CHAN_ADDR(channel)

BISS_EDS_FORMAT_CHAN_BASE

BISS_EDS_FORMAT_CHAN_ADDR(channel)

BISS_EDS_CPOLY_CHAN_BASE

BISS_EDS_CPOLY_CHAN_ADDR(channel)

BISS_EDS_FORMAT_TYPE_OFFSET

BISS_EDS_FORMAT_TYPE_MASK

BISS_EDS_FORMAT_GET_TYPE(x)

BISS_EDS_FORMAT_ALIGN_OFFSET

BISS_EDS_FORMAT_ALIGN_MASK

BISS_EDS_FORMAT_GET_ALIGN(x)

BISS_EDS_FORMAT_STOPBIT_OFFSET

BISS_EDS_FORMAT_STOPBIT_MASK

BISS_EDS_FORMAT_GET_STOPBIT(x)

BISS_FORMAT_TYPE_MASK

BISS_FORMAT_TYPE_SHIFT

BISS_FORMAT_GET_TYPE(x)

BISS_SENSOR_ROLE

BISS_ACTUATOR_ROLE

BISS_FORMAT_LSTOP_MASK

BISS_FORMAT_LSTOP_SHIFT

BISS_FORMAT_LSTOP_GET(x)

BISS_FORMAT_LSTOP_DISABLE

BISS_FORMAT_LSTOP_ENABLE

BISS_FORMAT_ALIGN_MASK

BISS_FORMAT_ALIGN_SHIFT

BISS_FORMAT_ALIGN_GET(x)

BISS_FORMAT_ALIGN_RIGHT

BISS_FORMAT_ALIGN_LEFT

BISS_EDS_BC_OFFSET_ADDR

BISS_EDS_BC_OFFSET_LEN

BISS_BC_ENABLE_MASK

BISS_BC_OFFSET_MASK

BISS_EDS_MTLEN_ADDR

BISS_EDS_MTLEN_LEN

BISS_EDS_MTFMT_ADDR

BISS_EDS_MTFMT_LEN

BISS_EDS_SIPCNT_ADDR

BISS_EDS_SIPCNT_LEN

BISS_EDS_ENTYP_ADDR

BISS_EDS_ENTYP_LEN

BISS_BP0_PROFILE_ID: BiSS slave device BP0 register.

BISS_BP0_PROFILE_ID_MASK

BISS_BP0_PROFILE_ID_SHIFT

BISS_BP0_PROFILE_ID_GET(x)

BISS_BP0_DATA_LEN_MASK

BISS_BP0_DATA_LEN_SHIFT

BISS_BP0_DATA_LEN_GET(x)

BISS_BP0_APL_ID_MASK

BISS_BP0_APL_ID_SHIFT

BISS_BP0_APL_TYPE_MASK

BISS_BP0_APL_TYPE_SHIFT

BISS_BP0_APL_TYPE_GET(x)

BISS_BP0_SENSOR

BISS_BP0_ACTUATOR

BISS_BP0_CRCPOLY

BISS_TEMP_8BIT_MASK

BISS_TEMP_12BIT_SYM_MASK

BISS_TEMP_16BIT_MASK

BISS_BP3_PROFILE_ID: BiSS slave device BP3 register.

BISS_BP3_PROFILE_ID_MASK

BISS_BP3_PROFILE_ID_SHIFT

BISS_BP3_PROFILE_ID_GET(x)

BISS_BP3_CRC_MASK

BISS_BP3_VER_MASK

BISS_BP3_VER_SHIFT

BISS_BP3_DATA_LEN_MASK

BISS_BP3_DATA_LEN_SHIFT

BISS_BP3_DATA_LEN_GET(x)

BISS_BP3_CRCPOLY

BISS_BP3S_PROFILE_ID

BISS_BP3S_PROFILE_ID_MASK

BISS_BP3S_PROFILE_ID_SHIFT

BISS_BP3S_PROFILE_ID_GET(x)

BISS_BP3S_CRC_MASK

BISS_BP3S_VER_MASK

BISS_BP3S_VER_SHIFT

BISS_BP3S_DATA_LEN_MASK

BISS_BP3S_DATA_LEN_SHIFT

BISS_BP3S_DATA_LEN_GET(x)

BISS_BP3S_CRCPOLY

BISS_SPEC_CPOLY_ADDR

BISS_SPEC_CPOLY_LEN

BISS_SPEC_CSTART_ADDR

BISS_SPEC_CSTART_LEN

BISS_SCD_BINARY_CODED

BISS_SCD_GRAY_CODED

BISS_SEL_SCRCLEN

BISS_SEL_SCRCPOLY

BISS_LINEDELAY_MASK

BISS_BREAK_ENABLE

struct _biss_slave_info_t

#include <fsl_biss.h>

BiSS slave information.

Public Members

bool stopBit: Stop bit enable flag, enabled with role is Actuator

uint8_t EDSSlvID: The slave ID which has EDS info

uint8_t commEDS: common EDS ID, enabled with commEDS != 0

uint8_t profileEDS: specification EDS ID, enabled with specEDS != 0

uint8_t crcLen: CRC length of tranfered data

uint32_t crcPoly: CRC poly for transfer, enabled with dataLen != 0

uint32_t crcStart: CRC start value, enabled with dataLen != 0

biss_data_type_t dataType: Sensor or Actuator

uint8_t dataLen: Data length of tranfered data

uint8_t errWarLen: error and warning bit number

uint8_t mtLen: Multiturn number, enabled with role = rotary

uint8_t stLen: Singleturn number, enabled with role = rotary

biss_align_type_t dataAlign: Data align type, the align show data format which stored in SCData register, left align or right align

uint8_t mtAlign: Multiturn data align type

uint8_t stAlign: Singleturn data align type stored in SCData

uint64_t mtMask: Multiturn mask for multitrun data getting

uint64_t stMask: Singleturn mask for singleturn data getting

uint32_t step: The resolution ratio for singleturn data

struct _biss_master_t

#include <fsl_biss.h>

BiSS Master information.

Public Members

uint8_t maxProcTime: The max process time allowed

uint8_t processTime: Additional processing time SCD in clocks

CACHE: ARMV7-M7 CACHE Memory Controller#

static inline void L1CACHE_EnableICache(void): Enables cortex-m7 L1 instruction cache.

static inline void L1CACHE_DisableICache(void): Disables cortex-m7 L1 instruction cache.

static inline void L1CACHE_InvalidateICache(void): Invalidate cortex-m7 L1 instruction cache.

void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)

Invalidate cortex-m7 L1 instruction cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The start address of the memory to be invalidated.
size_byte – The memory size.

static inline void L1CACHE_EnableDCache(void): Enables cortex-m7 L1 data cache.

static inline void L1CACHE_DisableDCache(void): Disables cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCache(void): Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_CleanDCache(void): Cleans cortex-m7 L1 data cache.

static inline void L1CACHE_CleanInvalidateDCache(void): Cleans and Invalidates cortex-m7 L1 data cache.

static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m7 L1 data cache by range.

Note

The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The start address of the memory to be invalidated.
size_byte – The memory size.

static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cortex-m7 L1 data cache by range.

Note

Parameters:

address – The start address of the memory to be cleaned.
size_byte – The memory size.

static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates cortex-m7 L1 data cache by range.

Note

Parameters:

address – The start address of the memory to be clean and invalidated.
size_byte – The memory size.

void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address.
size_byte – size of the memory to be invalidated.

void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

Parameters:

address – The physical address.
size_byte – size of the memory to be invalidated.

void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

Parameters:

address – The physical address.
size_byte – size of the memory to be cleaned.

void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Note

Parameters:

address – The physical address.
size_byte – size of the memory to be cleaned and invalidated.

FSL_CACHE_DRIVER_VERSION: cache driver version 2.0.6.

Clock Driver#

DCIF: Display control Interface#

void DCIF_Init(DCIF_Type *base)

Initializes the DCIF .

This function ungates the DCIF clock and release the peripheral reset.

Parameters:

base – DCIF peripheral base address.

void DCIF_Deinit(DCIF_Type *base)

Deinitializes the DCIF peripheral.

Parameters:

base – DCIF peripheral base address.

void DCIF_Reset(DCIF_Type *base)

Reset the DCIF.

Parameters:

base – DCIF peripheral base address.

void DCIF_DisplayGetDefaultConfig(dcif_display_config_t *config)

Gets the DCIF display default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config->panelWidth    = 0U;
config->panelHeight   = 0U;
config->hsw           = 3U;
config->hfp           = 3U;
config->hbp           = 3U;
config->vsw           = 3U;
config->vfp           = 3U;
config->vbp           = 3U;
config->polarityFlags = kDCIF_VsyncActiveHigh | kDCIF_HsyncActiveHigh | kDCIF_DataEnableActiveHigh |
                        kDCIF_DriveDataOnRisingClkEdge | kDCIF_DataActiveHigh;
config->lineOrder       = kDCIF_LineOrderRGB;

Parameters:

config – Pointer to the DCIF configuration structure.

void DCIF_SetDisplayConfig(DCIF_Type *base, const dcif_display_config_t *config)

Set the DCIF display configurations.

Parameters:

base – DCIF peripheral base address.
config – Pointer to the DCIF configuration structure.

static inline void DCIF_EnableDisplay(DCIF_Type *base, bool enable)

Enable or disable the display.

Parameters:

base – DCIF peripheral base address.
enable – Enable or disable.

static inline void DCIF_EnableInterrupts(DCIF_Type *base, uint32_t mask)

Enables DCIF interrupt requests.

Parameters:

base – DCIF peripheral base address.
mask – interrupt source, OR’ed value of _dcif_interrupt.

static inline void DCIF_DisableInterrupts(DCIF_Type *base, uint8_t domain, uint32_t mask)

Disables DCIF interrupt requests.

Parameters:

base – DCIF peripheral base address.
domain – CPU domain the interrupt signal routed to.
mask – interrupt source, OR’ed value of _dcif_interrupt.

static inline uint32_t DCIF_GetInterruptStatus(DCIF_Type *base)

Get DCIF interrupt peding status.

Parameters:

base – DCIF peripheral base address.

Returns:

Interrupt pending status, OR’ed value of _dcif_interrupt.

static inline void DCIF_ClearInterruptStatus(DCIF_Type *base, uint32_t mask)

Clear DCIF interrupt peding status.

Parameters:

base – DCIF peripheral base address.
mask – of the flags to clear, OR’ed value of _dcif_interrupt.

static inline void DCIF_SetLayerPosition(DCIF_Type *base, uint8_t layerIndex, uint16_t posy, uint16_t posx)

Set the layer origin position.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.
posy – Layer vertical position.
posx – Layer horizontal position.

static inline void DCIF_SetLayerSize(DCIF_Type *base, uint8_t layerIndex, uint16_t width, uint16_t height)

Set the layer dimension.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.
width – Layer width in pixel.
height – Layer height.

void DCIF_SetLayerBufferConfig(DCIF_Type *base, uint8_t layerIndex, const dcif_buffer_config_t *config)

Set the layer source buffer configuration.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.
config – Pointer to the configuration.

static inline void DCIF_SetLayerBufferAddr(DCIF_Type *base, uint8_t layerIndex, uint32_t addr)

Set the layer source buffer address.

This function is used for fast runtime source buffer change.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.
addr – The new source buffer address passed to the layer, should be 16-bit aligned.

static inline void DCIF_EnableLayer(DCIF_Type *base, uint8_t layerIndex, bool enable)

Enable or disable the layer.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.
enable – Pass in true to enable, false to disable.

static inline void DCIF_TriggerLayerShadowLoad(DCIF_Type *base, uint8_t layerIndex)

Trigger the layer configuration shadow load.

The new layer configurations are written to the shadow registers first, When all configurations written finished, call this function, then shadowed control registers are updated to the active control registers on VSYNC of next frame.

Parameters:

base – DCIF peripheral base address.
layerIndex – Layer layerIndex.

void DCIF_SetCscMode(DCIF_Type *base, dcif_csc_mode_t mode)

Set the color space conversion mode.

Supports YUV2RGB and YCbCr2RGB.

Parameters:

base – DCIF peripheral base address.
layerIndex – Index of the layer.
mode – The conversion mode.

FSL_DCIF_DRIVER_VERSION: DCIF driver version.

enum _dcif_polarity_flags

DCIF signal polarity flags.

Values:

enumerator kDCIF_VsyncActiveHigh: VSYNC active high.

enumerator kDCIF_HsyncActiveHigh: HSYNC active high.

enumerator kDCIF_DataEnableActiveHigh: Data enable line active high.

enumerator kDCIF_DriveDataOnRisingClkEdge: Output data on rising clock edge, capture data on falling clock edge.

enumerator kDCIF_DataActiveHigh: Data active high.

enumerator kDCIF_VsyncActiveLow: VSYNC active low.

enumerator kDCIF_HsyncActiveLow: HSYNC active low.

enumerator kDCIF_DataEnableActiveLow: Data enable line active low.

enumerator kDCIF_DriveDataOnFallingClkEdge: Output data on falling clock edge, capture data on rising clock edge.

enumerator kDCIF_DataActiveLow: Data active high.

enum _dcif_interrupt

The DCIF interrupts.

Values:

enumerator kDCIF_CrcErrorSaturationInterrupt

enumerator kDCIF_CrcErrorEnableInterrupt

enumerator kDCIF_HistogramMeasureDoneInterrupt

enumerator kDCIF_FifoEmptyInterrupt: FIFO empty.

enumerator kDCIF_DmaDoneInterrupt: DMA done.

enumerator kDCIF_DmaErrorInterrupt: DMA error.

enumerator kDCIF_VerticalBlankingInterrupt: Start of vertical blanking period.

enumerator kDCIF_OutputUnderrunInterrupt: Output buffer underrun.

enumerator kDCIF_VsyncEdgeInterrupt: Interrupt at VSYNC edge.

enum _dcif_line_order

The DCIF output line order.

Values:

enumerator kDCIF_LineOrderRGB: RGB

enumerator kDCIF_LineOrderRBG: RBG

enumerator kDCIF_LineOrderGBR: GBR

enumerator kDCIF_LineOrderGRB: GRB

enumerator kDCIF_LineOrderBRG: BRG

enumerator kDCIF_LineOrderBGR: BGR

enumerator kDCIF_LineOrderRGB555: RGB555

enumerator kDCIF_LineOrderRGB565: RGB565

enum _dcif_csc_mode

DCIF color space conversion mode.

Values:

enumerator kDCIF_CscYUV2RGB: YUV to RGB.

enumerator kDCIF_CscYCbCr2RGB: YCbCr to RGB.

enum _dcif_pixel_format

DCIF pixel format.

Values:

enumerator kDCIF_PixelFormat1bpp: 1bpp, only use for layer 0.

enumerator kDCIF_PixelFormat2bpp: 2bpp, only use for layer 0.

enumerator kDCIF_PixelFormat4bpp: 4bpp, only use for layer 0.

enumerator kDCIF_PixelFormat8bpp: 8bpp, only use for layer 0.

enumerator kDCIF_PixelFormatRGB565: RGB565, two pixels use 32 bits.

enumerator kDCIF_PixelFormatARGB1555: ARGB1555, two pixels use 32 bits.

enumerator kDCIF_PixelFormatARGB4444: ARGB4444, two pixels use 32 bits.

enumerator kDCIF_PixelFormatYVYU: YVYU {Y2,V1,Y1,U1}

enumerator kDCIF_PixelFormatYUYV: YUYV {Y2,U1,Y1,V1}

enumerator kDCIF_PixelFormatVYUY: VYUY {V1,Y2,U1,Y1}

enumerator kDCIF_PixelFormatUYVY: UYVY {U1,Y2,V1,Y1}

enumerator kDCIF_PixelFormatRGB888: RGB888 packed, one pixel uses 24 bits.

enumerator kDCIF_PixelFormatARGB8888: ARGB8888 unpacked, one pixel uses 32 bits.

enumerator kDCIF_PixelFormatABGR8888: ABGR8888 unpacked, one pixel uses 32 bits.

typedef enum _dcif_line_order dcif_line_order_t: The DCIF output line order.

typedef struct _dcif_display_config dcif_display_config_t: DCIF display configure structure.

typedef enum _dcif_csc_mode dcif_csc_mode_t: DCIF color space conversion mode.

typedef enum _dcif_pixel_format dcif_pixel_format_t: DCIF pixel format.

typedef struct _dcif_buffer_config dcif_buffer_config_t: DCIF source buffer configuration.

DCIF_ADDR_CPU_2_IP(addr)

DCIF_MAKE_FIFO_EMPTY_INTERRUPT(layer): DCIF FIFO empty interrupt.

DCIF_MAKE_DMA_DONE_INTERRUPT(layer): DCIF DMA done interrupt.

DCIF_MAKE_DMA_ERROR_INTERRUPT(layer): DCIF DMA error interrupt.

struct _dcif_display_config

#include <fsl_dcif.h>

DCIF display configure structure.

Public Members

uint16_t panelWidth: Display panel width, pixels per line.

uint16_t panelHeight: Display panel height, how many lines per panel.

uint8_t hsw: HSYNC pulse width.

uint8_t hfp: Horizontal front porch.

uint8_t hbp: Horizontal back porch.

uint8_t vsw: VSYNC pulse width.

uint8_t vfp: Vrtical front porch.

uint8_t vbp: Vertical back porch.

uint32_t polarityFlags: OR’ed value of _dcif_polarity_flags, used to contol the signal polarity.

dcif_line_order_t lineOrder: Line order.

struct _dcif_buffer_config

#include <fsl_dcif.h>

DCIF source buffer configuration.

Public Members

dcif_pixel_format_t pixelFormat: Source buffer pixel format.

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)

EDMA Channel initialization.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)

Set channel memory attribute.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)

Set channel sign extension.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)

Set channel swap size.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)

Set channel access type.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)

Set channel request source.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)

Gets the channel identification and attribute information on the system bus interface.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)

Set channel master ID replication.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an async request for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Parameters:

tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

Parameters:

tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.

Return values:

kStatus_Success –
kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

submit single transfer

edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit static link transfer,

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

submit dynamic link transfer

edma_tcd_t tcdpool[2];
EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit loop transfer

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

handle – eDMA handle pointer.

void EDMA_TcdInit(EDMA_Type *base, edma_tcd_t *tcdRegs)

Initialize all fields to 0 for the TCD structure.

This function initialize all fields for this TCD structure to 0.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.10.12.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull: TCD queue is full.

enumerator kStatus_EDMA_Busy: Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes: Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes: Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes: Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes: Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes: Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes: Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes: Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes: Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable: Disable modulo

enumerator kEDMA_Modulo2bytes: Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes: Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes: Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes: Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes: Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes: Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes: Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes: Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes: Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes: Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes: Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes: Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes: Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes: Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes: Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes: Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes: Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes: Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes: Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes: Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes: Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes: Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes: Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes: Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes: Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes: Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes: Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes: Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes: Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes: Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes: Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone: No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle: eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle: eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone: No channel link

enumerator kEDMA_MinorLink: Channel link after each minor loop

enumerator kEDMA_MajorLink: Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag: DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag: eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag: eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag: Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag: Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag: Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag: NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag: Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag: Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag: Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag: Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag: Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag: Transfer cancelled

enumerator kEDMA_ValidFlag: No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable: Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable: Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable: Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory: Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory: Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral: Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral: Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer: No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable: No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer: No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable: No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer: No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable: No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer: No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable: No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer: write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable: write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer: write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable: write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer: write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable: write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer: write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable: write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled: Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap: Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap: Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap: Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap: Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap: Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap: Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel: Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId: DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess: Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess: Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser: user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged: Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t: eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t: eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t: Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t: Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t: eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t: eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t: eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t: eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t: eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t: eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t: eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t: eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

typedef struct _edma_config edma_config_t: eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:: EDMA handle pointer, users shall not touch the values inside.
Param userData:: The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
Param transferDone:: If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
Param tcds:: How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t: eDMA transfer handle structure

FSL_EDMA_DRIVER_EDMA4: eDMA driver name

EDMA_ALLOCATE_TCD(name, number): Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel): Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption: If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility: If true: a channel can suspend other channel with low priority

uint8_t channelPriority: Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset: Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset: Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset: Offset for a minor loop mapping.

struct _edma_channel_config

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig: channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute: channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute: channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize: channel swap size configuration

edma_channel_access_type_t channelAccessType: channel access type configuration

uint8_t channelDataSignExtensionBitPosition: channel data sign extension bit psition configuration

uint32_t channelRequestSource: hardware service request source for the channel

bool enableMasterIDReplication: enable master ID replication

edma_channel_protection_level_t protectionLevel: protection level

struct _edma_transfer_config

#include <fsl_edma.h>

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

Public Members

uint32_t srcAddr: Source data address.

uint32_t destAddr: Destination data address.

edma_transfer_size_t srcTransferSize: Source data transfer size.

edma_transfer_size_t destTransferSize: Destination data transfer size.

int16_t srcOffset: Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset: Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes: bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts: minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask: channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo: source circular data queue range

int32_t srcMajorLoopOffset: source major loop offset

edma_modulo_t dstAddrModulo: destination circular data queue range

int32_t dstMajorLoopOffset: destination major loop offset

bool enableSrcMinorLoopOffset: enable source minor loop offset

bool enableDstMinorLoopOffset: enable dest minor loop offset

int32_t minorLoopOffset: burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink: channel link when major loop complete

uint32_t majorLoopLinkChannel: major loop link channel number

bool enableChannelMinorLoopLink: channel link when minor loop complete

uint32_t minorLoopLinkChannel: minor loop link channel number

edma_tcd_t *linkTCD: pointer to the link transfer control descriptor

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableContinuousLinkMode: Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.

bool enableMasterIdReplication: Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink: Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError: Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode: Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration: Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]: channel preemption configuration

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback: Callback function for major count exhausted.

void *userData: Callback function parameter.

EDMA_ChannelType *channelBase: eDMA peripheral channel base address.

EDMA_Type *base: eDMA peripheral base address

EDMA_TCDType *tcdBase: eDMA peripheral tcd base address.

edma_tcd_t *tcdPool: Pointer to memory stored TCDs.

uint32_t channel: eDMA channel number.

volatile int8_t header: The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail: The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed: The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize: The total number of TCD slots in the queue.

eDMA core Driver#

enum _edma_tcd_type

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag: Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag: Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t: edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t: edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t: eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t: edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t: edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t: edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType: EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType

typedef void EDMA_Type

DMA_CORE_MP_CSR_EDBG_MASK

DMA_CORE_MP_CSR_ERCA_MASK

DMA_CORE_MP_CSR_HAE_MASK

DMA_CORE_MP_CSR_HALT_MASK

DMA_CORE_MP_CSR_GCLC_MASK

DMA_CORE_MP_CSR_GMRC_MASK

DMA_CORE_MP_CSR_EDBG(x)

DMA_CORE_MP_CSR_ERCA(x)

DMA_CORE_MP_CSR_HAE(x)

DMA_CORE_MP_CSR_HALT(x)

DMA_CORE_MP_CSR_GCLC(x)

DMA_CORE_MP_CSR_GMRC(x)

DMA_CSR_INTMAJOR_MASK

DMA_CSR_INTHALF_MASK

DMA_CSR_DREQ_MASK

DMA_CSR_ESG_MASK

DMA_CSR_BWC_MASK

DMA_CSR_BWC(x)

DMA_CSR_START_MASK

DMA_CITER_ELINKNO_CITER_MASK

DMA_BITER_ELINKNO_BITER_MASK

DMA_CITER_ELINKNO_CITER_SHIFT

DMA_CITER_ELINKYES_CITER_MASK

DMA_CITER_ELINKYES_CITER_SHIFT

DMA_ATTR_SMOD_MASK

DMA_ATTR_DMOD_MASK

DMA_CITER_ELINKNO_ELINK_MASK

DMA_CSR_MAJORELINK_MASK

DMA_BITER_ELINKYES_ELINK_MASK

DMA_CITER_ELINKYES_ELINK_MASK

DMA_CSR_MAJORLINKCH_MASK

DMA_BITER_ELINKYES_LINKCH_MASK

DMA_CITER_ELINKYES_LINKCH_MASK

DMA_NBYTES_MLOFFYES_MLOFF_MASK

DMA_NBYTES_MLOFFYES_DMLOE_MASK

DMA_NBYTES_MLOFFYES_SMLOE_MASK

DMA_NBYTES_MLOFFNO_NBYTES_MASK

DMA_ATTR_DMOD(x)

DMA_ATTR_SMOD(x)

DMA_BITER_ELINKYES_LINKCH(x)

DMA_CITER_ELINKYES_LINKCH(x)

DMA_NBYTES_MLOFFYES_MLOFF(x)

DMA_NBYTES_MLOFFYES_DMLOE(x)

DMA_NBYTES_MLOFFYES_SMLOE(x)

DMA_NBYTES_MLOFFNO_NBYTES(x)

DMA_NBYTES_MLOFFYES_NBYTES(x)

DMA_ATTR_DSIZE(x)

DMA_ATTR_SSIZE(x)

DMA_CSR_DREQ(x)

DMA_CSR_MAJORLINKCH(x)

DMA_CH_MATTR_WCACHE(x)

DMA_CH_MATTR_RCACHE(x)

DMA_CH_CSR_SIGNEXT_MASK

DMA_CH_CSR_SIGNEXT_SHIFT

DMA_CH_CSR_SWAP_MASK

DMA_CH_CSR_SWAP_SHIFT

DMA_CH_SBR_INSTR_MASK

DMA_CH_SBR_INSTR_SHIFT

DMA_CH_SBR_EMI_MASK

DMA_CH_SBR_EMI_SHIFT

DMA_CH_MUX_SOURCE(x)

DMA_ERR_DBE_FLAG: DMA error flag.

DMA_ERR_SBE_FLAG

DMA_ERR_SGE_FLAG

DMA_ERR_NCE_FLAG

DMA_ERR_DOE_FLAG

DMA_ERR_DAE_FLAG

DMA_ERR_SOE_FLAG

DMA_ERR_SAE_FLAG

DMA_ERR_ERRCHAN_FLAG

DMA_ERR_ECX_FLAG

DMA_ERR_FLAG

DMA_CLEAR_DONE_STATUS(base, channel): get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)

DMA_ENABLE_ERROR_INT(base, channel): enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)

DMA_CLEAR_ERROR_STATUS(base, channel): get/clear error status

DMA_GET_ERROR_STATUS(base, channel)

DMA_CLEAR_INT_STATUS(base, channel): get/clear INT status

DMA_GET_INT_STATUS(base, channel)

DMA_ENABLE_MAJOR_INT(base, channel): enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)

DMA_DISABLE_MAJOR_INT(base, channel)

DMA_DISABLE_HALF_INT(base, channel)

EDMA_TCD_ALIGN_SIZE: EDMA tcd align size.

EDMA_CORE_BASE(base): EDMA base address convert macro.

EDMA_MP_BASE(base)

EDMA_CHANNEL_BASE(base, channel)

EDMA_TCD_BASE(base, channel)

EDMA_TCD_TYPE(x): EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag): EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)

EDMA_TCD_ATTR(tcd, flag)

EDMA_TCD_NBYTES(tcd, flag)

EDMA_TCD_SLAST(tcd, flag)

EDMA_TCD_DADDR(tcd, flag)

EDMA_TCD_DOFF(tcd, flag)

EDMA_TCD_CITER(tcd, flag)

EDMA_TCD_DLAST_SGA(tcd, flag)

EDMA_TCD_CSR(tcd, flag)

EDMA_TCD_BITER(tcd, flag)

struct _edma_core_mp

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT: Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR: Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI: Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint32_t SADDR_HIGH: SADDR HIGH register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t SLAST_SDA_HIGH: SLAST SDA HIGH register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint32_t DADDR_HIGH: DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH: DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

uint8_t RESERVED[16]: Aligned 64 bytes

struct _edma4_core_tcd

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

struct _edma_core_tcd: #include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS

Public Members

struct _edma_core_mp EDMA5_REG

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW: Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH: Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW: Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH: Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH: Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW: Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH: Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]: Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]: Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]: Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS

Public Members

struct _edma_core_channel EDMA5_REG

struct _edma_core_channel EDMA4_REG

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX: Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS

Public Members

edma4_core_tcd_t edma4_tcd

eDMA soc Driver#

enum _dma1_request_source

Values:

enumerator kDma1RequestMuxReserved0: nan

enumerator kDma1RequestMuxCan1: CAN-FD 1 DMA request and response

enumerator kDma1RequestMuxLptmr1: LPTIMER1 DMA request and response

enumerator kDma1RequestMuxReserved1: nan

enumerator kDma1RequestMuxTpm1Overflow: LPTPM1 DMA Overflow request and response

enumerator kDma1RequestMuxTpm2Overflow: LPTPM2 DMA Overflow request and response

enumerator kDma1RequestMuxPdm: PDM DMA request and response

enumerator kDma1RequestMuxAdc1: ADC DMA request

enumerator kDma1RequestMuxGpio1Ch0: GPIO1 channel 0 DMA request and response

enumerator kDma1RequestMuxGpio1Ch1: GPIO1 channel 1 DMA request and response

enumerator kDma1RequestMuxI3c1ToBus: I3C1 “To-bus” DMA request and response

enumerator kDma1RequestMuxI3c1FromBus: I3C1 “from-bus” DMA request and response

enumerator kDma1RequestMuxLpi2c1Tx: LPI2C1 Master TX DMA request; LPI2C1 Slave TX DMA request

enumerator kDma1RequestMuxLpi2c1Rx: LPI2C1 Master RX DMA request; LPI2C1 Slave RX DMA request

enumerator kDma1RequestMuxLpi2c2Tx: LPI2C2 Master TX DMA request; LPI2C2 Slave TX DMA request

enumerator kDma1RequestMuxLpi2c2Rx: LPI2C2 Master RX DMA request; LPI2C2 Slave RX DMA request

enumerator kDma1RequestMuxLpspi1Tx: LPSPI1 TX DMA request

enumerator kDma1RequestMuxLpspi1Rx: LPSPI1 RX DMA request

enumerator kDma1RequestMuxLpspi2Tx: LPSPI2 TX DMA request

enumerator kDma1RequestMuxLpspi2Rx: LPSPI2 RX DMA request

enumerator kDma1RequestMuxLpuart1Tx: LPUART1 DMA TX request

enumerator kDma1RequestMuxLpuart1Rx: LPUART1 DMA RX request and response

enumerator kDma1RequestMuxLpuart2Tx: LPUART2 DMA TX request

enumerator kDma1RequestMuxLpuart2Rx: LPUART2 DMA RX request and response

enumerator kDma1RequestMuxSai1Tx: SAI1 TX DMA request and response

enumerator kDma1RequestMuxSai1Rx: SAI1 RX DMA request and response

enumerator kDma1RequestMuxTpm1Ch0Ch2: LPTPM1 DMA Channel 0 request and response; LPTPM1 DMA Channel 2 request and response

enumerator kDma1RequestMuxTpm1Ch1Ch3: LPTPM1 DMA Channel 1 request and response; LPTPM1 DMA Channel 3 request and response

enumerator kDma1RequestMuxTpm2Ch0Ch2: LPTPM2 DMA Channel 0 request and response; LPTPM2 DMA Channel 2 request and response

enumerator kDma1RequestMuxTpm2Ch1Ch3: LPTPM2 DMA Channel 1 request and response; LPTPM2 DMA Channel 3 request and response

enumerator kDma1RequestMuxReserved2: Reserved - PDM Digital Microphone Interface DMA request and response

enumerator kDma1RequestMuxReserved3: nan

enum _dma2_request_source

Values:

enumerator kDma2RequestMuxReserved0: Default - Channel Disabled (Do Not Re-assign)

enumerator kDma2RequestMuxGpio2Ch0: GPIO2 channel 0 DMA request and response

enumerator kDma2RequestMuxGpio2Ch1: GPIO2 channel 1 DMA request and response

enumerator kDma2RequestMuxI3c2ToBus: I3C2 “To-bus” DMA request and response

enumerator kDma2RequestMuxI3c2FromBus: I3C2 “from-bus” DMA request and response

enumerator kDma2RequestMuxLpi2c3Tx: LPI2C3 Master TX DMA request; LPI2C3 Slave TX DMA request

enumerator kDma2RequestMuxLpi2c3Rx: LPI2C3 Master RX DMA request; LPI2C3 Slave RX DMA request

enumerator kDma2RequestMuxLpspi3Tx: LPSPI3 TX DMA request

enumerator kDma2RequestMuxLpspi3Rx: LPSPI3 RX DMA request

enumerator kDma2RequestMuxLpuart3Tx: LPUART3 DMA TX request

enumerator kDma2RequestMuxLpuart3Rx: LPUART3 DMA RX request and response

enumerator kDma2RequestMuxLpuart5Tx: LPUART5 DMA TX request

enumerator kDma2RequestMuxLpuart5Rx: LPUART5 DMA RX request and response

enumerator kDma2RequestMuxTpm3Ch0Ch2: LPTPM3 DMA Channel 0 request and response; LPTPM3 DMA Channel 2 request and response

enumerator kDma2RequestMuxTpm3Ch1Ch3: LPTPM3 DMA Channel 1 request and response; LPTPM3 DMA Channel 3 request and response

enumerator kDma2RequestMuxTpm3Overflow: LPTPM3 DMA Overflow request and response

enumerator kDma2RequestMuxTpm5Ch0Ch2: LPTPM5 DMA Channel 0 request and response; LPTPM5 DMA Channel 2 request and response

enumerator kDma2RequestMuxTpm5Ch1Ch3: LPTPM5 DMA Channel 1 request and response; LPTPM5 DMA Channel 3 request and response

enumerator kDma2RequestMuxTpm5Overflow: LPTPM5 DMA Overflow request and response

enumerator kDma2RequestMuxFlexio2Ch0: FLEXIO2 Shifter DMA Channel 0 request; FLEXIO2 Timer DMA Channel 0 request

enumerator kDma2RequestMuxFlexio2Ch1: FLEXIO2 Shifter DMA Channel 1 request; FLEXIO2 Timer DMA Channel 1 request

enumerator kDma2RequestMuxFlexio2Ch2: FLEXIO2 Shifter DMA Channel 2 request; FLEXIO2 Timer DMA Channel 2 request

enumerator kDma2RequestMuxFlexio2Ch3: FLEXIO2 Shifter DMA Channel 3 request; FLEXIO2 Timer DMA Channel 3 request

enumerator kDma2RequestMuxFlexio2Ch4: FLEXIO2 Shifter DMA Channel 4 request; FLEXIO2 Timer DMA Channel 4 request

enumerator kDma2RequestMuxFlexio2Ch5: FLEXIO2 Shifter DMA Channel 5 request; FLEXIO2 Timer DMA Channel 5 request

enumerator kDma2RequestMuxFlexio2Ch6: FLEXIO2 Shifter DMA Channel 6 request; FLEXIO2 Timer DMA Channel 6 request

enumerator kDma2RequestMuxFlexio2Ch7: FLEXIO2 Shifter DMA Channel 7 request; FLEXIO2 Timer DMA Channel 7 request

enumerator kDma2RequestMuxXspi1Tx: xspi1 DMA TX request

enumerator kDma2RequestMuxXspi1Rx: xspi1 DMA RX request

enumerator kDma2RequestMuxSai2Tx: SAI2 TX DMA request and response

enumerator kDma2RequestMuxSai2Rx: SAI2 RX DMA request and response

enumerator kDma2RequestMuxSai3Tx: SAI3 TX DMA request and response

enumerator kDma2RequestMuxSai3Rx: SAI3 RX DMA request and response

enumerator kDma2RequestMuxGpio4Ch0: GPIO4 channel 0 DMA request and response

enumerator kDma2RequestMuxGpio4Ch1: GPIO4 channel 1 DMA request and response

enumerator kDma2RequestMuxSai4Tx: SAI4 TX DMA request and response

enumerator kDma2RequestMuxSai4Rx: SAI4 RX DMA request and response

enumerator kDma2RequestMuxLpi2c5Tx: LPI2C5 Master TX DMA request; LPI2C5 Slave TX DMA request

enumerator kDma2RequestMuxLpi2c5Rx: LPI2C5 Master RX DMA request; LPI2C5 Slave RX DMA request

enumerator kDma2RequestMuxLpi2c7Tx: LPI2C7 Master TX DMA request; LPI2C7 Slave TX DMA request

enumerator kDma2RequestMuxLpi2c7Rx: LPI2C7 Master RX DMA request; LPI2C7 Slave RX DMA request

enumerator kDma2RequestMuxLpspi5Tx: LPSPI5 TX DMA request

enumerator kDma2RequestMuxLpspi5Rx: LPSPI5 RX DMA request

enumerator kDma2RequestMuxLpspi7Tx: LPSPI7 TX DMA request

enumerator kDma2RequestMuxLpspi7Rx: LPSPI7 RX DMA request

enumerator kDma2RequestMuxLpuart7Tx: LPUART7 DMA TX request

enumerator kDma2RequestMuxLpuart7Rx: LPUART7 DMA RX request and response

enumerator kDma2RequestMuxV2xfh: V2X_FH DMA request

enumerator kDma2RequestMuxGpio6Ch0: GPIO6 channel 0 DMA request and response

enumerator kDma2RequestMuxGpio6Ch1: GPIO6 channel 1 DMA request and response

enumerator kDma2RequestMuxLpuart9Tx: LPUART9 DMA TX request

enumerator kDma2RequestMuxLpuart9Rx: LPUART9 DMA RX request and response

enumerator kDma2RequestMuxLpuart11Tx: LPUART11 DMA TX request

enumerator kDma2RequestMuxLpuart11Rx: LPUART11 DMA RX request and response

enumerator kDma2RequestMuxSinc2Ch0: SIN2 DMA request Ch0

enumerator kDma2RequestMuxSinc2Ch1: SIN2 DMA request Ch1

enumerator kDma2RequestMuxSinc2Ch2: SIN2 DMA request Ch2

enumerator kDma2RequestMuxSinc2Ch3: SIN2 DMA request Ch3

enumerator kDma2RequestMuxSinc4Ch0: SIN4 DMA request Ch0

enumerator kDma2RequestMuxSinc4Ch1: SIN4 DMA request Ch1

enumerator kDma2RequestMuxSinc4Ch2: SIN4 DMA request Ch2

enumerator kDma2RequestMuxSinc4Ch3: SIN4 DMA request Ch3

enumerator kDma2RequestMuxFlexpwm2CaptureRegsOfSubmodule0: FLEXPWM2 Read DMA request for capture regs of sub-module0

enumerator kDma2RequestMuxFlexpwm2CaptureRegsOfSubmodule1: FLEXPWM2 Read DMA request for capture regs of sub-module1

enumerator kDma2RequestMuxFlexpwm2CaptureRegsOfSubmodule2: FLEXPWM2 Read DMA request for capture regs of sub-module2

enumerator kDma2RequestMuxFlexpwm2CaptureRegsOfSubmodule3: FLEXPWM2 Read DMA request for capture regs of sub-module3

enumerator kDma2RequestMuxFlexpwm2ValueRegsOfSubmodule0: FLEXPWM2 Write DMA request for value regs of sub-module0

enumerator kDma2RequestMuxFlexpwm2ValueRegsOfSubmodule1: FLEXPWM2 Write DMA request for value regs of sub-module1

enumerator kDma2RequestMuxFlexpwm2ValueRegsOfSubmodule2: FLEXPWM2 Write DMA request for value regs of sub-module2

enumerator kDma2RequestMuxFlexpwm2ValueRegsOfSubmodule3: FLEXPWM2 Write DMA request for value regs of sub-module3

enumerator kDma2RequestMuxFlexpwm4CaptureRegsOfSubmodule0: FLEXPWM4 Read DMA request for capture regs of sub-module0

enumerator kDma2RequestMuxFlexpwm4CaptureRegsOfSubmodule1: FLEXPWM4 Read DMA request for capture regs of sub-module1

enumerator kDma2RequestMuxFlexpwm4CaptureRegsOfSubmodule2: FLEXPWM4 Read DMA request for capture regs of sub-module2

enumerator kDma2RequestMuxFlexpwm4CaptureRegsOfSubmodule3: FLEXPWM4 Read DMA request for capture regs of sub-module3

enumerator kDma2RequestMuxFlexpwm4ValueRegsOfSubmodule0: FLEXPWM4 Write DMA request for value regs of sub-module0

enumerator kDma2RequestMuxFlexpwm4ValueRegsOfSubmodule1: FLEXPWM4 Write DMA request for value regs of sub-module1

enumerator kDma2RequestMuxFlexpwm4ValueRegsOfSubmodule2: FLEXPWM4 Write DMA request for value regs of sub-module2

enumerator kDma2RequestMuxFlexpwm4ValueRegsOfSubmodule3: FLEXPWM4 Write DMA request for value regs of sub-module3

enumerator kDma2RequestMuxEnc2: nan

enumerator kDma2RequestMuxEnc4: nan

enumerator kDma2RequestMuxFlexio4Ch0: flexio4 Shifter DMA Channel 0 request; flexio4 Timer DMA Channel 0 request

enumerator kDma2RequestMuxFlexio4Ch1: flexio4 Shifter DMA Channel 1 request; flexio4 Timer DMA Channel 1 request

enumerator kDma2RequestMuxFlexio4Ch2: flexio4 Shifter DMA Channel 2 request; flexio4 Timer DMA Channel 2 request

enumerator kDma2RequestMuxFlexio4Ch3: flexio4 Shifter DMA Channel 3 request; flexio4 Timer DMA Channel 3 request

enumerator kDma2RequestMuxFlexio4Ch4: flexio4 Shifter DMA Channel 4 request; flexio4 Timer DMA Channel 4 request

enumerator kDma2RequestMuxFlexio4Ch5: flexio4 Shifter DMA Channel 5 request; flexio4 Timer DMA Channel 5 request

enumerator kDma2RequestMuxFlexio4Ch6: flexio4 Shifter DMA Channel 6 request; flexio4 Timer DMA Channel 6 request

enumerator kDma2RequestMuxFlexio4Ch7: flexio4 Shifter DMA Channel 7 request; flexio4 Timer DMA Channel 7 request

enumerator kDma2RequestMuxQtimer2CaptInTimer0: QUADTIMER2 DMA read request for capt in timer #0

enumerator kDma2RequestMuxQtimer2CaptInTimer1: QUADTIMER2 DMA read request for capt in timer #1

enumerator kDma2RequestMuxQtimer2CaptInTimer2: QUADTIMER2 DMA read request for capt in timer #2

enumerator kDma2RequestMuxQtimer2CaptInTimer3: QUADTIMER2 DMA read request for capt in timer #3

enumerator kDma2RequestMuxQtimer2Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER2 DMA write request for cmpld1 in timer #0; QUADTIMER2 DMA write request for cmpld2 in timer #1

enumerator kDma2RequestMuxQtimer2Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER2 DMA write request for cmpld1 in timer #1; QUADTIMER2 DMA write request for cmpld2 in timer #0

enumerator kDma2RequestMuxQtimer2Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER2 DMA write request for cmpld1 in timer #2; QUADTIMER2 DMA write request for cmpld2 in timer #3

enumerator kDma2RequestMuxQtimer2Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER2 DMA write request for cmpld1 in timer #3; QUADTIMER2 DMA write request for cmpld2 in timer #2

enumerator kDma2RequestMuxQtimer4CaptInTimer0: QUADTIMER4 DMA read request for capt in timer #0

enumerator kDma2RequestMuxQtimer4CaptInTimer1: QUADTIMER4 DMA read request for capt in timer #1

enumerator kDma2RequestMuxQtimer4CaptInTimer2: QUADTIMER4 DMA read request for capt in timer #2

enumerator kDma2RequestMuxQtimer4CaptInTimer3: QUADTIMER4 DMA read request for capt in timer #3

enumerator kDma2RequestMuxQtimer4Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER4 DMA write request for cmpld1 in timer #0; QUADTIMER4 DMA write request for cmpld2 in timer #1

enumerator kDma2RequestMuxQtimer4Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER4 DMA write request for cmpld1 in timer #1; QUADTIMER4 DMA write request for cmpld2 in timer #0

enumerator kDma2RequestMuxQtimer4Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER4 DMA write request for cmpld1 in timer #2; QUADTIMER4 DMA write request for cmpld2 in timer #3

enumerator kDma2RequestMuxQtimer4Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER4 DMA write request for cmpld1 in timer #3; QUADTIMER4 DMA write request for cmpld2 in timer #2

enumerator kDma2RequestMuxQtimer6CaptInTimer0: QUADTIMER6 DMA read request for capt in timer #0

enumerator kDma2RequestMuxQtimer6CaptInTimer1: QUADTIMER6 DMA read request for capt in timer #1

enumerator kDma2RequestMuxQtimer6CaptInTimer2: QUADTIMER6 DMA read request for capt in timer #2

enumerator kDma2RequestMuxQtimer6CaptInTimer3: QUADTIMER6 DMA read request for capt in timer #3

enumerator kDma2RequestMuxQtimer6Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER6 DMA write request for cmpld1 in timer #0; QUADTIMER6 DMA write request for cmpld2 in timer #1

enumerator kDma2RequestMuxQtimer6Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER6 DMA write request for cmpld1 in timer #1; QUADTIMER6 DMA write request for cmpld2 in timer #0

enumerator kDma2RequestMuxQtimer6Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER6 DMA write request for cmpld1 in timer #2; QUADTIMER6 DMA write request for cmpld2 in timer #3

enumerator kDma2RequestMuxQtimer6Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER6 DMA write request for cmpld1 in timer #3; QUADTIMER6 DMA write request for cmpld2 in timer #2

enumerator kDma2RequestMuxQtimer8CaptInTimer0: QUADTIMER8 DMA read request for capt in timer #0

enumerator kDma2RequestMuxQtimer8CaptInTimer1: QUADTIMER8 DMA read request for capt in timer #1

enumerator kDma2RequestMuxQtimer8CaptInTimer2: QUADTIMER8 DMA read request for capt in timer #2

enumerator kDma2RequestMuxQtimer8CaptInTimer3: QUADTIMER8 DMA read request for capt in timer #3

enumerator kDma2RequestMuxQtimer8Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER8 DMA write request for cmpld1 in timer #0; QUADTIMER8 DMA write request for cmpld2 in timer #1

enumerator kDma2RequestMuxQtimer8Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER8 DMA write request for cmpld1 in timer #1; QUADTIMER8 DMA write request for cmpld2 in timer #0

enumerator kDma2RequestMuxQtimer8Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER8 DMA write request for cmpld1 in timer #2; QUADTIMER8 DMA write request for cmpld2 in timer #3

enumerator kDma2RequestMuxQtimer8Cmpld1InTimer3: QUADTIMER8 DMA write request for cmpld1 in timer #3

enumerator kDma2RequestMuxHiperface2SafePos1: HIPERFACE2 Safe Pos1

enumerator kDma2RequestMuxHiperface2FastPos: HIPERFACE2 Fast Pos

enumerator kDma2RequestMuxHiperface2SafePos2: HIPERFACE2 Safe Pos2

enumerator kDma2RequestMuxReserved1: nan

enum _dma3_request_source

Values:

enumerator kDma3RequestMuxReserved0: Default - Channel Disabled (Do Not Re-assign)

enumerator kDma3RequestMuxCan2: CAN-FD 2 DMA request and response

enumerator kDma3RequestMuxGpio2Ch0: GPIO2 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio2Ch1: GPIO2 channel 1 DMA request and response

enumerator kDma3RequestMuxGpio3Ch0: GPIO3 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio3Ch1: GPIO3 channel 1 DMA request and response

enumerator kDma3RequestMuxI3c2ToBus: I3C2 “To-bus” DMA request and response

enumerator kDma3RequestMuxI3c2FromBus: I3C2 “from-bus” DMA request and response

enumerator kDma3RequestMuxLpi2c3Tx: LPI2C3 Master TX DMA request; LPI2C3 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c3Rx: LPI2C3 Master RX DMA request; LPI2C3 Slave RX DMA request

enumerator kDma3RequestMuxLpi2c4Tx: LPI2C4 Master TX DMA request; LPI2C4 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c4Rx: LPI2C4 Master RX DMA request; LPI2C4 Slave RX DMA request

enumerator kDma3RequestMuxLpspi3Tx: LPSPI3 TX DMA request

enumerator kDma3RequestMuxLpspi3Rx: LPSPI3 RX DMA request

enumerator kDma3RequestMuxLpspi4Tx: LPSPI4 TX DMA request

enumerator kDma3RequestMuxLpspi4Rx: LPSPI4 RX DMA request

enumerator kDma3RequestMuxLptmr2: LPTIMER2 DMA request and response

enumerator kDma3RequestMuxLpuart3Tx: LPUART3 DMA TX request

enumerator kDma3RequestMuxLpuart3Rx: LPUART3 DMA RX request and response

enumerator kDma3RequestMuxLpuart4Tx: LPUART4 DMA TX request

enumerator kDma3RequestMuxLpuart4Rx: LPUART4 DMA RX request and response

enumerator kDma3RequestMuxLpuart5Tx: LPUART5 DMA TX request

enumerator kDma3RequestMuxLpuart5Rx: LPUART5 DMA RX request and response

enumerator kDma3RequestMuxLpuart6Tx: LPUART6 DMA TX request

enumerator kDma3RequestMuxLpuart6Rx: LPUART6 DMA RX request and response

enumerator kDma3RequestMuxTpm3Ch0Ch2: LPTPM3 DMA Channel 0 request and response; LPTPM3 DMA Channel 2 request and response

enumerator kDma3RequestMuxTpm3Ch1Ch3: LPTPM3 DMA Channel 1 request and response; LPTPM3 DMA Channel 3 request and response

enumerator kDma3RequestMuxTpm3Overflow: LPTPM3 DMA Overflow request and response

enumerator kDma3RequestMuxTpm4Ch0Ch2: LPTPM4 DMA Channel 0 request and response; LPTPM4 DMA Channel 2 request and response

enumerator kDma3RequestMuxTpm4Ch1Ch3: LPTPM4 DMA Channel 1 request and response; LPTPM4 DMA Channel 3 request and response

enumerator kDma3RequestMuxTpm4Overflow: LPTPM4 DMA Overflow request and response

enumerator kDma3RequestMuxTpm5Ch0Ch2: LPTPM5 DMA Channel 0 request and response; LPTPM5 DMA Channel 2 request and response

enumerator kDma3RequestMuxTpm5Ch1Ch3: LPTPM5 DMA Channel 1 request and response; LPTPM5 DMA Channel 3 request and response

enumerator kDma3RequestMuxTpm5Overflow: LPTPM5 DMA Overflow request and response

enumerator kDma3RequestMuxTpm6Ch0Ch2: LPTPM6 DMA Channel 0 request and response; LPTPM6 DMA Channel 2 request and response

enumerator kDma3RequestMuxTpm6Ch1Ch3: LPTPM6 DMA Channel 1 request and response; LPTPM6 DMA Channel 3 request and response

enumerator kDma3RequestMuxTpm6Overflow: LPTPM6 DMA Overflow request and response

enumerator kDma3RequestMuxFlexio1Ch0: FLEXIO1 Shifter DMA Channel 0 request; FLEXIO1 Timer DMA Channel 0 request

enumerator kDma3RequestMuxFlexio1Ch1: FLEXIO1 Shifter DMA Channel 1 request; FLEXIO1 Timer DMA Channel 1 request

enumerator kDma3RequestMuxFlexio1Ch2: FLEXIO1 Shifter DMA Channel 2 request; FLEXIO1 Timer DMA Channel 2 request

enumerator kDma3RequestMuxFlexio1Ch3: FLEXIO1 Shifter DMA Channel 3 request; FLEXIO1 Timer DMA Channel 3 request

enumerator kDma3RequestMuxFlexio1Ch4: FLEXIO1 Shifter DMA Channel 4 request; FLEXIO1 Timer DMA Channel 4 request

enumerator kDma3RequestMuxFlexio1Ch5: FLEXIO1 Shifter DMA Channel 5 request; FLEXIO1 Timer DMA Channel 5 request

enumerator kDma3RequestMuxFlexio1Ch6: FLEXIO1 Shifter DMA Channel 6 request; FLEXIO1 Timer DMA Channel 6 request

enumerator kDma3RequestMuxFlexio1Ch7: FLEXIO1 Shifter DMA Channel 7 request; FLEXIO1 Timer DMA Channel 7 request

enumerator kDma3RequestMuxFlexio2Ch0: FLEXIO2 Shifter DMA Channel 0 request; FLEXIO2 Timer DMA Channel 0 request

enumerator kDma3RequestMuxFlexio2Ch1: FLEXIO2 Shifter DMA Channel 1 request; FLEXIO2 Timer DMA Channel 1 request

enumerator kDma3RequestMuxFlexio2Ch2: FLEXIO2 Shifter DMA Channel 2 request; FLEXIO2 Timer DMA Channel 2 request

enumerator kDma3RequestMuxFlexio2Ch3: FLEXIO2 Shifter DMA Channel 3 request; FLEXIO2 Timer DMA Channel 3 request

enumerator kDma3RequestMuxFlexio2Ch4: FLEXIO2 Shifter DMA Channel 4 request; FLEXIO2 Timer DMA Channel 4 request

enumerator kDma3RequestMuxFlexio2Ch5: FLEXIO2 Shifter DMA Channel 5 request; FLEXIO2 Timer DMA Channel 5 request

enumerator kDma3RequestMuxFlexio2Ch6: FLEXIO2 Shifter DMA Channel 6 request; FLEXIO2 Timer DMA Channel 6 request

enumerator kDma3RequestMuxFlexio2Ch7: FLEXIO2 Shifter DMA Channel 7 request; FLEXIO2 Timer DMA Channel 7 request

enumerator kDma3RequestMuxFlexspi1Tx: FLEXSPI1 DMA TX request

enumerator kDma3RequestMuxFlexspi1Rx: FLEXSPI1 DMA RX request

enumerator kDma3RequestMuxGpio5Ch0: GPIO5 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio5Ch1: GPIO5 channel 1 DMA request and response

enumerator kDma3RequestMuxCan3: CAN-FD 3 DMA request and response

enumerator kDma3RequestMuxSai2Tx: SAI2 TX DMA request and response

enumerator kDma3RequestMuxSai2Rx: SAI2 RX DMA request and response

enumerator kDma3RequestMuxSai3Tx: SAI3 TX DMA request and response

enumerator kDma3RequestMuxSai3Rx: SAI3 RX DMA request and response

enumerator kDma3RequestMuxGpio4Ch0: GPIO4 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio4Ch1: GPIO4 channel 1 DMA request and response

enumerator kDma3RequestMuxSai4Tx: SAI4 TX DMA request and response

enumerator kDma3RequestMuxSai4Rx: SAI4 RX DMA request and response

enumerator kDma3RequestMuxLpi2c5Tx: LPI2C5 Master TX DMA request; LPI2C5 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c5Rx: LPI2C5 Master RX DMA request; LPI2C5 Slave RX DMA request

enumerator kDma3RequestMuxLpi2c6Tx: LPI2C6 Master TX DMA request; LPI2C6 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c6Rx: LPI2C6 Master RX DMA request; LPI2C6 Slave RX DMA request

enumerator kDma3RequestMuxLpi2c7Tx: LPI2C7 Master TX DMA request; LPI2C7 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c7Rx: LPI2C7 Master RX DMA request; LPI2C7 Slave RX DMA request

enumerator kDma3RequestMuxLpi2c8Tx: LPI2C8 Master TX DMA request; LPI2C8 Slave TX DMA request

enumerator kDma3RequestMuxLpi2c8Rx: LPI2C8 Master RX DMA request; LPI2C8 Slave RX DMA request

enumerator kDma3RequestMuxLpspi5Tx: LPSPI5 TX DMA request

enumerator kDma3RequestMuxLpspi5Rx: LPSPI5 RX DMA request

enumerator kDma3RequestMuxLpspi6Tx: LPSPI6 TX DMA request

enumerator kDma3RequestMuxLpspi6Rx: LPSPI6 RX DMA request

enumerator kDma3RequestMuxLpspi7Tx: LPSPI7 TX DMA request

enumerator kDma3RequestMuxLpspi7Rx: LPSPI7 RX DMA request

enumerator kDma3RequestMuxLpspi8Tx: LPSPI8 TX DMA request

enumerator kDma3RequestMuxLpspi8Rx: LPSPI8 RX DMA request

enumerator kDma3RequestMuxLpuart7Tx: LPUART7 DMA TX request

enumerator kDma3RequestMuxLpuart7Rx: LPUART7 DMA RX request and response

enumerator kDma3RequestMuxLpuart8Tx: LPUART8 DMA TX request

enumerator kDma3RequestMuxLpuart8Rx: LPUART8 DMA RX request and response

enumerator kDma3RequestMuxCan4: CAN-FD 4 DMA request and response

enumerator kDma3RequestMuxCan5: CAN-FD 5 DMA request and response

enumerator kDma3RequestMuxV2xfh: V2X_FH DMA request

enumerator kDma3RequestMuxFlexspi2Tx: FLEXSPI2 DMA TX request

enumerator kDma3RequestMuxFlexspi2Rx: FLEXSPI2 DMA RX request

enumerator kDma3RequestMuxGpio6Ch0: GPIO6 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio6Ch1: GPIO6 channel 1 DMA request and response

enumerator kDma3RequestMuxGpio7Ch0: GPIO7 channel 0 DMA request and response

enumerator kDma3RequestMuxGpio7Ch1: GPIO7 channel 1 DMA request and response

enumerator kDma3RequestMuxLpuart9Tx: LPUART9 DMA TX request

enumerator kDma3RequestMuxLpuart9Rx: LPUART9 DMA RX request and response

enumerator kDma3RequestMuxLpuart10Tx: LPUART10 DMA TX request

enumerator kDma3RequestMuxLpuart10Rx: LPUART10 DMA RX request and response

enumerator kDma3RequestMuxLpuart11Tx: LPUART11 DMA TX request

enumerator kDma3RequestMuxLpuart11Rx: LPUART11 DMA RX request and response

enumerator kDma3RequestMuxLpuart12Tx: LPUART12 DMA TX request

enumerator kDma3RequestMuxLpuart12Rx: LPUART12 DMA RX request and response

enumerator kDma3RequestMuxFlexio3Ch0: flexio3 Shifter DMA Channel 0 request; flexio3 Timer DMA Channel 0 request

enumerator kDma3RequestMuxFlexio3Ch1: flexio3 Shifter DMA Channel 1 request; flexio3 Timer DMA Channel 1 request

enumerator kDma3RequestMuxFlexio3Ch2: flexio3 Shifter DMA Channel 2 request; flexio3 Timer DMA Channel 2 request

enumerator kDma3RequestMuxFlexio3Ch3: flexio3 Shifter DMA Channel 3 request; flexio3 Timer DMA Channel 3 request

enumerator kDma3RequestMuxFlexio3Ch4: flexio3 Shifter DMA Channel 4 request; flexio3 Timer DMA Channel 4 request

enumerator kDma3RequestMuxFlexio3Ch5: flexio3 Shifter DMA Channel 5 request; flexio3 Timer DMA Channel 5 request

enumerator kDma3RequestMuxFlexio3Ch6: flexio3 Shifter DMA Channel 6 request; flexio3 Timer DMA Channel 6 request

enumerator kDma3RequestMuxFlexio3Ch7: flexio3 Shifter DMA Channel 7 request; flexio3 Timer DMA Channel 7 request

enumerator kDma3RequestMuxFlexio4Ch0: flexio4 Shifter DMA Channel 0 request; flexio4 Timer DMA Channel 0 request

enumerator kDma3RequestMuxFlexio4Ch1: flexio4 Shifter DMA Channel 1 request; flexio4 Timer DMA Channel 1 request

enumerator kDma3RequestMuxFlexio4Ch2: flexio4 Shifter DMA Channel 2 request; flexio4 Timer DMA Channel 2 request

enumerator kDma3RequestMuxFlexio4Ch3: flexio4 Shifter DMA Channel 3 request; flexio4 Timer DMA Channel 3 request

enumerator kDma3RequestMuxFlexio4Ch4: flexio4 Shifter DMA Channel 4 request; flexio4 Timer DMA Channel 4 request

enumerator kDma3RequestMuxFlexio4Ch5: flexio4 Shifter DMA Channel 5 request; flexio4 Timer DMA Channel 5 request

enumerator kDma3RequestMuxFlexio4Ch6: flexio4 Shifter DMA Channel 6 request; flexio4 Timer DMA Channel 6 request

enumerator kDma3RequestMuxFlexio4Ch7: flexio4 Shifter DMA Channel 7 request; flexio4 Timer DMA Channel 7 request

enumerator kDma3RequestMuxQtimer1CaptInTimer0: QUADTIMER1 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer1CaptInTimer1: QUADTIMER1 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer1CaptInTimer2: QUADTIMER1 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer1CaptInTimer3: QUADTIMER1 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer1Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER1 DMA write request for cmpld1 in timer #0; QUADTIMER1 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer1Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER1 DMA write request for cmpld1 in timer #1; QUADTIMER1 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer1Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER1 DMA write request for cmpld1 in timer #2; QUADTIMER1 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer1Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER1 DMA write request for cmpld1 in timer #3; QUADTIMER1 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer2CaptInTimer0: QUADTIMER2 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer2CaptInTimer1: QUADTIMER2 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer2CaptInTimer2: QUADTIMER2 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer2CaptInTimer3: QUADTIMER2 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer2Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER2 DMA write request for cmpld1 in timer #0; QUADTIMER2 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer2Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER2 DMA write request for cmpld1 in timer #1; QUADTIMER2 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer2Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER2 DMA write request for cmpld1 in timer #2; QUADTIMER2 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer2Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER2 DMA write request for cmpld1 in timer #3; QUADTIMER2 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer3CaptInTimer0: QUADTIMER3 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer3CaptInTimer1: QUADTIMER3 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer3CaptInTimer2: QUADTIMER3 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer3CaptInTimer3: QUADTIMER3 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer3Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER3 DMA write request for cmpld1 in timer #0; QUADTIMER3 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer3Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER3 DMA write request for cmpld1 in timer #1; QUADTIMER3 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer3Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER3 DMA write request for cmpld1 in timer #2; QUADTIMER3 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer3Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER3 DMA write request for cmpld1 in timer #3; QUADTIMER3 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer4CaptInTimer0: QUADTIMER4 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer4CaptInTimer1: QUADTIMER4 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer4CaptInTimer2: QUADTIMER4 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer4CaptInTimer3: QUADTIMER4 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer4Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER4 DMA write request for cmpld1 in timer #0; QUADTIMER4 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer4Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER4 DMA write request for cmpld1 in timer #1; QUADTIMER4 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer4Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER4 DMA write request for cmpld1 in timer #2; QUADTIMER4 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer4Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER4 DMA write request for cmpld1 in timer #3; QUADTIMER4 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer5CaptInTimer0: QUADTIMER5 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer5CaptInTimer1: QUADTIMER5 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer5CaptInTimer2: QUADTIMER5 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer5CaptInTimer3: QUADTIMER5 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer5Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER5 DMA write request for cmpld1 in timer #0; QUADTIMER5 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer5Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER5 DMA write request for cmpld1 in timer #1; QUADTIMER5 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer5Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER5 DMA write request for cmpld1 in timer #2; QUADTIMER5 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer5Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER5 DMA write request for cmpld1 in timer #3; QUADTIMER5 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer6CaptInTimer0: QUADTIMER6 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer6CaptInTimer1: QUADTIMER6 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer6CaptInTimer2: QUADTIMER6 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer6CaptInTimer3: QUADTIMER6 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer6Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER6 DMA write request for cmpld1 in timer #0; QUADTIMER6 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer6Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER6 DMA write request for cmpld1 in timer #1; QUADTIMER6 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer6Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER6 DMA write request for cmpld1 in timer #2; QUADTIMER6 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer6Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER6 DMA write request for cmpld1 in timer #3; QUADTIMER6 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer7CaptInTimer0: QUADTIMER7 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer7CaptInTimer1: QUADTIMER7 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer7CaptInTimer2: QUADTIMER7 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer7CaptInTimer3: QUADTIMER7 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer7Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER7 DMA write request for cmpld1 in timer #0; QUADTIMER7 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer7Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER7 DMA write request for cmpld1 in timer #1; QUADTIMER7 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer7Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER7 DMA write request for cmpld1 in timer #2; QUADTIMER7 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer7Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER7 DMA write request for cmpld1 in timer #3; QUADTIMER7 DMA write request for cmpld2 in timer #2

enumerator kDma3RequestMuxQtimer8CaptInTimer0: QUADTIMER8 DMA read request for capt in timer #0

enumerator kDma3RequestMuxQtimer8CaptInTimer1: QUADTIMER8 DMA read request for capt in timer #1

enumerator kDma3RequestMuxQtimer8CaptInTimer2: QUADTIMER8 DMA read request for capt in timer #2

enumerator kDma3RequestMuxQtimer8CaptInTimer3: QUADTIMER8 DMA read request for capt in timer #3

enumerator kDma3RequestMuxQtimer8Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER8 DMA write request for cmpld1 in timer #0; QUADTIMER8 DMA write request for cmpld2 in timer #1

enumerator kDma3RequestMuxQtimer8Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER8 DMA write request for cmpld1 in timer #1; QUADTIMER8 DMA write request for cmpld2 in timer #0

enumerator kDma3RequestMuxQtimer8Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER8 DMA write request for cmpld1 in timer #2; QUADTIMER8 DMA write request for cmpld2 in timer #3

enumerator kDma3RequestMuxQtimer8Cmpld1InTimer3: QUADTIMER8 DMA write request for cmpld1 in timer #3

enumerator kDma3RequestMuxReserved1: nan

enum _dma4_request_source

Values:

enumerator kDma4RequestMuxReserved0: Default - Channel Disabled (Do Not Re-assign)

enumerator kDma4RequestMuxCan2: CAN-FD 2 DMA request and response

enumerator kDma4RequestMuxGpio3Ch0: GPIO3 channel 0 DMA request and response

enumerator kDma4RequestMuxGpio3Ch1: GPIO3 channel 1 DMA request and response

enumerator kDma4RequestMuxLpi2c4Tx: LPI2C4 Master TX DMA request; LPI2C4 Slave TX DMA request

enumerator kDma4RequestMuxLpi2c4Rx: LPI2C4 Master RX DMA request; LPI2C4 Slave RX DMA request

enumerator kDma4RequestMuxLpspi4Tx: LPSPI4 TX DMA request

enumerator kDma4RequestMuxLpspi4Rx: LPSPI4 RX DMA request

enumerator kDma4RequestMuxLptmr2: LPTIMER2 DMA request and response

enumerator kDma4RequestMuxLpuart4Tx: LPUART4 DMA TX request

enumerator kDma4RequestMuxLpuart4Rx: LPUART4 DMA RX request and response

enumerator kDma4RequestMuxLpuart6Tx: LPUART6 DMA TX request

enumerator kDma4RequestMuxLpuart6Rx: LPUART6 DMA RX request and response

enumerator kDma4RequestMuxTpm4Ch0Ch2: LPTPM4 DMA Channel 0 request and response; LPTPM4 DMA Channel 2 request and response

enumerator kDma4RequestMuxTpm4Ch1Ch3: LPTPM4 DMA Channel 1 request and response; LPTPM4 DMA Channel 3 request and response

enumerator kDma4RequestMuxTpm4Overflow: LPTPM4 DMA Overflow request and response

enumerator kDma4RequestMuxTpm6Ch0Ch2: LPTPM6 DMA Channel 0 request and response; LPTPM6 DMA Channel 2 request and response

enumerator kDma4RequestMuxTpm6Ch1Ch3: LPTPM6 DMA Channel 1 request and response; LPTPM6 DMA Channel 3 request and response

enumerator kDma4RequestMuxTpm6Overflow: LPTPM6 DMA Overflow request and response

enumerator kDma4RequestMuxFlexio1Ch0: FLEXIO1 Shifter DMA Channel 0 request; FLEXIO1 Timer DMA Channel 0 request

enumerator kDma4RequestMuxFlexio1Ch1: FLEXIO1 Shifter DMA Channel 1 request; FLEXIO1 Timer DMA Channel 1 request

enumerator kDma4RequestMuxFlexio1Ch2: FLEXIO1 Shifter DMA Channel 2 request; FLEXIO1 Timer DMA Channel 2 request

enumerator kDma4RequestMuxFlexio1Ch3: FLEXIO1 Shifter DMA Channel 3 request; FLEXIO1 Timer DMA Channel 3 request

enumerator kDma4RequestMuxFlexio1Ch4: FLEXIO1 Shifter DMA Channel 4 request; FLEXIO1 Timer DMA Channel 4 request

enumerator kDma4RequestMuxFlexio1Ch5: FLEXIO1 Shifter DMA Channel 5 request; FLEXIO1 Timer DMA Channel 5 request

enumerator kDma4RequestMuxFlexio1Ch6: FLEXIO1 Shifter DMA Channel 6 request; FLEXIO1 Timer DMA Channel 6 request

enumerator kDma4RequestMuxFlexio1Ch7: FLEXIO1 Shifter DMA Channel 7 request; FLEXIO1 Timer DMA Channel 7 request

enumerator kDma4RequestMuxGpio5Ch0: GPIO5 channel 0 DMA request and response

enumerator kDma4RequestMuxGpio5Ch1: GPIO5 channel 1 DMA request and response

enumerator kDma4RequestMuxCan3: CAN-FD 3 DMA request and response

enumerator kDma4RequestMuxLpi2c6Tx: LPI2C6 Master TX DMA request; LPI2C6 Slave TX DMA request

enumerator kDma4RequestMuxLpi2c6Rx: LPI2C6 Master RX DMA request; LPI2C6 Slave RX DMA request

enumerator kDma4RequestMuxLpi2c8Tx: LPI2C8 Master TX DMA request; LPI2C8 Slave TX DMA request

enumerator kDma4RequestMuxLpi2c8Rx: LPI2C8 Master RX DMA request; LPI2C8 Slave RX DMA request

enumerator kDma4RequestMuxLpspi6Tx: LPSPI6 TX DMA request

enumerator kDma4RequestMuxLpspi6Rx: LPSPI6 RX DMA request

enumerator kDma4RequestMuxLpspi8Tx: LPSPI8 TX DMA request

enumerator kDma4RequestMuxLpspi8Rx: LPSPI8 RX DMA request

enumerator kDma4RequestMuxLpuart8Tx: LPUART8 DMA TX request

enumerator kDma4RequestMuxLpuart8Rx: LPUART8 DMA RX request and response

enumerator kDma4RequestMuxCan4: CAN-FD 4 DMA request and response

enumerator kDma4RequestMuxCan5: CAN-FD 5 DMA request and response

enumerator kDma4RequestMuxXspi2Tx: xspi2 DMA TX request

enumerator kDma4RequestMuxXspi2Rx: xspi2 DMA RX request

enumerator kDma4RequestMuxGpio7Ch0: GPIO7 channel 0 DMA request and response

enumerator kDma4RequestMuxGpio7Ch1: GPIO7 channel 1 DMA request and response

enumerator kDma4RequestMuxLpuart10Tx: LPUART10 DMA TX request

enumerator kDma4RequestMuxLpuart10Rx: LPUART10 DMA RX request and response

enumerator kDma4RequestMuxLpuart12Tx: LPUART12 DMA TX request

enumerator kDma4RequestMuxLpuart12Rx: LPUART12 DMA RX request and response

enumerator kDma4RequestMuxSinc1Ch0: nan

enumerator kDma4RequestMuxSinc1Ch1: nan

enumerator kDma4RequestMuxSinc1Ch2: nan

enumerator kDma4RequestMuxSinc1Ch3: nan

enumerator kDma4RequestMuxSinc3Ch0: nan

enumerator kDma4RequestMuxSinc3Ch1: nan

enumerator kDma4RequestMuxSinc3Ch2: nan

enumerator kDma4RequestMuxSinc3Ch3: nan

enumerator kDma4RequestMuxFlexpwm1CaptureRegsOfSubmodule0: FLEXPWM1 Read DMA request for capture regs of sub-module0

enumerator kDma4RequestMuxFlexpwm1CaptureRegsOfSubmodule1: FLEXPWM1 Read DMA request for capture regs of sub-module1

enumerator kDma4RequestMuxFlexpwm1CaptureRegsOfSubmodule2: FLEXPWM1 Read DMA request for capture regs of sub-module2

enumerator kDma4RequestMuxFlexpwm1CaptureRegsOfSubmodule3: FLEXPWM1 Read DMA request for capture regs of sub-module3

enumerator kDma4RequestMuxFlexpwm1ValueRegsOfSubmodule0: FLEXPWM1 Write DMA request for value regs of sub-module0

enumerator kDma4RequestMuxFlexpwm1ValueRegsOfSubmodule1: FLEXPWM1 Write DMA request for value regs of sub-module1

enumerator kDma4RequestMuxFlexpwm1ValueRegsOfSubmodule2: FLEXPWM1 Write DMA request for value regs of sub-module2

enumerator kDma4RequestMuxFlexpwm1ValueRegsOfSubmodule3: FLEXPWM1 Write DMA request for value regs of sub-module3

enumerator kDma4RequestMuxFlexpwm3CaptureRegsOfSubmodule0: FLEXPWM3 Read DMA request for capture regs of sub-module0

enumerator kDma4RequestMuxFlexpwm3CaptureRegsOfSubmodule1: FLEXPWM3 Read DMA request for capture regs of sub-module1

enumerator kDma4RequestMuxFlexpwm3CaptureRegsOfSubmodule2: FLEXPWM3 Read DMA request for capture regs of sub-module2

enumerator kDma4RequestMuxFlexpwm3CaptureRegsOfSubmodule3: FLEXPWM3 Read DMA request for capture regs of sub-module3

enumerator kDma4RequestMuxFlexpwm3ValueRegsOfSubmodule0: FLEXPWM3 Write DMA request for value regs of sub-module0

enumerator kDma4RequestMuxFlexpwm3ValueRegsOfSubmodule1: FLEXPWM3 Write DMA request for value regs of sub-module1

enumerator kDma4RequestMuxFlexpwm3ValueRegsOfSubmodule2: FLEXPWM3 Write DMA request for value regs of sub-module2

enumerator kDma4RequestMuxFlexpwm3ValueRegsOfSubmodule3: FLEXPWM3 Write DMA request for value regs of sub-module3

enumerator kDma4RequestMuxEnc1: nan

enumerator kDma4RequestMuxEnc3: nan

enumerator kDma4RequestMuxXbar1Ch0: XBAR DMA request 0

enumerator kDma4RequestMuxXbar1Ch1: XBAR DMA request 1

enumerator kDma4RequestMuxXbar1Ch2: XBAR DMA request 2

enumerator kDma4RequestMuxXbar1Ch3: XBAR DMA request 3

enumerator kDma4RequestMuxFlexio3Ch0: flexio3 Shifter DMA Channel 0 request; flexio3 Timer DMA Channel 0 request

enumerator kDma4RequestMuxFlexio3Ch1: flexio3 Shifter DMA Channel 1 request; flexio3 Timer DMA Channel 1 request

enumerator kDma4RequestMuxFlexio3Ch2: flexio3 Shifter DMA Channel 2 request; flexio3 Timer DMA Channel 2 request

enumerator kDma4RequestMuxFlexio3Ch3: flexio3 Shifter DMA Channel 3 request; flexio3 Timer DMA Channel 3 request

enumerator kDma4RequestMuxFlexio3Ch4: flexio3 Shifter DMA Channel 4 request; flexio3 Timer DMA Channel 4 request

enumerator kDma4RequestMuxFlexio3Ch5: flexio3 Shifter DMA Channel 5 request; flexio3 Timer DMA Channel 5 request

enumerator kDma4RequestMuxFlexio3Ch6: flexio3 Shifter DMA Channel 6 request; flexio3 Timer DMA Channel 6 request

enumerator kDma4RequestMuxFlexio3Ch7: flexio3 Shifter DMA Channel 7 request; flexio3 Timer DMA Channel 7 request

enumerator kDma4RequestMuxQtimer1CaptInTimer0: QUADTIMER1 DMA read request for capt in timer #0

enumerator kDma4RequestMuxQtimer1CaptInTimer1: QUADTIMER1 DMA read request for capt in timer #1

enumerator kDma4RequestMuxQtimer1CaptInTimer2: QUADTIMER1 DMA read request for capt in timer #2

enumerator kDma4RequestMuxQtimer1CaptInTimer3: QUADTIMER1 DMA read request for capt in timer #3

enumerator kDma4RequestMuxQtimer1Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER1 DMA write request for cmpld1 in timer #0; QUADTIMER1 DMA write request for cmpld2 in timer #1

enumerator kDma4RequestMuxQtimer1Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER1 DMA write request for cmpld1 in timer #1; QUADTIMER1 DMA write request for cmpld2 in timer #0

enumerator kDma4RequestMuxQtimer1Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER1 DMA write request for cmpld1 in timer #2; QUADTIMER1 DMA write request for cmpld2 in timer #3

enumerator kDma4RequestMuxQtimer1Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER1 DMA write request for cmpld1 in timer #3; QUADTIMER1 DMA write request for cmpld2 in timer #2

enumerator kDma4RequestMuxQtimer3CaptInTimer0: QUADTIMER3 DMA read request for capt in timer #0

enumerator kDma4RequestMuxQtimer3CaptInTimer1: QUADTIMER3 DMA read request for capt in timer #1

enumerator kDma4RequestMuxQtimer3CaptInTimer2: QUADTIMER3 DMA read request for capt in timer #2

enumerator kDma4RequestMuxQtimer3CaptInTimer3: QUADTIMER3 DMA read request for capt in timer #3

enumerator kDma4RequestMuxQtimer3Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER3 DMA write request for cmpld1 in timer #0; QUADTIMER3 DMA write request for cmpld2 in timer #1

enumerator kDma4RequestMuxQtimer3Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER3 DMA write request for cmpld1 in timer #1; QUADTIMER3 DMA write request for cmpld2 in timer #0

enumerator kDma4RequestMuxQtimer3Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER3 DMA write request for cmpld1 in timer #2; QUADTIMER3 DMA write request for cmpld2 in timer #3

enumerator kDma4RequestMuxQtimer3Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER3 DMA write request for cmpld1 in timer #3; QUADTIMER3 DMA write request for cmpld2 in timer #2

enumerator kDma4RequestMuxQtimer5CaptInTimer0: QUADTIMER5 DMA read request for capt in timer #0

enumerator kDma4RequestMuxQtimer5CaptInTimer1: QUADTIMER5 DMA read request for capt in timer #1

enumerator kDma4RequestMuxQtimer5CaptInTimer2: QUADTIMER5 DMA read request for capt in timer #2

enumerator kDma4RequestMuxQtimer5CaptInTimer3: QUADTIMER5 DMA read request for capt in timer #3

enumerator kDma4RequestMuxQtimer5Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER5 DMA write request for cmpld1 in timer #0; QUADTIMER5 DMA write request for cmpld2 in timer #1

enumerator kDma4RequestMuxQtimer5Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER5 DMA write request for cmpld1 in timer #1; QUADTIMER5 DMA write request for cmpld2 in timer #0

enumerator kDma4RequestMuxQtimer5Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER5 DMA write request for cmpld1 in timer #2; QUADTIMER5 DMA write request for cmpld2 in timer #3

enumerator kDma4RequestMuxQtimer5Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER5 DMA write request for cmpld1 in timer #3; QUADTIMER5 DMA write request for cmpld2 in timer #2

enumerator kDma4RequestMuxQtimer7CaptInTimer0: QUADTIMER7 DMA read request for capt in timer #0

enumerator kDma4RequestMuxQtimer7CaptInTimer1: QUADTIMER7 DMA read request for capt in timer #1

enumerator kDma4RequestMuxQtimer7CaptInTimer2: QUADTIMER7 DMA read request for capt in timer #2

enumerator kDma4RequestMuxQtimer7CaptInTimer3: QUADTIMER7 DMA read request for capt in timer #3

enumerator kDma4RequestMuxQtimer7Cmpld1InTimer0Cmpld2InTimer1: QUADTIMER7 DMA write request for cmpld1 in timer #0; QUADTIMER7 DMA write request for cmpld2 in timer #1

enumerator kDma4RequestMuxQtimer7Cmpld1InTimer1Cmpld2InTimer0: QUADTIMER7 DMA write request for cmpld1 in timer #1; QUADTIMER7 DMA write request for cmpld2 in timer #0

enumerator kDma4RequestMuxQtimer7Cmpld1InTimer2Cmpld2InTimer3: QUADTIMER7 DMA write request for cmpld1 in timer #2; QUADTIMER7 DMA write request for cmpld2 in timer #3

enumerator kDma4RequestMuxQtimer7Cmpld1InTimer3Cmpld2InTimer2: QUADTIMER7 DMA write request for cmpld1 in timer #3; QUADTIMER7 DMA write request for cmpld2 in timer #2

enumerator kDma4RequestMuxHiperface1SafePos1: HIPERFACE1 Safe Pos1

enumerator kDma4RequestMuxHiperface1FastPos: HIPERFACE1 Fast Pos

enumerator kDma4RequestMuxHiperface1SafePos2: HIPERFACE1 Safe Pos2

enumerator kDma4RequestMuxReserved1: nan

typedef enum _dma1_request_source dma1_request_source_t

typedef enum _dma2_request_source dma2_request_source_t

typedef enum _dma3_request_source dma3_request_source_t

typedef enum _dma4_request_source dma4_request_source_t: Verify dma base and request source

FSL_EDMA_SOC_DRIVER_VERSION: Driver version 2.0.0.

FSL_EDMA_SOC_IP_DMA3: DMA IP version.

FSL_EDMA_SOC_IP_DMA5

EDMA_BASE_PTRS

DMA base table.

DMA3 is ip version, the instance index is 1, so it can be EDMA1_CH1(EDMA1), EDMA5 is ip version, the instance index is 2

EDMA_CHN_IRQS

EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source)

EDMA_CHANNEL_OFFSET: EDMA base address convert macro.

EDMA_CHANNEL_ARRAY_STEP(base)

EnDat2.2: EnDat2.2 Interface#

FSL_ENDAT2P2_DRIVER_VERSION: Version 1.0.1

ENDAT2P2_CLK_100M

ENDAT2P2_CLK_64M

ENDAT2P2_CLK_50M

ENDAT2P2_CLK_48M

ENDAT2P2_CLK_32M

ENDAT2P2_CLK_16M

ENDAT2P2_CLK_8M

ENDAT2P2_CLK_4M

ENDAT2P2_CLK_2M

ENDAT2P2_CLK_1M

ENDAT2P2_CLK_200K

ENDAT2P2_CLK_100K

enum _ENDAT2P2P2_mode_cmd

EnDat2.2 mode command.

Values:

enumerator ENDAT2P2_CMD_SEND_POSITION_VALUE

enumerator ENDAT2P2_CMD_SELECT_MEM_AREA

enumerator ENDAT2P2_CMD_RECEIVE_PARAMETERS

enumerator ENDAT2P2_CMD_SEND_PARAMETERS

enumerator ENDAT2P2_CMD_RECEIVE_RESET

enumerator ENDAT2P2_CMD_SEND_TEST_VALUES

enumerator ENDAT2P2_CMD_RECEIVE_TEST_COMMAND

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO_SEL_MEM

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO_RECV_PARAM

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO_SEND_PARAM

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO_RECV_ERR_RST

enumerator ENDAT2P2_CMD_SEND_POSVAL_WITH_ADDINFO_RECV_TESTCMD

enumerator ENDAT2P2_CMD_RECEIVE_COMMUNICATION_CMD

enum _mrs_mode

EnDat2.2 MRS code.

Values:

enumerator MRS_CODE_OPERATING_STATUS

enumerator MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE0

enumerator MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE1

enumerator MRS_CODE_PARAM_ENCODER_MANUFACTURER_PAGE2

enumerator MRS_CODE_PARAM_OPERATING_PARAMS

enumerator MRS_CODE_PARAM_OEM_PAGE0

enumerator MRS_CODE_PARAM_OEM_PAGE1

enumerator MRS_CODE_PARAM_OEM_PAGE2

enumerator MRS_CODE_PARAM_OEM_PAGE3

enumerator MRS_CODE_COMPENSATION_ENCODER_MANUFACTURER_1

enumerator MRS_CODE_COMPENSATION_ENCODER_MANUFACTURER_2

enumerator MRS_CODE_COMPENSATION_ENCODER_MANUFACTURER_3

enumerator MRS_CODE_COMPENSATION_ENCODER_MANUFACTURER_4

enumerator MRS_CODE_PARAM_ENCODER_MFG_ENDAT2P2_2

enumerator MRS_CODE_PARAM_SECTION2_MEMORY_AREA

enumerator MRS_CODE_OPERATING_PARAMETERS

enumerator MRS_CODE_ADDITIONAL_INFO1_WITHOUT_DATA

enumerator MRS_CODE_ADDITIONAL_INFO1_DIAGNOSTIC

enumerator MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD1_LSB

enumerator MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD2

enumerator MRS_CODE_ADDITIONAL_INFO1_POSVAL2_WORD3_MSB

enumerator MRS_CODE_ADDITIONAL_INFO1_ACK_MEM_LSB

enumerator MRS_CODE_ADDITIONAL_INFO1_ACK_MEM_MSB

enumerator MRS_CODE_ADDITIONAL_INFO1_ACK_MRS_CODE

enumerator MRS_CODE_ADDITIONAL_INFO1_ACK_TEST_CMD

enumerator MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD1_LSB

enumerator MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD2

enumerator MRS_CODE_ADDITIONAL_INFO1_TESTVAL_WORD3_MSB

enumerator MRS_CODE_ADDITIONAL_INFO1_TEMPERATURE1

enumerator MRS_CODE_ADDITIONAL_INFO1_TEMPERATURE2

enumerator MRS_CODE_ADDITIONAL_INFO1_ADTL_SENSORS

enumerator MRS_CODE_ADDITIONAL_INFO1_STOP_DATA

enumerator MRS_CODE_ADDITIONAL_INFO2_WITHOUT_DATA

enumerator MRS_CODE_ADDITIONAL_INFO2_COMMUNICATION

enumerator MRS_CODE_ADDITIONAL_INFO2_ACCELERATION

enumerator MRS_CODE_ADDITIONAL_INFO2_COMM_AND_ACCLN

enumerator MRS_CODE_ADDITIONAL_INFO2_LIMIT_POS_SIGNAL

enumerator MRS_CODE_ADDITIONAL_INFO2_LPS_AND_ACCLN

enumerator MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD1_LSB

enumerator MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD2

enumerator MRS_CODE_ADDITIONAL_INFO2_ASYNCPOSVAL2_WORD3_MSB

enumerator MRS_CODE_ADDITIONAL_INFO2_OPSTATUS_ERRSOURCE

enumerator MRS_CODE_ADDITIONAL_INFO2_TIMESTAMP

enumerator MRS_CODE_ADDITIONAL_INFO2_STOP_DATA

enum _endat2p2_mem_word_addr

EnDat2.2 memory address.

Values:

enumerator ENDAT2P2_MEM_WORD_0

enumerator ENDAT2P2_MEM_WORD_1

enumerator ENDAT2P2_MEM_WORD_2

enumerator ENDAT2P2_MEM_WORD_3

enumerator ENDAT2P2_MEM_WORD_4

enumerator ENDAT2P2_MEM_WORD_5

enumerator ENDAT2P2_MEM_WORD_6

enumerator ENDAT2P2_MEM_WORD_7

enumerator ENDAT2P2_MEM_WORD_8

enumerator ENDAT2P2_MEM_WORD_9

enumerator ENDAT2P2_MEM_WORD_10

enumerator ENDAT2P2_MEM_WORD_11

enumerator ENDAT2P2_MEM_WORD_12

enumerator ENDAT2P2_MEM_WORD_13

enumerator ENDAT2P2_MEM_WORD_14

enumerator ENDAT2P2_MEM_WORD_15

enumerator ENDAT2P2_MEM_WORD_16

enumerator ENDAT2P2_MEM_WORD_17

enumerator ENDAT2P2_MEM_WORD_18

enumerator ENDAT2P2_MEM_WORD_19

enum _encoder_type

EnDat2.2 encoder type.

Values:

enumerator ENDAT2P2_ENCODER_TYPE_INCR_LINEAR_WITHOUT_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_LINEAR_WITH_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_LINEAR_WITH_BAT_WITHOUT_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_LINEAR_WITH_BAT_WITH_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_ABSO_LINEAR

enumerator ENDAT2P2_ENCODER_TYPE_ABSO_LINEAR_WITH_CYCLIC

enumerator ENDAT2P2_ENCODER_TYPE_NOTE_TOUCH_D

enumerator ENDAT2P2_ENCODER_TYPE_NOTE_D

enumerator ENDAT2P2_ENCODER_TYPE_INCR_ROTARY_WITHOUT_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_ROTARY_WITH_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_ROTARY_WITH_BAT_WITHOUT_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_INCR_ROTARY_WITH_BAT_WITH_DCRM

enumerator ENDAT2P2_ENCODER_TYPE_ABSO_ROTARY_SINGLETURN

enumerator ENDAT2P2_ENCODER_TYPE_ABSO_ROTARY_MULTITURN_WITH_BAT

enumerator ENDAT2P2_ENCODER_TYPE_ABSO_ROTARY_MULTITURN_WITH_GEARS

enumerator ENDAT2P2_ENCODER_TYPE_EIB

typedef enum _ENDAT2P2P2_mode_cmd endat2p2_mode_cmd_t: EnDat2.2 mode command.

typedef enum _mrs_mode mrs_mode_t: EnDat2.2 MRS code.

typedef enum _endat2p2_mem_word_addr endatp2p_mem_word_addr_t: EnDat2.2 memory address.

typedef enum _encoder_type encode_type_t: EnDat2.2 encoder type.

typedef struct _endat2p2_dev endat2p2_dev_t: EnDat2.2 device.

typedef struct _endat2p2_data endat2p2_data_t: EnDat2.2 received data - position, additional information 1 & 2.

typedef struct _endat2p2_position endat2p2_position_t: EnDat2.2 position value.

typedef struct endat2p2_position_addinfo endat2p2_position_addinfo_t: EnDat2.2 position and additional information.

typedef struct _endat2p2_addr_param endat2p2_addr_param_t: EnDat2.2 memory addr and parameter.

typedef struct _endat2p2_recv_data endat2p2_recv_data_t: EnDat2.2 encoder received data.

ENDAT2P2_Type *base

uint32_t fsys

uint32_t ftclk

uint32_t master_id

uint32_t pos_res

uint32_t id_ascii

uint32_t id_binary

uint32_t sn_binary

uint32_t sn_ascii_msb

uint32_t sn_ascii_lsb

uint32_t cmd_set_2_2

uint32_t has_safety

uint32_t single_turn_res

uint32_t multi_turn_res

int step

int type

int rx_en_cnt

int status_addinfo2

int status_addinfo1

uint64_t recvd1

uint32_t recvd2

uint32_t recvd3

uint64_t position

uint64_t revolution

uint64_t position

uint64_t revolution

uint32_t addinfo1

uint32_t addinfo2

uint8_t address

uint16_t param

endat2p2_position_t position

endat2p2_position_addinfo_t position_addinfo

endat2p2_addr_param_t addr_param

union _endat2p2_recv_data

uint32_t status

char *ENDAT2P2_GetTypeStr(encode_type_t encode_t)

Convert sensor type to descriptor string.

Parameters:

encode_t – Encoder type.

Returns:

The encoder descriptor.

endat2p2_dev_t *ENDAT2P2_GetDev(ENDAT2P2_Type *base)

Get EnDat2.2 device handle pointer.

Parameters:

base – EnDat2.2 peripheral address.

Returns:

EnDat2.2 device handle pointer.

endat2p2_dev_t *ENDAT2P2_InitMaster(ENDAT2P2_Type *base, uint32_t fsys)

Initialize the EnDat2.2 device. This function configures the EnDat2.2 module with the input parameters. User should call this function before any EnDat2.2 operations.

Parameters:

base – EnDat2.2 peripheral base address.
fsys – EnDat2.2 sys clock frequency.

Returns:

The EnDat2.2 device handle pointer.

bool ENDAT2P2_EncoderIsRotary(endat2p2_dev_t *dev)

Check if encoder is rotary.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

true - is rotary.

bool ENDAT2P2_CheckRecv(endat2p2_dev_t *dev)

Check if the receive register is updated by new data.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

true - receive new data.

Returns:

false - not receive new data.

uint32_t ENDAT2P2_GetConfR1(endat2p2_dev_t *dev)

Get configuration register 1.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of configration register 1.

uint32_t ENDAT2P2_GetStatus(endat2p2_dev_t *dev)

Get the status register.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the vaule of status register.

void ENDAT2P2_CleanStatus(endat2p2_dev_t *dev)

Clear the status register.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_SetInterruptMask(endat2p2_dev_t *dev, uint32_t mask)

Set the interupt mask register.

Parameters:

dev – EnDat2.2 device handle pointer.
mask – The mask value of interrupt mask.

uint64_t ENDAT2P2_GetRecvReg1(endat2p2_dev_t *dev)

Get the receive register 1.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of receive register 1.

uint32_t ENDAT2P2_GetRecvReg2(endat2p2_dev_t *dev)

Get the receive register 2.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of receive register 2.

uint32_t ENDAT2P2_GetRecvReg3(endat2p2_dev_t *dev)

Get the receive register 3.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of receive register 3.

uint32_t ENDAT2P2_GetAddInfo1(endat2p2_dev_t *dev)

Get the additional information 1.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of additional information 1.

uint32_t ENDAT2P2_GetAddInfo2(endat2p2_dev_t *dev)

Get the additional information 2.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of additional information 2.

endat2p2_position_t ENDAT2P2_RecvPosition(endat2p2_dev_t *dev)

Get the position value.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

position data including MT and ST.

endat2p2_position_addinfo_t ENDAT2P2_RecvPositionAddInfo(endat2p2_dev_t *dev)

Get the position value and additional information.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

position value and additional information.

endat2p2_addr_param_t ENDAT2P2_RecvAddrParam(endat2p2_dev_t *dev)

Get the address and parameter.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

address and parameter.

int ENDAT2P2_RecvData(endat2p2_dev_t *dev, endat2p2_mode_cmd_t cmd, endat2p2_recv_data_t *data)

Get the received data.

Parameters:

dev – EnDat2.2 device handle pointer.
cmd – Mode command.
pointer – of received data

Returns:

0 - successfully get the data

Returns:

-EINVAL - invalid mode command

void ENDAT2P2_CMDBuild(endat2p2_dev_t *dev, endat2p2_mode_cmd_t cmd, uint8_t mrs_or_addr, uint16_t param)

Create the command and write to the send register.

Parameters:

dev – EnDat2.2 device handle pointer.
cmd – Mode command.
mrs_or_addr – MRS code or memory address.
param – Parameter of memory.

void ENDAT2P2_CMDSend(endat2p2_dev_t *dev)

trigger master to send out the command.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_CMDWait(endat2p2_dev_t *dev)

Wait for the command to be processed.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_CMDProcess(endat2p2_dev_t *dev, endat2p2_mode_cmd_t cmd, uint8_t msr_or_addr, uint16_t param)

Process the command.

Parameters:

dev – EnDat2.2 device handle pointer.
cmd – Mode command.
mrs_or_addr – MRS code or memory address.
param – Parameter of memory.

void ENDAT2P2_EncoderRest(endat2p2_dev_t *dev)

Reset encoder.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetParam(endat2p2_dev_t *dev, uint8_t page, uint8_t addr)

Get the parameter of memory.

Parameters:

dev – EnDat2.2 device handle pointer.
page – Memory page.
addr – Memory address.

Returns:

the value of the parameter.

void ENDAT2P2_SetParam(endat2p2_dev_t *dev, uint8_t page, uint8_t addr, uint16_t data)

Set the parameter of memory.

Parameters:

dev – EnDat2.2 device handle pointer.
page – Memory page.
addr – Memory address.
data – Parameter of memory.

void ENDAT2P2_EncoderRestWithPos(endat2p2_dev_t *dev)

Reset encoder and get the position resolution.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetParamWithPos(endat2p2_dev_t *dev, uint8_t page, uint8_t addr)

Get the parameter and get the position resolution.

Parameters:

dev – EnDat2.2 device handle pointer.
page – Memory page.
addr – Memory address.

Returns:

the value of the memory.

void ENDAT2P2_SetParamWithPos(endat2p2_dev_t *dev, uint8_t page, uint8_t addr, uint16_t data)

Set the parameter and get the position resolution.

Parameters:

dev – EnDat2.2 device handle pointer.
page – Memory page.
addr – Memory address.
data – Parameter of memory.

int ENDAT2P2_GetPosRes(endat2p2_dev_t *dev)

Get the position resolution.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the position resolution.

int ENDAT2P2_GetType(endat2p2_dev_t *dev)

Get the type of encoder.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the type value.

int ENDAT2P2_GetMultiTurnRes(endat2p2_dev_t *dev)

Get the multiple turn resolution.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the multiple turn resolution.

int ENDAT2P2_GetStep(endat2p2_dev_t *dev)

Get the step resolution.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the step resolution.

void ENDAT2P2_GetID(endat2p2_dev_t *dev)

Get the ID of encoder and store to dev->id_ascii and dev->id_binary.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_GetSN(endat2p2_dev_t *dev)

Get the serial number of encoder and store to dev->sn_ascii_msb and dev->sn_ascii_lsb.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_GetCommandSet(endat2p2_dev_t *dev)

Get the command set of encoder and store to dev->cmd_set_2_2 and dev->has_safety.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_GetStatusAddInfo(endat2p2_dev_t *dev)

Get the additional information. Store to dev->status_addinfo1 and dev->status_addinfo2.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetEncoderError(endat2p2_dev_t *dev)

Get the encoder error.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the encoder error.

void ENDAT2P2_ClearEncoderError(endat2p2_dev_t *dev)

Clear the encoder error.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetEncoderWarning(endat2p2_dev_t *dev)

Get the encoder warning.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the encoder warning.

void ENDAT2P2_ClearEncoderWarning(endat2p2_dev_t *dev)

Clear the encoder warning.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetEncoderInfo(endat2p2_dev_t *dev)

Get the encoder information.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

0 - sucessfully get the encoder information.

int ENDAT2P2_InitEncoder(endat2p2_dev_t *dev)

Initialize encoder.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetEncoderErrorWithPos(endat2p2_dev_t *dev)

Get encoder error with the position value.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the error value.

void ENDAT2P2_ClearEncoderErrorWithPos(endat2p2_dev_t *dev)

Clear encoder error with the position value.

Parameters:

dev – EnDat2.2 device handle pointer.

int ENDAT2P2_GetEncoderWarningWithPos(endat2p2_dev_t *dev)

Get encoder warning with the position value.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the warning value.

void ENDAT2P2_ClearEncoderWarningWithPos(endat2p2_dev_t *dev)

Clear encoder warning with the position value.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_AddInfoSelect(endat2p2_dev_t *dev, mrs_mode_t mrs)

Select the encoder additional information.

Parameters:

dev – EnDat2.2 device handle pointer.
mrs – MRS code.

void ENDAT2P2_AddInfo1Stop(endat2p2_dev_t *dev)

Stop getting additional information 1.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_AddInfo2Stop(endat2p2_dev_t *dev)

Stop getting additional information 2.

Parameters:

dev – EnDat2.2 device handle pointer.

uint64_t ENDAT2P2_GetPosVal2(endat2p2_dev_t *dev)

Get the position value 2.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of the position value 2.

double ENDAT2P2_GetTemperature1(endat2p2_dev_t *dev)

Get the temperature.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of temperature.

double ENDAT2P2_GetTemperature2(endat2p2_dev_t *dev)

Get the temperature 2.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of temperature.

uint64_t ENDAT2P2_GetAsyncPosVal2(endat2p2_dev_t *dev)

Get the async position value 2.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of async position value 2.

int ENDAT2P2_GetOPSERRSRC(endat2p2_dev_t *dev)

Get the operating status error source.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of error source.

int ENDAT2P2_GetTimeStamp(endat2p2_dev_t *dev)

Get the timestamp.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of timestamp.

void ENDAT2P2_SetHWStrobe(endat2p2_dev_t *dev, bool enable)

Enable hardware strobe mode.

Parameters:

dev – EnDat2.2 device handle pointer.
enable – enable/disable hardware strobe mode .

void ENDAT2P2_SetDU(endat2p2_dev_t *dev, bool on)

Set DU bit of configuration register.

Parameters:

dev – EnDat2.2 device handle pointer.
on – set or clear DU bit.

void ENDAT2P2_SetDT(endat2p2_dev_t *dev, bool on)

Set DT bit to select continuous clock mode.

Parameters:

dev – EnDat2.2 device handle pointer.
on – set or clear DT bit.

void ENDAT2P2_SetDataWordLength(endat2p2_dev_t *dev, int length)

Set the data word length.

Parameters:

dev – EnDat2.2 device handle pointer.
length – the length of data word.

void ENDAT2P2_SetResetWindow(endat2p2_dev_t *dev, bool reset)

Set bit Reset window.

Parameters:

dev – EnDat2.2 device handle pointer.
reset – set to 0 or 1 to this bit.

void ENDAT2P2_SetAutoReset(endat2p2_dev_t *dev, bool enable)

Set the auto reset.

Parameters:

dev – EnDat2.2 device handle pointer.
enable – enable/disable auto reset.

void ENDAT2P2_SetCablePropagationTime(endat2p2_dev_t *dev, uint32_t time)

Set cable propagation time.

Parameters:

dev – EnDat2.2 device handle pointer.
time – the time of cable propagation.

uint32_t ENDAT2P2_GetCablePropagationTime(endat2p2_dev_t *dev)

Get the cable propagation time.

Parameters:

dev – EnDat2.2 device handle pointer.

Returns:

the value of cable propagation time.

uint32_t ENDAT2P2_CalculatePropagationTime(endat2p2_dev_t *dev, int count)

Calculate the propagation time.

Parameters:

dev – EnDat2.2 device handle pointer.
count – the count of the propagation time.

Returns:

the value of the propagation time.

void ENDAT2P2_SetDelayCompensation(endat2p2_dev_t *dev, bool enable)

Set the delay compensation.

Parameters:

dev – EnDat2.2 device handle pointer.
enable – enable/disable delay compensation.

void ENDAT2P2_EnableDelayCompensation(endat2p2_dev_t *dev)

Enable the delay compensation.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_ConfigSYSClock(endat2p2_dev_t *dev, uint32_t sysclock)

Set sysclock of the master.

Parameters:

dev – EnDat2.2 device handle pointer.
sysclock – system clock.

int ENDAT2P2_SetFTCLOCK(endat2p2_dev_t *dev, uint32_t clock)

Set the transmission rate for EnDat.

Parameters:

dev – EnDat2.2 device handle pointer.
clock – transmission rate.

Returns:

0 - successfully set ftclk.

Returns:

-EINVAL - invalid clock parameter.

void ENDAT2P2_ICReset(endat2p2_dev_t *dev)

Reset entire interface component.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_SetEnDatMode(endat2p2_dev_t *dev)

Set the EnDat mode.

Parameters:

dev – EnDat2.2 device handle pointer.

void ENDAT2P2_SetSamplingRate(endat2p2_dev_t *dev, int us)

Set sampling rate.

Parameters:

dev – EnDat2.2 device handle pointer.
us – the clock of sampling.

void ENDAT2P2_SetWatchdogTimer(endat2p2_dev_t *dev, int us)

Set the watchdog timer.

Parameters:

dev – EnDat2.2 device handle pointer.
us – the time of watchdog timer.

void ENDAT2P2_SetRecoveryTimer(endat2p2_dev_t *dev, int us)

Set the recovery timer.

Parameters:

dev – EnDat2.2 device handle pointer.
us – the time ofrecovery timer.

SSI_MODE

ENDAT_MODE

ENDAT2P2_ADDINFO_MASK: EnDat2.2 addation information.

ENDAT2P2_ADDINFO_POS_MASK

ENDAT2P2_ADDINFO_TEMP_MASK

ENDAT2P2_ADDINFO_MEM_DATA_MASK

ENDAT2P2_ADDINFO_MEM_ADDR_SHIFT

ENDAT2P2_ADDINFO_MEM_ADDR_MASK

ENDAT2P2_ADDINFO_INS_SHIFT

ENDAT2P2_ADDINFO_INS_MASK

ENDAT2P2_ADDINFO_BUSY_MASK

ENDAT2P2_ADDINFO_RM_MASK

ENDAT2P2_ADDINFO_WRN_MASK

ENDAT2P2_ADDINFO1_STATUS_POS2_MASK: EnDat2.2 addation information 1.

ENDAT2P2_ADDINFO1_STATUS_TEST_MASK

ENDAT2P2_ADDINFO1_STATUS_TEMP1_MASK

ENDAT2P2_ADDINFO1_STATUS_TEMP2_MASK

ENDAT2P2_ADDINFO1_STATUS_SENSORS_MASK

ENDAT2P2_ADDINFO2_STATUS_COMMUTATION_MASK: EnDat2.2 addation information 2.

ENDAT2P2_ADDINFO2_STATUS_ACCELERATION_MASK

ENDAT2P2_ADDINFO2_STATUS_LIMITPOS_MASK

ENDAT2P2_ADDINFO2_STATUS_ASYNCPOS_MASK

ENDAT2P2_ADDINFO2_STATUS_OPTERRSRC_MASK

ENDAT2P2_ADDINFO2_STATUS_POS2_MASK

ENDAT2P2_ADDINFO2_STATUS_TIMESTAMP_MASK

ENDAT2P2_OPT_ERR_LIGHTING_MASk: EnDat2.2 operating status.

ENDAT2P2_OPT_ERR_SIGNAL_AMPLITUDE_MASk

ENDAT2P2_OPT_ERR_POSITION_MASk

ENDAT2P2_OPT_ERR_OVERVOLTAGE_MASk

ENDAT2P2_OPT_ERR_UNDERVLOTAGE_MASk

ENDAT2P2_OPT_ERR_OVERCURRENT_MASk

ENDAT2P2_OPT_ERR_BATTERY_MASk

ENDAT2P2_OPT_WARN_FREQ_COLLISION_MASk

ENDAT2P2_OPT_WARN_TEMP_EXCEEDED_MASk

ENDAT2P2_OPT_WARN_LIGHT_RESERVE_MASk

ENDAT2P2_OPT_WARN_BATTERY_CHARGE_MASk

ENDAT2P2_OPT_WARN_REGERNVE_POINT_MASk

ENDAT2P2_OPT_WARN_CYCLIC_MODE_MASk

ENDAT2P2_OPT_WARN_LIMIT_POSITION_MASk

ENDAT2P2_OPT_WARN_STANDBY_MASk

ENDAT2P2_OPT_WARN_DIAGNOSTICS_MASk

ENDAT_NUM_BITS_POSITION_CRC

ENDAT_NUM_BITS_F1

ENDAT_NUM_BITS_F2

ENDAT_NUM_BITS_PARAMETER

ENDAT_NUM_BITS_ADDRESS

ENDAT2P2_TYPE_WITH_BATTERY_SHIFT

ENDAT2P2_TYPE_ABSOLUTE_SHIFT

ENDAT2P2_TYPE_ROTARY_SHIFT

struct _endat2p2_dev: #include <fsl_endat2p2.h>

EnDat2.2 device.

struct _endat2p2_data: #include <fsl_endat2p2.h>

EnDat2.2 received data - position, additional information 1 & 2.

struct _endat2p2_position: #include <fsl_endat2p2.h>

EnDat2.2 position value.

struct endat2p2_position_addinfo: #include <fsl_endat2p2.h>

EnDat2.2 position and additional information.

struct _endat2p2_addr_param: #include <fsl_endat2p2.h>

EnDat2.2 memory addr and parameter.

struct _endat2p2_recv_data: #include <fsl_endat2p2.h>

EnDat2.2 encoder received data.

union __unnamed13__

Public Members

endat2p2_position_t position

endat2p2_position_addinfo_t position_addinfo

endat2p2_addr_param_t addr_param

Endat3: Endat3 encoder Driver#

EQDC: Enhanced Quadrature Encoder/Decoder#

void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)

Initializes the EQDC module.

This function initializes the EQDC by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
psConfig – Pointer to configuration structure.

void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)

Gets an available pre-defined configuration.

The default value are:

psConfig->enableReverseDirection              = false;
psConfig->countOnce                           = false;
psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
psConfig->countMode                           = kEQDC_QuadratureX4;
psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
psConfig->enableIndexInitPositionCounter      = false;
psConfig->enableDma                           = false;
psConfig->bufferedRegisterLoadMode            = false;
psConfig->enableTriggerInitPositionCounter    = false;
psConfig->enableTriggerClearPositionRegisters = false;
psConfig->enableTriggerHoldPositionRegisters  = false;
psConfig->enableWatchdog                      = false;
psConfig->watchdogTimeoutValue                = 0xFFFFU;
psConfig->filterPhaseA                        = 0U;
psConfig->filterPhaseB                        = 0U;
psConfig->filterIndPre                        = 0U;
psConfig->filterHomEna                        = 0U;
psConfig->filterClockSourceselection          = false;
psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
psConfig->filterSamplePeriod                  = 0U;
psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
psConfig->positionCompareValue[0]                = 0xFFFFFFFFU;
psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
psConfig->positionModulusValue                = 0U;
psConfig->positionInitialValue                = 0U;
psConfig->positionCounterValue                = 0U;
psConfig->enablePeriodMeasurement             = false;
psConfig->prescaler                           = kEQDC_Prescaler1;
psConfig->enabledInterruptsMask               = 0U;

Parameters:

psConfig – Pointer to configuration structure.

void EQDC_Deinit(EQDC_Type *base)

De-initializes the EQDC module.

This function deinitializes the EQDC by disabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.

void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)

Initializes the mode of operation.

This function initializes mode of operation by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
operateMode – Select operation mode.

static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode)

Initializes the mode of count.

These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved

Parameters:

base – EQDC peripheral base address.
countMode – Select count mode.

static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable)

Enable watchdog for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the watchdog

static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout)

Set watchdog timeout value.

Parameters:

base – EQDC peripheral base address
u16Timeout – Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out

static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable)

Enable DMA for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the DMA

static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Set Buffered Register Load (Update) Mode.

This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base)

Clear Buffered Register Load (Update) Mode.

Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_SetEqdcLdok(EQDC_Type *base)

Set load okay.

Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.

Parameters:

base – EQDC peripheral base address.

static inline uint16_t EQDC_GetEqdcLdok(EQDC_Type *base)

Get load okay.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_ClearEqdcLdok(EQDC_Type *base)

Clear load okay.

Parameters:

base – EQDC peripheral base address.

static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base)

Get the status flags.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the status flags, _eqdc_status_flags.

static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags)

Clear the status flags.

Parameters:

base – EQDC peripheral base address.
u32Flags – Logical OR’ed value of the flags to clear, _eqdc_status_flags.

static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base)

Get the signals’ real-time status.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the real-time signal status, _eqdc_signal_status.

static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base)

Get the direction of the last count.

Parameters:

base – EQDC peripheral base address.

Returns:

Direction of the last count.

static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Enable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)

Disable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base)

Load the initial position value to position counter.

Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue)

Set initial position value for EQDC module.

Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionInitValue – Position initial value

static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue)

Set position counter value.

Set the position counter value (POS or UPOS, LPOS).

Parameters:

base – EQDC peripheral base address
positionCounterValue – Position counter value

static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue)

Set position counter modulus value.

Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
positionModulusValue – Position modulus value

static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value)

Set position counter compare 0 value.

Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp0Value – Position modulus value

static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value)

Set position counter compare 1 value.

Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp1Value – Position modulus value

static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value)

Set position counter compare 2 value.

Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp2Value – Position modulus value

static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value)

Set position counter compare 3 value.

Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp3Value – Position modulus value

static inline uint32_t EQDC_GetPosition(EQDC_Type *base)

Get the current position counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

Current position counter’s value.

static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base)

Get the hold position counter’s value.

The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter’s value.

static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base)

Get the hold position counter1’s value.

The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter1’s value.

static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base)

Get the hold position counter2’s value.

The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter2’s value.

static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base)

Get the hold position counter3’s value.

The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter3’s value.

static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base)

Get the position difference counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference counter’s value.

static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base)

Get the hold position difference counter’s value.

The position difference (POSD) value is loaded to hold position difference (POSDH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position difference counter’s value.

static inline uint16_t EQDC_GetRevolution(EQDC_Type *base)

Get the revolution counter’s value.

Get the revolution counter (REV) value.

Parameters:

base – EQDC peripheral base address.

Returns:

The revolution counter’s value.

static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base)

Get the hold revolution counter’s value.

The revolution counter (REV) value is loaded to hold revolution (REVH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position revolution counter’s value.

static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base)

Get the last edge time.

Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The last edge time.

static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base)

Get the hold last edge time.

The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold of last edge time.

static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base)

Get the Position Difference Period counter value.

The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference period counter value.

static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base)

Get buffered Position Difference Period counter value.

The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The buffered position difference period counter value.

static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)

Get Hold Position Difference Period counter value.

The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.

Parameters:

base – EQDC peripheral base address.

Returns:

The hold position difference period counter value.

enum _eqdc_status_flags

EQDC status flags, these flags indicate the counter’s events. .

Values:

enumerator kEQDC_HomeEnableTransitionFlag: HOME/ENABLE signal transition occured.

enumerator kEQDC_IndexPresetPulseFlag: INDEX/PRESET pulse occured.

enumerator kEQDC_WatchdogTimeoutFlag: Watchdog timeout occured.

enumerator kEQDC_SimultPhaseChangeFlag: Simultaneous change of PHASEA and PHASEB occured.

enumerator kEQDC_CountDirectionChangeFlag: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverFlag: Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.

enumerator kEQDC_PositionRollUnderFlag: Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.

enumerator kEQDC_PositionCompare0Flag: Position counter match the COMP0 value.

enumerator kEQDC_PositionCompare1Flag: Position counter match the COMP1 value.

enumerator kEQDC_PositionCompare2Flag: Position counter match the COMP2 value.

enumerator kEQDC_PositionCompare3Flag: Position counter match the COMP3 value.

enumerator kEQDC_StatusAllFlags

enum _eqdc_signal_status

Signal status, these flags indicate the raw and filtered input signal status. .

Values:

enumerator kEQDC_SignalStatusRawHomeEnable: Raw HOME/ENABLE input.

enumerator kEQDC_SignalStatusRawIndexPreset: Raw INDEX/PRESET input.

enumerator kEQDC_SignalStatusRawPhaseB: Raw PHASEB input.

enumerator kEQDC_SignalStatusRawPhaseA: Raw PHASEA input.

enumerator kEQDC_SignalStatusFilteredHomeEnable: The filtered HOME/ENABLE input.

enumerator kEQDC_SignalStatusFilteredIndexPreset: The filtered INDEX/PRESET input.

enumerator kEQDC_SignalStatusFilteredPhaseB: The filtered PHASEB input.

enumerator kEQDC_SignalStatusFilteredPhaseA: The filtered PHASEA input.

enumerator kEQDC_SignalStatusPositionCompare0Flag: Position Compare 0 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare1Flag: Position Compare 1 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare2Flag: Position Compare 2 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare3Flag: Position Compare 3 Flag Output.

enumerator kEQDC_SignalStatusCountDirectionFlagHold: Count Direction Flag Hold.

enumerator kEQDC_SignalStatusCountDirectionFlag: Count Direction Flag Output.

enumerator kEQDC_SignalStatusAllFlags

enum _eqdc_interrupt_enable

Interrupt enable/disable mask. .

Values:

enumerator kEQDC_HomeEnableTransitionInterruptEnable: HOME/ENABLE signal transition interrupt enable.

enumerator kEQDC_IndexPresetPulseInterruptEnable: INDEX/PRESET pulse interrupt enable.

enumerator kEQDC_WatchdogTimeoutInterruptEnable: Watchdog timeout interrupt enable.

enumerator kEQDC_SimultPhaseChangeInterruptEnable: Simultaneous PHASEA and PHASEB change interrupt enable.

enumerator kEQDC_CountDirectionChangeInterruptEnable: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverInterruptEnable: Roll-over interrupt enable.

enumerator kEQDC_PositionRollUnderInterruptEnable: Roll-under interrupt enable.

enumerator kEQDC_AllInterruptEnable

enum _eqdc_home_enable_init_pos_counter_mode

Define HOME/ENABLE signal’s trigger mode.

Values:

enumerator kEQDC_HomeInitPosCounterDisabled: Don’t use HOME/ENABLE signal to initialize the position counter.

enumerator kEQDC_HomeInitPosCounterOnRisingEdge: Use positive going edge to trigger initialization of position counters.

enumerator kEQDC_HomeInitPosCounterOnFallingEdge: Use negative going edge to trigger initialization of position counters.

enum _eqdc_index_preset_init_pos_counter_mode

Define INDEX/PRESET signal’s trigger mode.

Values:

enumerator kEQDC_IndexInitPosCounterDisabled: INDEX/PRESET pulse does not initialize the position counter.

enumerator kEQDC_IndexInitPosCounterOnRisingEdge: Use INDEX/PRESET pulse rising edge to initialize position counter.

enumerator kEQDC_IndexInitPosCounterOnFallingEdge: Use INDEX/PRESET pulse falling edge to initialize position counter.

enum _eqdc_operate_mode

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

Values:

enumerator kEQDC_QuadratureDecodeOperationMode: Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_QuadratureCountOperationMode: Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.

enumerator kEQDC_SinglePhaseDecodeOperationMode: Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_SinglePhaseCountOperationMode: Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.

enum _eqdc_count_mode

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

Values:

enumerator kEQDC_QuadratureX4: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX2: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX1: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_UpDownPulseCount: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountDoubleEdge: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountSingleEdge: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enum _eqdc_output_pulse_mode

Define type for the condition of POSMATCH pulses.

Values:

enumerator kEQDC_OutputPulseOnCounterEqualCompare: POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).

enumerator kEQDC_OutputPulseOnReadingPositionCounter: POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).

enum _eqdc_revolution_count_condition

Define type for determining how the revolution counter (REV) is incremented/decremented.

Values:

enumerator kEQDC_RevolutionCountOnIndexPulse: Use INDEX pulse to increment/decrement revolution counter.

enumerator kEQDC_RevolutionCountOnRollOverModulus: Use modulus counting roll-over/under to increment/decrement revolution counter.

enum _eqdc_filter_sample_count

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

Values:

enumerator kEQDC_Filter3Samples: 3 samples.

enumerator kEQDC_Filter4Samples: 4 samples.

enumerator kEQDC_Filter5Samples: 5 samples.

enumerator kEQDC_Filter6Samples: 6 samples.

enumerator kEQDC_Filter7Samples: 7 samples.

enumerator kEQDC_Filter8Samples: 8 samples.

enumerator kEQDC_Filter9Samples: 9 samples.

enumerator kEQDC_Filter10Samples: 10 samples.

enum _eqdc_count_direction_flag

Count direction.

Values:

enumerator kEQDC_CountDirectionDown: Last count was in down direction.

enumerator kEQDC_CountDirectionUp: Last count was in up direction.

enum _eqdc_prescaler

Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

Values:

enumerator kEQDC_Prescaler1: Prescaler value 1.

enumerator kEQDC_Prescaler2: Prescaler value 2.

enumerator kEQDC_Prescaler4: Prescaler value 4.

enumerator kEQDC_Prescaler8: Prescaler value 8.

enumerator kEQDC_Prescaler16: Prescaler value 16.

enumerator kEQDC_Prescaler32: Prescaler value 32.

enumerator kEQDC_Prescaler64: Prescaler value 64.

enumerator kEQDC_Prescaler128: Prescaler value 128.

enumerator kEQDC_Prescaler256: Prescaler value 256.

enumerator kEQDC_Prescaler512: Prescaler value 512.

enumerator kEQDC_Prescaler1024: Prescaler value 1024.

enumerator kEQDC_Prescaler2048: Prescaler value 2048.

enumerator kEQDC_Prescaler4096: Prescaler value 4096.

enumerator kEQDC_Prescaler8192: Prescaler value 8192.

enumerator kEQDC_Prescaler16384: Prescaler value 16384.

enumerator kEQDC_Prescaler32768: Prescaler value 32768.

typedef enum _eqdc_home_enable_init_pos_counter_mode eqdc_home_enable_init_pos_counter_mode_t: Define HOME/ENABLE signal’s trigger mode.

typedef enum _eqdc_index_preset_init_pos_counter_mode eqdc_index_preset_init_pos_counter_mode_t: Define INDEX/PRESET signal’s trigger mode.

typedef enum _eqdc_operate_mode eqdc_operate_mode_t

Define type for decoder opertion mode.

typedef enum _eqdc_count_mode eqdc_count_mode_t

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

typedef enum _eqdc_output_pulse_mode eqdc_output_pulse_mode_t: Define type for the condition of POSMATCH pulses.

typedef enum _eqdc_revolution_count_condition eqdc_revolution_count_condition_t: Define type for determining how the revolution counter (REV) is incremented/decremented.

typedef enum _eqdc_filter_sample_count eqdc_filter_sample_count_t

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

typedef enum _eqdc_count_direction_flag eqdc_count_direction_flag_t: Count direction.

typedef enum _eqdc_prescaler eqdc_prescaler_t: Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

typedef struct _eqdc_config eqdc_config_t: Define user configuration structure for EQDC module.

FSL_EQDC_DRIVER_VERSION

EQDC_CTRL_W1C_FLAGS: W1C bits in EQDC CTRL registers.

EQDC_INTCTRL_W1C_FLAGS: W1C bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_EN: Interrupt enable bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_EN: Interrupt enable bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_FLAGS: Interrupt flag bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_FLAGS: Interrupt flag bits in EQDC INTCTRL registers.

struct _eqdc_config

#include <fsl_eqdc.h>

Define user configuration structure for EQDC module.

Public Members

bool enableReverseDirection: Enable reverse direction counting.

bool countOnce: Selects modulo loop or one shot counting mode.

bool enableDma: Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)

bool bufferedRegisterLoadMode: selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD).

bool enableTriggerInitPositionCounter: Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER’s rising edge.

bool enableIndexInitPositionCounter

Enables the feature that the position counter to be initialized by Index Event Edge Mark.

This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:

When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.

When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.

bool enableTriggerClearPositionRegisters: Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER’s rising edge.

bool enableTriggerHoldPositionRegisters: Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER’s rising edge.

bool filterPhaseA: Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed.

bool filterPhaseB: Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed.

bool filterIndPre: Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed.

bool filterHomEna: Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed.

bool enableWatchdog: Enable the watchdog to detect if the target is moving or not.

uint16_t watchdogTimeoutValue: Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer.

eqdc_prescaler_t prescaler: Prescaler.

bool filterClockSourceselection: Filter Clock Source selection.

eqdc_filter_sample_count_t filterSampleCount: Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.

uint8_t filterSamplePeriod: Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

eqdc_operate_mode_t operateMode: Selects operation mode.

eqdc_count_mode_t countMode: Selects count mode.

eqdc_home_enable_init_pos_counter_mode_t homeEnableInitPosCounterMode: Select how HOME/Enable signal used to initialize position counters.

eqdc_index_preset_init_pos_counter_mode_t indexPresetInitPosCounterMode: Select how INDEX/Preset signal used to initialize position counters.

eqdc_output_pulse_mode_t outputPulseMode: The condition of POSMATCH pulses.

uint32_t positionCompareValue[4]: Position compare 0 ~ 3 value. The available value is a 32-bit number.

eqdc_revolution_count_condition_t revolutionCountCondition: Revolution Counter Modulus Enable.

uint32_t positionModulusValue: Position modulus value. The available value is a 32-bit number.

uint32_t positionInitialValue: Position initial value. The available value is a 32-bit number.

uint32_t positionCounterValue: Position counter value. When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.

bool enablePeriodMeasurement: Enable period measurement. When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.

uint16_t enabledInterruptsMask: Mask of interrupts to be enabled, should be OR’ed value of _eqdc_interrupt_enable.

EWM: External Watchdog Monitor Driver#

void EWM_Init(EWM_Type *base, const ewm_config_t *config)

Initializes the EWM peripheral.

This function is used to initialize the EWM. After calling, the EWM runs immediately according to the configuration. Note that, except for the interrupt enable control bit, other control bits and registers are write once after a CPU reset. Modifying them more than once generates a bus transfer error.

This is an example.

ewm_config_t config;
EWM_GetDefaultConfig(&config);
config.compareHighValue = 0xAAU;
EWM_Init(ewm_base,&config);

Parameters:

base – EWM peripheral base address
config – The configuration of the EWM

void EWM_Deinit(EWM_Type *base)

Deinitializes the EWM peripheral.

This function is used to shut down the EWM.

Parameters:

base – EWM peripheral base address

void EWM_GetDefaultConfig(ewm_config_t *config)

Initializes the EWM configuration structure.

This function initializes the EWM configuration structure to default values. The default values are as follows.

ewmConfig->enableEwm = true;
ewmConfig->enableEwmInput = false;
ewmConfig->setInputAssertLogic = false;
ewmConfig->enableInterrupt = false;
ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
ewmConfig->prescaler = 0;
ewmConfig->compareLowValue = 0;
ewmConfig->compareHighValue = 0xFEU;

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)

Determine whether the FlexCAN instance support CAN FD mode at run time.

Note

Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.

uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)

Get Mailbox offset number by dword.

This function gets the offset number of the specified mailbox. Mailbox is not consecutive between memory regions when payload is not 8 bytes so need to calculate the specified mailbox address. For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword after the 0x4002_4080, which is actually the address of mailbox MB[1].CS.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – Mailbox index.

Returns:

Mailbox address offset in word.

status_t FLEXCAN_EnterFreezeMode(CAN_Type *base)

Enter FlexCAN Freeze Mode.

This function makes the FlexCAN work under Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

status_t FLEXCAN_ExitFreezeMode(CAN_Type *base)

Exit FlexCAN Freeze Mode.

This function makes the FlexCAN leave Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

uint32_t FLEXCAN_GetInstance(CAN_Type *base)

Get the FlexCAN instance from peripheral base address.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN instance.

bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit Rates for classical CAN.

This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration.

void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit rates for CANFD.

This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The CANFD bus control speed in bps defined by user.
bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration

void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.bitRateFD            = 2000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.
dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.
brs – True if bit rate switch is enabled in FD mode.

void FLEXCAN_Deinit(CAN_Type *base)

De-initializes a FlexCAN instance.

This function disables the FlexCAN module clock and sets all register values to the reset value.

Parameters:

base – FlexCAN peripheral base address.

void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)

Gets the default configuration structure.

This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;

Parameters:

pConfig – Pointer to the FlexCAN configuration structure.

void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN classical CAN protocol timing characteristic.

This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.

Note

Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)

Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.

This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.

Note

Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRate_Bps – Bit rate in Bps.

Returns:

kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.

void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN CANFD data phase timing characteristic.

This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.

Note

Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)

Set bit rate of FlexCAN FD frame.

This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRateN_Bps – Nominal bit Rate in Bps.
bitRateD_Bps – Data bit Rate in Bps.

Returns:

kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.

void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive message buffer global mask.

This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Message Buffer Global Mask value.

void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive FIFO global mask.

This function sets the global mask for FlexCAN FIFO in a matching process.

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Fifo Global Mask value.

void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)

Sets the FlexCAN receive individual mask.

This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.

Parameters:

base – FlexCAN peripheral base address.
maskIdx – The Index of individual Mask.
mask – Rx Individual Mask value.

void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetFDMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)

Configures a FlexCAN Remote Response Message Buffer.

User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pFrame – Pointer to CAN message frame structure for response.

void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)

Configures the FlexCAN Legacy Rx FIFO.

This function configures the FlexCAN Rx FIFO with given configuration.

Note

Legacy Rx FIFO only can receive classic CAN message.

Parameters:

base – FlexCAN peripheral base address.
pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Legacy Rx FIFO.
- true: Enable Legacy Rx FIFO.
- false: Disable Legacy Rx FIFO.

void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable)

Configures the FlexCAN Enhanced Rx FIFO.

This function configures the Enhanced Rx FIFO with given configuration.

Note

Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Enhanced Rx FIFO.
- true: Enable Enhanced Rx FIFO.
- false: Disable Enhanced Rx FIFO.

void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)

Configures the FlexCAN Pretended Networking mode.

This function configures the FlexCAN Pretended Networking mode with given configuration.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.

static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)

Gets the FlexCAN module interrupt flags.

This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.

static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)

Clears status flags with the provided mask.

This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.

Parameters:

base – FlexCAN peripheral base address.
mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.

static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)

Gets the FlexCAN Bus Error Counter value.

This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.

Parameters:

base – FlexCAN peripheral base address.
txErrBuf – Buffer to store Tx Error Counter value.
rxErrBuf – Buffer to store Rx Error Counter value.

static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN low 64 Message Buffer interrupt flags.

This function gets the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN low 64 Message Buffer interrupt flags.

This function clears the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)

Gets the FlexCAN Memory Error Report registers status.

This function gets the FlexCAN Memory Error Report registers status.

Parameters:

base – FlexCAN peripheral base address.
errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.

static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)

Gets the FlexCAN Number of Matches when in Pretended Networking.

This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of received wake up msessages.

static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)

Gets the number of FlexCAN Enhanced Rx FIFO available frames.

This function gets the number of CAN messages stored in the Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of available CAN messages stored in the Enhanced Rx FIFO.

static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN interrupts according to the provided mask.

This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN interrupts according to the provided mask.

This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN low 64 Message Buffer interrupts.

This function enables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN low 64 Message Buffer interrupts.

This function disables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)

Enables or disables the FlexCAN Rx FIFO DMA request.

This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
enable – true to enable, false to disable.

static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)

Gets the Rx FIFO Head address.

This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN Rx FIFO Head address.

static inline status_t FLEXCAN_Enable(CAN_Type *base, bool enable)

Enables or disables the FlexCAN module operation.

This function enables or disables the FlexCAN module.

Parameters:

base – FlexCAN base pointer.
enable – true to enable, false to disable.

Returns:

kStatus_Success Enable FlexCAN module successful kStatus_Timeout Timeout when wait for Low-Power Mode Acknowledge

status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)

Writes a FlexCAN Message to the Transmit Message Buffer.

This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Receive Message Buffer.

This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty or inactive.
kStatus_Timeout – - Timeout when wait for Rx Message Buffer busy.

status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)

Writes a FlexCAN FD Message to the Transmit Message Buffer.

This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN FD Message from Receive Message Buffer.

This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty or inactive.
kStatus_Timeout – - Timeout when wait for Rx Message Buffer busy.

status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Legacy Rx FIFO.

This function reads a CAN message from the FlexCAN Legacy Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN Message from Enhanced Rx FIFO.

This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Wake Up MB.

This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.
mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.

Return values:

kStatus_Success – - Read Message from Wake up Message Buffer successfully.
kStatus_Fail – - Wake up Message Buffer has no valid content.

status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)

Initializes the FlexCAN handle.

This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
callback – The callback function.
userData – The parameter of the callback function.

status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

status_t FLEXCAN_TransferRemoteRequestNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a remote request frame using IRQ.

This function sends a remote request frame using IRQ. This is a non-blocking function, which returns right away. When the remote request frame has been sent out, the send callback function is called. User should invoke API FLEXCAN_TransferReceiveNonBlocking to receive the response frame. Receive message buffer index should less than send message buffer index.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx remote request frame sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Message Buffer is transmitting remote request frame.

status_t FLEXCAN_TransferRemoteResponseNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Configures a FlexCAN Message Buffer for automatic remote response using IRQ.

This function configures a Message Buffer to automatically respond to remote request frames using IRQ. This is a non-blocking function, which returns right away. When a matching remote request frame is received, the configured response frame will be transmitted automatically, and the callback function will be called. User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, if a remote request frame is received and matches a mailbox configured with CODE=kFLEXCAN_RxMbRanswer, the mailbox content will be transmitted as a response frame automatically. The received remote request frame is not stored.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Configure remote response Message Buffer successfully.
kStatus_Busy – Message Buffer is waiting for remote request frame or transmitting response frame.

status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Enhanced Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)

Gets the detail index of Mailbox’s Timestamp by handle.

Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking

Parameters:

handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

Return values:

the – index of mailbox ‘s timestamp stored in the handle.

static inline uint32_t FLEXCAN_GetHighResolutionTimeStamp(CAN_Type *base, uint8_t mbIdx)

void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Rx FIFO process.

This function aborts the interrupt driven message receive from Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Enhanced Rx FIFO process.

This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN IRQ handle function.

This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MbHandleIRQ(CAN_Type *base, flexcan_handle_t *handle, uint32_t startMbIdx, uint32_t endMbIdx)

FlexCAN Message Buffer IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
startMbIdx – First Message Buffer to handle.
endMbIdx – Last Message Buffer to handle.

void FLEXCAN_EnhancedRxFifoHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Enhanced Rx FIFO IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_BusoffErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Bus Off, Error and Warning IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_PNWakeUpHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Pretended Networking Wake-up IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MemoryErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Memory Error IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

FSL_FLEXCAN_DRIVER_VERSION: FlexCAN driver version.

FlexCAN transfer status.

Values:

enumerator kStatus_FLEXCAN_TxBusy: Tx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_TxIdle: Tx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_TxSwitchToRx: Remote Message is send out and Message buffer changed to Receive one.

enumerator kStatus_FLEXCAN_RxBusy: Rx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_RxIdle: Rx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_RxOverflow: Rx Message Buffer is Overflowed.

enumerator kStatus_FLEXCAN_RxFifoBusy: Rx Message FIFO is Busy.

enumerator kStatus_FLEXCAN_RxFifoIdle: Rx Message FIFO is Idle.

enumerator kStatus_FLEXCAN_RxFifoOverflow: Rx Message FIFO is overflowed.

enumerator kStatus_FLEXCAN_RxFifoWarning: Rx Message FIFO is almost overflowed.

enumerator kStatus_FLEXCAN_RxFifoDisabled: Rx Message FIFO is disabled during reading.

enumerator kStatus_FLEXCAN_ErrorStatus: FlexCAN Module Error and Status.

enumerator kStatus_FLEXCAN_WakeUp: FlexCAN is waken up from STOP mode.

enumerator kStatus_FLEXCAN_UnHandled: UnHadled Interrupt asserted.

enumerator kStatus_FLEXCAN_RxRemote: Rx Remote Message Received in Mail box.

enumerator kStatus_FLEXCAN_RxFifoUnderflow: Enhanced Rx Message FIFO is underflow.

enumerator kStatus_FLEXCAN_MemoryError: FlexCAN Memory Error.

enum _flexcan_frame_format

FlexCAN frame format.

Values:

enumerator kFLEXCAN_FrameFormatStandard: Standard frame format attribute.

enumerator kFLEXCAN_FrameFormatExtend: Extend frame format attribute.

enum _flexcan_frame_type

FlexCAN frame type.

Values:

enumerator kFLEXCAN_FrameTypeData: Data frame type attribute.

enumerator kFLEXCAN_FrameTypeRemote: Remote frame type attribute.

enum _flexcan_clock_source

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

Values:

enumerator kFLEXCAN_ClkSrcOsc: FlexCAN Protocol Engine clock from Oscillator.

enumerator kFLEXCAN_ClkSrcPeri: FlexCAN Protocol Engine clock from Peripheral Clock.

enumerator kFLEXCAN_ClkSrc0: FlexCAN Protocol Engine clock selected by user as SRC == 0.

enumerator kFLEXCAN_ClkSrc1: FlexCAN Protocol Engine clock selected by user as SRC == 1.

enum _flexcan_wake_up_source

FlexCAN wake up source.

Values:

enumerator kFLEXCAN_WakeupSrcUnfiltered: FlexCAN uses unfiltered Rx input to detect edge.

enumerator kFLEXCAN_WakeupSrcFiltered: FlexCAN uses filtered Rx input to detect edge.

enum _flexcan_endianness

FlexCAN payload endianness.

Values:

enumerator kFLEXCAN_bigEndian: Transmit frame with MSB first, receive frame with big-endian format.

enumerator kFLEXCAN_littleEndian: Transmit frame with LSB first, receive frame with little-endian format.

enum _flexcan_MB_timestamp_base

FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

Values:

enumerator kFLEXCAN_CANTimer: FlexCAN free-running timer.

enumerator kFLEXCAN_Lower16bitsHRTimer: Lower 16 bits of high-resolution on-chip timer.

enumerator kFLEXCAN_Upper16bitsHRTimer: Upper 16 bits of high-resolution on-chip timer.

enum _flexcan_capture_point

FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

Values:

enumerator kFLEXCAN_CANFrameID2ndBit: Second bit of identifier field of any frame is on the CAN bus. HR_TIME_STAMPn register will not capture 32-bit counter value.

enumerator kFLEXCAN_CANFrameEnd: End of the CAN frame.

enumerator kFLEXCAN_CANFrameStart: Start of the CAN frame.

enumerator kFLEXCAN_CANFDFrameRes: Start of frame for classical CAN frames; res bit for CAN FD frames.

enum _flexcan_rx_fifo_filter_type

FlexCAN Rx Fifo Filter type.

Values:

enumerator kFLEXCAN_RxFifoFilterTypeA: One full ID (standard and extended) per ID Filter element.

enumerator kFLEXCAN_RxFifoFilterTypeB: Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeC: Four partial 8-bit Standard or extended ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeD: All frames rejected.

enum _flexcan_mb_size

FlexCAN Message Buffer Payload size.

Values:

enumerator kFLEXCAN_8BperMB: Selects 8 bytes per Message Buffer.

enumerator kFLEXCAN_16BperMB: Selects 16 bytes per Message Buffer.

enumerator kFLEXCAN_32BperMB: Selects 32 bytes per Message Buffer.

enumerator kFLEXCAN_64BperMB: Selects 64 bytes per Message Buffer.

enum _flexcan_fd_frame_length

FlexCAN CAN FD frame supporting data length (available DLC values).

For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.

Values:

enumerator kFLEXCAN_0BperFrame: Frame contains 0 valid data bytes.

enumerator kFLEXCAN_1BperFrame: Frame contains 1 valid data bytes.

enumerator kFLEXCAN_2BperFrame: Frame contains 2 valid data bytes.

enumerator kFLEXCAN_3BperFrame: Frame contains 3 valid data bytes.

enumerator kFLEXCAN_4BperFrame: Frame contains 4 valid data bytes.

enumerator kFLEXCAN_5BperFrame: Frame contains 5 valid data bytes.

enumerator kFLEXCAN_6BperFrame: Frame contains 6 valid data bytes.

enumerator kFLEXCAN_7BperFrame: Frame contains 7 valid data bytes.

enumerator kFLEXCAN_8BperFrame: Frame contains 8 valid data bytes.

enumerator kFLEXCAN_12BperFrame: Frame contains 12 valid data bytes.

enumerator kFLEXCAN_16BperFrame: Frame contains 16 valid data bytes.

enumerator kFLEXCAN_20BperFrame: Frame contains 20 valid data bytes.

enumerator kFLEXCAN_24BperFrame: Frame contains 24 valid data bytes.

enumerator kFLEXCAN_32BperFrame: Frame contains 32 valid data bytes.

enumerator kFLEXCAN_48BperFrame: Frame contains 48 valid data bytes.

enumerator kFLEXCAN_64BperFrame: Frame contains 64 valid data bytes.

enum _flexcan_efifo_dma_per_read_length

FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

Values:

enumerator kFLEXCAN_1WordPerRead: Transfer 1 32-bit words (CS).

enumerator kFLEXCAN_2WordPerRead: Transfer 2 32-bit words (CS + ID).

enumerator kFLEXCAN_3WordPerRead: Transfer 3 32-bit words (CS + ID + 1~4 bytes data).

enumerator kFLEXCAN_4WordPerRead: Transfer 4 32-bit words (CS + ID + 5~8 bytes data).

enumerator kFLEXCAN_5WordPerRead: Transfer 5 32-bit words (CS + ID + 9~12 bytes data).

enumerator kFLEXCAN_6WordPerRead: Transfer 6 32-bit words (CS + ID + 13~16 bytes data).

enumerator kFLEXCAN_7WordPerRead: Transfer 7 32-bit words (CS + ID + 17~20 bytes data).

enumerator kFLEXCAN_8WordPerRead: Transfer 8 32-bit words (CS + ID + 21~24 bytes data).

enumerator kFLEXCAN_9WordPerRead: Transfer 9 32-bit words (CS + ID + 25~28 bytes data).

enumerator kFLEXCAN_10WordPerRead: Transfer 10 32-bit words (CS + ID + 29~32 bytes data).

enumerator kFLEXCAN_11WordPerRead: Transfer 11 32-bit words (CS + ID + 33~36 bytes data).

enumerator kFLEXCAN_12WordPerRead: Transfer 12 32-bit words (CS + ID + 37~40 bytes data).

enumerator kFLEXCAN_13WordPerRead: Transfer 13 32-bit words (CS + ID + 41~44 bytes data).

enumerator kFLEXCAN_14WordPerRead: Transfer 14 32-bit words (CS + ID + 45~48 bytes data).

enumerator kFLEXCAN_15WordPerRead: Transfer 15 32-bit words (CS + ID + 49~52 bytes data).

enumerator kFLEXCAN_16WordPerRead: Transfer 16 32-bit words (CS + ID + 53~56 bytes data).

enumerator kFLEXCAN_17WordPerRead: Transfer 17 32-bit words (CS + ID + 57~60 bytes data).

enumerator kFLEXCAN_18WordPerRead: Transfer 18 32-bit words (CS + ID + 61~64 bytes data).

enumerator kFLEXCAN_19WordPerRead: Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).

enumerator kFLEXCAN_20WordPerRead: Transfer 20 32-bit words (CS + ID + 64 bytes data + ID HIT + HR timestamp).

enum _flexcan_rx_fifo_priority

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

Values:

enumerator kFLEXCAN_RxFifoPrioLow: Matching process start from Rx Message Buffer first.

enumerator kFLEXCAN_RxFifoPrioHigh: Matching process start from Enhanced/Legacy Rx FIFO first.

enum _flexcan_interrupt_enable

FlexCAN interrupt enable enumerations.

This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.

Note

FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.

Values:

enumerator kFLEXCAN_BusOffInterruptEnable: Bus Off interrupt, use bit 15.

enumerator kFLEXCAN_ErrorInterruptEnable: CAN Error interrupt, use bit 14.

enumerator kFLEXCAN_TxWarningInterruptEnable: Tx Warning interrupt, use bit 11.

enumerator kFLEXCAN_RxWarningInterruptEnable: Rx Warning interrupt, use bit 10.

enumerator kFLEXCAN_FDErrorInterruptEnable: CAN FD Error interrupt, use bit 31.

enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable: PN Match Wake Up interrupt, use high word bit 17.

enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable: PN Timeout Wake Up interrupt, use high word bit 16. Enhanced Rx FIFO Underflow interrupt, use high word bit 31.

enumerator kFLEXCAN_ERxFifoUnderflowInterruptEnable: Enhanced Rx FIFO Overflow interrupt, use high word bit 30.

enumerator kFLEXCAN_ERxFifoOverflowInterruptEnable: Enhanced Rx FIFO Watermark interrupt, use high word bit 29.

enumerator kFLEXCAN_ERxFifoWatermarkInterruptEnable: Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28.

enumerator kFLEXCAN_ERxFifoDataAvlInterruptEnable

enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable: Host Access With Non-Correctable Errors interrupt, use high word bit 0.

enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable: FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.

enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable: Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.

enum _flexcan_flags

FlexCAN status flags.

This provides constants for the FlexCAN status flags for use in the FlexCAN functions.

Note

The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.

Values:

enumerator kFLEXCAN_ErrorOverrunFlag: Error Overrun Status.

enumerator kFLEXCAN_FDErrorIntFlag: CAN FD Error Interrupt Flag.

enumerator kFLEXCAN_BusoffDoneIntFlag: Bus Off process completed Interrupt Flag.

enumerator kFLEXCAN_SynchFlag: CAN Synchronization Status.

enumerator kFLEXCAN_TxWarningIntFlag: Tx Warning Interrupt Flag.

enumerator kFLEXCAN_RxWarningIntFlag: Rx Warning Interrupt Flag.

enumerator kFLEXCAN_IdleFlag: FlexCAN In IDLE Status.

enumerator kFLEXCAN_FaultConfinementFlag: FlexCAN Fault Confinement State.

enumerator kFLEXCAN_TransmittingFlag: FlexCAN In Transmission Status.

enumerator kFLEXCAN_ReceivingFlag: FlexCAN In Reception Status.

enumerator kFLEXCAN_BusOffIntFlag: Bus Off Interrupt Flag.

enumerator kFLEXCAN_ErrorIntFlag: CAN Error Interrupt Flag.

enumerator kFLEXCAN_ErrorFlag

enumerator kFLEXCAN_PNMatchIntFlag: PN Matching Event Interrupt Flag.

enumerator kFLEXCAN_PNTimeoutIntFlag: PN Timeout Event Interrupt Flag.

enumerator kFLEXCAN_ERxFifoUnderflowIntFlag: Enhanced Rx FIFO underflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoOverflowIntFlag: Enhanced Rx FIFO overflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoWatermarkIntFlag: Enhanced Rx FIFO watermark Interrupt Flag.

enumerator kFLEXCAN_ERxFifoDataAvlIntFlag: Enhanced Rx FIFO data available Interrupt Flag.

enumerator kFLEXCAN_ERxFifoEmptyFlag: Enhanced Rx FIFO empty status.

enumerator kFLEXCAN_ERxFifoFullFlag: Enhanced Rx FIFO full status.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag: Host Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag: FlexCAN Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_CorrectableErrorIntFlag: Correctable Error Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag: Host Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag: FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_CorrectableErrorOverrunFlag: Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_AllMemoryErrorIntFlag: All Memory Error Interrupt Flags.

enumerator kFLEXCAN_AllMemoryErrorFlag: All Memory Error Flags.

enum _flexcan_error_flags

FlexCAN error status flags.

The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.

Values:

enumerator kFLEXCAN_FDStuffingError: Stuffing Error.

enumerator kFLEXCAN_FDFormError: Form Error.

enumerator kFLEXCAN_FDCrcError: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_FDBit0Error: Unable to send dominant bit.

enumerator kFLEXCAN_FDBit1Error: Unable to send recessive bit.

enumerator kFLEXCAN_TxErrorWarningFlag: Tx Error Warning Status.

enumerator kFLEXCAN_RxErrorWarningFlag: Rx Error Warning Status.

enumerator kFLEXCAN_StuffingError: Stuffing Error.

enumerator kFLEXCAN_FormError: Form Error.

enumerator kFLEXCAN_CrcError: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_AckError: Received no ACK on transmission.

enumerator kFLEXCAN_Bit0Error: Unable to send dominant bit.

enumerator kFLEXCAN_Bit1Error: Unable to send recessive bit.

FlexCAN Legacy Rx FIFO status flags.

The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.

Values:

enumerator kFLEXCAN_RxFifoOverflowFlag: Rx FIFO overflow flag.

enumerator kFLEXCAN_RxFifoWarningFlag: Rx FIFO almost full flag.

enumerator kFLEXCAN_RxFifoFrameAvlFlag: Frames available in Rx FIFO flag.

enum _flexcan_memory_error_type

FlexCAN Memory Error Type.

Values:

enumerator kFLEXCAN_CorrectableError: The memory error is correctable which means on bit error.

enumerator kFLEXCAN_NonCorrectableError: The memory error is non-correctable which means two bit errors.

enum _flexcan_memory_access_type

FlexCAN Memory Access Type.

Values:

enumerator kFLEXCAN_MoveOutFlexCanAccess: The memory error was detected during move-out FlexCAN access.

enumerator kFLEXCAN_MoveInAccess: The memory error was detected during move-in FlexCAN access.

enumerator kFLEXCAN_TxArbitrationAccess: The memory error was detected during Tx Arbitration FlexCAN access.

enumerator kFLEXCAN_RxMatchingAccess: The memory error was detected during Rx Matching FlexCAN access.

enumerator kFLEXCAN_MoveOutHostAccess: The memory error was detected during Rx Matching Host (CPU) access.

enum _flexcan_byte_error_syndrome

FlexCAN Memory Error Byte Syndrome.

Values:

enumerator kFLEXCAN_NoError: No bit error in this byte.

enumerator kFLEXCAN_ParityBits0Error: Parity bit 0 error in this byte.

enumerator kFLEXCAN_ParityBits1Error: Parity bit 1 error in this byte.

enumerator kFLEXCAN_ParityBits2Error: Parity bit 2 error in this byte.

enumerator kFLEXCAN_ParityBits3Error: Parity bit 3 error in this byte.

enumerator kFLEXCAN_ParityBits4Error: Parity bit 4 error in this byte.

enumerator kFLEXCAN_DataBits0Error: Data bit 0 error in this byte.

enumerator kFLEXCAN_DataBits1Error: Data bit 1 error in this byte.

enumerator kFLEXCAN_DataBits2Error: Data bit 2 error in this byte.

enumerator kFLEXCAN_DataBits3Error: Data bit 3 error in this byte.

enumerator kFLEXCAN_DataBits4Error: Data bit 4 error in this byte.

enumerator kFLEXCAN_DataBits5Error: Data bit 5 error in this byte.

enumerator kFLEXCAN_DataBits6Error: Data bit 6 error in this byte.

enumerator kFLEXCAN_DataBits7Error: Data bit 7 error in this byte.

enumerator kFLEXCAN_AllZeroError: All-zeros non-correctable error in this byte.

enumerator kFLEXCAN_AllOneError: All-ones non-correctable error in this byte.

enumerator kFLEXCAN_NonCorrectableErrors: Non-correctable error in this byte.

enum _flexcan_pn_match_source

FlexCAN Pretended Networking match source selection.

Values:

enumerator kFLEXCAN_PNMatSrcID: Message match with ID filtering.

enumerator kFLEXCAN_PNMatSrcIDAndData: Message match with ID filtering and payload filtering.

enum _flexcan_pn_match_mode

FlexCAN Pretended Networking mode match type.

Values:

enumerator kFLEXCAN_PNMatModeEqual: Match upon ID/Payload contents against an exact target value.

enumerator kFLEXCAN_PNMatModeGreater: Match upon an ID/Payload value greater than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeSmaller: Match upon an ID/Payload value smaller than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeRange: Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit

typedef enum _flexcan_frame_format flexcan_frame_format_t: FlexCAN frame format.

typedef enum _flexcan_frame_type flexcan_frame_type_t: FlexCAN frame type.

typedef enum _flexcan_clock_source flexcan_clock_source_t

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t: FlexCAN wake up source.

typedef enum _flexcan_endianness flexcan_endianness_t: FlexCAN payload endianness.

typedef enum _flexcan_MB_timestamp_base flexcan_MB_timestamp_base_t: FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

typedef enum _flexcan_capture_point flexcan_capture_point_t: FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t: FlexCAN Rx Fifo Filter type.

typedef enum _flexcan_mb_size flexcan_mb_size_t: FlexCAN Message Buffer Payload size.

typedef enum _flexcan_efifo_dma_per_read_length flexcan_efifo_dma_per_read_length_t: FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t

FlexCAN Enhanced/Legacy Rx FIFO priority.

typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t: FlexCAN Memory Error Type.

typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t: FlexCAN Memory Access Type.

typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t: FlexCAN Memory Error Byte Syndrome.

typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

typedef struct _flexcan_frame flexcan_frame_t: FlexCAN message frame structure.

typedef struct _flexcan_fd_frame flexcan_fd_frame_t

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

typedef struct _flexcan_timing_config flexcan_timing_config_t: FlexCAN protocol timing characteristic configuration structure.

typedef struct _flexcan_config flexcan_config_t

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t: FlexCAN Pretended Networking match source selection.

typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t: FlexCAN Pretended Networking mode match type.

typedef struct _flexcan_pn_config flexcan_pn_config_t

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t: FlexCAN Legacy Rx FIFO configuration structure.

typedef struct _flexcan_enhanced_rx_fifo_std_id_filter flexcan_enhanced_rx_fifo_std_id_filter_t: FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter flexcan_enhanced_rx_fifo_ext_id_filter_t: FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_config flexcan_enhanced_rx_fifo_config_t: FlexCAN Enhanced Rx FIFO configuration structure.

typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t: FlexCAN Message Buffer transfer.

typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t: FlexCAN Rx FIFO transfer.

typedef struct _flexcan_handle flexcan_handle_t: FlexCAN handle structure definition.

typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)

FLEXCAN_WAIT_TIMEOUT

FLEXCAN_POLLING_TIMEOUT: Max loops to wait for polling transfer.

FLEXCAN_MODULE_TIMEOUT: Max loops to wait for FlexCAN register access complete.

FLEXCAN_MB_BUSY_TIMEOUT: Max loops to wait for FlexCAN RX Message Buffer busy.

DLC_LENGTH_DECODE(dlc): FlexCAN frame length helper macro.

FLEXCAN_ID_STD(id)

FlexCAN Frame ID helper macro.

Standard Frame ID helper macro.

FLEXCAN_ID_EXT(id): Extend Frame ID helper macro.

FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)

FlexCAN Rx Message Buffer Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide): Extend Rx Message Buffer Mask helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)

FlexCAN Legacy Rx FIFO Mask helper macro.

Standard Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide): Standard Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide): Standard Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id): Standard Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id): Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id): Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id): Standard Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide): Extend Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide): Extend Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide): Extend Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id): Extend Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id): Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id): Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id): Extend Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)

FlexCAN Rx FIFO Filter helper macro.

Standard Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide): Standard Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide): Standard Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id): Standard Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id): Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id): Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id): Standard Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide): Extend Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide): Extend Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide): Extend Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id): Extend Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id): Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id): Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id): Extend Rx FIFO Filter helper macro Type C lower part helper macro.

ENHANCED_RX_FIFO_FSCH(x): FlexCAN Enhanced Rx FIFO Filter and Mask helper macro.

RTR_STD_HIGH(x)

RTR_STD_LOW(x)

RTR_EXT(x)

ID_STD_LOW(id)

ID_STD_HIGH(id)

ID_EXT(id)

FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask): Standard ID filter element with filter + mask scheme.

FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask): Standard ID filter element with filter range.

FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2): Standard ID filter element with two filters without masks.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr): Extended ID filter element with filter + mask scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask): Extended ID filter element with filter + mask scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr): Extended ID filter element with range scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask): Extended ID filter element with range scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2): Extended ID filter element with two filters without masks low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1): Extended ID filter element with two filters without masks high word.

FLEXCAN_PN_STD_MASK(id, rtr)

FlexCAN Pretended Networking ID Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_PN_EXT_MASK(id, rtr): Extend Rx Message Buffer Mask helper macro.

FLEXCAN_PN_INT_MASK(x): FlexCAN interrupt/status flag helper macro.

FLEXCAN_PN_INT_UNMASK(x)

FLEXCAN_PN_STATUS_MASK(x)

FLEXCAN_PN_STATUS_UNMASK(x)

FLEXCAN_EFIFO_INT_MASK(x)

FLEXCAN_EFIFO_INT_UNMASK(x)

FLEXCAN_EFIFO_STATUS_MASK(x)

FLEXCAN_EFIFO_STATUS_UNMASK(x)

FLEXCAN_MECR_INT_MASK(x)

FLEXCAN_MECR_INT_UNMASK(x)

FLEXCAN_MECR_STATUS_MASK(x)

FLEXCAN_MECR_STATUS_UNMASK(x)

FLEXCAN_ERROR_AND_STATUS_INT_FLAG

FLEXCAN_PNWAKE_UP_FLAG

FLEXCAN_WAKE_UP_FLAG

FLEXCAN_MEMORY_ERROR_INT_FLAG

FLEXCAN_ENHANCED_RX_FIFO_INT_FLAG: FlexCAN Enhanced Rx FIFO base address helper macro.

E_RX_FIFO(base)

FLEXCAN_CALLBACK(x)

FlexCAN transfer callback function.

The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.

struct _flexcan_memory_error_report_status

#include <fsl_flexcan.h>

FlexCAN memory error register status structure.

Public Members

flexcan_memory_error_type_t errorType: The type of memory error that giving rise to the report.

flexcan_memory_access_type_t accessType: The type of memory access that giving rise to the memory error.

uint16_t accessAddress: The address where memory error detected.

uint32_t errorData: The raw data word read from memory with error.

struct _flexcan_frame: #include <fsl_flexcan.h>

FlexCAN message frame structure.

struct _flexcan_fd_frame

#include <fsl_flexcan.h>

CAN FD message frame structure.

Public Members

uint32_t idhit: Note

ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is correct. CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive mode).

uint32_t hrtimestamp: Note

HR timestamp offset is changed dynamically according to data length code (DLC). External 32-bit on-chip timer high-resolution timestamp.

struct _flexcan_timing_config

#include <fsl_flexcan.h>

FlexCAN protocol timing characteristic configuration structure.

Public Members

uint32_t preDivider: Classic CAN or CAN FD nominal phase bit rate prescaler.

uint32_t rJumpwidth: Classic CAN or CAN FD nominal phase Re-sync Jump Width.

uint32_t phaseSeg1: Classic CAN or CAN FD nominal phase Segment 1.

uint32_t phaseSeg2: Classic CAN or CAN FD nominal phase Segment 2.

uint32_t propSeg: Classic CAN or CAN FD nominal phase Propagation Segment.

uint32_t fpreDivider: CAN FD data phase bit rate prescaler.

uint32_t frJumpwidth: CAN FD data phase Re-sync Jump Width.

uint32_t fphaseSeg1: CAN FD data phase Phase Segment 1.

uint32_t fphaseSeg2: CAN FD data phase Phase Segment 2.

uint32_t fpropSeg: CAN FD data phase Propagation Segment.

struct _flexcan_config

#include <fsl_flexcan.h>

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

Public Members

flexcan_clock_source_t clkSrc: Clock source for FlexCAN Protocol Engine.

flexcan_wake_up_source_t wakeupSrc: Wake up source selection.

uint8_t maxMbNum: The maximum number of Message Buffers used by user.

bool enableLoopBack: Enable or Disable Loop Back Self Test Mode.

bool enableTimerSync: Enable or Disable Timer Synchronization.

bool enableIndividMask: Enable or Disable Rx Individual Mask and Queue feature.

bool disableSelfReception: Enable or Disable Self Reflection.

bool enableListenOnlyMode: Enable or Disable Listen Only Mode.

bool enableDoze: Enable or Disable Doze Mode.

bool enablePretendedeNetworking: Enable or Disable the Pretended Networking mode.

bool enableMemoryErrorControl: Enable or Disable the memory errors detection and correction mechanism.

bool enableNonCorrectableErrorEnterFreeze: Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.

bool enableTransceiverDelayMeasure: Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.

bool enableRemoteRequestFrameStored: true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.

flexcan_endianness_t payloadEndianness: Selects the byte order for the payload of transmit and receive frames, see flexcan_endianness_t.

bool enableExternalTimeTick: true: External time tick clocks the free-running timer. false: FlexCAN bit clock clocks the free-running timer.

flexcan_MB_timestamp_base_t captureTimeBase: Timebase of message buffer 16-bit TIME_STAMP field.

flexcan_capture_point_t capturePoint: Point in time when 32-bit timebase is captured during CAN frame.

struct _flexcan_rx_mb_config

#include <fsl_flexcan.h>

FlexCAN Receive Message Buffer configuration structure.

Public Members

uint32_t id: CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

flexcan_frame_format_t format: CAN Frame Identifier format(Standard of Extend).

flexcan_frame_type_t type: CAN Frame Type(Data or Remote for classical CAN only).

struct _flexcan_pn_config

#include <fsl_flexcan.h>

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

Public Members

bool enableTimeout: Enable or Disable timeout event trigger wakeup.

uint16_t timeoutValue: The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.

bool enableMatch: Enable or Disable match event trigger wakeup.

flexcan_pn_match_source_t matchSrc: Selects the match source (ID and/or data match) to trigger wakeup.

uint8_t matchNum: The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.

flexcan_pn_match_mode_t idMatchMode: The ID match type.

flexcan_pn_match_mode_t dataMatchMode: The data match type.

uint32_t idLower: The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.

uint32_t idUpper

The ID target values 2 which used only as the upper limit value in ID match “range

detection” or used to store the ID mask in “equal to”.

uint8_t lengthLower

The lower limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

uint8_t lengthUpper

The upper limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

struct _flexcan_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Legacy Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable: Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.

uint8_t idFilterNum: The FlexCAN Legacy Rx FIFO Filter elements quantity.

flexcan_rx_fifo_filter_type_t idFilterType: The FlexCAN Legacy Rx FIFO Filter type.

flexcan_rx_fifo_priority_t priority: The FlexCAN Legacy Rx FIFO receive priority.

struct _flexcan_enhanced_rx_fifo_std_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

Public Members

uint32_t filterType: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2: CAN Frame Identifier(STD or EXT format).

uint32_t std2: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_ext_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

Public Members

uint32_t filterType: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2: CAN Frame Identifier(STD or EXT format).

uint32_t std2: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable: Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member occupies 32 bit word, table size should be equal to idFilterNum. There are two types of Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table members), the extended-ID filter element needs to be placed in front of the table.

uint8_t idFilterPairNum: idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two standard ID filter elements.

uint8_t extendIdFilterNum: The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO identifier filter table, each extended-ID filter element occupies 2 words, extendIdFilterNum need less than or equal to idFilterPairNum.

uint8_t fifoWatermark: (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO which can trigger FIFO watermark interrupt or a DMA request.

flexcan_efifo_dma_per_read_length_t dmaPerReadLength: Define the length of each read of the Enhanced RX FIFO element by the DAM, see _flexcan_fd_frame_length.

flexcan_rx_fifo_priority_t priority: The FlexCAN Enhanced Rx FIFO receive priority.

struct _flexcan_mb_transfer

#include <fsl_flexcan.h>

FlexCAN Message Buffer transfer.

Public Members

flexcan_frame_t *frame: The buffer of CAN Message to be transfer.

uint8_t mbIdx: The index of Message buffer used to transfer Message.

struct _flexcan_fifo_transfer

#include <fsl_flexcan.h>

FlexCAN Rx FIFO transfer.

Public Members

flexcan_fd_frame_t *framefd: The buffer of CAN Message to be received from Enhanced Rx FIFO.

flexcan_frame_t *frame: The buffer of CAN Message to be received from Legacy Rx FIFO.

size_t frameNum: Depth of CAN Message receive array of Legacy or Enhanced Rx FIFO.

struct _flexcan_handle

#include <fsl_flexcan.h>

FlexCAN handle structure.

Public Members

flexcan_transfer_callback_t callback: Callback function.

void *userData: FlexCAN callback function parameter.

flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]: The buffer for received CAN data from Message Buffers.

flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]: The buffer for received CAN FD data from Message Buffers.

flexcan_frame_t *volatile rxFifoFrameBuf: The buffer for received CAN data from Legacy Rx FIFO.

flexcan_fd_frame_t *volatile rxFifoFDFrameBuf: The buffer for received CAN FD data from Enhanced Rx FIFO.

size_t rxFifoFrameNum: The number of CAN messages remaining to be received from Legacy or Enhanced Rx FIFO.

size_t rxFifoTransferTotalNum: Total CAN Message number need to be received from Legacy or Enhanced Rx FIFO.

volatile uint8_t mbState[CAN_WORD1_COUNT]: Message Buffer transfer state.

volatile uint8_t rxFifoState: Rx FIFO transfer state.

volatile uint32_t timestamp[CAN_WORD1_COUNT]: Mailbox transfer timestamp.

struct byteStatus

Public Members

bool byteIsRead: The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.

struct __unnamed23__

Public Members

uint32_t timestamp: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length: CAN frame data length in bytes (Range: 0~8).

uint32_t type: CAN Frame Type(DATA or REMOTE).

uint32_t format: CAN Frame Identifier(STD or EXT format).

uint32_t __pad0__: Reserved.

uint32_t idhit: CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).

struct __unnamed25__

Public Members

uint32_t id: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__: Reserved.

union __unnamed27__

Public Members

struct _flexcan_frame

struct _flexcan_frame

struct __unnamed29__

Public Members

uint32_t dataWord0: CAN Frame payload word0.

uint32_t dataWord1: CAN Frame payload word1.

struct __unnamed31__

Public Members

uint8_t dataByte3: CAN Frame payload byte3.

uint8_t dataByte2: CAN Frame payload byte2.

uint8_t dataByte1: CAN Frame payload byte1.

uint8_t dataByte0: CAN Frame payload byte0.

uint8_t dataByte7: CAN Frame payload byte7.

uint8_t dataByte6: CAN Frame payload byte6.

uint8_t dataByte5: CAN Frame payload byte5.

uint8_t dataByte4: CAN Frame payload byte4.

struct __unnamed33__

Public Members

uint32_t timestamp: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t type: CAN Frame Type(DATA only).

uint32_t format: CAN Frame Identifier(STD or EXT format).

uint32_t srr: Substitute Remote request.

uint32_t esi: Error State Indicator.

uint32_t brs: Bit Rate Switch.

uint32_t edl: Extended Data Length.

struct __unnamed35__

Public Members

uint32_t id: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__: Reserved.

union __unnamed37__

Public Members

struct _flexcan_fd_frame

struct _flexcan_fd_frame

struct __unnamed39__

Public Members

uint32_t dataWord[16]: CAN FD Frame payload, 16 double word maximum.

struct __unnamed41__

Public Members

uint8_t dataByte3: CAN Frame payload byte3.

uint8_t dataByte2: CAN Frame payload byte2.

uint8_t dataByte1: CAN Frame payload byte1.

uint8_t dataByte0: CAN Frame payload byte0.

uint8_t dataByte7: CAN Frame payload byte7.

uint8_t dataByte6: CAN Frame payload byte6.

uint8_t dataByte5: CAN Frame payload byte5.

uint8_t dataByte4: CAN Frame payload byte4.

union __unnamed43__

Public Members

struct _flexcan_config

struct _flexcan_config

struct __unnamed45__

Public Members

uint32_t baudRate: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t baudRateFD: FlexCAN FD bit rate in bps, for CANFD data phase.

struct __unnamed47__

Public Members

uint32_t bitRate: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t bitRateFD: FlexCAN FD bit rate in bps, for CANFD data phase.

union __unnamed49__

Public Members

struct _flexcan_pn_config

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

struct _flexcan_pn_config

struct __unnamed53__

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

Public Members

uint32_t lowerWord0: CAN Frame payload word0.

uint32_t lowerWord1: CAN Frame payload word1.

struct __unnamed55__

Public Members

uint8_t lowerByte3: CAN Frame payload byte3.

uint8_t lowerByte2: CAN Frame payload byte2.

uint8_t lowerByte1: CAN Frame payload byte1.

uint8_t lowerByte0: CAN Frame payload byte0.

uint8_t lowerByte7: CAN Frame payload byte7.

uint8_t lowerByte6: CAN Frame payload byte6.

uint8_t lowerByte5: CAN Frame payload byte5.

uint8_t lowerByte4: CAN Frame payload byte4.

union __unnamed51__

Public Members

struct _flexcan_pn_config

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

struct _flexcan_pn_config

struct __unnamed57__

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

Public Members

uint32_t upperWord0: CAN Frame payload word0.

uint32_t upperWord1: CAN Frame payload word1.

struct __unnamed59__

Public Members

uint8_t upperByte3: CAN Frame payload byte3.

uint8_t upperByte2: CAN Frame payload byte2.

uint8_t upperByte1: CAN Frame payload byte1.

uint8_t upperByte0: CAN Frame payload byte0.

uint8_t upperByte7: CAN Frame payload byte7.

uint8_t upperByte6: CAN Frame payload byte6.

uint8_t upperByte5: CAN Frame payload byte5.

uint8_t upperByte4: CAN Frame payload byte4.

FlexCAN eDMA Driver#

void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)

Initializes the FlexCAN handle, which is used in transactional functions.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.

void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)

Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.

This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.

Parameters:

base – FlexCAN peripheral base address.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)

Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.

This function to Update edma transfer confiugration and Start eDMA transfer

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN Message from the Legacy Rx FIFO using eDMA.

This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)

Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.

status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.

This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

FSL_FLEXCAN_EDMA_DRIVER_VERSION: FlexCAN EDMA driver version.

typedef struct _flexcan_edma_handle flexcan_edma_handle_t

typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData): FlexCAN transfer callback function.

struct _flexcan_edma_handle

#include <fsl_flexcan_edma.h>

FlexCAN eDMA handle.

Public Members

flexcan_edma_transfer_callback_t callback: Callback function.

void *userData: FlexCAN callback function parameter.

edma_handle_t *rxFifoEdmaHandle: The EDMA handler for Rx FIFO.

volatile uint8_t rxFifoState: Rx FIFO transfer state.

size_t frameNum: The number of messages that need to be received.

flexcan_fd_frame_t *framefd: Point to the buffer of CAN Message to be received from Enhanced Rx FIFO.

FlexIO: FlexIO Driver#

Flexio_a-format#

Error codes for the A_Format driver.

Values:

enumerator kStatus_FLEXIO_A_FORMAT_TxBusy: Transmitter is busy.

enumerator kStatus_FLEXIO_A_FORMAT_RxBusy: Receiver is busy.

enumerator kStatus_FLEXIO_A_FORMAT_TxIdle: Transmitter is idle.

enumerator kStatus_FLEXIO_A_FORMAT_RxIdle: Receiver is idle.

enumerator kStatus_FLEXIO_A_FORMAT_NotSyncCMD: This Command doesn’t support sync mode.

enumerator kStatus_FLEXIO_A_FORMAT_OutOfIDRange: A-format encoder ID is out of range.

enumerator kStatus_FLEXIO_A_FORMAT_RxRingBufferOverrun: A-format RX software ring buffer overrun.

enumerator kStatus_FLEXIO_A_FORMAT_RxHardwareOverrun: A-format RX receiver overrun.

enumerator kStatus_FLEXIO_A_FORMAT_FrameErr: Frame format error.

enumerator kStatus_FLEXIO_A_FORMAT_Timeout: A-format times out.

enumerator kStatus_FLEXIO_A_FORMAT_BaudrateNotSupport: Baudrate is not supported in current clock source

enum _flexio_a_format_encoder_status

Values:

enumerator kFLEXIO_A_FORMAT_ES_NoErr

enumerator kFLEXIO_A_FORMAT_ES_Busy_MemBusy

enumerator kFLEXIO_A_FORMAT_ES_Batt

enumerator kFLEXIO_A_FORMAT_ES_OvSpd_MemErr_OvTemp_OvFlow

enumerator kFLEXIO_A_FORMAT_ES_STErr_PSErr_MTErr_INCErr

enumerator kFLEXIO_A_FORMAT_ES_FrameErr

enumerator kFLEXIO_A_FORMAT_ES_Anyone

enum _flexio_a_format_baud_rate_bps

FlexIO A_FORMAT baud rate.

Values:

enumerator kFLEXIO_A_FORMAT_2_5MHZ: Baud rate is 2.5Mbps

enumerator kFLEXIO_A_FORMAT_4MHZ: Baud rate is 4Mbps

enumerator kFLEXIO_A_FORMAT_6_67MHZ: Baud rate is 6.67Mbps

enumerator kFLEXIO_A_FORMAT_8MHZ: Baud rate is 8Mbps

enumerator kFLEXIO_A_FORMAT_16MHZ: Baud rate is 16Mbps

enum _flexio_a_format_user_modes

FlexIO A_FORMAT user modes.

Values:

enumerator kFLEXIO_A_FORMAT_USERMODE_ONESHOT: User mode is oneshot

enumerator kFLEXIO_A_FORMAT_USERMODE_SYNC: User mode is sync

enum _flexio_a_format_interrupt_enable

Define FlexIO A-format interrupt mask.

Values:

enumerator kFLEXIO_A_FORMAT_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_A_FORMAT_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_a_format_status_flags

Define FlexIO A-format status mask.

Values:

enumerator kFLEXIO_A_FORMAT_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_A_FORMAT_RxDataRegFullFlag: Receive buffer full flag.

enumerator kFLEXIO_A_FORMAT_RxOverRunFlag: Receive buffer over run flag.

typedef enum _flexio_a_format_encoder_status flexio_a_format_es_t

typedef enum _flexio_a_format_baud_rate_bps flexio_a_format_baud_rate_bps_t: FlexIO A_FORMAT baud rate.

typedef enum _flexio_a_format_user_modes flexio_a_format_user_modes_t: FlexIO A_FORMAT user modes.

typedef struct _flexio_a_format_handle flexio_a_format_handle_t

typedef struct _flexio_a_format_type FLEXIO_A_FORMAT_Type: Define FlexIO A_FORMAT access structure typedef.

typedef struct _flexio_a_format_config flexio_a_format_config_t: Define FlexIO A_FORMAT user configuration structure.

typedef struct _flexio_a_format_transfer flexio_a_format_transfer_t: Define FlexIO A-format transfer structure.

typedef void (*flexio_a_format_transfer_callback_t)(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, status_t status, void *userData): FlexIO UART transfer callback function.

static inline void FLEXIO_A_Format_WriteHalfWord(FLEXIO_A_FORMAT_Type *base, const uint16_t *buffer)

Writes one half word of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_A_Format_ReadHalfWord(FLEXIO_A_FORMAT_Type *base, uint16_t *buffer)

Reads one half word of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
buffer – The buffer to store the received bytes.

void FLEXIO_A_Format_Config_DR_length(FLEXIO_A_FORMAT_Type *base, uint32_t nFrames)

The duration of the high level of the RS485 DR Pin is set according to the number of frames.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure
nFrames – The number of frames (Each 16bit of data is one frame)

status_t FLEXIO_A_Format_Init(FLEXIO_A_FORMAT_Type *base, const flexio_a_format_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO A-Format hardware, and configures the FlexIO A-Format with FlexIO A-Format configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_A_Format_GetDefaultConfig().

Example

FLEXIO_A_FORMAT_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_a_format_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_bps = 2500000
};
FLEXIO_A_Format_Init(&base, &config, srcClock_Hz);

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
userConfig – Pointer to the flexio_a_format_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Configuration success.
kStatus_FLEXIO_A_FORMAT_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_A_Format_Deinit(FLEXIO_A_FORMAT_Type *base)

Resets the FlexIO A-Format shifter and timer config.

note After calling this API, call the FLEXIO_A_Format_Init to use the FlexIO A_format module.

Parameters:

base – Pointer to FLEXIO_A_FORMAT_Type structure

void FLEXIO_A_Format_GetDefaultConfig(flexio_a_format_config_t *userConfig)

Gets the default configuration to configure the FlexIO A-format. The configuration can be used directly for calling the FLEXIO_A_Format_Init(). Example:

flexio_a_format_config_t config;
FLEXIO_A_Format_GetDefaultConfig(&userConfig);

param userConfig Pointer to the flexio_a_format_config_t structure.

void FLEXIO_A_Format_EnableInterrupts(FLEXIO_A_FORMAT_Type *base, uint32_t mask)

Enables the FlexIO A-format interrupt.

This function enables the FlexIO A-format interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Interrupt source.

void FLEXIO_A_Format_DisableInterrupts(FLEXIO_A_FORMAT_Type *base, uint32_t mask)

Disables the FlexIO A-format interrupt.

This function disables the FlexIO A-format interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Interrupt source.

uint32_t FLEXIO_A_Format_GetStatusFlags(FLEXIO_A_FORMAT_Type *base)

Gets the FlexIO A-format status flags.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.

Returns:

FlexIO A-format status flags.

void FLEXIO_A_Format_ClearStatusFlags(FLEXIO_A_FORMAT_Type *base, uint32_t mask)

Clears the FlexIO A-format status flags.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Status flag. The parameter can be any combination of the following values: arg kFLEXIO_A_FORMAT_TxDataRegEmptyFlag arg kFLEXIO_A_FORMAT_RxDataRegFullFlag arg kFLEXIO_A_FORMAT_RxOverRunFlag

status_t FLEXIO_A_Format_WriteBlocking(FLEXIO_A_FORMAT_Type *base, const uint16_t *txData, size_t txSize)

Sends a buffer of data bytes.

note This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_A_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_A_Format_ReadBlocking(FLEXIO_A_FORMAT_Type *base, uint16_t *rxData, size_t rxSize)

Receives a buffer of bytes.

note This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_A_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_A_Format_TransferCreateHandle(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_callback_t callback, void *userData)

Initializes the A-format handle.

This function initializes the FlexIO A-format handle, which can be used for other FlexIO A-format transactional APIs. Call this API once to get the initialized handle.

The A-format driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_A_Format_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as p ringBuffer.

Parameters:

base – to FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_A_Format_TransferStartRingBuffer(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, uint16_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific A-format handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the A_Format_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

note When using the RX ring buffer, one byte is reserved for internal use. In other words, if p ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_A_Format_TransferStopRingBuffer(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferSendNonBlocking(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO A-format driver calls the callback function and passes the ref kStatus_FLEXIO_A_FORMAT_TxIdle as status parameter.

note The kStatus_FLEXIO_A_FORMAT_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
xfer – FlexIO A-format transfer structure. See flexio_a_format_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_A_FORMAT_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_A_Format_TransferAbortSend(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainHalfwords to find out how many half-words are still not sent out.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferGetSendCount(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, size_t *count)

Gets the number of half-words sent.

This function gets the number of half-words sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
count – Number of half-words sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_A_Format_TransferReceiveNonBlocking(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_t *xfer, size_t *receivedHalfWords)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter p receivedHalfWords shows how many half-words are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the A-format driver. When new data arrives, the receive request is serviced first. When all data is received, the A-format driver notifies the upper layer through a callback function and passes the status parameter ref kStatus_A_FORMAT_RxIdle. For example, if the upper layer needs 10 half-words but there are only 5 half-words in the ring buffer, the 5 half-words are copied to xfer->data. This function returns with the parameter p receivedHalfWords set to 5. For the last 5 half-words, newly arrived data is saved from the xfer->data[5]. When 5 half-words are received, the A-format driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
xfer – A-format transfer structure. See flexio_a_format_transfer_t.
receivedHalfWords – Half-words received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_A_FORMAT_RxBusy – Previous receive request is not finished.

void FLEXIO_A_Format_TransferAbortReceive(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferGetReceiveCount(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, size_t *count)

Gets the number of half-words received.

This function gets the number of half-words received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
count – Number of half-words received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_A_Format_TransferHandleIRQ(void *uartType, void *uartHandle)

FlexIO A-format IRQ handler function.

This function processes the FlexIO A-format transmit and receives the IRQ request.

Parameters:

uartType – Pointer to the FLEXIO_A_FORMAT_Type structure.
uartHandle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

void FLEXIO_A_Format_FlushShifters(FLEXIO_A_FORMAT_Type *base)

brief Flush tx/rx shifters.

param base Pointer to the FLEXIO_A_FORMAT_Type structure.

A_FORMAT_SYNC_CODE_CMD: The command data frame sync code of A-format.

A_FORMAT_SYNC_CODE_IF: The encoder information field sync code of A-format.

A_FORMAT_FRAME_CODE_CDF: A-format CDF frame code.

A_FORMAT_FRAME_CODE_MDF0: A-format MDF frame code.

A_FORMAT_FRAME_CODE_MDF1

A_FORMAT_FRAME_CODE_MDF2

A_FORMAT_CDF(x): A-format command code.

A_FORMAT_REQ_IT_ABS_FULL_40BIT

brief Give the command code an alias

IT: Individual Transmission MT: Multiple Transmission

A_FORMAT_REQ_IT_ABS_LOWER_24BIT

A_FORMAT_REQ_IT_ABS_UPPER_24BIT

A_FORMAT_REQ_IT_ENCODER_STAT

A_FORMAT_REQ_MT_ABS_FULL_40BIT

A_FORMAT_REQ_MT_ABS_LOWER_24BIT

A_FORMAT_REQ_MT_ABS_UPPER_24BIT

A_FORMAT_REQ_MT_ENCODER_STAT

A_FORMAT_REQ_IT_CLEAR_STAT_FLAG

A_FORMAT_REQ_IT_CLEAR_MULTI_TURN

A_FORMAT_REQ_IT_CLEAR_STAT_MULTI

A_FORMAT_REQ_IT_SET_ENCODER_ADDR1

A_FORMAT_REQ_IT_PRESET_SINGLE_TURN_0

A_FORMAT_REQ_IT_MEMORY_READ

A_FORMAT_REQ_IT_MEMORY_WRITE

A_FORMAT_REQ_IT_TEMPERATURE_10BIT

A_FORMAT_REQ_IT_ID_CODE_READ1

A_FORMAT_REQ_IT_ID_CODE_READ2

A_FORMAT_REQ_IT_ID_CODE_WRITE1

A_FORMAT_REQ_IT_ID_CODE_WRITE2

A_FORMAT_REQ_IT_SET_ENCODER_ADDR2

A_FORMAT_REQ_IT_ABS_LOWER_17BIT

A_FORMAT_REQ_MT_ABS_LOWER_17BIT

A_FORMAT_REQ_IT_ABS_LOWER_24BIT_STAT

A_FORMAT_REQ_MT_ABS_LOWER_24BIT_STAT

A_FORMAT_REQ_IT_ABS_LOWER_24BIT_TEMP

A_FORMAT_REQ_MT_ABS_LOWER_24BIT_TEMP

A_FORMAT_CRC_POLY_COMMAND_DATA: The command data CRC polynomial of A-format.

A_FORMAT_CRC_POLY_ENCODER_DATA: The encoder data CRC polynomial of A-format.

A_FORMAT_CDF_MASK_SYNC_CODE: The mask of the CDF sync code.

A_FORMAT_CDF_MASK_FRAME_CODE: The mask of the CDF frame code.

A_FORMAT_CDF_MASK_ENCODER_ADDR: The mask of the CDF encoder address.

A_FORMAT_CDF_MASK_COMMAND_CODE: The mask of the CDF command code.

A_FORMAT_CDF_MASK_CRC_CODE: The mask of the CDF CRC code.

A_FORMAT_MDF_MASK_SYNC_CODE: The mask of the MDF sync code.

A_FORMAT_MDF_MASK_FRAME_CODE: The mask of the MDF frame code.

A_FORMAT_MDF_MASK_DATA_BIT: The mask of the MDF data bit.

A_FORMAT_MDF_MASK_CRC_CODE: The mask of the MDF CRC code.

A_FORMAT_IF_MASK_ENCODER_ADDR: The mask of the IF encoder address.

A_FORMAT_IF_MASK_COMMAND_CODE: The mask of the IF command code.

A_FORMAT_IF_MASK_ENCODER_STAT: The mask of the IF encoder status.

A_FORMAT_CDF_SHIFT_SYNC_CODE(x): Shift the sync code for command data frame.

A_FORMAT_CDF_SHIFT_FRAME_CODE(x): Shift the frame code for command data frame.

A_FORMAT_CDF_SHIFT_ENCODER_ADDR(x): Shift the encoder address for command data frame.

A_FORMAT_CDF_SHIFT_COMMAND_CODE(x): Shift the command code for command data frame.

A_FORMAT_CDF_SHIFT_CRC_CODE(x): Shift the CRC code for command data frame.

A_FORMAT_MDF_SHIFT_SYNC_CODE(x): Shift the sync code for memory data frame.

A_FORMAT_MDF_SHIFT_FRAME_CODE(x): Shift the frame code for memory data frame.

A_FORMAT_MDF_SHIFT_DATA_BIT(x): Shift the data bit for memory data frame.

A_FORMAT_MDF_SHIFT_CRC_CODE(x): Shift the CRC code for memory data frame.

A_FORMAT_PACK_CDF(EA, CC, CRC): Pack the command data frame.

A_FORMAT_PACK_MDF(FC, DA, CRC): Pack the memory data frame.

A_FORMAT_GET_ENC_ADDR_CDF(x): Get encoder address from the CDF frame.

A_FORMAT_GET_CMD_CODE_CDF(x): Get command code from the CDF frame.

A_FORMAT_CRC_RANGE_IN_CDF: The mask of CRC-applied range in CDF frame.

A_FORMAT_GET_CRC_DATA_CDF(x): Get CRC data from the CDF frame.

A_FORMAT_GET_CRC_CODE_CDF(x): Get CRC code from the CDF frame.

A_FORMAT_SET_CRC_CODE_CDF(cdf, crc): Set CRC code to the CDF frame.

A_FORMAT_CRC_RANGE_IN_MDF: The mask of CRC-applied range in MDF frame.

A_FORMAT_GET_CRC_DATA_MDF(x): Get CRC data from the MDF frame.

A_FORMAT_SET_CRC_CODE_MDF(mdf, crc): Set CRC code to the MDF frame.

A_FORMAT_GET_ENC_ADDR_IF(x): Get encoder address from the IF frame.

A_FORMAT_GET_CMD_CODE_IF(x): Get command code from the IF frame.

A_FORMAT_GET_ENC_STAT_IF(x): Get encoder status from the IF frame.

ENCODER_ADDRESS_IT(x)

ENCODER_ADDRESS_MT(x)

ENCODER_ADDRESS_IS_MT(x)

ENCODER_ADDRESS(x)

HALFWORD_NUM(x)

GET_TEMPERATURE_IS_BELOW_ZERO(x)

GET_TEMPERATURE_DATA(x)

GET_TEMPERATURE_VALUE(x)

GET_ENCODER_ID(x)

A_FORMAT_TIMER_TX_INDEX

A_FORMAT_TIMER_TX_CLOCK_INDEX

A_FORMAT_TIMER_RX_INDEX

A_FORMAT_TIMER_RX_CLOCK_INDEX

A_FORMAT_TIMER_DR_INDEX

FSL_FLEXIO_A_FORMAT_DRIVER_VERSION: FlexIO A_Format driver version.

A_FORMAT_RETRY_TIMES: Retry times for waiting flag.

A_FORMAT_ENCODER_MAX_NUM: Maximum number of encoders on an A-format bus.

A_FORMAT_BITS_PER_FRAME_DATA: The number of bits per frame without start and stop bits.

A_FORMAT_BITS_PER_FRAME_WHOLE: The number of bits per frame with start and stop bits.

A_FORMAT_TIMER_COMPARE_VALUE(cmp): Calculate the value of the FlexIO timer compare register.

FLEXIO_Type *flexioBase: FlexIO base pointer.

flexio_a_format_handle_t *hanlde

uint16_t timerDiv: srcClock_Hz / baudRate_bps

uint16_t TxDR_Offset: The offset between Tx and DR pins

uint16_t interval: Interval between frames

uint8_t TxPinIndex: Pin select for A_FORMAT_Tx.

uint8_t RxPinIndex: Pin select for A_FORMAT_Rx.

uint8_t DRPinIndex: Pin select for A_FORMAT_DR.

uint8_t shifterIndex[2]: Shifter index used in FlexIO A_FORMAT.

uint8_t timerIndex[5]: Timer index used in FlexIO A_FORMAT.

uint8_t triggerIn: Trigger signal for sync mode.

bool enableA_Format: Enable/disable FlexIO A_FORMAT TX & RX.

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_a_format_baud_rate_bps_t baudRate_bps: Baud rate in bps.

uint8_t userMode

uint16_t *data: The buffer of data to be transfer.

uint16_t *rxData: The buffer to receive data.

const uint16_t *txData: The buffer of data to be sent.

union _flexio_a_format_transfer

size_t dataSize: Transfer size

const uint16_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

uint16_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

uint16_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

flexio_a_format_transfer_callback_t callback: Callback function.

void *userData: A-format callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

struct _flexio_a_format_type: #include <fsl_flexio_a-format.h>

Define FlexIO A_FORMAT access structure typedef.

struct _flexio_a_format_config: #include <fsl_flexio_a-format.h>

Define FlexIO A_FORMAT user configuration structure.

struct _flexio_a_format_transfer: #include <fsl_flexio_a-format.h>

Define FlexIO A-format transfer structure.

struct _flexio_a_format_handle: #include <fsl_flexio_a-format.h>

Define FLEXIO A-format handle structure.

union __unnamed221__

Public Members

uint16_t *data: The buffer of data to be transfer.

uint16_t *rxData: The buffer to receive data.

const uint16_t *txData: The buffer of data to be sent.

FlexIO Driver#

void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)

Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().

Example:

flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);

Parameters:

userConfig – pointer to flexio_config_t structure

void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)

Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().

Example

flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);

Parameters:

base – FlexIO peripheral base address
userConfig – pointer to flexio_config_t structure

void FLEXIO_Deinit(FLEXIO_Type *base)

Gates the FlexIO clock. Call this API to stop the FlexIO clock.

Note

After calling this API, call the FLEXO_Init to use the FlexIO module.

Parameters:

base – FlexIO peripheral base address

uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)

Get instance number for FLEXIO module.

Parameters:

base – FLEXIO peripheral base address.

void FLEXIO_Reset(FLEXIO_Type *base)

Resets the FlexIO module.

Parameters:

base – FlexIO peripheral base address

static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)

Enables the FlexIO module operation.

Parameters:

base – FlexIO peripheral base address
enable – true to enable, false to disable.

static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)

Reads the input data on each of the FlexIO pins.

Parameters:

base – FlexIO peripheral base address

Returns:

FlexIO pin input data

static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)

Gets the current state pointer for state mode use.

Parameters:

base – FlexIO peripheral base address

Returns:

current State pointer

void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)

Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.

Example

flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Shifter index
shifterConfig – Pointer to flexio_shifter_config_t structure

void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)

Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.

Example

flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Timer index
timerConfig – Pointer to the flexio_timer_config_t structure

static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)

This function set the value of the prescaler on flexio channels.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
index – Timer index
clocksource – Set clock value

static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)

Gets the shifter status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter status flags

static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter status flags.

Note

For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)

Gets the shifter error flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter error flags

static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter error flags.

Note

For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)

Gets the timer status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Timer status flags

static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the timer status flags.

Note

For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)

Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.

Note

For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
enable – True to enable, false to disable.

uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)

Gets the shifter buffer address for the DMA transfer usage.

Parameters:

base – FlexIO peripheral base address
type – Shifter type of flexio_shifter_buffer_type_t
index – Shifter index

Returns:

Corresponding shifter buffer index

status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)

Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
handle – Pointer to the handler for FlexIO simulated peripheral.
isr – FlexIO simulated peripheral interrupt handler.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_UnregisterHandleIRQ(void *base)

Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 0.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 1.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple FLEXIO pins.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the FLEXIO pins to the logic 1 or 0.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
output – FLEXIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)

Enables the FLEXIO output pin function.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)

Reads the current input value of the FLEXIO pin.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)

Gets the FLEXIO input pin status.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input status

0: corresponding pin input capture no status.
1: corresponding pin input capture rising or falling edge.

static inline void FLEXIO_SetPinLevel(FLEXIO_Type *base, uint8_t pin, bool level)

Sets the FLEXIO output pin level.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.
level – FlexIO output pin level to set, can be either 0 or 1.

static inline bool FLEXIO_GetPinOverride(const FLEXIO_Type *const base, uint8_t pin)

Gets the enabled status of a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.

Return values:

FlexIO – port enabled status

0: corresponding output pin is in disabled state.
1: corresponding output pin is in enabled state.

static inline void FLEXIO_ConfigPinOverride(FLEXIO_Type *base, uint8_t pin, bool enabled)

Enables or disables a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – Flexio pin number.
enabled – Enable or disable the FlexIO pin.

static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)

Clears the multiple FLEXIO input pins status.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

FSL_FLEXIO_DRIVER_VERSION: FlexIO driver version.

enum _flexio_timer_trigger_polarity

Define time of timer trigger polarity.

Values:

enumerator kFLEXIO_TimerTriggerPolarityActiveHigh: Active high.

enumerator kFLEXIO_TimerTriggerPolarityActiveLow: Active low.

enum _flexio_timer_trigger_source

Define type of timer trigger source.

Values:

enumerator kFLEXIO_TimerTriggerSourceExternal: External trigger selected.

enumerator kFLEXIO_TimerTriggerSourceInternal: Internal trigger selected.

enum _flexio_pin_config

Define type of timer/shifter pin configuration.

Values:

enumerator kFLEXIO_PinConfigOutputDisabled: Pin output disabled.

enumerator kFLEXIO_PinConfigOpenDrainOrBidirection: Pin open drain or bidirectional output enable.

enumerator kFLEXIO_PinConfigBidirectionOutputData: Pin bidirectional output data.

enumerator kFLEXIO_PinConfigOutput: Pin output.

enum _flexio_pin_polarity

Definition of pin polarity.

Values:

enumerator kFLEXIO_PinActiveHigh: Active high.

enumerator kFLEXIO_PinActiveLow: Active low.

enum _flexio_timer_mode

Define type of timer work mode.

Values:

enumerator kFLEXIO_TimerModeDisabled: Timer Disabled.

enumerator kFLEXIO_TimerModeDual8BitBaudBit: Dual 8-bit counters baud/bit mode.

enumerator kFLEXIO_TimerModeDual8BitPWM: Dual 8-bit counters PWM mode.

enumerator kFLEXIO_TimerModeSingle16Bit: Single 16-bit counter mode.

enumerator kFLEXIO_TimerModeDual8BitPWMLow: Dual 8-bit counters PWM Low mode.

enum _flexio_timer_output

Define type of timer initial output or timer reset condition.

Values:

enumerator kFLEXIO_TimerOutputOneNotAffectedByReset: Logic one when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset: Logic zero when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputOneAffectedByReset: Logic one when enabled and on timer reset.

enumerator kFLEXIO_TimerOutputZeroAffectedByReset: Logic zero when enabled and on timer reset.

enum _flexio_timer_decrement_source

Define type of timer decrement.

Values:

enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput: Decrement counter on FlexIO clock, Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput: Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput: Decrement counter on Pin input (both edges), Shift clock equals Pin input.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput: Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

enum _flexio_timer_reset_condition

Define type of timer reset condition.

Values:

enumerator kFLEXIO_TimerResetNever: Timer never reset.

enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput: Timer reset on Timer Pin equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput: Timer reset on Timer Trigger equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge: Timer reset on Timer Pin rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge: Timer reset on Trigger rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge: Timer reset on Trigger rising or falling edge.

enum _flexio_timer_disable_condition

Define type of timer disable condition.

Values:

enumerator kFLEXIO_TimerDisableNever: Timer never disabled.

enumerator kFLEXIO_TimerDisableOnPreTimerDisable: Timer disabled on Timer N-1 disable.

enumerator kFLEXIO_TimerDisableOnTimerCompare: Timer disabled on Timer compare.

enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow: Timer disabled on Timer compare and Trigger Low.

enumerator kFLEXIO_TimerDisableOnPinBothEdge: Timer disabled on Pin rising or falling edge.

enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh: Timer disabled on Pin rising or falling edge provided Trigger is high.

enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge: Timer disabled on Trigger falling edge.

enum _flexio_timer_enable_condition

Define type of timer enable condition.

Values:

enumerator kFLEXIO_TimerEnabledAlways: Timer always enabled.

enumerator kFLEXIO_TimerEnableOnPrevTimerEnable: Timer enabled on Timer N-1 enable.

enumerator kFLEXIO_TimerEnableOnTriggerHigh: Timer enabled on Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh: Timer enabled on Trigger high and Pin high.

enumerator kFLEXIO_TimerEnableOnPinRisingEdge: Timer enabled on Pin rising edge.

enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh: Timer enabled on Pin rising edge and Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge: Timer enabled on Trigger rising edge.

enumerator kFLEXIO_TimerEnableOnTriggerBothEdge: Timer enabled on Trigger rising or falling edge.

enum _flexio_timer_stop_bit_condition

Define type of timer stop bit generate condition.

Values:

enumerator kFLEXIO_TimerStopBitDisabled: Stop bit disabled.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare: Stop bit is enabled on timer compare.

enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable: Stop bit is enabled on timer disable.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable: Stop bit is enabled on timer compare and timer disable.

enum _flexio_timer_start_bit_condition

Define type of timer start bit generate condition.

Values:

enumerator kFLEXIO_TimerStartBitDisabled: Start bit disabled.

enumerator kFLEXIO_TimerStartBitEnabled: Start bit enabled.

enum _flexio_timer_output_state

FlexIO as PWM channel output state.

Values:

enumerator kFLEXIO_PwmLow: The output state of PWM channel is low

enumerator kFLEXIO_PwmHigh: The output state of PWM channel is high

enum _flexio_shifter_timer_polarity

Define type of timer polarity for shifter control.

Values:

enumerator kFLEXIO_ShifterTimerPolarityOnPositive: Shift on positive edge of shift clock.

enumerator kFLEXIO_ShifterTimerPolarityOnNegitive: Shift on negative edge of shift clock.

enum _flexio_shifter_mode

Define type of shifter working mode.

Values:

enumerator kFLEXIO_ShifterDisabled: Shifter is disabled.

enumerator kFLEXIO_ShifterModeReceive: Receive mode.

enumerator kFLEXIO_ShifterModeTransmit: Transmit mode.

enumerator kFLEXIO_ShifterModeMatchStore: Match store mode.

enumerator kFLEXIO_ShifterModeMatchContinuous: Match continuous mode.

enumerator kFLEXIO_ShifterModeState: SHIFTBUF contents are used for storing programmable state attributes.

enumerator kFLEXIO_ShifterModeLogic: SHIFTBUF contents are used for implementing programmable logic look up table.

enum _flexio_shifter_input_source

Define type of shifter input source.

Values:

enumerator kFLEXIO_ShifterInputFromPin: Shifter input from pin.

enumerator kFLEXIO_ShifterInputFromNextShifterOutput: Shifter input from Shifter N+1.

enum _flexio_shifter_stop_bit

Define of STOP bit configuration.

Values:

enumerator kFLEXIO_ShifterStopBitDisable: Disable shifter stop bit.

enumerator kFLEXIO_ShifterStopBitLow: Set shifter stop bit to logic low level.

enumerator kFLEXIO_ShifterStopBitHigh: Set shifter stop bit to logic high level.

enum _flexio_shifter_start_bit

Define type of START bit configuration.

Values:

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable: Disable shifter start bit, transmitter loads data on enable.

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift: Disable shifter start bit, transmitter loads data on first shift.

enumerator kFLEXIO_ShifterStartBitLow: Set shifter start bit to logic low level.

enumerator kFLEXIO_ShifterStartBitHigh: Set shifter start bit to logic high level.

enum _flexio_shifter_buffer_type

Define FlexIO shifter buffer type.

Values:

enumerator kFLEXIO_ShifterBuffer: Shifter Buffer N Register.

enumerator kFLEXIO_ShifterBufferBitSwapped: Shifter Buffer N Bit Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferByteSwapped: Shifter Buffer N Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferBitByteSwapped: Shifter Buffer N Bit Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleByteSwapped: Shifter Buffer N Nibble Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferHalfWordSwapped: Shifter Buffer N Half Word Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleSwapped: Shifter Buffer N Nibble Swapped Register.

enum _flexio_gpio_direction

FLEXIO gpio direction definition.

Values:

enumerator kFLEXIO_DigitalInput: Set current pin as digital input

enumerator kFLEXIO_DigitalOutput: Set current pin as digital output

enum _flexio_pin_input_config

FLEXIO gpio input config.

Values:

enumerator kFLEXIO_InputInterruptDisabled: Interrupt request is disabled.

enumerator kFLEXIO_InputInterruptEnable: Interrupt request is enable.

enumerator kFLEXIO_FlagRisingEdgeEnable: Input pin flag on rising edge.

enumerator kFLEXIO_FlagFallingEdgeEnable: Input pin flag on falling edge.

typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t: Define time of timer trigger polarity.

typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t: Define type of timer trigger source.

typedef enum _flexio_pin_config flexio_pin_config_t: Define type of timer/shifter pin configuration.

typedef enum _flexio_pin_polarity flexio_pin_polarity_t: Definition of pin polarity.

typedef enum _flexio_timer_mode flexio_timer_mode_t: Define type of timer work mode.

typedef enum _flexio_timer_output flexio_timer_output_t: Define type of timer initial output or timer reset condition.

typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t: Define type of timer decrement.

typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t: Define type of timer reset condition.

typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t: Define type of timer disable condition.

typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t: Define type of timer enable condition.

typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t: Define type of timer stop bit generate condition.

typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t: Define type of timer start bit generate condition.

typedef enum _flexio_timer_output_state flexio_timer_output_state_t: FlexIO as PWM channel output state.

typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t: Define type of timer polarity for shifter control.

typedef enum _flexio_shifter_mode flexio_shifter_mode_t: Define type of shifter working mode.

typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t: Define type of shifter input source.

typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t: Define of STOP bit configuration.

typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t: Define type of START bit configuration.

typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t: Define FlexIO shifter buffer type.

typedef struct _flexio_config_ flexio_config_t: Define FlexIO user configuration structure.

typedef struct _flexio_timer_config flexio_timer_config_t: Define FlexIO timer configuration structure.

typedef struct _flexio_shifter_config flexio_shifter_config_t: Define FlexIO shifter configuration structure.

typedef enum _flexio_gpio_direction flexio_gpio_direction_t: FLEXIO gpio direction definition.

typedef enum _flexio_pin_input_config flexio_pin_input_config_t: FLEXIO gpio input config.

typedef struct _flexio_gpio_config flexio_gpio_config_t

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

typedef void (*flexio_isr_t)(void *base, void *handle): typedef for FlexIO simulated driver interrupt handler.

FLEXIO_Type *const s_flexioBases[]: Pointers to flexio bases for each instance.

const clock_ip_name_t s_flexioClocks[]: Pointers to flexio clocks for each instance.

void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)

Configure a FLEXIO pin used by the board.

To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
}
Define a digital output pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalOutput,
  0U,
  0U
}

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
config – FLEXIO pin configuration pointer.

FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x): Calculate FlexIO timer trigger.

FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)

FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)

struct _flexio_config_

#include <fsl_flexio.h>

Define FlexIO user configuration structure.

Public Members

bool enableFlexio: Enable/disable FlexIO module

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_timer_config

#include <fsl_flexio.h>

Define FlexIO timer configuration structure.

Public Members

uint32_t triggerSelect: The internal trigger selection number using MACROs.

flexio_timer_trigger_polarity_t triggerPolarity: Trigger Polarity.

flexio_timer_trigger_source_t triggerSource: Trigger Source, internal (see ‘trgsel’) or external.

flexio_pin_config_t pinConfig: Timer Pin Configuration.

uint32_t pinSelect: Timer Pin number Select.

flexio_pin_polarity_t pinPolarity: Timer Pin Polarity.

flexio_timer_mode_t timerMode: Timer work Mode.

flexio_timer_output_t timerOutput: Configures the initial state of the Timer Output and whether it is affected by the Timer reset.

flexio_timer_decrement_source_t timerDecrement: Configures the source of the Timer decrement and the source of the Shift clock.

flexio_timer_reset_condition_t timerReset: Configures the condition that causes the timer counter (and optionally the timer output) to be reset.

flexio_timer_disable_condition_t timerDisable: Configures the condition that causes the Timer to be disabled and stop decrementing.

flexio_timer_enable_condition_t timerEnable: Configures the condition that causes the Timer to be enabled and start decrementing.

flexio_timer_stop_bit_condition_t timerStop: Timer STOP Bit generation.

flexio_timer_start_bit_condition_t timerStart: Timer STRAT Bit generation.

uint32_t timerCompare: Value for Timer Compare N Register.

struct _flexio_shifter_config

#include <fsl_flexio.h>

Define FlexIO shifter configuration structure.

Public Members

uint32_t timerSelect: Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.

flexio_shifter_timer_polarity_t timerPolarity: Timer Polarity.

flexio_pin_config_t pinConfig: Shifter Pin Configuration.

uint32_t pinSelect: Shifter Pin number Select.

flexio_pin_polarity_t pinPolarity: Shifter Pin Polarity.

flexio_shifter_mode_t shifterMode: Configures the mode of the Shifter.

uint32_t parallelWidth: Configures the parallel width when using parallel mode.

flexio_shifter_input_source_t inputSource: Selects the input source for the shifter.

flexio_shifter_stop_bit_t shifterStop: Shifter STOP bit.

flexio_shifter_start_bit_t shifterStart: Shifter START bit.

struct _flexio_gpio_config

#include <fsl_flexio.h>

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

Public Members

flexio_gpio_direction_t pinDirection: FLEXIO pin direction, input or output

uint8_t outputLogic: Set a default output logic, which has no use in input

uint8_t inputConfig: Set an input config

FlexIO eDMA I2S Driver#

void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S eDMA handle.

This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S Rx eDMA handle.

This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S Tx audio format.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.

status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S transfer using DMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA send successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_TxBusy – FlexIO I2S is busy sending data.

status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S receive using eDMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA receive successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_RxBusy – FlexIO I2S is busy receiving data.

void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S transfer using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S receive using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Get the remaining bytes to be received.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes received.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION: FlexIO I2S EDMA driver version 2.1.9.

typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t

typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData): FlexIO I2S eDMA transfer callback function for finish and error.

struct _flexio_i2s_edma_handle

#include <fsl_flexio_i2s_edma.h>

FlexIO I2S DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle: DMA handler for FlexIO I2S send

uint8_t bytesPerFrame: Bytes in a frame

uint8_t nbytes: eDMA minor byte transfer count initially configured.

uint32_t state: Internal state for FlexIO I2S eDMA transfer

flexio_i2s_edma_callback_t callback: Callback for users while transfer finish or error occurred

void *userData: User callback parameter

edma_tcd_t tcd[(4U) + 1U]: TCD pool for eDMA transfer.

flexio_i2s_transfer_t queue[(4U)]: Transfer queue storing queued transfer.

size_t transferSize[(4U)]: Data bytes need to transfer

volatile uint8_t queueUser: Index for user to queue transfer.

volatile uint8_t queueDriver: Index for driver to get the transfer data and size

FlexIO eDMA SPI Driver#

status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI master eDMA handle.

This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.

status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI master eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI slave eDMA handle.

This function initializes the FlexIO SPI slave eDMA handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION: FlexIO SPI EDMA driver version.

typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t: typedef for flexio_spi_master_edma_handle_t in advance.

typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData): FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData): FlexIO SPI slave callback for finished transmit.

struct _flexio_spi_master_edma_handle

#include <fsl_flexio_spi_edma.h>

FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.

Public Members

size_t transferSize: Total bytes to be transferred.

uint8_t nbytes: eDMA minor byte transfer count initially configured.

bool txInProgress: Send transfer in progress

bool rxInProgress: Receive transfer in progress

edma_handle_t *txHandle: DMA handler for SPI send

edma_handle_t *rxHandle: DMA handler for SPI receive

flexio_spi_master_edma_transfer_callback_t callback: Callback for SPI DMA transfer

void *userData: User Data for SPI DMA callback

FlexIO eDMA UART Driver#

status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the UART handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_UART_Type.
handle – Pointer to flexio_uart_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.
txEdmaHandle – User requested DMA handle for TX DMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – UART handle pointer.
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.

status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_UART_RxBusy – Previous transfer on going.

void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the sent data which using eDMA.

This function aborts sent data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the receive data which using eDMA.

This function aborts the receive data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes sent out.

This function gets the number of bytes sent out.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

FSL_FLEXIO_UART_EDMA_DRIVER_VERSION: FlexIO UART EDMA driver version.

typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t

typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData): UART transfer callback function.

struct _flexio_uart_edma_handle

#include <fsl_flexio_uart_edma.h>

UART eDMA handle.

Public Members

flexio_uart_edma_transfer_callback_t callback: Callback function.

void *userData: UART callback function parameter.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

edma_handle_t *txEdmaHandle: The eDMA TX channel used.

edma_handle_t *rxEdmaHandle: The eDMA RX channel used.

uint8_t nbytes: eDMA minor byte transfer count initially configured.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

FlexIO I2C Master Driver#

status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)

Make sure the bus isn’t already pulled down.

Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure..

Return values:

kStatus_Success –
kStatus_FLEXIO_I2C_Busy –

status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.

Example

FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
masterConfig – Pointer to flexio_i2c_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Initialization successful
kStatus_InvalidArgument – The source clock exceed upper range limitation

void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)

De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().

Example:

flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);

Parameters:

masterConfig – Pointer to flexio_i2c_master_config_t structure.

static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)

Enables/disables the FlexIO module operation.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – Pass true to enable module, false does not have any effect.

uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)

Gets the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure

Returns:

Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.

void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)

Clears the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_I2C_RxFullFlag
- kFLEXIO_I2C_ReceiveNakFlag

void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Enables the FlexIO i2c master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source. Currently only one interrupt request source:
- kFLEXIO_I2C_TransferCompleteInterruptEnable

void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Disables the FlexIO I2C master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source.

void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the FlexIO I2C master transfer baudrate.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
baudRate_Bps – the baud rate value in HZ
srcClock_Hz – source clock in HZ

void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)

Sends START + 7-bit address to the bus.

Note

This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
address – 7-bit address.
direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:
- kFLEXIO_I2C_Write: Transmit
- kFLEXIO_I2C_Read: Receive

void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)

Sends the stop signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)

Sends the repeated start signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)

Sends the stop signal when transfer is still on-going.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)

Configures the sent ACK/NAK for the following byte.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – True to configure send ACK, false configure to send NAK.

status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)

Sets the number of bytes to be transferred from a start signal to a stop signal.

Note

Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
count – Number of bytes need to be transferred from a start signal to a re-start/stop signal

Return values:

kStatus_Success – Successfully configured the count.
kStatus_InvalidArgument – Input argument is invalid.

static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)

Writes one byte of data to the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
data – a byte of data.

static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)

Reads one byte of data from the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

Returns:

data byte read.

status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)

Sends a buffer of data in bytes.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
txBuff – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
rxBuff – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to receiving NAK.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.
xfer – pointer to flexio_i2c_master_transfer_t structure.

Returns:

status of status_t.

status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
callback – Pointer to user callback function.
userData – User param passed to the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.

status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
xfer – pointer to flexio_i2c_master_transfer_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.

status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)

Master interrupt handler.

Parameters:

i2cType – Pointer to FLEXIO_I2C_Type structure
i2cHandle – Pointer to flexio_i2c_master_transfer_t structure

FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION

FlexIO I2C transfer status.

Values:

enumerator kStatus_FLEXIO_I2C_Busy: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Idle: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Nak: NAK received during transfer.

enumerator kStatus_FLEXIO_I2C_Timeout: Timeout polling status flags.

enum _flexio_i2c_master_interrupt

Define FlexIO I2C master interrupt mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyInterruptEnable: Tx buffer empty interrupt enable.

enumerator kFLEXIO_I2C_RxFullInterruptEnable: Rx buffer full interrupt enable.

enum _flexio_i2c_master_status_flags

Define FlexIO I2C master status mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyFlag: Tx shifter empty flag.

enumerator kFLEXIO_I2C_RxFullFlag: Rx shifter full/Transfer complete flag.

enumerator kFLEXIO_I2C_ReceiveNakFlag: Receive NAK flag.

enum _flexio_i2c_direction

Direction of master transfer.

Values:

enumerator kFLEXIO_I2C_Write: Master send to slave.

enumerator kFLEXIO_I2C_Read: Master receive from slave.

typedef enum _flexio_i2c_direction flexio_i2c_direction_t: Direction of master transfer.

typedef struct _flexio_i2c_type FLEXIO_I2C_Type: Define FlexIO I2C master access structure typedef.

typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t: Define FlexIO I2C master user configuration structure.

typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t: Define FlexIO I2C master transfer structure.

typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t: FlexIO I2C master handle typedef.

typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData): FlexIO I2C master transfer callback typedef.

I2C_RETRY_TIMES: Retry times for waiting flag.

struct _flexio_i2c_type

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t SDAPinIndex: Pin select for I2C SDA.

uint8_t SCLPinIndex: Pin select for I2C SCL.

uint8_t shifterIndex[2]: Shifter index used in FlexIO I2C.

uint8_t timerIndex[3]: Timer index used in FlexIO I2C.

uint32_t baudrate: Master transfer baudrate, used to calculate delay time.

struct _flexio_i2c_master_config

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master user configuration structure.

Public Members

bool enableMaster: Enables the FlexIO I2C peripheral at initialization time.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

struct _flexio_i2c_master_transfer

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master transfer structure.

Public Members

uint32_t flags: Transfer flag which controls the transfer, reserved for FlexIO I2C.

uint8_t slaveAddress: 7-bit slave address.

flexio_i2c_direction_t direction: Transfer direction, read or write.

uint32_t subaddress: Sub address. Transferred MSB first.

uint8_t subaddressSize: Size of sub address.

uint8_t volatile *data: Transfer buffer.

volatile size_t dataSize: Transfer size.

struct _flexio_i2c_master_handle

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master handle structure.

Public Members

flexio_i2c_master_transfer_t transfer: FlexIO I2C master transfer copy.

size_t transferSize: Total bytes to be transferred.

uint8_t state: Transfer state maintained during transfer.

flexio_i2c_master_transfer_callback_t completionCallback: Callback function called at transfer event. Callback function called at transfer event.

void *userData: Callback parameter passed to callback function.

bool needRestart: Whether master needs to send re-start signal.

FlexIO I2S Driver#

void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)

Initializes the FlexIO I2S.

This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.

Parameters:

base – FlexIO I2S base pointer
config – FlexIO I2S configure structure.

void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)

Sets the FlexIO I2S configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().

Parameters:

config – pointer to master configuration structure

void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)

De-initializes the FlexIO I2S.

Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.

Parameters:

base – FlexIO I2S base pointer

static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S module operation.

Parameters:

base – Pointer to FLEXIO_I2S_Type
enable – True to enable, false dose not have any effect.

uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S status flags.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.

void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Enables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
mask – interrupt source

void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Disables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – pointer to FLEXIO_I2S_Type structure
mask – interrupt source

static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Tx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Rx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S send data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s send data register address.

static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S receive data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s receive data register address.

void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format in master mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – I2S master clock source frequency in Hz.

void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)

Configures the FlexIO I2S audio format in slave mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.

status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)

Sends data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
txData – Pointer to the data to be written.
size – Bytes to be written.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)

Writes data into a data register.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
data – Data to be written.

status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)

Receives a piece of data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
rxData – Pointer to the data to be read.
size – Bytes to be read.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)

Reads a data from the data register.

Parameters:

base – FlexIO I2S base pointer

Returns:

Data read from data register.

void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format.

Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – FlexIO I2S handle pointer.
format – Pointer to audio data format structure.
srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.

void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S receive handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.
kStatus_InvalidArgument – The input parameter is invalid.

status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data receive.
kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.

void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current send.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current receive.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be received.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes recieved.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

Returns:

count Bytes received.

void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)

Tx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure

void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)

Rx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure.

FSL_FLEXIO_I2S_DRIVER_VERSION: FlexIO I2S driver version 2.2.2.

FlexIO I2S transfer status.

Values:

enumerator kStatus_FLEXIO_I2S_Idle: FlexIO I2S is in idle state

enumerator kStatus_FLEXIO_I2S_TxBusy: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_RxBusy: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_Error: FlexIO I2S error occurred

enumerator kStatus_FLEXIO_I2S_QueueFull: FlexIO I2S transfer queue is full.

enumerator kStatus_FLEXIO_I2S_Timeout: FlexIO I2S timeout polling status flags.

enum _flexio_i2s_master_slave

Master or slave mode.

Values:

enumerator kFLEXIO_I2S_Master: Master mode

enumerator kFLEXIO_I2S_Slave: Slave mode

_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_I2S_RxDataRegFullFlag: Receive buffer full flag.

enum _flexio_i2s_sample_rate

Audio sample rate.

Values:

enumerator kFLEXIO_I2S_SampleRate8KHz: Sample rate 8000Hz

enumerator kFLEXIO_I2S_SampleRate11025Hz: Sample rate 11025Hz

enumerator kFLEXIO_I2S_SampleRate12KHz: Sample rate 12000Hz

enumerator kFLEXIO_I2S_SampleRate16KHz: Sample rate 16000Hz

enumerator kFLEXIO_I2S_SampleRate22050Hz: Sample rate 22050Hz

enumerator kFLEXIO_I2S_SampleRate24KHz: Sample rate 24000Hz

enumerator kFLEXIO_I2S_SampleRate32KHz: Sample rate 32000Hz

enumerator kFLEXIO_I2S_SampleRate44100Hz: Sample rate 44100Hz

enumerator kFLEXIO_I2S_SampleRate48KHz: Sample rate 48000Hz

enumerator kFLEXIO_I2S_SampleRate96KHz: Sample rate 96000Hz

enum _flexio_i2s_word_width

Audio word width.

Values:

enumerator kFLEXIO_I2S_WordWidth8bits: Audio data width 8 bits

enumerator kFLEXIO_I2S_WordWidth16bits: Audio data width 16 bits

enumerator kFLEXIO_I2S_WordWidth24bits: Audio data width 24 bits

enumerator kFLEXIO_I2S_WordWidth32bits: Audio data width 32 bits

typedef struct _flexio_i2s_type FLEXIO_I2S_Type: Define FlexIO I2S access structure typedef.

typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t: Master or slave mode.

typedef struct _flexio_i2s_config flexio_i2s_config_t: FlexIO I2S configure structure.

typedef struct _flexio_i2s_format flexio_i2s_format_t: FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t: Audio sample rate.

typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t: Audio word width.

typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t: Define FlexIO I2S transfer structure.

typedef struct _flexio_i2s_handle flexio_i2s_handle_t

typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData): FlexIO I2S xfer callback prototype.

I2S_RETRY_TIMES: Retry times for waiting flag.

FLEXIO_I2S_XFER_QUEUE_SIZE: FlexIO I2S transfer queue size, user can refine it according to use case.

struct _flexio_i2s_type

#include <fsl_flexio_i2s.h>

Define FlexIO I2S access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer

uint8_t txPinIndex: Tx data pin index in FlexIO pins

uint8_t rxPinIndex: Rx data pin index

uint8_t bclkPinIndex: Bit clock pin index

uint8_t fsPinIndex: Frame sync pin index

uint8_t txShifterIndex: Tx data shifter index

uint8_t rxShifterIndex: Rx data shifter index

uint8_t bclkTimerIndex: Bit clock timer index

uint8_t fsTimerIndex: Frame sync timer index

struct _flexio_i2s_config

#include <fsl_flexio_i2s.h>

FlexIO I2S configure structure.

Public Members

bool enableI2S: Enable FlexIO I2S

flexio_i2s_master_slave_t masterSlave: Master or slave

flexio_pin_polarity_t txPinPolarity: Tx data pin polarity, active high or low

flexio_pin_polarity_t rxPinPolarity: Rx data pin polarity

flexio_pin_polarity_t bclkPinPolarity: Bit clock pin polarity

flexio_pin_polarity_t fsPinPolarity: Frame sync pin polarity

flexio_shifter_timer_polarity_t txTimerPolarity: Tx data valid on bclk rising or falling edge

flexio_shifter_timer_polarity_t rxTimerPolarity: Rx data valid on bclk rising or falling edge

struct _flexio_i2s_format

#include <fsl_flexio_i2s.h>

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

Public Members

uint8_t bitWidth: Bit width of audio data, always 8/16/24/32 bits

uint32_t sampleRate_Hz: Sample rate of the audio data

struct _flexio_i2s_transfer

#include <fsl_flexio_i2s.h>

Define FlexIO I2S transfer structure.

Public Members

uint8_t *data: Data buffer start pointer

size_t dataSize: Bytes to be transferred.

struct _flexio_i2s_handle

#include <fsl_flexio_i2s.h>

Define FlexIO I2S handle structure.

Public Members

uint32_t state: Internal state

flexio_i2s_callback_t callback: Callback function called at transfer event

void *userData: Callback parameter passed to callback function

uint8_t bitWidth: Bit width for transfer, 8/16/24/32bits

flexio_i2s_transfer_t queue[(4U)]: Transfer queue storing queued transfer

size_t transferSize[(4U)]: Data bytes need to transfer

volatile uint8_t queueUser: Index for user to queue transfer

volatile uint8_t queueDriver: Index for driver to get the transfer data and size

FlexIO SPI Driver#

void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().

Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);

Note

1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
masterConfig – Pointer to the flexio_spi_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)

Resets the FlexIO SPI timer and shifter config.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:

flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

masterConfig – Pointer to the flexio_spi_master_config_t structure.

void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().

Note

1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)

Gates the FlexIO clock.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)

Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:

flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)

Gets FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

Returns:

status flag; Use the status flag to AND the following flag mask and get the status.

kFLEXIO_SPI_TxEmptyFlag
kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)

Clears FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – status flag The parameter can be any combination of the following values:
- kFLEXIO_SPI_TxEmptyFlag
- kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Enables the FlexIO SPI interrupt.

This function enables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source. The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Disables the FlexIO SPI interrupt.

This function disables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)

Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – SPI DMA source.
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI transmit data register address for MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI transmit data register address.

static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI receive data register address for the MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI receive data register address.

static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)

Enables/disables the FlexIO SPI module operation.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.
enable – True to enable, false does not have any effect.

void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)

Sets baud rate for the FlexIO SPI transfer, which is only used for the master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
baudRate_Bps – Baud Rate needed in Hz.
srcClockHz – SPI source clock frequency in Hz.

static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)

Writes one byte of data, which is sent using the MSB method.

Note

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
data – 8/16/32 bit data.

static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Reads 8 bit/16 bit data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

8 bit/16 bit data received.

status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The data bytes to send.
size – The number of data bytes to send.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The buffer to store the received bytes.
size – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – pointer to FLEXIO_SPI_Type structure
xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Master handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)

Master transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)

Aborts the master data transfer, which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI master IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Slave handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)

Slave transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
base – Pointer to the FLEXIO_SPI_Type structure.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)

Aborts the slave data transfer which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI slave IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

FSL_FLEXIO_SPI_DRIVER_VERSION: FlexIO SPI driver version.

Error codes for the FlexIO SPI driver.

Values:

enumerator kStatus_FLEXIO_SPI_Busy: FlexIO SPI is busy.

enumerator kStatus_FLEXIO_SPI_Idle: SPI is idle

enumerator kStatus_FLEXIO_SPI_Error: FlexIO SPI error.

enumerator kStatus_FLEXIO_SPI_Timeout: FlexIO SPI timeout polling status flags.

enum _flexio_spi_clock_phase

FlexIO SPI clock phase configuration.

Values:

enumerator kFLEXIO_SPI_ClockPhaseFirstEdge: First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kFLEXIO_SPI_ClockPhaseSecondEdge: First edge on SPSCK occurs at the start of the first cycle of a data transfer.

enum _flexio_spi_shift_direction

FlexIO SPI data shifter direction options.

Values:

enumerator kFLEXIO_SPI_MsbFirst: Data transfers start with most significant bit.

enumerator kFLEXIO_SPI_LsbFirst: Data transfers start with least significant bit.

enum _flexio_spi_data_bitcount_mode

FlexIO SPI data length mode options.

Values:

enumerator kFLEXIO_SPI_8BitMode: 8-bit data transmission mode.

enumerator kFLEXIO_SPI_16BitMode: 16-bit data transmission mode.

enumerator kFLEXIO_SPI_32BitMode: 32-bit data transmission mode.

enum _flexio_spi_interrupt_enable

Define FlexIO SPI interrupt mask.

Values:

enumerator kFLEXIO_SPI_TxEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_SPI_RxFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_spi_status_flags

Define FlexIO SPI status mask.

Values:

enumerator kFLEXIO_SPI_TxBufferEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_SPI_RxBufferFullFlag: Receive buffer full flag.

enum _flexio_spi_dma_enable

Define FlexIO SPI DMA mask.

Values:

enumerator kFLEXIO_SPI_TxDmaEnable: Tx DMA request source

enumerator kFLEXIO_SPI_RxDmaEnable: Rx DMA request source

enumerator kFLEXIO_SPI_DmaAllEnable: All DMA request source

enum _flexio_spi_transfer_flags

Define FlexIO SPI transfer flags.

Note

Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.

Values:

enumerator kFLEXIO_SPI_8bitMsb: FlexIO SPI 8-bit MSB first

enumerator kFLEXIO_SPI_8bitLsb: FlexIO SPI 8-bit LSB first

enumerator kFLEXIO_SPI_16bitMsb: FlexIO SPI 16-bit MSB first

enumerator kFLEXIO_SPI_16bitLsb: FlexIO SPI 16-bit LSB first

enumerator kFLEXIO_SPI_32bitMsb: FlexIO SPI 32-bit MSB first

enumerator kFLEXIO_SPI_32bitLsb: FlexIO SPI 32-bit LSB first

enumerator kFLEXIO_SPI_csContinuous: Enable the CS signal continuous mode

typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t: FlexIO SPI clock phase configuration.

typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t: FlexIO SPI data shifter direction options.

typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t: FlexIO SPI data length mode options.

typedef struct _flexio_spi_type FLEXIO_SPI_Type: Define FlexIO SPI access structure typedef.

typedef struct _flexio_spi_master_config flexio_spi_master_config_t: Define FlexIO SPI master configuration structure.

typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t: Define FlexIO SPI slave configuration structure.

typedef struct _flexio_spi_transfer flexio_spi_transfer_t: Define FlexIO SPI transfer structure.

typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t: typedef for flexio_spi_master_handle_t in advance.

typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData): FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData): FlexIO SPI slave callback for finished transmit.

FLEXIO_SPI_DUMMYDATA: FlexIO SPI dummy transfer data, the data is sent while txData is NULL.

SPI_RETRY_TIMES: Retry times for waiting flag.

FLEXIO_SPI_XFER_DATA_FORMAT(flag): Get the transfer data format of width and bit order.

struct _flexio_spi_type

#include <fsl_flexio_spi.h>

Define FlexIO SPI access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t SDOPinIndex: Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.

uint8_t SDIPinIndex: Pin select for data input.

uint8_t SCKPinIndex: Pin select for clock.

uint8_t CSnPinIndex: Pin select for enable.

uint8_t shifterIndex[2]: Shifter index used in FlexIO SPI.

uint8_t timerIndex[2]: Timer index used in FlexIO SPI.

struct _flexio_spi_master_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI master configuration structure.

Public Members

bool enableMaster: Enable/disable FlexIO SPI master after configuration.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

flexio_spi_clock_phase_t phase: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode: 8bit or 16bit mode.

struct _flexio_spi_slave_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI slave configuration structure.

Public Members

bool enableSlave: Enable/disable FlexIO SPI slave after configuration.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_spi_clock_phase_t phase: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode: 8bit or 16bit mode.

struct _flexio_spi_transfer

#include <fsl_flexio_spi.h>

Define FlexIO SPI transfer structure.

Public Members

const uint8_t *txData: Send buffer.

uint8_t *rxData: Receive buffer.

size_t dataSize: Transfer bytes.

uint8_t flags: FlexIO SPI control flag, MSB first or LSB first.

struct _flexio_spi_master_handle

#include <fsl_flexio_spi.h>

Define FlexIO SPI handle structure.

Public Members

const uint8_t *txData: Transfer buffer.

uint8_t *rxData: Receive buffer.

size_t transferSize: Total bytes to be transferred.

volatile size_t txRemainingBytes: Send data remaining in bytes.

volatile size_t rxRemainingBytes: Receive data remaining in bytes.

volatile uint32_t state: FlexIO SPI internal state.

uint8_t bytePerFrame: SPI mode, 2bytes or 1byte in a frame

flexio_spi_shift_direction_t direction: Shift direction.

flexio_spi_master_transfer_callback_t callback: FlexIO SPI callback.

void *userData: Callback parameter.

bool isCsContinuous: Is current transfer using CS continuous mode.

uint32_t timer1Cfg: TIMER1 TIMCFG regiser value backup.

Flexio_t-format#

Error codes for the T_Format driver.

Values:

enumerator kStatus_FLEXIO_T_FORMAT_EncErr0_CountingErr: Transmitter is busy.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr1_LogicOR: Encoder error: Logic-OR of Over-heat, Multi-turn error, Battery error and Battery alarm.

enumerator kStatus_FLEXIO_T_FORMAT_ComAlr0_ParityErr: Communication alarm: Parity error.

enumerator kStatus_FLEXIO_T_FORMAT_ComAlr1_DelimiterErr: Communication alarm: Delimiter error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OS: Over speed.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_FS: Full absolute status.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_CE: Countering error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OF: Countering overflow.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OH: Over heat.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_ME: Multi-turn error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_BE: Battery error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_BA: Battery alarm.

enumerator kStatus_FLEXIO_T_FORMAT_FrameErr: Frame format error.

enumerator kStatus_FLEXIO_T_FORMAT_BaudrateNotSupport

enumerator kStatus_FLEXIO_T_FORMAT_Timeout: T_FORMAT times out.

enumerator kStatus_FLEXIO_T_FORMAT_TxBusy: Transmitter is busy.

enumerator kStatus_FLEXIO_T_FORMAT_RxBusy: Receiver is busy.

enumerator kStatus_FLEXIO_T_FORMAT_TxIdle: Transmitter is idle.

enumerator kStatus_FLEXIO_T_FORMAT_RxIdle: Receiver is idle.

enumerator kStatus_FLEXIO_T_FORMAT_RxRingBufferOverrun: A-format RX software ring buffer overrun.

enumerator kStatus_FLEXIO_T_FORMAT_RxHardwareOverrun: A-format RX receiver overrun.

enum _flexio_t_format_interrupt_enable

Define FlexIO T-format interrupt mask.

Values:

enumerator kFLEXIO_T_FORMAT_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_T_FORMAT_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_t_format_flags

Values:

enumerator kFLEXIO_T_FORMAT_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_T_FORMAT_RxDataRegFullFlag: Receive buffer full flag.

enumerator kFLEXIO_T_FORMAT_RxOverRunFlag: Receive buffer over run flag.

enum _flexio_t_format_user_modes

FlexIO T_FORMAT user modes.

Values:

enumerator kFLEXIO_T_FORMAT_USERMODE_ONESHOT: User mode is oneshot

enumerator kFLEXIO_T_FORMAT_USERMODE_SYNC: User mode is sync

typedef enum _flexio_t_format_user_modes flexio_t_format_user_modes_t: FlexIO T_FORMAT user modes.

typedef struct _flexio_t_format_handle flexio_t_format_handle_t

typedef struct _flexio_t_format_type FLEXIO_T_FORMAT_Type: Define FlexIO T_FORMAT access structure typedef.

typedef struct _flexio_t_format_config flexio_t_format_config_t: Define FlexIO T_FORMAT user configuration structure.

typedef struct _flexio_t_format_transfer flexio_t_format_transfer_t: Define FlexIO T-format transfer structure.

typedef void (*flexio_t_format_transfer_callback_t)(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, status_t status, void *userData): FlexIO T-format transfer callback function.

static inline void FLEXIO_T_Format_WriteByte(FLEXIO_T_FORMAT_Type *base, const uint8_t *buffer)

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_T_Format_ReadByte(FLEXIO_T_FORMAT_Type *base, uint8_t *buffer)

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
buffer – The buffer to store the received bytes.

void FLEXIO_T_Format_Config_DR_length(FLEXIO_T_FORMAT_Type *base, uint32_t nFrames)

The duration of the high level of the RS485 DR Pin is set according to the number of frames.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure
nFrames – The number of frames (Each 8bit of data is one frame)

status_t FLEXIO_T_Format_Init(FLEXIO_T_FORMAT_Type *base, flexio_t_format_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO T-Format hardware, and configures the FlexIO T-Format with FlexIO T-Format configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_T_FORMAT_GetDefaultConfig().

Example

FLEXIO_T_FORMAT_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_t_format_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_bps = 2500000
};
FLEXIO_T_Format_Init(&base, &config);

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
userConfig – Pointer to the flexio_t_format_config_t structure.

Return values:

kStatus_Success – Configuration success.

void FLEXIO_T_Format_Deinit(FLEXIO_T_FORMAT_Type *base)

Resets the FlexIO T-Format shifter and timer config.

note After calling this API, call the FLEXIO_T_Format_Init to use the FlexIO T_format module.

Parameters:

base – Pointer to FLEXIO_T_FORMAT_Type structure

void FLEXIO_T_Format_GetDefaultConfig(flexio_t_format_config_t *userConfig)

Gets the default configuration to configure the FlexIO T-format. The configuration can be used directly for calling the FLEXIO_T_Format_Init(). Example:

flexio_t_format_config_t config;
FLEXIO_T_Format_GetDefaultConfig(&userConfig);

Parameters:

userConfig – Pointer to the flexio_t_format_config_t structure.

void FLEXIO_T_Format_EnableInterrupts(FLEXIO_T_FORMAT_Type *base, uint32_t mask)

Enables the FlexIO T-format interrupt.

This function enables the FlexIO T-format interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Interrupt source.

void FLEXIO_T_Format_DisableInterrupts(FLEXIO_T_FORMAT_Type *base, uint32_t mask)

Disables the FlexIO T-format interrupt.

This function disables the FlexIO T-format interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Interrupt source.

uint32_t FLEXIO_T_Format_GetStatusFlags(FLEXIO_T_FORMAT_Type *base)

Gets the FlexIO T-format status flags.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.

Returns:

FlexIO T-format status flags.

void FLEXIO_T_Format_ClearStatusFlags(FLEXIO_T_FORMAT_Type *base, uint32_t mask)

Clears the FlexIO T-format status flags.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Status flag. The parameter can be any combination of the following values: arg kFLEXIO_T_FORMAT_TxDataRegEmptyFlag arg kFLEXIO_T_FORMAT_RxDataRegFullFlag arg kFLEXIO_T_FORMAT_RxOverRunFlag

status_t FLEXIO_T_Format_WriteBlocking(FLEXIO_T_FORMAT_Type *base, const uint8_t *txData, size_t txSize)

Sends a buffer of data bytes.

note This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_T_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_T_Format_ReadBlocking(FLEXIO_T_FORMAT_Type *base, uint8_t *rxData, size_t rxSize)

Receives a buffer of bytes.

note This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_T_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_T_Format_TransferCreateHandle(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_callback_t callback, void *userData)

Initializes the T-format handle.

This function initializes the FlexIO T-format handle, which can be used for other FlexIO T-format transactional APIs. Call this API once to get the initialized handle.

The T-format driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_T_Format_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as p ringBuffer.

Parameters:

base – to FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_T_Format_TransferStartRingBuffer(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific T-format handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the T_Format_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

note When using the RX ring buffer, one byte is reserved for internal use. In other words, if p ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_T_Format_TransferStopRingBuffer(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferSendNonBlocking(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO T-format driver calls the callback function and passes the ref kStatus_FLEXIO_T_FORMAT_TxIdle as status parameter.

note The kStatus_FLEXIO_T_FORMAT_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
xfer – FlexIO T-format transfer structure. See flexio_t_format_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_T_FORMAT_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_T_Format_TransferAbortSend(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainHalfwords to find out how many half-words are still not sent out.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferGetSendCount(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, size_t *count)

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_T_Format_TransferReceiveNonBlocking(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter p receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the T-format driver. When new data arrives, the receive request is serviced first. When all data is received, the T-format driver notifies the upper layer through a callback function and passes the status parameter ref kStatus_T_FORMAT_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the T-format driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
xfer – T-format transfer structure. See flexio_t_format_transfer_t.
receivedBytes – bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_T_FORMAT_RxBusy – Previous receive request is not finished.

void FLEXIO_T_Format_TransferAbortReceive(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferGetReceiveCount(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_T_Format_SendSyncReq(FLEXIO_T_FORMAT_Type *base, const uint8_t cf)

FlexIO T-format IRQ handler function.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
cf – Sets commands to be sent in synchronous mode.

Returns:

kStatus_Success

T_FORMAT_SINK_CODE_CF: The Sink code of the control field of T-format.

T_FORMAT_CF_MASK_SINK_CODE: The mask of the CF sink code.

T_FORMAT_CF_MASK_DATA_ID_CODE: The mask of the CF data ID code.

T_FORMAT_CF_MASK_ID_PARITY: The mask of the CF ID parity.

T_FORMAT_CF_DATA_ID_CODE(x): Data ID code for the control field.

T_FORMAT_CF_ID_PARITY(x): ID parity for the control field.

T_FORMAT_DATA_ID(code, parity): The DATA ID Code of the T-format.

T_FORMAT_CF(DataID): The control field of T-format.

T_FORMAT_CF_GET_ABS: List of the control field value.

T_FORMAT_CF_GET_ABM

T_FORMAT_CF_GET_ENCID

T_FORMAT_CF_GET_ALL

T_FORMAT_CF_RESET_ALL_ERROR

T_FORMAT_CF_RESET_ABS

T_FORMAT_CF_RESET_ABM_ERROR

T_FORMAT_CF_EEPROM_WRITE

T_FORMAT_CF_EEPROM_READOUT

T_FORMAT_ALMC_MASK_OVER_SPEED: The mask bit of ALMC(Encoder error)

T_FORMAT_ALMC_MASK_FULL_ABSOLUTE_STATUS

T_FORMAT_ALMC_MASK_COUNTING_ERROR

T_FORMAT_ALMC_MASK_COUNTER_OVERFLOW

T_FORMAT_ALMC_MASK_OVERHEAT

T_FORMAT_ALMC_MASK_MULTITURN_ERROR

T_FORMAT_ALMC_MASK_BATTERY_ERROR

T_FORMAT_ALMC_MASK_BATTERY_ALARM

T_FORMAT_SF_MASK_ENCODER_ERROR: The mask of the SF encoder error.

T_FORMAT_SF_MASK_COMMUNICATION_ALARM: The mask of the SF communication alarm.

T_FORMAT_SF_GET_ENCODER_ERROR(x): Get the SF encoder error.

T_FORMAT_SF_GET_COMMUNICATION_ALARM(x): Get the SF communication alarm.

T_FORMAT_ADF_MASK_ADDRESS: The mask of the ADF address.

T_FORMAT_SF_MASK_BUSY_STATUS: The mask of the ADF busy status.

T_FORMAT_CRC_POLYNOMIAL: The CRC polynomial.

T_FORMAT_ABS_BYTE: The number of the byte in the received data.

T_FORMAT_ABM_BYTE

T_FORMAT_ENCODER_ID_BYTE

T_FORMAT_ALL_INFO_BYTE

T_FORMAT_EEPROM_BYTE

T_FORMAT_OVER_HEAT_NOT_CAUSE: Do not cause Over-heat.

T_FORMAT_OVER_HEAT_TEMPERATURE(x)

T_FORMAT_TIMER_TX_INDEX

T_FORMAT_TIMER_RX_INDEX

T_FORMAT_TIMER_DR_INDEX

FSL_FLEXIO_T_FORMAT_DRIVER_VERSION: FlexIO T_Format driver version.

T_FORMAT_RETRY_TIMES: Retry times for waiting flag.

T_FORMAT_ENCODER_MAX_NUM: Maximum number of encoders on an T-format bus.

T_FORMAT_BITS_PER_FRAME_DATA: The number of bits per frame without start and stop bits.

T_FORMAT_BITS_PER_FRAME_WHOLE: The number of bits per frame with start and stop bits.

T_FORMAT_TIMER_COMPARE_VALUE(cmp): Calculate the value of the FlexIO timer compare register.

FLEXIO_Type *flexioBase: FlexIO base pointer.

flexio_t_format_handle_t *hanlde

uint16_t timerDiv: srcClock_Hz / baudRate_bps

uint16_t TxDR_Offset: The offset between Tx and DR pins

uint16_t interval: Interval between frames

uint8_t TxPinIndex: Pin select for T_FORMAT_Tx.

uint8_t RxPinIndex: Pin select for T_FORMAT_Rx.

uint8_t DRPinIndex: Pin select for T_FORMAT_DR.

uint8_t shifterIndex[2]: Shifter index used in FlexIO T_FORMAT.

uint8_t timerIndex[3]: Timer index used in FlexIO T_FORMAT.

uint8_t triggerIn: Trigger signal for sync mode.

bool enableT_Format: Enable/disable FlexIO T_FORMAT TX & RX.

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint8_t userMode

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

union _flexio_t_format_transfer

size_t dataSize: Transfer size

const uint8_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

uint8_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

uint8_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

flexio_t_format_transfer_callback_t callback: Callback function.

void *userData: A-format callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

struct _flexio_t_format_type: #include <fsl_flexio_t-format.h>

Define FlexIO T_FORMAT access structure typedef.

struct _flexio_t_format_config: #include <fsl_flexio_t-format.h>

Define FlexIO T_FORMAT user configuration structure.

struct _flexio_t_format_transfer: #include <fsl_flexio_t-format.h>

Define FlexIO T-format transfer structure.

struct _flexio_t_format_handle: #include <fsl_flexio_t-format.h>

Define FLEXIO T-format handle structure.

union __unnamed229__

Public Members

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

FlexIO UART Driver#

status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().

Example

FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
userConfig – Pointer to the flexio_uart_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Configuration success.
kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)

Resets the FlexIO UART shifter and timer config.

Note

After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.

Parameters:

base – Pointer to FLEXIO_UART_Type structure

void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)

Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:

flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);

Parameters:

userConfig – Pointer to the flexio_uart_config_t structure.

uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART status flags.

void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_UART_TxDataRegEmptyFlag
- kFLEXIO_UART_RxEmptyFlag
- kFLEXIO_UART_RxOverRunFlag

void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Enables the FlexIO UART interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Disables the FlexIO UART interrupt.

This function disables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UARt transmit data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART transmit data register address.

static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UART receive data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART receive data register address.

static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART module operation.

Parameters:

base – Pointer to the FLEXIO_UART_Type.
enable – True to enable, false does not have any effect.

static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The buffer to store the received bytes.

status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)

Initializes the UART handle.

This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.

The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – to FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.

Note

The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – UART transfer structure. See flexio_uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.

void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)

FlexIO UART IRQ handler function.

This function processes the FlexIO UART transmit and receives the IRQ request.

Parameters:

uartType – Pointer to the FLEXIO_UART_Type structure.
uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

FSL_FLEXIO_UART_DRIVER_VERSION: FlexIO UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_FLEXIO_UART_TxBusy: Transmitter is busy.

enumerator kStatus_FLEXIO_UART_RxBusy: Receiver is busy.

enumerator kStatus_FLEXIO_UART_TxIdle: UART transmitter is idle.

enumerator kStatus_FLEXIO_UART_RxIdle: UART receiver is idle.

enumerator kStatus_FLEXIO_UART_ERROR: ERROR happens on UART.

enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun: UART RX software ring buffer overrun.

enumerator kStatus_FLEXIO_UART_RxHardwareOverrun: UART RX receiver overrun.

enumerator kStatus_FLEXIO_UART_Timeout: UART times out.

enumerator kStatus_FLEXIO_UART_BaudrateNotSupport: Baudrate is not supported in current clock source

enum _flexio_uart_bit_count_per_char

FlexIO UART bit count per char.

Values:

enumerator kFLEXIO_UART_7BitsPerChar: 7-bit data characters

enumerator kFLEXIO_UART_8BitsPerChar: 8-bit data characters

enumerator kFLEXIO_UART_9BitsPerChar: 9-bit data characters

enum _flexio_uart_interrupt_enable

Define FlexIO UART interrupt mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_uart_status_flags

Define FlexIO UART status mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_UART_RxDataRegFullFlag: Receive buffer full flag.

enumerator kFLEXIO_UART_RxOverRunFlag: Receive buffer over run flag.

typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t: FlexIO UART bit count per char.

typedef struct _flexio_uart_type FLEXIO_UART_Type: Define FlexIO UART access structure typedef.

typedef struct _flexio_uart_config flexio_uart_config_t: Define FlexIO UART user configuration structure.

typedef struct _flexio_uart_transfer flexio_uart_transfer_t: Define FlexIO UART transfer structure.

typedef struct _flexio_uart_handle flexio_uart_handle_t

typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData): FlexIO UART transfer callback function.

UART_RETRY_TIMES: Retry times for waiting flag.

struct _flexio_uart_type

#include <fsl_flexio_uart.h>

Define FlexIO UART access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t TxPinIndex: Pin select for UART_Tx.

uint8_t RxPinIndex: Pin select for UART_Rx.

uint8_t shifterIndex[2]: Shifter index used in FlexIO UART.

uint8_t timerIndex[2]: Timer index used in FlexIO UART.

struct _flexio_uart_config

#include <fsl_flexio_uart.h>

Define FlexIO UART user configuration structure.

Public Members

bool enableUart: Enable/disable FlexIO UART TX & RX.

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

flexio_uart_bit_count_per_char_t bitCountPerChar: number of bits, 7/8/9 -bit

struct _flexio_uart_transfer

#include <fsl_flexio_uart.h>

Define FlexIO UART transfer structure.

Public Members

size_t dataSize: Transfer size

struct _flexio_uart_handle

#include <fsl_flexio_uart.h>

Define FLEXIO UART handle structure.

Public Members

const uint8_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

uint8_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

uint8_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

flexio_uart_transfer_callback_t callback: Callback function.

void *userData: UART callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

union __unnamed232__

Public Members

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

FlexPWM: Enhanced Flex Pulse Width Modulator#

void FLEXPWM_GetDefaultSubmoduleConfig(flexpwm_submodule_config_t *config)

Get default configuration for FlexPWM submodule.

This function initializes the FlexPWM submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigSubmodule().

Default values:

Clock source: IPBus clock (kFLEXPWM_ClockSource_IPBusClock)
Prescaler: Divide by 1 (no prescaling)
Counter initial value: 0
Counter modulo value: 0xFFFF (maximum range)
Initialization source: Local sync
Load mode: Opportunity (load at PWM reload opportunity)
Load frequency: 0 (every PWM cycle)
Half-cycle reload: Disabled
Full-cycle reload: Enabled
Reload source: Local reload
Half-cycle value: 0
Debug mode: Disabled (PWM stops in Debug mode)
Wait mode: Disabled (PWM stops in Wait mode)

Parameters:

config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_submodule_config_t *config)

Configure a FlexPWM submodule.

This function configures the basic parameters of a FlexPWM submodule, including:

Clock source and prescaler (CTRL2[CLK_SEL], CTRL[PRSC])
Counter initialization and modulo values (INIT, VAL1)
Counter initialization source (CTRL2[INIT_SEL])
Register reload mode, frequency, and timing (CTRL[LDMOD, LDFQ, HALF, FULL], CTRL2[RELOAD_SEL])
Half-cycle reload point (VAL0)
Debug and Wait mode behavior (CTRL2[DBGEN, WAITEN])

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration write behavior:

This function writes configuration values to buffered registers.
The configuration does NOT take effect immediately.
After calling this function, you must set MCTRL[LDOK] bit using a separate function to transfer buffered register values to active registers.
The actual transfer timing depends on the configured reload mode and reload opportunities.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Start the PWM counter (use a separate start API)
Configure PWM waveform parameters (VAL2-VAL5, deadtime, polarity, etc.)
Configure fault protection or capture functionality
Configure FORCE_OUT behavior (use FLEXPWM_ConfigForceOut)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigPWM(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_config_t *config)

Configure PWM output for a FlexPWM submodule.

This function configures the PWM output parameters for a FlexPWM submodule, including:

Compare values (VAL2, VAL3, VAL4, VAL5)
Output polarity (POLA, POLB)
Initial values (PWM23_INIT, PWM45_INIT)
Operating mode: independent or complementary (INDEP)
Complementary mode source selection (MCTRL[IPOL]) - only in complementary mode

Note

For complementary mode (complementary = true):

Only the selected channel compare values (pwma if ipolSource=kFLEXPWM_IPOL_PWM23, or pwmb if ipolSource=kFLEXPWM_IPOL_PWM45) needs to be configured.
But polarity still needs to be set for the complementary output to work correctly.
The unselected channel will be ignored by the hardware.
MCTRL[IPOL] will be set according to ipolSource parameter.

Note

For independent mode (complementary = false):

Both pwma and pwmb must be fully configured.
INDEP bit will be set to 1 in SMxCTRL2.
MCTRL[IPOL] is ignored by the hardware in this mode.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Trigger FORCE_OUT events (in complementary mode, MCTRL[IPOL] requires FORCE_OUT to take effect)
Enable PWM_A Output or PWM_B Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the PWM configuration structure.

void FLEXPWM_ConfigPWMChannelX(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_channel_config_t *pwmx)

Configure PWM_X output for a FlexPWM submodule.

This function configures the PWM_X output parameters for a FlexPWM submodule, including:

Compare values (VAL0, VAL1)
Output polarity (POLX)
Initial values (PWMX_INIT)

Note

When submodule works in local sync mode, PWM_X polarity is inverted, because VAL1 determines both counter modulo and PWM_X turn-off edge. VAL0 determines PWM_X turn-on edge. Recommend setting submodule counter works in master sync mode if you want to use the PWM_X output, then both VAL0 and VAL1 can be used to control PWM_X waveform shape and polarity is normal.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Enable PWM_X Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
pwmx – Pointer to the PWM_X configuration structure.

void FLEXPWM_GetDefaultForceOutConfig(flexpwm_force_out_config_t *config)

Get default configuration for force output.

This function initializes the force output configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigForceOut().

Default values:

FORCE_OUT trigger source: Local software force (kFLEXPWM_ForceOutputSource_LocalForce)
Counter initialization on FORCE_OUT: Disabled (false)
PWM_A source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_A software value: Logic 0 (false)
PWM_B source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_B software value: Logic 0 (false)

Parameters:

config – Pointer to the force output configuration structure.

void FLEXPWM_ConfigForceOut(PWM_Type *base, uint8_t submodule, const flexpwm_force_out_config_t *config)

Configure FORCE_OUT for a FlexPWM submodule.

This function configures the FORCE_OUT event parameters for a FlexPWM submodule, including:

FORCE_OUT trigger source (CTRL2[FORCE_SEL]): software, master, external, sync signals, etc.
Counter initialization triggered by FORCE_OUT (CTRL2[FRCEN])
PWM source selection for deadtime logic (DTSRCSEL[SMxSEL23/45]): generated, inverted, software-controlled, or external signals
Software-controlled output values (SWCOUT[SMxOUT23/45]) when source is software-controlled

Note

Configuration write behavior:

This function performs read-modify-write operations on global registers (DTSRCSEL, SWCOUT) to protect other submodules’ configurations.
Register writes are immediate and take effect when the corresponding FORCE_OUT event occurs.
SWCOUT and DTSRCSEL are NOT affected by MCTRL[LDOK]; they are independent double-buffered registers that update on FORCE_OUT events.

Note

FORCE_OUT event effects: When a FORCE_OUT event occurs, the following updated values take effect simultaneously:

PWM source routing from DTSRCSEL
Software-controlled output values from SWCOUT
Counter may be reinitialized if FRCEN is enabled

Note

This function does NOT:

Trigger FORCE_OUT events (DTSRCSEL and SWCOUT settings require FORCE_OUT event to take effect)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the force output configuration structure.

void FLEXPWM_GetDefaultFaultConfig(flexpwm_fault_config_t *config)

Get default configuration for fault protection.

This function initializes the fault protection configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultProtection().

Default values:

Fault Input Active Level (faultInputActiveLevel): Active high (true)
Fault Clearing Mode (faultClearingMode): Automatic fault clearing
Safety Mode (enableSafetyMode): Enabled (safe mode)
Full Cycle Recovery (enableFullCycleRecovery): Enabled
Half Cycle Recovery (enableHalfCycleRecovery): Disabled
Combinational Path (enableCombinatorialPath): Enabled (allow combinational path for fastest response)

Parameters:

config – Pointer to the fault protection configuration structure.

void FLEXPWM_GetDefaultFaultSubmoduleConfig(flexpwm_fault_submodule_config_t *config)

Get default configuration for fault submodule protection.

This function initializes the fault submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultSubmodule().

Default values:

Disable Mask: All faults (0x0F) affect each output
Output Behavior: High-Z (high impedance) for all outputs

For single-channel platforms: disableMask_ch0 = 0x0F For dual-channel platforms: disableMask_ch0 = 0x0F, disableMask_ch1 = 0x0F

Parameters:

config – Pointer to the fault submodule configuration structure.

void FLEXPWM_GetDefaultFaultFilterConfig(flexpwm_fault_filter_config_t *config)

Get default configuration for fault filter.

This function initializes the fault filter configuration structure with safe default values. The default configuration provides moderate debouncing suitable for typical applications.

Default values:

Filter Period (FILT_PER): 0x08 (8 IPBus clock cycles)
Filter Count (FILT_CNT): 0x04 (7 consecutive samples = 4+3)
Glitch Stretching (GSTR): Enabled

Effective debounce window: ~56 IPBus clock cycles

Parameters:

config – Pointer to the fault filter configuration structure.

void FLEXPWM_ConfigFaultProtection(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_config_t *config, uint16_t faultMask)

Configure fault protection for a FlexPWM fault channel.

This function configures global fault protection parameters for one fault channel, including fault input active level, clearing mode, safety mode, and fault recovery timing.

Configuration details:

Fault input active level (faultInputActiveLevel): Selects whether fault is triggered by high or low
Fault clearing mode (faultClearingMode): Controls how and when PWM outputs are re-enabled
Safety mode (enableSafetyMode): Adds extra requirement that fault input be de-asserted before re-enable
Fault recovery timing (enableFullCycleRecovery, enableHalfCycleRecovery): Specifies during which PWM cycle phase outputs re-enable
Combinational path (enableCombinatorialPath): Trades off response speed vs. latency

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (all submodules that reference it). For platforms with dual fault channels, call this function separately for each channel.

Note

For platforms with dual fault channels:

faultChannel 0: Configures FAULT0-3 (FCTRL/FSTS/FFILT at offset 0x18C)
faultChannel 1: Configures FAULT4-7 (FCTRL/FSTS/FFILT at offset 0x198)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault protection configuration structure.
faultMask – Fault input selection mask for the channel. Each bit corresponds to one fault input:
- bit[0] = FAULT0 (or FAULT4 for channel 1)
- bit[1] = FAULT1 (or FAULT5 for channel 1)
- bit[2] = FAULT2 (or FAULT6 for channel 1)
- bit[3] = FAULT3 (or FAULT7 for channel 1) Example: 0x05 = configure FAULT0 and FAULT2 with the same settings. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults: (kFLEXPWM_FaultMask_0 | kFLEXPWM_FaultMask_2) = 0x05.

void FLEXPWM_ConfigFaultSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_fault_submodule_config_t *config)

Configure fault submodule protection for a FlexPWM submodule.

This function configures fault-to-PWM-output mapping and output behavior for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a single submodule. Each output can independently select which faults affect it and how it responds during a fault.

Configuration per output:

Disable Mask: Selects which fault inputs can disable this output
- disableMask_ch0: Bits [0-3] for FAULT0-3
- disableMask_ch1: Bits [0-3] for FAULT4-7 (dual-channel platforms only)
Output Behavior: Specifies pin state during fault (Force 0, Force 1, or High-Z)

Note

Configuration applies to SMxDISMAP and SMxOCTRL registers. These registers are not affected by LDOK or FORCE_OUT; configuration takes effect immediately upon register write.

Note

For dual-channel platforms, specify disableMask_ch0 and disableMask_ch1 to control which faults (from either channel) can disable each output.

Note

For single-channel platforms, only disableMask_ch0 is used; disableMask_ch1 is conditionally compiled out.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the fault submodule configuration structure.

void FLEXPWM_ConfigFaultFilter(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_filter_config_t *config)

Configure fault filter for a FlexPWM fault channel.

This function configures the input filter for fault protection pins, including sampling period, sample count requirement, and glitch stretching logic.

The filter helps reject electrical noise and false fault triggers by requiring the FAULTx signal to be stable for N consecutive samples before a fault is reported. With GSTR enabled, narrow fault glitches (< 2 IPBus cycles) are automatically stretched.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (FFILT register). For platforms with dual fault channels, call this function separately for each channel.

Note

Filter delay calculation:

Without GSTR: delay = FILT_PER * (FILT_CNT + 3) IPBus cycles
With GSTR: may be reduced due to glitch stretching logic

Note

To disable filtering:

Set filterPeriod = 0 (sampling disabled, filter bypassed)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault filter configuration structure.

void FLEXPWM_GetDefaultOutputTriggerConfig(flexpwm_output_trigger_config_t *config)

Get default configuration for output trigger.

This function initializes the output trigger configuration structure with safe default values:

outTriggerEnable: 0 (all triggers disabled)
triggerFrequency: kFLEXPWM_TriggerFrequency_EveryCycle (trigger every PWM cycle)
muxTrig0Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG0)
muxTrig1Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG1)
stretchPrescaler: kFLEXPWM_StretchPrescaler_None (no prescaling, if supported)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigOutputTrigger().

void FLEXPWM_ConfigOutputTrigger(PWM_Type *base, uint8_t submodule, const flexpwm_output_trigger_config_t *config)

Configure output trigger for a FlexPWM submodule.

This function configures the output trigger parameters for a FlexPWM submodule, including:

Trigger source mapping from VAL0-5 register matches (SMxTCTRL[OUT_TRIG_EN])
Trigger output frequency control (SMxTCTRL[TRGFRQ])
PWM_MUX_TRIG0 port source selection (SMxTCTRL[PWAOT0])
PWM_MUX_TRIG1 port source selection (SMxTCTRL[PWBOT1])

The output trigger mechanism allows PWM events (counter matches with VAL registers) to trigger external modules such as ADC, DMA, or other peripherals for synchronized operation.

Note

Trigger source mapping:

VAL0, VAL2, VAL4 matches generate PWM_OUT_TRIG0
VAL1, VAL3, VAL5 matches generate PWM_OUT_TRIG1 Multiple sources can be enabled simultaneously (OR logic).

Note

Trigger frequency control (TRGFRQ): This setting only takes effect when CTRL[LDFQ] is non-zero (reload frequency divider active).

false: Trigger outputs every PWM cycle regardless of reload occurrence
true: Trigger outputs only on the last PWM cycle before a reload opportunity

Note

Port routing: PWM_MUX_TRIG0/1 ports can be routed to either:

Generated trigger signals (PWM_OUT_TRIG0/1) from VAL register matches
Direct PWM outputs (PWM_A/PWM_B) for waveform monitoring Both ports are independently configurable.

Note

Configuration takes effect immediately upon register write. This function does NOT require setting MCTRL[LDOK].

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the output trigger configuration structure.

void FLEXPWM_GetDefaultInputCaptureConfig(flexpwm_input_capture_config_t *config)

Get default configuration for input capture.

This function initializes the input capture configuration structure with safe default values. The default values are:

All channels (A/B/X):
- edge0 = kFLEXPWM_CaptureEdge_Disabled
- edge1 = kFLEXPWM_CaptureEdge_Disabled
- oneshot = false (free running mode)
- inputSelect = kFLEXPWM_CaptureInput_RawSignal
- edgeCompareValue = 0
- fifoWatermark = kFLEXPWM_CaptureFifoWatermark_1

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCapture().

Parameters:

config – Pointer to the input capture configuration structure.

void FLEXPWM_GetDefaultCaptureFilterConfig(flexpwm_capture_filter_config_t *config)

Get default configuration for capture filter.

This function initializes the capture filter configuration structure with safe default values. The default values are:

All channels (A/B/X):
- filterPeriod = 0 (filter bypassed, sampling disabled)
- filterCount = 0 (requires 3 consecutive samples)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCaptureFilter().

Parameters:

config – Pointer to the capture filter configuration structure.

void FLEXPWM_ConfigInputCapture(PWM_Type *base, uint8_t submodule, const flexpwm_input_capture_config_t *config)

Configure input capture for a FlexPWM submodule.

This function configures the input capture parameters for up to three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule, including:

Edge detection configuration for two edge detectors per channel (SMxCAPTCTRLA/B/X[EDGx0/1])
One-shot or free-running mode (SMxCAPTCTRLA/B/X[ONESHOTx])
Input source selection: raw signal or edge counter output (SMxCAPTCTRLA/B/X[INP_SELx])
Edge counter compare value (SMxCAPTCOMPA/B/X[EDGCMPx])
FIFO watermark level (SMxCAPTCTRLA/B/X[CFxWM])

Note

Edge counter behavior:

When inputSelect = kFLEXPWM_CaptureInput_EdgeCounter, the edge counter is automatically enabled (EDGCNTx_EN = 1) by this function.
When inputSelect = kFLEXPWM_CaptureInput_RawSignal, the edge counter remains disabled.

Note

Capture enable control:

This function does NOT control the capture enable bits (ARMA/ARMB/ARMX).
After calling this function, use a separate enable API to start capture operation.

Note

CVAL register mapping (NON-INTUITIVE):

Capture_X: Edge0 -> CVAL0, Edge1 -> CVAL1
Capture_A: Edge0 -> CVAL2, Edge1 -> CVAL3
Capture_B: Edge0 -> CVAL4, Edge1 -> CVAL5

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the input capture configuration structure.

void FLEXPWM_ConfigInputCaptureFilter(PWM_Type *base, uint8_t submodule, const flexpwm_capture_filter_config_t *config)

Configure input capture filter for a FlexPWM submodule.

This function configures the digital filter parameters for the three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule. The filter settings include:

Filter sampling period (SMxCAPTFILTA/B/X[CAPTx_FILT_PER])
Number of consecutive samples required (SMxCAPTFILTA/B/X[CAPTx_FILT_CNT])

The digital filter can eliminate glitches and noise on the capture input signals.

Note

Filter bypassing:

Set filterPeriod = 0 to bypass the filter (no sampling, filter disabled).

Note

Filter delay calculation:

Delay = filterPeriod * (filterCount + 3) IPBus clock cycles
Example: filterPeriod=5, filterCount=2 -> delay = 5*(2+3) = 25 cycles

Note

Hardware behavior:

This function always writes 0 to the filter register first, then writes the configuration value. This ensures correct behavior per hardware requirements.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the capture filter configuration structure.

uint16_t FLEXPWM_GetInputCaptureValue(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)

Read captured value from a FlexPWM capture channel.

This function reads the captured counter value from one of the six capture value registers (CVAL0-5) for the specified capture channel and edge detector.

Note

CVAL register mapping (NON-INTUITIVE):

kFLEXPWM_Capture_X_Edge0 -> CVAL0
kFLEXPWM_Capture_X_Edge1 -> CVAL1
kFLEXPWM_Capture_A_Edge0 -> CVAL2
kFLEXPWM_Capture_A_Edge1 -> CVAL3
kFLEXPWM_Capture_B_Edge0 -> CVAL4
kFLEXPWM_Capture_B_Edge1 -> CVAL5

Warning

Destructive read:

Reading a CVAL register decrements the FIFO count by 1.
If the FIFO is empty, the read value is undefined.
Check the FIFO empty flag (CFx) before reading to avoid invalid data.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured counter value (16-bit).

uint16_t FLEXPWM_GetInputCaptureCycle(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)

Read captured cycle counter value from a FlexPWM capture channel.

This function reads the captured cycle counter value from one of the six capture cycle registers (CCYC0-5) for the specified capture channel and edge detector. The cycle counter value represents the upper part of the extended timestamp when a capture event occurs.

Note

CCYC register mapping (matches CVAL mapping):

kFLEXPWM_Capture_X_Edge0 -> CCYC0
kFLEXPWM_Capture_X_Edge1 -> CCYC1
kFLEXPWM_Capture_A_Edge0 -> CCYC2
kFLEXPWM_Capture_A_Edge1 -> CCYC3
kFLEXPWM_Capture_B_Edge0 -> CCYC4
kFLEXPWM_Capture_B_Edge1 -> CCYC5

Note

Combined timestamp:

The full timestamp is {CCYC, CVAL} (cycle counter as upper 16 bits, capture value as lower 16 bits), forming a 32-bit extended timestamp.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured cycle counter value (16-bit).

void FLEXPWM_EnableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)

Enable input capture for a FlexPWM capture channel.

This function enables input capture operation for the specified capture channel by setting the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

ARM bit behavior in one-shot mode: When the capture channel is configured for one-shot mode (ONESHOT = 1), the ARM bit automatically clears after two capture events complete.

Note

Prerequisites: Before enabling capture, ensure:

Capture channel is configured (FLEXPWM_ConfigInputCapture)
Edge detectors are configured (EDGA0/EDGA1, EDGB0/EDGB1, or EDGX0/EDGX1)
Counter is running (FLEXPWM_EnableSubmoduleCounter)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

void FLEXPWM_DisableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)

Disable input capture for a FlexPWM capture channel.

This function disables input capture operation for the specified capture channel by clearing the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

FIFO handling: Disabling capture does not flush the FIFO. Any previously captured values remain readable. Clear the capture flags (CFx0/CFx1) separately if needed.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

static inline void FLEXPWM_SetINIT(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the INIT register value for a FlexPWM submodule.

This function directly writes a value to the INIT register (initial count register). The INIT register defines the starting value of the counter when it is initialized.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM parameters. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for:

Ensuring LDOK is clear before calling this function
Setting LDOK after updating registers to trigger reload
Managing reload timing and synchronization

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the INIT register (16-bit).

static inline void FLEXPWM_SetVAL0(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL0 register value for a FlexPWM submodule.

This function directly writes a value to the VAL0 register. VAL0 defines the half-cycle reload point for the PWM counter.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL0 register (16-bit).

static inline void FLEXPWM_SetVAL1(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL1 register value for a FlexPWM submodule.

This function directly writes a value to the VAL1 register. VAL1 defines the modulo (period) value for the PWM counter.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM period. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL1 register (16-bit).

static inline void FLEXPWM_SetVAL2(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL2 register value for a FlexPWM submodule.

This function directly writes a value to the VAL2 register. VAL2 defines the count value at which PWM23 (PWM_A) is set high, controlling the turn-on edge of PWM_A output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_A duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL2 register (16-bit).

static inline void FLEXPWM_SetVAL3(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL3 register value for a FlexPWM submodule.

This function directly writes a value to the VAL3 register. VAL3 defines the count value at which PWM23 (PWM_A) is set low, controlling the turn-off edge of PWM_A output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL3 register (16-bit).

static inline void FLEXPWM_SetVAL4(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL4 register value for a FlexPWM submodule.

This function directly writes a value to the VAL4 register. VAL4 defines the count value at which PWM45 (PWM_B) is set high, controlling the turn-on edge of PWM_B output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_B duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL4 register (16-bit).

static inline void FLEXPWM_SetVAL5(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the VAL5 register value for a FlexPWM submodule.

This function directly writes a value to the VAL5 register. VAL5 defines the count value at which PWM45 (PWM_B) is set low, controlling the turn-off edge of PWM_B output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL5 register (16-bit).

static inline void FLEXPWM_SetDTCNT0(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the DTCNT0 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT0 register (deadtime count register 0). DTCNT0 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT0 inserts software-selectable activation delays at PWM_A turn-on edge.

Note

DTCNT0 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT0 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetDTCNT1(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the DTCNT1 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT1 register (deadtime count register 1). DTCNT1 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT1 inserts software-selectable activation delays at PWM_B turn-on edge.

Note

DTCNT1 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT1 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetPhaseDelay(PWM_Type *base, uint8_t submodule, uint16_t value)

Set the Phase Delay register value for a FlexPWM submodule.

This function directly writes a value to the PHASEDLY register (phase delay register). PHASEDLY defines the time delay from the master sync signal (from submodule 0) to when this submodule recognizes the master sync, specified in PWM clock cycles.

Setting this register to a non-zero value and using the master sync signal as the initialization source allows this submodule’s output to be delayed by a fixed number of cycles relative to submodule 0, enabling phase-shifted PWM outputs.

Note

PHASEDLY is only valid for submodules 1-3. Submodule 0 is the master sync source and cannot have a phase delay relative to itself.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust phase delay. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (1-3, must NOT be 0).
value – The value to write to the PHASEDLY register (16-bit).

static inline void FLEXPWM_SetCompareMode(PWM_Type *base, uint8_t submodule, flexpwm_compare_mode_t compareMode)

Set Compare Mode for a FlexPWM submodule.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
compareMode – The compare mode to set for the submodule.

static inline void FLEXPWM_MaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)

Mask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function sets the MASK register bits to mask (disable) PWM outputs by forcing them to logic 0 before output polarity is applied. The mask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Note

MASK register characteristics:

Double-buffered register: writes take effect on next FORCE_OUT event
Use FLEXPWM_EnableUpdateMaskImmediately() to bypass FORCE_OUT requirement
Masking forces output to logic 0 before polarity inversion

Note

This function performs read-modify-write to preserve:

Mask settings for other submodules not specified in parameters
UPDATE_MASK bits (on platforms with FSL_FEATURE_PWM_MASK_HAS_UPDATE_MASK_BITFIELD)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_UnMaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)

Unmask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function clears the MASK register bits to unmask (enable) PWM outputs. The unmask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnableUpdateMaskImmediately(PWM_Type *base, uint16_t submoduleMask)

Enable immediate MASK register update for specified submodules.

This function configures the specified submodules to update their MASK register values immediately, bypassing the FORCE_OUT event requirement. This is useful for emergency stop or fault protection scenarios where immediate output masking is required.

Note

MASK[UPDATE_MASK] register characteristics:

Setting a bit to 1 enables immediate MASK update for that submodule
Once enabled, MASK updates take effect immediately without waiting for FORCE_OUT

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetPWMSource23(PWM_Type *base, uint8_t submodule, uint16_t source)

Set PWM source for PWM23 (PWM_A) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM23 (PWM_A) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Available sources:

Generated PWM: Normal PWM signal from PWM generator
Inverted PWM: Inverted version of generated PWM
Software: Software-controlled value from SWCOUT register
External: External input signal

Note

DTSRCSEL register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

When source is set to kFLEXPWM_ForcePwmSource_Software, use FLEXPWM_SetSoftwareControlOutput23() to set the output value.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetPWMSource45(PWM_Type *base, uint8_t submodule, uint16_t source)

Set PWM source for PWM45 (PWM_B) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM45 (PWM_B) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

See FLEXPWM_SetPWMSource23() documentation for detailed information about source selection, register characteristics, and usage notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetSoftwareControlOutput23(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)

Set software-controlled output value for PWM23 (PWM_A) of a submodule.

This function sets the software-controlled PWM output value in the SWCOUT register. This value is used as the PWM source when DTSRCSEL is configured to select software control (kFLEXPWM_ForcePwmSource_Software). The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

SWCOUT register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

Typical usage sequence:

Call FLEXPWM_SetPWMSource23(base, kFLEXPWM_ForcePwmSource_Software, submodule)
Call FLEXPWM_SetSoftwareControlOutput23(base, value, submodule)
Trigger FORCE_OUT event to make both settings take effect

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM23
- 1: Logic 1 provided to deadtime logic instead of PWM23

static inline void FLEXPWM_SetSoftwareControlOutput45(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)

Set software-controlled output value for PWM45 (PWM_B) of a submodule.

Note

See FLEXPWM_SetSoftwareControlOutput23() documentation for detailed information about register characteristics, usage sequence, and notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM45
- 1: Logic 1 provided to deadtime logic instead of PWM45

static inline void FLEXPWM_SetComplementaryPWMSource23(PWM_Type *base, uint16_t submoduleMask)

Select PWM23 (PWM_A) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM23 (PWM_A) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: PWM23 signal (non-inverted)
PWM_B output: ~PWM23 signal (inverted complement)

Note

MCTRL[IPOL] register characteristics:

Takes effect on FORCE_OUT event (double-buffered behavior)
Only applies when submodule is in complementary mode (INDEP = 0)
Ignored in independent mode (INDEP = 1)

Note

This function clears IPOL bits for specified submodules (IPOL = 0 selects PWM23).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetComplementaryPWMSource45(PWM_Type *base, uint16_t submoduleMask)

Select PWM45 (PWM_B) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM45 (PWM_B) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: ~PWM45 signal (inverted complement)
PWM_B output: PWM45 signal (non-inverted)

Note

See FLEXPWM_SetComplementaryPWMSource23() documentation for detailed information about MCTRL[IPOL] characteristics and complementary mode operation.

Note

This function sets IPOL bits for specified submodules (IPOL = 1 selects PWM45).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetLoadOkay(PWM_Type *base, uint16_t submoduleMask)

Set Load Okay (LDOK) for specified submodules.

This function sets the MCTRL[LDOK] bits to enable register reload for the specified submodules. When LDOK is set, buffered register values will be transferred to active registers according to the reload mode and timing configured in CTRL[LDMOD, LDFQ, HALF, FULL].

Note

LDOK behavior:

Can only be set when the corresponding LDOK bit is currently 0
Automatically cleared by hardware after reload completes
Can be manually cleared using FLEXPWM_ClearLoadOkay()
While LDOK=1, writes to buffered registers are blocked

Note

Typical usage flow:

Modify buffered registers (VAL0-5, INIT, etc.) using FLEXPWM_SetVALx() or similar
Call FLEXPWM_SetLoadOkay() to trigger reload
Hardware transfers buffered values at the configured reload opportunity
LDOK automatically clears after reload completes

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_ClearLoadOkay(PWM_Type *base, uint16_t submoduleMask)

Clear Load Okay (LDOK) for specified submodules.

This function clears the MCTRL[LDOK] bits by writing to MCTRL[CLDOK] bits. This cancels a pending reload operation for the specified submodules.

Note

MCTRL[CLDOK] (Clear LDOK) mechanism:

Writing 1 to CLDOK[x] clears the corresponding LDOK[x] bit
CLDOK is write-only; reading always returns 0
Use this when you need to cancel a pending reload

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline uint16_t FLEXPWM_GetLoadOkay(PWM_Type *base)

Get Load Okay (LDOK) status.

This function reads the MCTRL[LDOK] bits to check which submodules have pending reload operations.

Note

Return value format:

Bit[0]: Submodule 0 LDOK status
Bit[1]: Submodule 1 LDOK status
Bit[2]: Submodule 2 LDOK status
Bit[3]: Submodule 3 LDOK status

Note

Usage example:

uint16_t ldokStatus = FLEXPWM_GetLoadOkay(PWM0);
if (ldokStatus & kFLEXPWM_SubmoduleMask_0) {
}

Parameters:

base – FlexPWM peripheral base address.

Returns:

LDOK status bits (bit[3:0] correspond to submodules 3-0). Use flexpwm_submodule_mask_t enum values to check specific submodules.

static inline void FLEXPWM_SetLocalForceOut(PWM_Type *base, uint8_t submodule)

Set local FORCE_OUT event for a submodule.

This function sets the SMxCTRL2[FORCE] bit to trigger a local FORCE_OUT event. When a FORCE_OUT event occurs, several double-buffered registers immediately update:

DTSRCSEL (PWM source selection)
SWCOUT (software-controlled output values)
MASK (output masking)
MCTRL[IPOL] (complementary PWM source selection)

Additionally, if CTRL2[FRCEN] is enabled and the counter is running, the counter will be initialized to the INIT register value.

Note

FORCE_OUT trigger source: This function triggers a local FORCE_OUT event by setting CTRL2[FORCE]. The FORCE_OUT event only occurs if CTRL2[FORCE_SEL] = 0 (local force selected). If FORCE_SEL selects a different source, setting FORCE has no effect.

Note

Counter initialization: The counter is reinitialized only if:

CTRL2[FRCEN] = 1 (force initialization enabled), AND
MCTRL[RUN] = 1 (counter running) OR CTRL2[CLK_SEL] = 2 (submodule 0 aux clock)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

static inline void FLEXPWM_SetCounterForceInitialization(PWM_Type *base, uint8_t submodule, bool enable)

Enable or disable counter initialization on FORCE_OUT event.

This function controls whether FORCE_OUT events can trigger counter initialization by configuring the CTRL2[FRCEN] bit. When enabled, the counter will be reset to the INIT register value when local software forced event occurs.

Note

Counter initialization conditions: The counter is reinitialized only when ALL of the following conditions are met:

CTRL2[FRCEN] = 1 (enabled via this function), AND
A local FORCE_OUT event occurs (CTRL2[FORCE_SEL] = 0, CTRL2[FORCE] = 1)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
enable – Enable or disable counter force initialization:
- true: FORCE_OUT events can trigger counter initialization (FRCEN = 1)
- false: FORCE_OUT events do not affect counter initialization (FRCEN = 0)

static inline void FLEXPWM_EnableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)

Enable PWM counter for specified submodules.

This function enables the PWM counters for the specified submodules by setting MCTRL[RUN] bits. When enabled, the counters start running and generating PWM waveforms.

Note

Effects of enabling counter (RUN=1):

Counter begins incrementing/decrementing according to configuration
PWM generation starts (if outputs are also enabled)
Reload events can occur at configured opportunities
FORCE_OUT can trigger counter initialization (if FRCEN enabled)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)

Disable PWM counter for specified submodules.

This function disables the PWM counters for the specified submodules by clearing MCTRL[RUN] bits. When disabled, the counters stop running but retain their configuration.

Note

Effects of disabling counter (RUN=0):

Counter stops incrementing/decrementing
PWM generation ceases (outputs hold last state or go to fault state)
Configuration registers remain intact
Fault clearing behavior changes (see fault protection documentation)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)

Enable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function enables PWM outputs by setting the corresponding bits in the OUTEN register. Each output (PWM_A, PWM_B, PWM_X) can be independently enabled for each submodule.

Note

OUTEN register layout (same as MASK register):

bit[11:8]: PWMA_EN - PWM_A output enable for submodules 3-0
bit[7:4]: PWMB_EN - PWM_B output enable for submodules 3-0
bit[3:0]: PWMX_EN - PWM_X output enable for submodules 3-0

Note

Prerequisites: Before enabling outputs, ensure:

PWM waveform is configured (FLEXPWM_ConfigPWM)
Counter is running (FLEXPWM_EnableSubmoduleCounter)
Outputs are not masked (check MASK register)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)

Disable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function disables PWM outputs by clearing the corresponding bits in the OUTEN register. When an output is disabled, the pin is released from FlexPWM control and may be controlled by other peripherals or GPIO.

Note

Output disable effects:

Pin is tri-stated or controlled by GPIO/other peripherals
PWM waveform generation continues internally
Re-enabling the output will resume PWM operation seamlessly

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetWriteProtection(PWM_Type *base, flexpwm_write_protect_t config)

Set FlexPWM write protection mode.

This function configures the write protection for FlexPWM registers by setting MCTRL2[WRPROT]. Write protection prevents accidental modification of critical PWM configuration registers.

Note

Write protection modes:

kFLEXPWM_WriteProtect_Off: Write protection is disabled (default after reset)
kFLEXPWM_WriteProtect_On: Write protection is enabled but can be disabled
kFLEXPWM_WriteProtect_OffLocked: Write protection is disabled and locked until chip reset
kFLEXPWM_WriteProtect_OnLocked: Write protection is enabled and locked until chip reset

Note

Once a locked mode is set (OffLocked or OnLocked), the write protection state cannot be changed until the next chip reset. Use locked modes for safety-critical applications.

Parameters:

base – FlexPWM peripheral base address.
config – Write protection mode selection.

static inline void FLEXPWM_EnableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)

Enable FlexPWM submodule interrupts.

This function enables the specified interrupt sources for a FlexPWM submodule by setting the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt enable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline void FLEXPWM_DisableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)

Disable FlexPWM submodule interrupts.

This function disables the specified interrupt sources for a FlexPWM submodule by clearing the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt disable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule)

Get FlexPWM submodule status flags.

This function returns the current status flags from the SMxSTS register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

Returns:

Current status flags (combination of _flexpwm_submodule_status_flag values).

static inline void FLEXPWM_ClearSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule, uint16_t mask)

Clear FlexPWM submodule status flags.

This function clears the specified status flags in the SMxSTS register using the write-1-to-clear (W1C) mechanism.

Note

Do not attempt to clear kFLEXPWM_RegisterUpdatedFlag (RUF) as it is read-only.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Status flag clear mask (OR’ed combination of _flexpwm_submodule_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline void FLEXPWM_EnableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)

Enable FlexPWM fault interrupts.

This function enables the specified fault interrupt sources by setting the corresponding bits in the FCTRL[FIE] field.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same mask bit values are used for both fault channels. The faultChannel parameter determines which set of fault inputs is controlled:

faultChannel = 0: Controls FAULT0-3 interrupts
faultChannel = 1: Controls FAULT4-7 interrupts

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt enable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline void FLEXPWM_DisableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)

Disable FlexPWM fault interrupts.

This function disables the specified fault interrupt sources by clearing the corresponding bits in the FCTRL[FIE] field.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt disable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetFaultStatusFlags(PWM_Type *base, uint8_t faultChannel)

Get FlexPWM fault status flags.

This function returns the current fault status flags (FFLAG bits) from the FSTS register. These are latched flags that indicate a fault event has occurred.

Note

To check real-time hardware pin status (rather than latched flags), use FLEXPWM_GetFaultFilteredPinStatusFlags() instead.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)

Returns:

Current fault flags (combination of _flexpwm_fault_status_flag values).

static inline void FLEXPWM_ClearFaultStatusFlags(PWM_Type *base, uint8_t faultChannel, uint16_t mask)

Clear FlexPWM fault status flags.

This function clears the specified fault status flags (FFLAG bits) in the FSTS register using the write-1-to-clear (W1C) mechanism.

Note

Clearing FFLAG does not automatically re-enable PWM outputs. The re-enable timing depends on fault clearing mode (FAUTO), safety mode (FSAFE), recovery timing (FHALF/FFULL), and the state of FFPIN (filtered pin status).

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault flag clear mask (OR’ed combination of _flexpwm_fault_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline uint16_t FLEXPWM_GetFaultFilteredPinStatusFlags(PWM_Type *base, uint8_t faultChannel)

Get FlexPWM filtered fault pin status.

This function returns the real-time status of fault pins after filtering (FFPIN bits) from the FSTS register. These are read-only hardware status bits that reflect the current state of external fault signals.

Note

Key differences:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3 pins)
- 1: Fault channel 1 (FAULT4-7 pins, if supported)

Returns:

Current filtered fault pin status (combination of _flexpwm_fault_pin_status values).

void FLEXPWM_ConfigDMA(PWM_Type *base, uint8_t submodule, const flexpwm_dma_config_t *config)

Configures the DMA control strategy for a FlexPWM submodule.

This function configures the DMA trigger source and FIFO watermark logic. These settings define the DMA request generation strategy and should typically be configured once during initialization.

Note

This function only configures CAPTDE[7:6] and FAND bits in SMxDMAEN register. To enable/disable individual DMA channels at runtime, use FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA().

Note

Prerequisites: Before calling this function, ensure:

FIFO watermark levels are configured in FLEXPWM_ConfigInputCapture()
Capture channels are properly configured if using capture DMA

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
config – Pointer to DMA configuration structure

static inline void FLEXPWM_EnableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)

Enable FlexPWM submodule DMA requests.

This function enables DMA request generation for the specified channels. It controls the VALDE bit (VALx/FRACVALx write) and capture channel enables (CX0DE, CX1DE, CB0DE, CB1DE, CA0DE, CA1DE).

Note

Before calling this function, ensure FLEXPWM_ConfigDMA() has been called to set up the DMA trigger strategy.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

static inline void FLEXPWM_DisableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)

Disable FlexPWM submodule DMA requests.

This function disables DMA request generation for the specified channels.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

FSL_FLEXPWM_DRIVER_VERSION: Version 2.0.0

enum _flexpwm_clock_source

FlexPWM clock source selection.

Values:

enumerator kFLEXPWM_ClockSource_IPBusClock: IPBus clock

enumerator kFLEXPWM_ClockSource_ExtClock: External clock (EXT_CLK)

enumerator kFLEXPWM_ClockSource_Submodule0Clock: Submodule 0 auxiliary clock

enum _flexpwm_prescaler

FlexPWM clock prescaler selection.

Values:

enumerator kFLEXPWM_Prescale_Divide_1: Divide by 1

enumerator kFLEXPWM_Prescale_Divide_2: Divide by 2

enumerator kFLEXPWM_Prescale_Divide_4: Divide by 4

enumerator kFLEXPWM_Prescale_Divide_8: Divide by 8

enumerator kFLEXPWM_Prescale_Divide_16: Divide by 16

enumerator kFLEXPWM_Prescale_Divide_32: Divide by 32

enumerator kFLEXPWM_Prescale_Divide_64: Divide by 64

enumerator kFLEXPWM_Prescale_Divide_128: Divide by 128

enum _flexpwm_load_mode

FlexPWM load mode selection.

Values:

enumerator kFLEXPWM_LoadMode_Opportunity: Load at PWM reload opportunity

enumerator kFLEXPWM_LoadMode_Immediate: Load immediately after LDOK is set

enum _flexpwm_reload_source

FlexPWM reload source selection.

Values:

enumerator kFLEXPWM_ReloadSource_LocalReload: Local reload signal

enumerator kFLEXPWM_ReloadSource_MasterReload: Master reload signal from submodule 0

enum _flexpwm_init_source

FlexPWM counter initialization source selection.

Values:

enumerator kFLEXPWM_InitSource_LocalSync: Local sync signal

enumerator kFLEXPWM_InitSource_MasterReload: Master reload signal from submodule 0

enumerator kFLEXPWM_InitSource_MasterSync: Master sync signal from submodule 0

enumerator kFLEXPWM_InitSource_ExtSync: External sync signal (EXT_SYNC)

enum _flexpwm_compare_mode

FlexPWM PWM compare mode selection.

Values:

enumerator kFLEXPWM_CompareMode_Equal: Compare when counter equals compare value

enumerator kFLEXPWM_CompareMode_EqualGreater: Compare when counter is equal or greater than compare value

enum _flexpwm_submodule_mask

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

Values:

enumerator kFLEXPWM_SubmoduleMask_0: Submodule 0

enumerator kFLEXPWM_SubmoduleMask_1: Submodule 1

enumerator kFLEXPWM_SubmoduleMask_2: Submodule 2

enum _flexpwm_pwm_polarity

FlexPWM PWM output polarity selection.

Values:

enumerator kFLEXPWM_Polarity_ActiveHigh: PWM signal is normal (active high)

enumerator kFLEXPWM_Polarity_ActiveLow: PWM signal is inverted (active low)

enum _flexpwm_ipol_source

FlexPWM PWM output source selection for complementary mode.

Values:

enumerator kFLEXPWM_IPOL_PWM23: Use PWM23 (PWM_A) as complementary PWM source

enumerator kFLEXPWM_IPOL_PWM45: Use PWM45 (PWM_B) as complementary PWM source

enum _flexpwm_force_output_source

FlexPWM FORCE_OUT event source selection.

Values:

enumerator kFLEXPWM_ForceOutputSource_LocalForce: Local software forced event

enumerator kFLEXPWM_ForceOutputSource_MasterForce: Master force signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalReload: Local reload signal

enumerator kFLEXPWM_ForceOutputSource_MasterReload: Master reload signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalSync: Local sync signal

enumerator kFLEXPWM_ForceOutputSource_MasterSync: Master sync signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_ExtForce: External force signal (EXT_FORCE)

enumerator kFLEXPWM_ForceOutputSource_ExtSync: External sync signal (EXT_SYNC)

enum _flexpwm_force_pwm_source

FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

Values:

enumerator kFLEXPWM_ForcePwmSource_Generated: Generated PWM signal

enumerator kFLEXPWM_ForcePwmSource_Inverted: Inverted PWM signal

enumerator kFLEXPWM_ForcePwmSource_Software: Software controlled output (SWCOUT)

enumerator kFLEXPWM_ForcePwmSource_External: External signal

enum _flexpwm_fault_output_behavior

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

Values:

enumerator kFLEXPWM_FaultOutput_Force0: 0b00 - Force output to logic 0

enumerator kFLEXPWM_FaultOutput_Force1: 0b01 - Force output to logic 1

enumerator kFLEXPWM_FaultOutput_HighZ: 0b10/0b11 - High impedance (3-state) output

enum _flexpwm_fault_mask

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

Values:

enumerator kFLEXPWM_FaultMask_0: FAULT0 (ch0) or FAULT4 (ch1)

enumerator kFLEXPWM_FaultMask_1: FAULT1 (ch0) or FAULT5 (ch1)

enumerator kFLEXPWM_FaultMask_2: FAULT2 (ch0) or FAULT6 (ch1)

enumerator kFLEXPWM_FaultMask_3: FAULT3 (ch0) or FAULT7 (ch1)

enum _flexpwm_fault_clearing_mode

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

Values:

enumerator kFLEXPWM_FaultClearingMode_Manual: Manual clearing - software must clear FSTS[FFLAGx]

enumerator kFLEXPWM_FaultClearingMode_Automatic: Automatic clearing when FAULTx de-asserts

enum _flexpwm_write_protect

FlexPWM write protection mode selection.

Values:

enumerator kFLEXPWM_WriteProtect_Off: Write protection off (default)

enumerator kFLEXPWM_WriteProtect_On: Write protection on

enumerator kFLEXPWM_WriteProtect_OffLocked: Write protection off and locked until chip reset

enumerator kFLEXPWM_WriteProtect_OnLocked: Write protection on and locked until chip reset

enum _flexpwm_stretch_prescaler

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

Values:

enumerator kFLEXPWM_StretchPrescaler_None: No stretch

enumerator kFLEXPWM_StretchPrescaler_2Clocks: Stretch for 2 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_4Clocks: Stretch for 4 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_8Clocks: Stretch for 8 IPBus clock periods

enum _flexpwm_trigger_mux_source

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

Values:

enumerator kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Use PWM_OUT_TRIG0/1 (generated trigger signal)

enumerator kFLEXPWM_TriggerMuxSource_PWMOutput: Use PWM_A/PWM_B output directly

enum _flexpwm_trigger_frequency

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

Values:

enumerator kFLEXPWM_TriggerFrequency_EveryCycle: Trigger every PWM cycle even if reload doesn’t occur

enumerator kFLEXPWM_TriggerFrequency_OnReload: Trigger only on last cycle before reload opportunity

enum _flexpwm_output_trigger_mask

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

Values:

enumerator kFLEXPWM_OutputTriggerMask_VAL0: VAL0 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL1: VAL1 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL2: VAL2 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL3: VAL3 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL4: VAL4 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL5: VAL5 match triggers PWM_OUT_TRIG1

enum _flexpwm_capture_edge

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

Values:

enumerator kFLEXPWM_CaptureEdge_Disabled: Disable capture (register bit value: 00b)

enumerator kFLEXPWM_CaptureEdge_Falling: Capture on falling edge (register bit value: 01b)

enumerator kFLEXPWM_CaptureEdge_Rising: Capture on rising edge (register bit value: 10b)

enumerator kFLEXPWM_CaptureEdge_Both: Capture on any edge (register bit value: 11b)

enum _flexpwm_capture_fifo_watermark

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

Values:

enumerator kFLEXPWM_CaptureFifoWatermark_1: Trigger when FIFO has 1 or more samples (00b)

enumerator kFLEXPWM_CaptureFifoWatermark_2: Trigger when FIFO has 2 or more samples (01b)

enumerator kFLEXPWM_CaptureFifoWatermark_3: Trigger when FIFO has 3 or more samples (10b)

enumerator kFLEXPWM_CaptureFifoWatermark_4: Trigger when FIFO is full with 4 samples (11b)

enum _flexpwm_capture_input_select

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

Values:

enumerator kFLEXPWM_CaptureInput_RawSignal: Use raw PWM input signal (register bit value: 0)

enumerator kFLEXPWM_CaptureInput_EdgeCounter: Use edge counter output (register bit value: 1). Used to reduce capture frequency by counting N edges

enum _flexpwm_capture_index

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

Values:

enumerator kFLEXPWM_Capture_X_Edge0: CVAL0 - Capture_X Edge0

enumerator kFLEXPWM_Capture_X_Edge1: CVAL1 - Capture_X Edge1

enumerator kFLEXPWM_Capture_A_Edge0: CVAL2 - Capture_A Edge0

enumerator kFLEXPWM_Capture_A_Edge1: CVAL3 - Capture_A Edge1

enumerator kFLEXPWM_Capture_B_Edge0: CVAL4 - Capture_B Edge0

enumerator kFLEXPWM_Capture_B_Edge1: CVAL5 - Capture_B Edge1

enum _flexpwm_capture_channel

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

Values:

enumerator kFLEXPWM_Capture_A: Capture channel A (PWM_A)

enumerator kFLEXPWM_Capture_B: Capture channel B (PWM_B)

enumerator kFLEXPWM_Capture_X: Capture channel X (PWM_X)

enum _flexpwm_submodule_interrupt_enable

FlexPWM submodule interrupt enable flags.

These flags can be OR’ed together to enable multiple interrupt sources simultaneously. Use with FLEXPWM_EnableSubmoduleInterrupts() and FLEXPWM_DisableSubmoduleInterrupts().

Values:

enumerator kFLEXPWM_Compare0InterruptEnable: VAL0 compare interrupt

enumerator kFLEXPWM_Compare1InterruptEnable: VAL1 compare interrupt

enumerator kFLEXPWM_Compare2InterruptEnable: VAL2 compare interrupt

enumerator kFLEXPWM_Compare3InterruptEnable: VAL3 compare interrupt

enumerator kFLEXPWM_Compare4InterruptEnable: VAL4 compare interrupt

enumerator kFLEXPWM_Compare5InterruptEnable: VAL5 compare interrupt

enumerator kFLEXPWM_CaptureX0InterruptEnable: Capture X0 interrupt

enumerator kFLEXPWM_CaptureX1InterruptEnable: Capture X1 interrupt

enumerator kFLEXPWM_CaptureB0InterruptEnable: Capture B0 interrupt

enumerator kFLEXPWM_CaptureB1InterruptEnable: Capture B1 interrupt

enumerator kFLEXPWM_CaptureA0InterruptEnable: Capture A0 interrupt

enumerator kFLEXPWM_CaptureA1InterruptEnable: Capture A1 interrupt

enumerator kFLEXPWM_ReloadInterruptEnable: Reload interrupt

enumerator kFLEXPWM_ReloadErrorInterruptEnable: Reload error interrupt

enum _flexpwm_submodule_status_flag

FlexPWM submodule status flags.

These flags represent the status of various events in a FlexPWM submodule. Use with FLEXPWM_GetSubmoduleStatusFlags() and FLEXPWM_ClearSubmoduleStatusFlags().

Note

kFLEXPWM_RegisterUpdatedFlag is read-only and cannot be cleared by software.

Values:

enumerator kFLEXPWM_Compare0Flag: VAL0 compare flag

enumerator kFLEXPWM_Compare1Flag: VAL1 compare flag

enumerator kFLEXPWM_Compare2Flag: VAL2 compare flag

enumerator kFLEXPWM_Compare3Flag: VAL3 compare flag

enumerator kFLEXPWM_Compare4Flag: VAL4 compare flag

enumerator kFLEXPWM_Compare5Flag: VAL5 compare flag

enumerator kFLEXPWM_CaptureX0Flag: Capture X0 flag

enumerator kFLEXPWM_CaptureX1Flag: Capture X1 flag

enumerator kFLEXPWM_CaptureB0Flag: Capture B0 flag

enumerator kFLEXPWM_CaptureB1Flag: Capture B1 flag

enumerator kFLEXPWM_CaptureA0Flag: Capture A0 flag

enumerator kFLEXPWM_CaptureA1Flag: Capture A1 flag

enumerator kFLEXPWM_ReloadFlag: Reload flag

enumerator kFLEXPWM_ReloadErrorFlag: Reload error flag

enumerator kFLEXPWM_RegisterUpdatedFlag: Register updated flag (read-only)

enum _flexpwm_fault_interrupt_enable

FlexPWM fault interrupt enable flags.

These flags can be OR’ed together to enable multiple fault interrupt sources. Use with FLEXPWM_EnableFaultInterrupts() and FLEXPWM_DisableFaultInterrupts().

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same bit mask values are used for both fault channels:

faultChannel = 0: Controls FAULT0-3
faultChannel = 1: Controls FAULT4-7 The bit positions are the same, but the function parameter determines which fault channel is configured.

Values:

enumerator kFLEXPWM_Fault0InterruptEnable: FAULT0 (ch0) or FAULT4 (ch1) interrupt

enumerator kFLEXPWM_Fault1InterruptEnable: FAULT1 (ch0) or FAULT5 (ch1) interrupt

enumerator kFLEXPWM_Fault2InterruptEnable: FAULT2 (ch0) or FAULT6 (ch1) interrupt

enumerator kFLEXPWM_Fault3InterruptEnable: FAULT3 (ch0) or FAULT7 (ch1) interrupt

enum _flexpwm_fault_status_flag

FlexPWM fault status flags (FFLAG)

These flags represent the latched fault status (FFLAG bits in FSTS register). Use with FLEXPWM_GetFaultStatusFlags() and FLEXPWM_ClearFaultStatusFlags().

Note

FFLAG characteristics:

Write-1-to-clear: Software must write 1 to clear each flag
Latched event: Set within 2 CPU cycles after FAULTx pin transitions to active state
Historical record: Indicates a fault event has occurred (not current pin state)
Interrupt capable: Can generate CPU interrupt requests when enabled
Manual clearing: Does not auto-clear; requires explicit software action

Note

To check the real-time, filtered hardware pin status (not the latched event), use FLEXPWM_GetFaultFilteredPinStatusFlags() to read FFPIN instead.

Note

For dual-channel platforms: The same bit mask values apply to both channels.

faultChannel = 0: FAULT0-3 flags
faultChannel = 1: FAULT4-7 flags

Values:

enumerator kFLEXPWM_Fault0Flag: FAULT0 (ch0) or FAULT4 (ch1) flag

enumerator kFLEXPWM_Fault1Flag: FAULT1 (ch0) or FAULT5 (ch1) flag

enumerator kFLEXPWM_Fault2Flag: FAULT2 (ch0) or FAULT6 (ch1) flag

enumerator kFLEXPWM_Fault3Flag: FAULT3 (ch0) or FAULT7 (ch1) flag

enum _flexpwm_fault_pin_status

FlexPWM filtered fault pin status (FFPIN - read-only)

These flags represent the real-time status of fault pins after filtering (FFPIN bits in FSTS register). Use with FLEXPWM_GetFaultFilteredPinStatusFlags() to check if external fault signals are currently active.

Note

FFPIN characteristics:

Read-only: Cannot be written or cleared by software
Real-time status: Reflects current state of filtered FAULTx pin (not historical)
Polarity converted: Always shows active-high logic (1 = fault present)
Filter output: Shows fault filter output, not raw pin state
No interrupt: Does not directly generate interrupts (use FFLAG for interrupts)
Filter delay: May remain high briefly after raw pin clears due to filter latency

Note

Key differences from FFLAG:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Note

For dual-channel platforms: The same bit positions apply to both channels.

faultChannel = 0: FAULT0-3 pin status
faultChannel = 1: FAULT4-7 pin status

Values:

enumerator kFLEXPWM_Fault0PinActive: FAULT0/4 pin active (filtered)

enumerator kFLEXPWM_Fault1PinActive: FAULT1/5 pin active (filtered)

enumerator kFLEXPWM_Fault2PinActive: FAULT2/6 pin active (filtered)

enumerator kFLEXPWM_Fault3PinActive: FAULT3/7 pin active (filtered)

enum _flexpwm_dma_capture_source

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

Values:

enumerator kFLEXPWM_DMADisable: Read DMA requests disabled

enumerator kFLEXPWM_DMAFIFOWatermark: Exceeding FIFO watermark sets read DMA request

enumerator kFLEXPWM_DMALocalSync: Local sync sets read DMA request

enumerator kFLEXPWM_DMALocalReload: Local reload sets read DMA request

enum _flexpwm_dma_enable

FlexPWM DMA enable flags.

These flags are used with FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA() to control individual DMA channel enables. Multiple flags can be ORed together.

Values:

enumerator kFLEXPWM_DMA_CaptureX0Enable: Capture X0 FIFO DMA enable (CX0DE)

enumerator kFLEXPWM_DMA_CaptureX1Enable: Capture X1 FIFO DMA enable (CX1DE)

enumerator kFLEXPWM_DMA_CaptureB0Enable: Capture B0 FIFO DMA enable (CB0DE)

enumerator kFLEXPWM_DMA_CaptureB1Enable: Capture B1 FIFO DMA enable (CB1DE)

enumerator kFLEXPWM_DMA_CaptureA0Enable: Capture A0 FIFO DMA enable (CA0DE)

enumerator kFLEXPWM_DMA_CaptureA1Enable: Capture A1 FIFO DMA enable (CA1DE)

enumerator kFLEXPWM_DMA_ValueWriteEnable: Value registers DMA write enable (VALDE)

typedef enum _flexpwm_clock_source flexpwm_clock_source_t: FlexPWM clock source selection.

typedef enum _flexpwm_prescaler flexpwm_prescaler_t: FlexPWM clock prescaler selection.

typedef enum _flexpwm_load_mode flexpwm_load_mode_t: FlexPWM load mode selection.

typedef enum _flexpwm_reload_source flexpwm_reload_source_t: FlexPWM reload source selection.

typedef enum _flexpwm_init_source flexpwm_init_source_t: FlexPWM counter initialization source selection.

typedef enum _flexpwm_compare_mode flexpwm_compare_mode_t: FlexPWM PWM compare mode selection.

typedef enum _flexpwm_submodule_mask flexpwm_submodule_mask_t

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

typedef struct _flexpwm_counter_config flexpwm_counter_config_t: FlexPWM counter configuration structure.

typedef struct _flexpwm_reload_config flexpwm_reload_config_t: FlexPWM reload configuration structure.

typedef struct _flexpwm_submodule_config flexpwm_submodule_config_t

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

typedef enum _flexpwm_pwm_polarity flexpwm_pwm_polarity_t: FlexPWM PWM output polarity selection.

typedef enum _flexpwm_ipol_source flexpwm_ipol_source_t: FlexPWM PWM output source selection for complementary mode.

typedef struct _flexpwm_pwm_channel_config flexpwm_pwm_channel_config_t

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

typedef struct _flexpwm_pwm_config flexpwm_pwm_config_t

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For complementary mode: Only the selected channel (specified by ipolSource) needs to be configured. The other channel will be ignored by the hardware. For example, if ipolSource = kFLEXPWM_IPOL_PWM23, only pwma will be used.

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

typedef enum _flexpwm_force_output_source flexpwm_force_output_source_t: FlexPWM FORCE_OUT event source selection.

typedef enum _flexpwm_force_pwm_source flexpwm_force_pwm_source_t: FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

typedef struct _flexpwm_force_out_channel_config flexpwm_force_out_channel_config_t

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

typedef struct _flexpwm_force_out_config flexpwm_force_out_config_t

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

typedef enum _flexpwm_fault_output_behavior flexpwm_fault_output_behavior_t

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

typedef enum _flexpwm_fault_mask flexpwm_fault_mask_t

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

typedef struct _flexpwm_fault_output_config flexpwm_fault_output_config_t

FlexPWM fault output configuration structure.

Configures fault protection for a single PWM output (PWM_A, PWM_B, or PWM_X). Supports both single-channel (FAULT0-3 only) and dual-channel (FAULT0-3 and FAULT4-7) platforms via conditional compilation. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults.

typedef struct _flexpwm_fault_submodule_config flexpwm_fault_submodule_config_t

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

typedef enum _flexpwm_fault_clearing_mode flexpwm_fault_clearing_mode_t

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

typedef struct _flexpwm_fault_config flexpwm_fault_config_t

FlexPWM fault protection configuration structure.

Configures global fault protection parameters for one fault channel. These settings apply to all submodules and their outputs that reference this channel. For platforms with dual fault channels (FAULT0-3 and FAULT4-7), configure each channel separately using FLEXPWM_ConfigFaultProtection().

typedef struct _flexpwm_fault_filter_config flexpwm_fault_filter_config_t

FlexPWM fault filter configuration structure.

Configures input filter for fault protection pins to debounce electrical noise. The filter requires the input signal to be stable for N consecutive samples (where each sample is taken every T IPBus clock cycles) before reporting a fault. Helps avoid false fault triggers from noise on FAULTx pins.

typedef enum _flexpwm_write_protect flexpwm_write_protect_t: FlexPWM write protection mode selection.

typedef enum _flexpwm_stretch_prescaler flexpwm_stretch_prescaler_t

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

typedef enum _flexpwm_trigger_mux_source flexpwm_trigger_mux_source_t

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

typedef enum _flexpwm_trigger_frequency flexpwm_trigger_frequency_t

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

typedef enum _flexpwm_output_trigger_mask flexpwm_output_trigger_mask_t

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

typedef struct _flexpwm_output_trigger_config flexpwm_output_trigger_config_t

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

typedef enum _flexpwm_capture_edge flexpwm_capture_edge_t

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

typedef enum _flexpwm_capture_fifo_watermark flexpwm_capture_fifo_watermark_t

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

typedef enum _flexpwm_capture_input_select flexpwm_capture_input_select_t

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

typedef enum _flexpwm_capture_index flexpwm_capture_index_t

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

typedef enum _flexpwm_capture_channel flexpwm_capture_channel_t

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

typedef struct _flexpwm_capture_channel_config flexpwm_capture_channel_config_t

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

typedef struct _flexpwm_input_capture_config flexpwm_input_capture_config_t

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

typedef struct _flexpwm_capture_filter_channel_config flexpwm_capture_filter_channel_config_t

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

typedef struct _flexpwm_capture_filter_config flexpwm_capture_filter_config_t

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

typedef enum _flexpwm_dma_capture_source flexpwm_dma_capture_source_t

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

typedef struct _flexpwm_dma_config flexpwm_dma_config_t

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

uint32_t FLEXPWM_GetInstance(PWM_Type *base)

Get the instance for FlexPWM module.

Parameters:

base – FlexPWM base address

Returns:

Instance number if valid base address is provided, otherwise returns ARRAY_SIZE(s_flexpwmBases)

status_t FLEXPWM_Init(PWM_Type *base)

Initialize the FlexPWM module.

This function initializes the FlexPWM peripheral by:

Enabling clocks for all submodules (SM0-SM3)
Releasing peripheral reset (if supported by platform)

After calling this function, the FlexPWM module is ready for configuration. Additional configuration functions (FLEXPWM_ConfigSubmodule, FLEXPWM_ConfigPWM, etc.) should be called to set up the desired PWM behavior.

Note

This function does not configure any PWM parameters. It only enables the peripheral.

Note

This function does not start PWM generation. Use FLEXPWM_EnableSubmoduleCounter() and FLEXPWM_EnablePWMOutput() to start PWM output.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if initialization is successful. kStatus_InvalidArgument if the base address is invalid.

status_t FLEXPWM_DeInit(PWM_Type *base)

Deinitialize the FlexPWM module.

This function deinitializes the FlexPWM peripheral by:

Disabling clocks for all submodules (SM0-SM3)
Asserting peripheral reset (if supported by platform)

After calling this function, all FlexPWM registers are reset.

Note

To re-enable PWM operation, call FLEXPWM_Init() again.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if deinitialization is successful. kStatus_InvalidArgument if the base address is invalid.

FLEXPWM_GET_FCTRL_REG(base, ch)

FLEXPWM_GET_FSTS_REG(base, ch)

FLEXPWM_GET_FFILT_REG(base, ch)

FLEXPWM_GET_FCTRL2_REG(base, ch)

struct _flexpwm_counter_config

#include <fsl_flexpwm.h>

FlexPWM counter configuration structure.

Public Members

uint16_t initValue: Counter initial value (INIT register).

uint16_t modValue: Counter modulo value (VAL1 register). Defines the PWM period upper limit.

flexpwm_init_source_t initSource: Counter initialization source selection. Determines when the counter resets to initValue.

struct _flexpwm_reload_config

#include <fsl_flexpwm.h>

FlexPWM reload configuration structure.

Public Members

flexpwm_load_mode_t loadMode

kFLEXPWM_LoadMode_Opportunity: Load at next reload opportunity (PWM cycle)
kFLEXPWM_LoadMode_Immediate: Load immediately after LDOK is set

uint8_t loadFrequency

Load frequency divider (LDFQ field, 0-15). Buffered registers reload every (loadFrequency + 1) PWM cycles.

0: Every PWM cycle
1: Every 2 PWM cycles
15: Every 16 PWM cycles

bool enableHalfCycleReload

Enable reload at half-cycle point (VAL0 match).

true: Reload can occur at VAL0 match
false: No reload at half-cycle

bool enableFullCycleReload

Enable reload at full-cycle point (VAL1 match).

true: Reload can occur at VAL1 match
false: No reload at full-cycle

flexpwm_reload_source_t reloadSource

Reload signal source selection.

kFLEXPWM_ReloadSource_LocalReload: Use local reload signal
kFLEXPWM_ReloadSource_MasterReload: Use master reload from submodule 0

uint16_t halfCycleValue: Half-cycle reload point (VAL0 register). This value determines when half-cycle reload occurs. Note: Does not need to be exactly half the PWM period.

struct _flexpwm_submodule_config

#include <fsl_flexpwm.h>

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

Public Members

flexpwm_clock_source_t clockSource: Clock source for the submodule PWM counter.

flexpwm_prescaler_t prescaler: Clock prescaler divider.

flexpwm_counter_config_t counterConfig: Counter initialization and behavior configuration.

flexpwm_reload_config_t reloadConfig: Register reload mechanism configuration.

bool enableDebugMode

PWM behavior in Debug mode.

true: PWM continues running when MCU enters Debug mode
false: PWM stops when MCU enters Debug mode

struct _flexpwm_pwm_channel_config

#include <fsl_flexpwm.h>

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

Public Members

uint16_t compareValue_ON

Compare value that defines the PWM turn-on edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL2
PWM_B: written to VAL4
PWM_X: written to VAL0

uint16_t compareValue_OFF

Compare value that defines the PWM turn-off edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL3
PWM_B: written to VAL5
PWM_X: written to VAL1

flexpwm_pwm_polarity_t polarity

Output polarity.

kFLEXPWM_Polarity_ActiveLow: PWM signal is inverted (active low)
kFLEXPWM_Polarity_ActiveHigh: PWM signal is normal (active high)

struct _flexpwm_pwm_config

#include <fsl_flexpwm.h>

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

Public Members

flexpwm_pwm_channel_config_t pwma: PWM_A (PWM23) channel configuration

flexpwm_pwm_channel_config_t pwmb: PWM_B (PWM45) channel configuration

bool complementary

Operating mode.

true: Complementary mode (PWM_A and PWM_B form a complementary pair)
false: Independent mode (PWM_A and PWM_B are independent channels)

flexpwm_ipol_source_t ipolSource

MCTRL[IPOL] - Select which channel pair as complementary source. Only used when complementary = true.

kFLEXPWM_IPOL_PWM23: Use PWM23 as source
kFLEXPWM_IPOL_PWM45: Use PWM45 as source

struct _flexpwm_force_out_channel_config

#include <fsl_flexpwm.h>

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

Public Members

flexpwm_force_pwm_source_t source: PWM source selection for this channel (DTSRCSEL).

bool softwareValue: When source=kFLEXPWM_ForcePwmSource_Software, this value (0 or 1) is output to deadtime logic (SWCOUT).

struct _flexpwm_force_out_config

#include <fsl_flexpwm.h>

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

Public Members

flexpwm_force_output_source_t forceSource: FORCE_OUT trigger source (CTRL2[FORCE_SEL]).

flexpwm_force_out_channel_config_t pwma: PWM_A (PWM23) force output configuration.

flexpwm_force_out_channel_config_t pwmb: PWM_B (PWM45) force output configuration.

bool pwma_initialValue

PWM_A (PWM23) logical initial value in normal polarity.

true: PWM_A output starts at logic 1
false: PWM_A output starts at logic 0

bool pwmb_initialValue

PWM_B (PWM45) logical initial value in normal polarity.

true: PWM_B output starts at logic 1
false: PWM_B output starts at logic 0

bool pwmx_initialValue

PWM_X logical initial value in normal polarity.

true: PWM_X output starts at logic 1
false: PWM_X output starts at logic 0

struct _flexpwm_fault_output_config

#include <fsl_flexpwm.h>

FlexPWM fault output configuration structure.

Public Members

uint16_t disableMask_ch0

Fault disable mask for channel 0 (FAULT0-3). Each bit selects one fault input:

bit[0] = FAULT0
bit[1] = FAULT1
bit[2] = FAULT2
bit[3] = FAULT3 Maps to SMxDISMAP[0] register.

flexpwm_fault_output_behavior_t outputBehavior: Output behavior when fault is detected Maps to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS].

struct _flexpwm_fault_submodule_config

#include <fsl_flexpwm.h>

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

Public Members

flexpwm_fault_output_config_t pwma: PWM_A (PWM23) fault configuration. Controls which faults disable PWM_A output and how PWM_A behaves during fault.

flexpwm_fault_output_config_t pwmb: PWM_B (PWM45) fault configuration. Controls which faults disable PWM_B output and how PWM_B behaves during fault.

flexpwm_fault_output_config_t pwmx: PWM_X fault configuration. Controls which faults disable PWM_X output and how PWM_X behaves during fault.

struct _flexpwm_fault_config

#include <fsl_flexpwm.h>

FlexPWM fault protection configuration structure.

Public Members

bool faultInputActiveLevel

FAULTx input active level (FCTRL[FLVL])

false: Logic 0 on FAULTx indicates fault (active low)
true: Logic 1 on FAULTx indicates fault (active high)

flexpwm_fault_clearing_mode_t faultClearingMode: Fault clearing mode (FCTRL[FAUTO])

bool enableSafetyMode

Safety Mode (FCTRL[FSAFE]) Only useful for Manual fault clearing mode

false: Normal mode (PWM outputs enabled when FFLAG clears)
true: Safe mode (PWM outputs enabled only when both FFLAG and FFPIN are clear)

bool enableFullCycleRecovery

Full Cycle Recovery (FSTS[FFULL])

true: PWM outputs can be re-enabled at PWM full cycle start
false: No re-enable at full cycle

bool enableHalfCycleRecovery

Half Cycle Recovery (FSTS[FHALF])

true: PWM outputs can be re-enabled at PWM half cycle start
false: No re-enable at half cycle

bool enableCombinatorialPath

Combinational Path Control (FCTRL2[NOCOMB])

true: Combinational path active - fault input directly disables PWM outputs (fastest response)
false: Combinational path disabled - only latched fault signal disables PWM outputs (adds latency)

struct _flexpwm_fault_filter_config

#include <fsl_flexpwm.h>

FlexPWM fault filter configuration structure.

Public Members

uint8_t filterPeriod

Fault Filter Period (FFILT[FILT_PER]) Sampling period in IPBus clock cycles. Range: 0-255

0: Input filter bypassed
N: FAULTx sampled every N IPBus cycles

uint8_t filterCount

Fault Filter Count (FFILT[FILT_CNT]) Number of consecutive stable samples required to accept input transition. Range: 0-7 (actual samples = value + 3)

0: 3 samples
1: 4 samples
7: 10 samples

bool enableGlitchStretch

Fault Glitch Stretching (FFILT[GSTR])

false: Glitch stretching disabled
true: Input fault signals stretched to min 2 IPBus cycles Prevents false triggers from narrow glitches

struct _flexpwm_output_trigger_config

#include <fsl_flexpwm.h>

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

Public Members

uint16_t outTriggerEnable: Output trigger enable mask (OUT_TRIG_EN[5:0]). Bit mask for VAL0-5 trigger sources. OR’ed combination of flexpwm_output_trigger_mask_t Example: 0x05 enables VAL0 and VAL2 for TRIG0.

flexpwm_trigger_mux_source_t muxTrig0Source

PWM_MUX_TRIG0 port source selection (PWAOT0).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG0 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_A output directly

flexpwm_trigger_mux_source_t muxTrig1Source

PWM_MUX_TRIG1 port source selection (PWBOT1).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG1 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_B output directly

flexpwm_trigger_frequency_t triggerFrequency

Trigger frequency control (TRGFRQ). Controls trigger output frequency when CTRL[LDFQ] > 0.

kFLEXPWM_TriggerFrequency_EveryCycle: Trigger every PWM cycle
kFLEXPWM_TriggerFrequency_OnReload: Trigger only on last cycle before reload

flexpwm_stretch_prescaler_t stretchPrescaler: Trigger signal stretch prescaler (MCTRL2[STRETCH_CNT_PRSC]). Stretches trigger signal pulse width by specified IPBus clock cycles.

struct _flexpwm_capture_channel_config

#include <fsl_flexpwm.h>

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

Public Members

flexpwm_capture_edge_t edge0: Edge0 capture edge selection

flexpwm_capture_edge_t edge1: Edge1 capture edge selection

bool oneshot

Capture mode.

true: One-shot mode
false: Free-running mode

flexpwm_capture_input_select_t inputSelect

Input signal source selection.

kFLEXPWM_CaptureInput_RawSignal: Raw PWM input
kFLEXPWM_CaptureInput_EdgeCounter: Edge counter output

bool enableEdgeCounter

Edge counter enable control.

true: Enable edge counter (EDGCNT_EN = 1)
false: Disable edge counter (EDGCNT_EN = 0)

uint8_t edgeCompareValue: Edge counter compare value (0-255). Capture occurs when edge count reaches this value. Only valid when enableEdgeCounter = true

flexpwm_capture_fifo_watermark_t fifoWatermark: FIFO watermark level

struct _flexpwm_input_capture_config

#include <fsl_flexpwm.h>

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

Public Members

flexpwm_capture_channel_config_t captureA: Capture_A (PWM_A) channel configuration

flexpwm_capture_channel_config_t captureB: Capture_B (PWM_B) channel configuration

flexpwm_capture_channel_config_t captureX: Capture_X (PWM_X) channel configuration

struct _flexpwm_capture_filter_channel_config

#include <fsl_flexpwm.h>

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

Public Members

uint8_t filterPeriod

Filter sampling period in IPBus clock cycles (0-255).

0: Bypass filter (default)
Non-zero: Enable filter with specified sampling period

uint8_t filterCount: Number of consecutive consistent samples required (0-7). Actual sample count = filterCount + 3 (i.e., 3-10 samples)

struct _flexpwm_capture_filter_config

#include <fsl_flexpwm.h>

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

Public Members

flexpwm_capture_filter_channel_config_t captureA: Capture_A filter configuration

flexpwm_capture_filter_channel_config_t captureB: Capture_B filter configuration

flexpwm_capture_filter_channel_config_t captureX: Capture_X filter configuration

struct _flexpwm_dma_config

#include <fsl_flexpwm.h>

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

Public Members

flexpwm_dma_capture_source_t captureSource: Capture DMA enable source selection (CAPTDE[7:6])

bool fifoWatermarkAND

FIFO watermark AND/OR control (FAND).

true: Selected FIFO watermarks are ANDed
false: Selected FIFO watermarks are ORed

GPT: General Purpose Timer#

void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)

Initialize GPT to reset state and initialize running mode.

Parameters:

base – GPT peripheral base address.
initConfig – GPT mode setting configuration.

void GPT_Deinit(GPT_Type *base)

Disables the module and gates the GPT clock.

Parameters:

base – GPT peripheral base address.

void GPT_GetDefaultConfig(gpt_config_t *config)

Fills in the GPT configuration structure with default settings.

The default values are:

config->clockSource = kGPT_ClockSource_Periph;
config->divider = 1U;
config->enableRunInStop = true;
config->enableRunInWait = true;
config->enableRunInDoze = false;
config->enableRunInDbg = false;
config->enableFreeRun = false;
config->enableMode  = true;

Parameters:

config – Pointer to the user configuration structure.

static inline void GPT_SoftwareReset(GPT_Type *base)

Software reset of GPT module.

Parameters:

base – GPT peripheral base address.

static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)

Set clock source of GPT.

Parameters:

base – GPT peripheral base address.
gptClkSource – Clock source (see gpt_clock_source_t typedef enumeration).

static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)

Get clock source of GPT.

Parameters:

base – GPT peripheral base address.

Returns:

clock source (see gpt_clock_source_t typedef enumeration).

static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)

Set pre scaler of GPT.

Parameters:

base – GPT peripheral base address.
divider – Divider of GPT (1-4096).

static inline uint32_t GPT_GetClockDivider(GPT_Type *base)

Get clock divider in GPT module.

Parameters:

base – GPT peripheral base address.

Returns:

clock divider in GPT module (1-4096).

static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)

OSC 24M pre-scaler before selected by clock source.

Parameters:

base – GPT peripheral base address.
divider – OSC Divider(1-16).

static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)

Get OSC 24M clock divider in GPT module.

Parameters:

base – GPT peripheral base address.

Returns:

OSC clock divider in GPT module (1-16).

static inline void GPT_StartTimer(GPT_Type *base)

Start GPT timer.

Parameters:

base – GPT peripheral base address.

static inline void GPT_StopTimer(GPT_Type *base)

Stop GPT timer.

Parameters:

base – GPT peripheral base address.

static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)

Reads the current GPT counting value.

Parameters:

base – GPT peripheral base address.

Returns:

Current GPT counter value.

static inline void GPT_SetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)

Set GPT operation mode of input capture channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
mode – GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT operation mode of input capture channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT input capture value of certain channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture value.

static inline void GPT_SetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)

Set GPT operation mode of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
mode – GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT operation mode of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)

Set GPT output compare value of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
value – GPT output compare value.

static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT output compare value of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output compare value.

static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)

Force GPT output action on output compare channel, ignoring comparator.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)

Enables the selected GPT interrupts.

Parameters:

base – GPT peripheral base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)

Disables the selected GPT interrupts.

Parameters:

base – GPT peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)

Gets the enabled GPT interrupts.

Parameters:

base – GPT peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Get GPT status flags.

Parameters:

base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

Returns:

GPT status, each bit represents one status flag.

static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Clears the GPT status flags.

Parameters:

base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

FSL_GPT_DRIVER_VERSION

enum _gpt_clock_source

List of clock sources.

Note

Actual number of clock sources is SoC dependent

Values:

enumerator kGPT_ClockSource_Off: GPT Clock Source Off.

enumerator kGPT_ClockSource_Periph: GPT Clock Source from Peripheral Clock.

enumerator kGPT_ClockSource_HighFreq: GPT Clock Source from High Frequency Reference Clock.

enumerator kGPT_ClockSource_Ext: GPT Clock Source from external pin.

enumerator kGPT_ClockSource_LowFreq: GPT Clock Source from Low Frequency Reference Clock.

enumerator kGPT_ClockSource_Osc: GPT Clock Source from Crystal oscillator.

enum _gpt_input_capture_channel

List of input capture channel number.

Values:

enumerator kGPT_InputCapture_Channel1: GPT Input Capture Channel1.

enumerator kGPT_InputCapture_Channel2: GPT Input Capture Channel2.

enum _gpt_input_operation_mode

List of input capture operation mode.

Values:

enumerator kGPT_InputOperation_Disabled: Don’t capture.

enumerator kGPT_InputOperation_RiseEdge: Capture on rising edge of input pin.

enumerator kGPT_InputOperation_FallEdge: Capture on falling edge of input pin.

enumerator kGPT_InputOperation_BothEdge: Capture on both edges of input pin.

enum _gpt_output_compare_channel

List of output compare channel number.

Values:

enumerator kGPT_OutputCompare_Channel1: Output Compare Channel1.

enumerator kGPT_OutputCompare_Channel2: Output Compare Channel2.

enumerator kGPT_OutputCompare_Channel3: Output Compare Channel3.

enum _gpt_output_operation_mode

List of output compare operation mode.

Values:

enumerator kGPT_OutputOperation_Disconnected: Don’t change output pin.

enumerator kGPT_OutputOperation_Toggle: Toggle output pin.

enumerator kGPT_OutputOperation_Clear: Set output pin low.

enumerator kGPT_OutputOperation_Set: Set output pin high.

enumerator kGPT_OutputOperation_Activelow: Generate a active low pulse on output pin.

enum _gpt_interrupt_enable

List of GPT interrupts.

Values:

enumerator kGPT_OutputCompare1InterruptEnable: Output Compare Channel1 interrupt enable

enumerator kGPT_OutputCompare2InterruptEnable: Output Compare Channel2 interrupt enable

enumerator kGPT_OutputCompare3InterruptEnable: Output Compare Channel3 interrupt enable

enumerator kGPT_InputCapture1InterruptEnable: Input Capture Channel1 interrupt enable

enumerator kGPT_InputCapture2InterruptEnable: Input Capture Channel1 interrupt enable

enumerator kGPT_RollOverFlagInterruptEnable: Counter rolled over interrupt enable

enum _gpt_status_flag

Status flag.

Values:

enumerator kGPT_OutputCompare1Flag: Output compare channel 1 event.

enumerator kGPT_OutputCompare2Flag: Output compare channel 2 event.

enumerator kGPT_OutputCompare3Flag: Output compare channel 3 event.

enumerator kGPT_InputCapture1Flag: Input Capture channel 1 event.

enumerator kGPT_InputCapture2Flag: Input Capture channel 2 event.

enumerator kGPT_RollOverFlag: Counter reaches maximum value and rolled over to 0 event.

typedef enum _gpt_clock_source gpt_clock_source_t: List of clock sources.

Note

Actual number of clock sources is SoC dependent

typedef enum _gpt_input_capture_channel gpt_input_capture_channel_t: List of input capture channel number.

typedef enum _gpt_input_operation_mode gpt_input_operation_mode_t: List of input capture operation mode.

typedef enum _gpt_output_compare_channel gpt_output_compare_channel_t: List of output compare channel number.

typedef enum _gpt_output_operation_mode gpt_output_operation_mode_t: List of output compare operation mode.

typedef enum _gpt_interrupt_enable gpt_interrupt_enable_t: List of GPT interrupts.

typedef enum _gpt_status_flag gpt_status_flag_t: Status flag.

typedef struct _gpt_init_config gpt_config_t: Structure to configure the running mode.

struct _gpt_init_config

#include <fsl_gpt.h>

Structure to configure the running mode.

Public Members

gpt_clock_source_t clockSource: clock source for GPT module.

uint32_t divider: clock divider (prescaler+1) from clock source to counter.

bool enableFreeRun: true: FreeRun mode, false: Restart mode.

bool enableRunInWait: GPT enabled in wait mode.

bool enableRunInStop: GPT enabled in stop mode.

bool enableRunInDoze: GPT enabled in doze mode.

bool enableRunInDbg: GPT enabled in debug mode.

bool enableMode: true: counter reset to 0 when enabled; false: counter retain its value when enabled.

Hiperface: Hiperface encoder Driver#

I3C: I3C Driver#

FSL_I3C_DRIVER_VERSION: I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy: The master is already performing a transfer.

enumerator kStatus_I3C_Idle: The slave driver is idle.

enumerator kStatus_I3C_Nak: The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort: The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term: The master terminates slave read.

enumerator kStatus_I3C_HdrParityError: Parity error from DDR read.

enumerator kStatus_I3C_CrcError: CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError: Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError: Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError: Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq: Invalid use of request.

enumerator kStatus_I3C_Timeout: The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed: The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon: The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError: Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError: Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak: Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart: Slave invalid start flag

enumerator kStatus_I3C_SdrParityError: SDR parity error

enumerator kStatus_I3C_S0S1Error: S0 or S1 error

enum _i3c_hdr_mode

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone

enumerator kI3C_HDRModeDDR

enumerator kI3C_HDRModeTSP

enumerator kI3C_HDRModeTSL

typedef enum _i3c_hdr_mode i3c_hdr_mode_t: I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t: I3C device information.

I3C_RETRY_TIMES

Max loops to wait for I3C operation status complete.

This is the maximum number of loops to wait for I3C operation status complete. If set to 0, it will wait indefinitely.

I3C_MAX_DEVCNT

I3C_IBI_BUFF_SIZE

struct _i3c_device_info

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr: Device dynamic address.

uint8_t staticAddr: Static address.

uint8_t dcr: Device characteristics register information.

uint8_t bcr: Bus characteristics register information.

uint16_t vendorID: Device vendor ID(manufacture ID).

uint32_t partNumber: Device part number info

uint16_t maxReadLength: Maximum read length.

uint16_t maxWriteLength: Maximum write length.

uint8_t hdrMode: Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver#

typedef struct _i3c_config i3c_config_t

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)

Get which instance current I3C is used.

Parameters:

base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->disableTimeout config->hKeep config->enableOpenDrainStop config->enableOpenDrainHigh config->baudRate_Hzconfig->baudRate_Hzconfig->baudRate_Hzconfig->masterDynamicAddress config->slowClock_Hz config->enableSlave config->vendorID config->enableRandomPart config->partNumber config->dcr config->bcr config->hdrMode config->nakAllRequest config->ignoreS0S1Error config->offline config->matchSlaveStartStop 

notranslate">

config->enableMaster                 = kI3C_MasterCapable; = false; = kI3C_MasterHighKeeperNone; = true; = true; class="o">.i2cBaud          = 400000U; class="o">.i3cPushPullBaud  = 12500000U; class="o">.i3cOpenDrainBaud = 2500000U; = 0x0AU; = 1000000U; = true; = 0x11BU; = false; = 0; = 0; = 0; = (uint8_t)kI3C_HDRModeDDR; = false; = false; = false; = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

config – [out] User provided configuration structure for default values. Refer to i3c_config_t. 







void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration. 

Parameters:

base – The I3C peripheral base address. 
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







struct _i3c_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay

I3C SCL delay after Repeated START. 




uint8_t masterDynamicAddress

Main master dynamic address configuration. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 




bool enableSlave

Whether to enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed. 







I3C Master Driver#


void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)

Provides a default configuration for the I3C master peripheral. 
This function provides the following default configuration for the I3C master peripheral: 
masterConfig->enableMaster            = kI3C_MasterOn;
masterConfig->disableTimeout          = false;
masterConfig->hKeep                   = kI3C_MasterHighKeeperNone;
masterConfig->enableOpenDrainStop     = true;
masterConfig->enableOpenDrainHigh     = true;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busType                 = kI3C_TypeI2C;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I3C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to i3c_master_config_t. 







void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the I3C master peripheral. 
This function enables the peripheral clock and initializes the I3C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The I3C peripheral base address. 
masterConfig – User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







void I3C_MasterDeinit(I3C_Type *base)

Deinitializes the I3C master peripheral. 
This function disables the I3C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)

Set I3C module master mode. 

Parameters:

base – The I3C peripheral base address. 
enable – Enable master mode. 







status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)





status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)





status_t I3C_CheckForBusyBus(I3C_Type *base)





void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)

Gets the I3C master status flags. 
A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master status flag state. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


Attempts to clear other flags has no effect.

See also
_i3c_master_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_master_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)

Gets the I3C master error status flags. 
A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master error status flag state. 

See also
_i3c_master_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_master_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







i3c_master_state_t I3C_MasterGetState(I3C_Type *base)

Gets the I3C master state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C master state. 






static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)





static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C master DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Transmit Data Register address. 






static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Receive Data Register address. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_MasterSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz)

Sets the I3C bus frequency for master transactions. 
The I3C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note
On devices affected by I3C errata ERR053429, an SDR read with PPBAUD < 2 can lose the last received byte when the RxFIFO fills before the CPU/DMA services it. For safe SDR reads, request a push-pull baud that yields PPBAUD > 1, or guarantee the CPU/DMA drains the RxFIFO fast enough to avoid a Full event.


Parameters:

base – The I3C peripheral base address. 
baudRate_Hz – Pointer to structure of requested bus frequency in Hertz. 
sourceClock_Hz – I3C functional clock frequency in Hertz. 







static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)

Returns whether the bus is idle. 
Requires the master mode to be enabled.

Parameters:

base – The I3C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







status_t I3C_MasterStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the a address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a START signal and slave address on the I2C/I3C bus. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterRepeatedStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize configuration.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a repeated START signal and slave address on the I2C/I3C bus. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)

Performs a polling send transfer on the I2C/I3C bus. 
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_I3C_Nak.

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was sent successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)

Performs a polling receive transfer on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterStop(I3C_Type *base)

Sends a STOP signal on the I2C/I3C bus. 
This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The I3C peripheral base address. 


Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_InvalidReq – Invalid use of request. 







void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq)

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
masterReq – I3C master request of type i3c_bus_request_t







static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
ibiResponse – I3C master emit IBI response of type i3c_ibi_response_t







void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master register IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to ibi rule description of type i3c_register_ibi_addr_t







void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master get IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to store the read out ibi rule description. 







i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base)

I3C master get IBI Type. 

Parameters:

base – The I3C peripheral base address. 


Return values:
i3c_ibi_type_t – Type of i3c_ibi_type_t. 






static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)

I3C master get IBI Address. 

Parameters:

base – The I3C peripheral base address. 


Return values:
The – 8-bit IBI address. 






status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint8_t *addressList, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate)

Performs a DAA in the i3c bus with specified temporary baud rate. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. 
daaBaudRate – The temporary baud rate in DAA process, NULL for using initial setting. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)

Performs a DAA in the i3c bus. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count)

Get device information list after DAA process is done. 

Parameters:

base – The I3C peripheral base address. 
count – [out] The pointer to store the available device count. 


Returns:
Pointer to the i3c_device_info_t array. 






void I3C_MasterClearDeviceCount(I3C_Type *base)

Clear the global device count which represents current devices number on the bus. When user resets all dynamic addresses on the bus, should call this API. 

Parameters:

base – The I3C peripheral base address. 







status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C/I3C bus. 

Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.


Parameters:

base – The I3C peripheral base address. 
transfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_IBIWon – The I3C slave event IBI or MR or HJ won the arbitration on a header address. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_MasterTransferCreateHandle(I3C_Type *base, i3c_master_handle_t *handle, const i3c_master_transfer_callback_t *callback, void *userData)

Creates a new handle for the I3C master non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 







status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the I3C peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to the I3C master driver handle. 







void I3C_DriverIRQHandler(uint32_t instance)

Common IRQ handler entry for all I3C instances. 
This function dispatches the IRQ to the correct instance handler using the instance index.

Parameters:

instance – I3C instance number. 







enum _i3c_master_flags

I3C master peripheral flags. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterBetweenFlag

Between messages/DAAs flag 




enumerator kI3C_MasterNackDetectFlag

NACK detected flag 




enumerator kI3C_MasterSlaveStartFlag

Slave request start flag 




enumerator kI3C_MasterControlDoneFlag

Master request complete flag 




enumerator kI3C_MasterCompleteFlag

Transfer complete flag 




enumerator kI3C_MasterRxReadyFlag

Rx data ready in Rx buffer flag 




enumerator kI3C_MasterTxReadyFlag

Tx buffer ready for Tx data flag 




enumerator kI3C_MasterArbitrationWonFlag

Header address won arbitration flag 




enumerator kI3C_MasterErrorFlag

Error occurred flag 




enumerator kI3C_MasterSlave2MasterFlag

Switch from slave to master flag 




enumerator kI3C_MasterClearFlags







enum _i3c_master_error_flags

I3C master error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterErrorNackFlag

Slave NACKed the last address 




enumerator kI3C_MasterErrorWriteAbortFlag

Slave NACKed the write data 




enumerator kI3C_MasterErrorParityFlag

Parity error from DDR read 




enumerator kI3C_MasterErrorCrcFlag

CRC error from DDR read 




enumerator kI3C_MasterErrorReadFlag

Read from MRDATAB register when FIFO empty 




enumerator kI3C_MasterErrorWriteFlag

Write to MWDATAB register when FIFO full 




enumerator kI3C_MasterErrorMsgFlag

Message SDR/DDR mismatch or read/write message in wrong state 




enumerator kI3C_MasterErrorInvalidReqFlag

Invalid use of request 




enumerator kI3C_MasterErrorTimeoutFlag

The module has stalled too long in a frame 




enumerator kI3C_MasterAllErrorFlags

All error flags 






enum _i3c_master_state

I3C working master state. 
Values:


enumerator kI3C_MasterStateIdle

Bus stopped. 




enumerator kI3C_MasterStateSlvReq

Bus stopped but slave holding SDA low. 




enumerator kI3C_MasterStateMsgSdr

In SDR Message mode from using MWMSG_SDR. 




enumerator kI3C_MasterStateNormAct

In normal active SDR mode. 




enumerator kI3C_MasterStateDdr

In DDR Message mode. 




enumerator kI3C_MasterStateDaa

In ENTDAA mode. 




enumerator kI3C_MasterStateIbiAck

Waiting on IBI ACK/NACK decision. 




enumerator kI3C_MasterStateIbiRcv

Receiving IBI. 






enum _i3c_master_enable

I3C master enable configuration. 
Values:


enumerator kI3C_MasterOff

Master off. 




enumerator kI3C_MasterOn

Master on. 




enumerator kI3C_MasterCapable

Master capable. 






enum _i3c_master_hkeep

I3C high keeper configuration. 
Values:


enumerator kI3C_MasterHighKeeperNone

Use PUR to hold SCL high. 




enumerator kI3C_MasterHighKeeperWiredIn

Use pin_HK controls. 




enumerator kI3C_MasterPassiveSDA

Hi-Z for Bus Free and hold SDA. 




enumerator kI3C_MasterPassiveSDASCL

Hi-Z both for Bus Free, and can Hi-Z SDA for hold. 






enum _i3c_bus_request

Emits the requested operation when doing in pieces vs. by message. 
Values:


enumerator kI3C_RequestNone

No request. 




enumerator kI3C_RequestEmitStartAddr

Request to emit start and address on bus. 




enumerator kI3C_RequestEmitStop

Request to emit stop on bus. 




enumerator kI3C_RequestIbiAckNack

Manual IBI ACK or NACK. 




enumerator kI3C_RequestProcessDAA

Process DAA. 




enumerator kI3C_RequestForceExit

Request to force exit. 




enumerator kI3C_RequestAutoIbi

Hold in stopped state, but Auto-emit START,7E. 






enum _i3c_bus_type

Bus type with EmitStartAddr. 
Values:


enumerator kI3C_TypeI3CSdr

SDR mode of I3C. 




enumerator kI3C_TypeI2C

Standard i2c protocol. 




enumerator kI3C_TypeI3CDdr

HDR-DDR mode of I3C. 






enum _i3c_ibi_response

IBI response. 
Values:


enumerator kI3C_IbiRespAck

ACK with no mandatory byte. 




enumerator kI3C_IbiRespNack

NACK. 




enumerator kI3C_IbiRespAckMandatory

ACK with mandatory byte. 




enumerator kI3C_IbiRespManual

Reserved. 






enum _i3c_ibi_type

IBI type. 
Values:


enumerator kI3C_IbiNormal

In-band interrupt. 




enumerator kI3C_IbiHotJoin

slave hot join. 




enumerator kI3C_IbiMasterRequest

slave master ship request. 






enum _i3c_ibi_state

IBI state. 
Values:


enumerator kI3C_IbiReady

In-band interrupt ready state, ready for user to handle. 




enumerator kI3C_IbiDataBuffNeed

In-band interrupt need data buffer for data receive. 




enumerator kI3C_IbiAckNackPending

In-band interrupt Ack/Nack pending for decision. 






enum _i3c_direction

Direction of master and slave transfers. 
Values:


enumerator kI3C_Write

Master transmit. 




enumerator kI3C_Read

Master receive. 






enum _i3c_tx_trigger_level

Watermark of TX int/dma trigger level. 
Values:


enumerator kI3C_TxTriggerOnEmpty

Trigger on empty. 




enumerator kI3C_TxTriggerUntilOneQuarterOrLess

Trigger on 1/4 full or less. 




enumerator kI3C_TxTriggerUntilOneHalfOrLess

Trigger on 1/2 full or less. 




enumerator kI3C_TxTriggerUntilOneLessThanFull

Trigger on 1 less than full or less. 






enum _i3c_rx_trigger_level

Watermark of RX int/dma trigger level. 
Values:


enumerator kI3C_RxTriggerOnNotEmpty

Trigger on not empty. 




enumerator kI3C_RxTriggerUntilOneQuarterOrMore

Trigger on 1/4 full or more. 




enumerator kI3C_RxTriggerUntilOneHalfOrMore

Trigger on 1/2 full or more. 




enumerator kI3C_RxTriggerUntilThreeQuarterOrMore

Trigger on 3/4 full or more. 






enum _i3c_rx_term_ops

I3C master read termination operations. 
Values:


enumerator kI3C_RxTermDisable

Master doesn’t terminate read, used for CCC transfer. 




enumerator kI3C_RxAutoTerm

Master auto terminate read after receiving specified bytes(<=255). 




enumerator kI3C_RxTermLastByte

Master terminates read at any time after START, no length limitation. 






enum _i3c_start_scl_delay

I3C start SCL delay options. 
Values:


enumerator kI3C_NoDelay

No delay. 




enumerator kI3C_IncreaseSclHalfPeriod

Increases SCL clock period by 1/2. 




enumerator kI3C_IncreaseSclOnePeriod

Increases SCL clock period by 1. 




enumerator kI3C_IncreaseSclOneAndHalfPeriod

Increases SCL clock period by 1 1/2 






enum _i3c_master_transfer_flags

Transfer option flags. 

Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _i3c_master_transfer::flags field. 

Values:


enumerator kI3C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal. 




enumerator kI3C_TransferNoStartFlag

Don’t send a start condition, address, and sub address 




enumerator kI3C_TransferRepeatedStartFlag

Send a repeated start condition 




enumerator kI3C_TransferNoStopFlag

Don’t send a stop condition. 




enumerator kI3C_TransferWordsFlag

Transfer in words, else transfer in bytes. 




enumerator kI3C_TransferDisableRxTermFlag

Disable Rx termination. Note: It’s for I3C CCC transfer. 




enumerator kI3C_TransferRxAutoTermFlag

Set Rx auto-termination. Note: It’s adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. 




enumerator kI3C_TransferStartWithBroadcastAddr

Start transfer with 0x7E, then read/write data with device address. 






typedef enum _i3c_master_state i3c_master_state_t

I3C working master state. 




typedef enum _i3c_master_enable i3c_master_enable_t

I3C master enable configuration. 




typedef enum _i3c_master_hkeep i3c_master_hkeep_t

I3C high keeper configuration. 




typedef enum _i3c_bus_request i3c_bus_request_t

Emits the requested operation when doing in pieces vs. by message. 




typedef enum _i3c_bus_type i3c_bus_type_t

Bus type with EmitStartAddr. 




typedef enum _i3c_ibi_response i3c_ibi_response_t

IBI response. 




typedef enum _i3c_ibi_type i3c_ibi_type_t

IBI type. 




typedef enum _i3c_ibi_state i3c_ibi_state_t

IBI state. 




typedef enum _i3c_direction i3c_direction_t

Direction of master and slave transfers. 




typedef enum _i3c_tx_trigger_level i3c_tx_trigger_level_t

Watermark of TX int/dma trigger level. 




typedef enum _i3c_rx_trigger_level i3c_rx_trigger_level_t

Watermark of RX int/dma trigger level. 




typedef enum _i3c_rx_term_ops i3c_rx_term_ops_t

I3C master read termination operations. 




typedef enum _i3c_start_scl_delay i3c_start_scl_delay_t

I3C start SCL delay options. 




typedef struct _i3c_register_ibi_addr i3c_register_ibi_addr_t

Structure with setting master IBI rules and slave registry. 




typedef struct _i3c_baudrate i3c_baudrate_hz_t

Structure with I3C baudrate settings. 




typedef struct _i3c_master_daa_baudrate i3c_master_daa_baudrate_t

I3C DAA baud rate configuration. 




typedef struct _i3c_master_config i3c_master_config_t

Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef struct _i3c_master_transfer i3c_master_transfer_t





typedef struct _i3c_master_handle i3c_master_handle_t





typedef struct _i3c_master_transfer_callback i3c_master_transfer_callback_t

i3c master callback functions. 




typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle)

Typedef for master interrupt handler. 




struct _i3c_register_ibi_addr


#include <fsl_i3c.h>
Structure with setting master IBI rules and slave registry. 

Public Members


uint8_t address[5]

Address array for registry. 




bool i3cFastStart

Allow the START header to run as push-pull speed if all dynamic addresses take MSB 0. 




bool ibiHasPayload

Whether the address array has mandatory IBI byte. 







struct _i3c_baudrate


#include <fsl_i3c.h>
Structure with I3C baudrate settings. 

Public Members


uint32_t i2cBaud

Desired I2C baud rate in Hertz. 




uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_daa_baudrate


#include <fsl_i3c.h>
I3C DAA baud rate configuration. 

Public Members


uint32_t sourceClock_Hz

FCLK, function clock in Hertz. 




uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay

I3C SCL delay after Repeated START. 







struct _i3c_master_transfer_callback


#include <fsl_i3c.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)

Transfer complete callback 




void (*ibiCallback)(I3C_Type *base, i3c_master_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback 




void (*transferComplete)(I3C_Type *base, i3c_master_handle_t *handle, status_t completionStatus, void *userData)

Transfer complete callback 







struct _i3c_master_transfer


#include <fsl_i3c.h>
Non-blocking transfer descriptor structure. 
This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. 

Public Members


uint32_t flags

Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. Set to 0 or kI3C_TransferDefaultFlag for normal transfers. 




uint8_t slaveAddress

The 7-bit slave address. 




i3c_direction_t direction

Either kI3C_Read or kI3C_Write. 




uint32_t subaddress

Sub address. Transferred MSB first. 




size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes. 




void *data

Pointer to data to transfer. 




size_t dataSize

Number of bytes to transfer. 




i3c_bus_type_t busType

bus type. 




i3c_ibi_response_t ibiResponse

ibi response during transfer. 







struct _i3c_master_handle


#include <fsl_i3c.h>
Driver handle for master non-blocking APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


uint8_t state

Transfer state machine current state. 




uint32_t remainingBytes

Remaining byte count in current state. 




i3c_rx_term_ops_t rxTermOps

Read termination operation. 




i3c_master_transfer_t transfer

Copy of the current transfer info. 




uint8_t ibiAddress

Slave address which request IBI. 




uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize

IBI payload size. 




i3c_ibi_type_t ibiType

IBI type. 




i3c_master_transfer_callback_t callback

Callback functions pointer. 




void *userData

Application data passed to callback. 







I3C Master DMA Driver#


void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, const i3c_master_edma_callback_t *callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C master DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I3C bus. 
The callback specified when the handle was created is invoked when the transaction has completed.

Note
On parts affected by ERR053412, the I3C controller stalls SCL when the RxFIFO becomes full and does not recover after CPU read FIFO, bus will be stalling indefinitely. This DMA-based API services the RxFIFO with EDMA so it never fills, and is the recommended workaround on affected parts.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 







status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress. 







void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the DMA peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C master DMA driver handle. 







typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t





typedef struct _i3c_master_edma_callback i3c_master_edma_callback_t

i3c master callback functions. 




struct _i3c_master_edma_callback


#include <fsl_i3c_edma.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)

Target asks for controller request. 




void (*ibiCallback)(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback. 




void (*transferComplete)(I3C_Type *base, i3c_master_edma_handle_t *handle, status_t status, void *userData)

Transfer complete callback. 







struct _i3c_master_edma_handle


#include <fsl_i3c_edma.h>
Driver handle for master EDMA APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base

I3C base pointer. 




uint8_t state

Transfer state machine current state. 




uint32_t transferCount

Indicates progress of the transfer 




uint8_t subaddressBuffer[4]

Saving subaddress command. 




uint8_t subaddressCount

Saving command count. 




i3c_master_transfer_t transfer

Copy of the current transfer info. 




i3c_master_edma_callback_t callback

Callback function pointer. 




void *userData

Application data passed to callback. 




edma_handle_t *rxDmaHandle

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle

Handle for transmit DMA channel. 




bool ibiFlag

IBIWON flag. 




uint8_t ibiAddress

Slave address which request IBI. 




uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize

IBI payload size. 




i3c_ibi_type_t ibiType

IBI type. 




status_t result

Transfer result. 







I3C Slave Driver#


void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_SlaveTransferCreateHandle(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the I3C slave non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers. 
Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i3c_slave_transfer_event_t enumerators for the events you wish to receive. The kI3C_SlaveTransmitEvent and kI3C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI3C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI3C_SlaveAllEvents to enable all events.


Return values:

kStatus_Success – Slave transfers were successfully started. 
kStatus_I3C_Busy – Slave transfers have already been started on this handle. 







status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to i2c_slave_handle_t structure. 
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – 







void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle)

Aborts the slave non-blocking transfers. 

Note
This API could be called at any time to stop slave for handling the bus events. 


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







enum _i3c_slave_flags

I3C slave peripheral flags. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveNotStopFlag

Slave status not stop flag 




enumerator kI3C_SlaveMessageFlag

Slave status message, indicating slave is listening to the bus traffic or responding 




enumerator kI3C_SlaveRequiredReadFlag

Slave status required, either is master doing SDR read from slave, or is IBI pushing out. 




enumerator kI3C_SlaveRequiredWriteFlag

Slave status request write, master is doing SDR write to slave, except slave in ENTDAA mode 




enumerator kI3C_SlaveBusDAAFlag

I3C bus is in ENTDAA mode 




enumerator kI3C_SlaveBusHDRModeFlag

I3C bus is in HDR mode 




enumerator kI3C_SlaveBusStartFlag

Start/Re-start event is seen since the bus was last cleared 




enumerator kI3C_SlaveMatchedFlag

Slave address(dynamic/static) matched since last cleared 




enumerator kI3C_SlaveBusStopFlag

Stop event is seen since the bus was last cleared 




enumerator kI3C_SlaveRxReadyFlag

Rx data ready in rx buffer flag 




enumerator kI3C_SlaveTxReadyFlag

Tx buffer ready for Tx data flag 




enumerator kI3C_SlaveDynamicAddrChangedFlag

Slave dynamic address has been assigned, re-assigned, or lost 




enumerator kI3C_SlaveReceivedCCCFlag

Slave received Common command code 




enumerator kI3C_SlaveErrorFlag

Error occurred flag 




enumerator kI3C_SlaveHDRCommandMatchFlag

High data rate command match 




enumerator kI3C_SlaveCCCHandledFlag

Slave received Common command code is handled by I3C module 




enumerator kI3C_SlaveEventSentFlag

Slave IBI/P2P/MR/HJ event has been sent 




enumerator kI3C_SlaveIbiDisableFlag

Slave in band interrupt is disabled. 




enumerator kI3C_SlaveMasterRequestDisabledFlag

Slave master request is disabled. 




enumerator kI3C_SlaveHotJoinDisabledFlag

Slave Hot-Join is disabled. 




enumerator kI3C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kI3C_SlaveAllIrqFlags







enum _i3c_slave_error_flags

I3C slave error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveErrorOverrunFlag

Slave internal from-bus buffer/FIFO overrun. 




enumerator kI3C_SlaveErrorUnderrunFlag

Slave internal to-bus buffer/FIFO underrun 




enumerator kI3C_SlaveErrorUnderrunNakFlag

Slave internal from-bus buffer/FIFO underrun and NACK error 




enumerator kI3C_SlaveErrorTermFlag

Terminate error from master 




enumerator kI3C_SlaveErrorInvalidStartFlag

Slave invalid start flag 




enumerator kI3C_SlaveErrorSdrParityFlag

SDR parity error 




enumerator kI3C_SlaveErrorHdrParityFlag

HDR parity error 




enumerator kI3C_SlaveErrorHdrCRCFlag

HDR-DDR CRC error 




enumerator kI3C_SlaveErrorS0S1Flag

S0 or S1 error 




enumerator kI3C_SlaveErrorOverreadFlag

Over-read error 




enumerator kI3C_SlaveErrorOverwriteFlag

Over-write error 






enum _i3c_slave_event

I3C slave.event. 
Values:


enumerator kI3C_SlaveEventNormal

Normal mode. 




enumerator kI3C_SlaveEventIBI

In band interrupt event. 




enumerator kI3C_SlaveEventMasterReq

Master request event. 




enumerator kI3C_SlaveEventHotJoinReq

Hot-join event. 






enum _i3c_slave_activity_state

I3C slave.activity state. 
Values:


enumerator kI3C_SlaveNoLatency

Normal bus operation 




enumerator kI3C_SlaveLatency1Ms

1ms of latency. 




enumerator kI3C_SlaveLatency100Ms

100ms of latency. 




enumerator kI3C_SlaveLatency10S

10s latency. 






enum _i3c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 

Values:


enumerator kI3C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start. 




enumerator kI3C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role). 




enumerator kI3C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveRequiredTransmitEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveStartEvent

A start/repeated start was detected. 




enumerator kI3C_SlaveHDRCommandMatchEvent

Slave Match HDR Command. 




enumerator kI3C_SlaveCompletionEvent

A stop was detected, completing the transfer. 




enumerator kI3C_SlaveRequestSentEvent

Slave request event sent. 




enumerator kI3C_SlaveReceivedCCCEvent

Slave received CCC event, need to handle by application. 




enumerator kI3C_SlaveAllEvents

Bit mask of all available events. 






typedef enum _i3c_slave_event i3c_slave_event_t

I3C slave.event. 




typedef enum _i3c_slave_activity_state i3c_slave_activity_state_t

I3C slave.activity state. 




typedef struct _i3c_slave_config i3c_slave_config_t

Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _i3c_slave_transfer_event i3c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 





typedef struct _i3c_slave_transfer i3c_slave_transfer_t

I3C slave transfer structure. 




typedef struct _i3c_slave_handle i3c_slave_handle_t





typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave non-blocking transfer API. To install a callback, use the I3C_SlaveSetCallback() function after you have created a handle.

Param base:
Base address for the I3C instance on which the event occurred. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle)

Typedef for slave interrupt handler. 




struct _i3c_slave_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableSlave

Whether to enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 







struct _i3c_slave_transfer


#include <fsl_i3c.h>
I3C slave transfer structure. 

Public Members


uint32_t event

Reason the callback is being invoked. 




uint8_t *txData

Transfer buffer 




size_t txDataSize

Transfer size 




uint8_t *rxData

Transfer buffer 




size_t rxDataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 




size_t transferredCount

Number of bytes actually transferred since start or last repeated start. 







struct _i3c_slave_handle


#include <fsl_i3c.h>
I3C slave handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


i3c_slave_transfer_t transfer

I3C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




uint32_t eventMask

Mask of enabled events. 




uint32_t transferredCount

Count of bytes transferred. 




i3c_slave_transfer_callback_t callback

Callback function called at transfer event. 




void *userData

Callback parameter passed to callback. 




size_t txFifoSize

Tx Fifo size 







I3C Slave DMA Driver#


void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C slave DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_SlaveTransferEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_transfer_t *transfer, uint32_t eventMask)

Prepares for a non-blocking DMA-based transaction on the I3C bus. 
The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when there’s bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned with master application to ensure the transfer is executed as expected. Callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
transfer – The pointer to the transfer descriptor. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. The transmit and receive events is not allowed to be enabled. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 
kStatus_Fail – The transaction can’t be set. 







void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)

Abort a slave edma non-blocking transfer in a early time. 

Parameters:

base – I3C peripheral base address 
handle – pointer to i3c_slave_edma_handle_t structure 







void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C slave DMA driver handle. 







typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t





typedef struct _i3c_slave_edma_transfer i3c_slave_edma_transfer_t

I3C slave transfer structure. 




typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave DMA transfer API.

Param base:
Base address for the I3C instance on which the event occurred. 

Param handle:
Pointer to slave DMA transfer handle. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _i3c_slave_edma_transfer


#include <fsl_i3c_edma.h>
I3C slave transfer structure. 

Public Members


uint32_t event

Reason the callback is being invoked. 




uint8_t *txData

Transfer buffer 




size_t txDataSize

Transfer size 




uint8_t *rxData

Transfer buffer 




size_t rxDataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 







struct _i3c_slave_edma_handle


#include <fsl_i3c_edma.h>
I3C slave edma handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base

I3C base pointer. 




i3c_slave_edma_transfer_t transfer

I3C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




bool isDdrMode

Whether this is HDR-DDR transfer. 




uint32_t eventMask

Mask of enabled events. 




i3c_slave_edma_callback_t callback

Callback function called at transfer event. 




edma_handle_t *rxDmaHandle

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle

Handle for transmit DMA channel. 




void *userData

Callback parameter passed to callback. 







IGF: Input Glitch Filter#


FSL_IGF_DRIVER_VERSION

Version 2.0.0. 




enum _igf_filter_type

IGF filter type enumeration. 
The selection item represents the Boolean evaluations. 
Values:


enumerator kIGF_FilterBypass

Bypass filter 




enumerator kIGF_FilterWindowing

Windowing filter 




enumerator kIGF_FilterIntegrating

Integrating filter 




enumerator kIGF_FilterIntegratingHold

Integrating-hold filter 




enumerator kIGF_FilterWindowingPostSample

Windowing with post sample filter 






enum _igf_status_flags

IGF status flags enumeration. 
These flags represent the status bits in the IGF MSR register. 
Values:


enumerator kIGF_StatusWaitingEdge

Filter is active waiting for an edge 




enumerator kIGF_StatusProcessingEdge

Filter is active processing an edge 




enumerator kIGF_StatusRiseNoiseDetected

Noise detected after rising edge 




enumerator kIGF_StatusFallNoiseDetected

Noise detected after falling edge 




enumerator kIGF_StatusInputLevel

Filter input level 




enumerator kIGF_StatusOutputLevel

Filter output level 






typedef enum _igf_filter_type igf_filter_type_t

IGF filter type enumeration. 
The selection item represents the Boolean evaluations. 




typedef enum _igf_status_flags igf_status_flags_t

IGF status flags enumeration. 
These flags represent the status bits in the IGF MSR register. 




typedef struct _igf_config igf_config_t

IGF configuration structure. 




void IGF_Init(IGF_Type *base)

Initializes the IGF module with user configuration. 

Parameters:

base – IGF peripheral base address. 
config – Pointer to user-defined configuration structure. 







void IGF_Deinit(IGF_Type *base)

Deinitializes the IGF module. 

Parameters:

base – IGF peripheral base address. 







void IGF_GetDefaultConfig(igf_config_t *config)

Gets the default configuration for IGF. 

Parameters:

config – Pointer to configuration structure to populate. 







void IGF_Enable(IGF_Type *base, uint32_t channel, bool enable)

Enables or disables the IGF filter. 

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
enable – True to enable, false to disable. 







uint32_t IGF_GetStatusFlags(IGF_Type *base, uint32_t channel)

Gets the status flags from IGF module. 

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 


Returns:
Status flags. 






void IGF_ClearStatusFlags(IGF_Type *base, uint32_t channel, uint32_t mask)

Clears the specified status flags. 

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
mask – Mask of status flags to clear. 







void IGF_SetIgfConfig(IGF_Type *base, uint32_t channel, const igf_config_t *config)

Set the IGF module with the specified configuration. 
This function config IGF module.

Parameters:

base – IGF peripheral address. 
channel – IGF corresponding pin channel value. 
config – Pointer to configuration structure. 







static inline void IGF_SetOutputPolarity(IGF_Type *base, uint32_t channel, bool invertPolarity)

Sets the output polarity of the IGF filter. 
Note This function should be called when the filter is disabled.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
invertPolarity – True to invert output, false for normal polarity. 







static inline void IGF_SetImmediatePropagation(IGF_Type *base, uint32_t channel, bool enable)

Sets the immediate propagation mode. 
Note This function should be called when the filter is disabled.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
enable – True to enable immediate propagation, false to use prescaler. 







static inline void IGF_SelectPrescalerSource(IGF_Type *base, uint32_t channel, bool external)

Selects the prescaler source. 
Note This function should be called when the filter is disabled.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
external – True to use external prescaler, false for internal. 







static inline void IGF_SetRisingEdgeFilter(IGF_Type *base, uint32_t channel, igf_filter_type_t type)

Sets the rising edge filter type. 
Note This function should be called when the filter is disabled.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
type – Filter type for rising edge. 







static inline void IGF_SetFallingEdgeFilter(IGF_Type *base, uint32_t channel, igf_filter_type_t type)

Sets the falling edge filter type. 
Note This function should be called when the filter is disabled.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
type – Filter type for falling edge. 







static inline void IGF_SetPrescaler(IGF_Type *base, uint32_t channel, uint32_t value)

Sets the prescaler value. 
This function sets the prescaler value for the IGF filter.

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
value – Prescaler value. 







static inline void IGF_SetRisingThreshold(IGF_Type *base, uint32_t channel, uint32_t threshold)

Sets the rising edge threshold. 

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
threshold – Rising edge threshold value. 







static inline void IGF_SetFallingThreshold(IGF_Type *base, uint32_t channel, uint32_t threshold)

Sets the falling edge threshold. 

Parameters:

base – IGF peripheral base address. 
channel – IGF corresponding pin channel value. 
threshold – Falling edge threshold value. 







struct _igf_config


#include <fsl_igf.h>
IGF configuration structure. 

Public Members


bool enableFilter

Enable or disable the filter 




bool invertOutput

Invert the output signal 




bool immediatePropagation

Immediate edge propagation 




bool useExternalPrescaler

Use external prescaler 




uint32_t prescaler

Prescaler value 




igf_filter_type_t risingEdgeFilter

Filter type for rising edge 




igf_filter_type_t fallingEdgeFilter

Filter type for falling edge 




uint32_t risingThreshold

Threshold for rising edge 




uint32_t fallingThreshold

Threshold for falling edge 







IOMUXC: IOMUX Controller#


static inline void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)

Sets the IOMUXC pin mux mode. 

Note
The first five parameters can be filled with the pin function ID macros.


Parameters:

muxRegister – The pin mux register 
muxMode – The pin mux mode 
inputRegister – The select input register 
inputDaisy – The input daisy 
configRegister – The config register 
inputOn – The software input on 







static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)

Sets the IOMUXC pin configuration. 

Note
The previous five parameters can be filled with the pin function ID macros.


Parameters:

muxRegister – The pin mux register 
muxMode – The pin mux mode 
inputRegister – The select input register 
inputDaisy – The input daisy 
configRegister – The config register 
configValue – The pin config value 







FSL_IOMUXC_DRIVER_VERSION

IOMUXC driver version 1.0.0. 




IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI





IOMUXC_PAD_DAP_TDI__MQS2_LEFT





IOMUXC_PAD_DAP_TDI__ECAT_LED_ERR





IOMUXC_PAD_DAP_TDI__CAN2_TX





IOMUXC_PAD_DAP_TDI__SINC_FILTER_GLUE3_BREAK





IOMUXC_PAD_DAP_TDI__GPIO4_IO4





IOMUXC_PAD_DAP_TDI__LPUART5_RX





IOMUXC_PAD_DAP_TDI__XBAR1_XBAR_INOUT26





IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS





IOMUXC_PAD_DAP_TMS_SWDIO__CAN5_TX





IOMUXC_PAD_DAP_TMS_SWDIO__GPT_MUX_INOUT10





IOMUXC_PAD_DAP_TMS_SWDIO__LPUART8_TX





IOMUXC_PAD_DAP_TMS_SWDIO__SINC3_MOD_CLK1





IOMUXC_PAD_DAP_TMS_SWDIO__GPIO4_IO5





IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B





IOMUXC_PAD_DAP_TMS_SWDIO__XBAR1_XBAR_INOUT27





IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK





IOMUXC_PAD_DAP_TCLK_SWCLK__CAN5_RX





IOMUXC_PAD_DAP_TCLK_SWCLK__GPT_MUX_INOUT11





IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART8_RX





IOMUXC_PAD_DAP_TCLK_SWCLK__SINC3_MOD_CLK0





IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO4_IO6





IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B





IOMUXC_PAD_DAP_TCLK_SWCLK__XBAR1_XBAR_INOUT28





IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO





IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT





IOMUXC_PAD_DAP_TDO_TRACESWO__ECAT_RESET_OUT





IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX





IOMUXC_PAD_DAP_TDO_TRACESWO__SINC3_MOD_CLK2





IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO4_IO7





IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX





IOMUXC_PAD_DAP_TDO_TRACESWO__XBAR1_XBAR_INOUT29





IOMUXC_PAD_GPIO_IO00__GPIO2_IO0





IOMUXC_PAD_GPIO_IO00__I3C2_PUR





IOMUXC_PAD_GPIO_IO00__XBAR1_XBAR_INOUT39





IOMUXC_PAD_GPIO_IO00__I3C2_PUR_B





IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0





IOMUXC_PAD_GPIO_IO00__LPUART5_TX





IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA





IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO0





IOMUXC_PAD_GPIO_IO01__GPIO2_IO1





IOMUXC_PAD_GPIO_IO01__I3C2_SCL





IOMUXC_PAD_GPIO_IO01__XBAR1_XBAR_INOUT40





IOMUXC_PAD_GPIO_IO01__EWM_OUT_B





IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN





IOMUXC_PAD_GPIO_IO01__LPUART5_RX





IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL





IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO1





IOMUXC_PAD_GPIO_IO02__GPIO2_IO2





IOMUXC_PAD_GPIO_IO02__I3C2_SDA





IOMUXC_PAD_GPIO_IO02__XBAR1_XBAR_INOUT41





IOMUXC_PAD_GPIO_IO02__GPT_MUX_INOUT1





IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT





IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B





IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA





IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO2





IOMUXC_PAD_GPIO_IO03__GPIO2_IO3





IOMUXC_PAD_GPIO_IO03__EWM_OUT_B





IOMUXC_PAD_GPIO_IO03__XBAR1_XBAR_INOUT42





IOMUXC_PAD_GPIO_IO03__GPT_MUX_INOUT4





IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK





IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B





IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL





IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO3





IOMUXC_PAD_GPIO_IO04__GPIO2_IO4





IOMUXC_PAD_GPIO_IO04__TPM3_CH0





IOMUXC_PAD_GPIO_IO04__PDM_CLK





IOMUXC_PAD_GPIO_IO04__GPT_MUX_INOUT5





IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0





IOMUXC_PAD_GPIO_IO04__LPUART6_TX





IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA





IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO4





IOMUXC_PAD_GPIO_IO05__GPIO2_IO5





IOMUXC_PAD_GPIO_IO05__TPM4_CH0





IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM0





IOMUXC_PAD_GPIO_IO05__GPT_MUX_INOUT7





IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN





IOMUXC_PAD_GPIO_IO05__LPUART6_RX





IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL





IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO5





IOMUXC_PAD_GPIO_IO06__GPIO2_IO6





IOMUXC_PAD_GPIO_IO06__TPM5_CH0





IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM1





IOMUXC_PAD_GPIO_IO06__GPT_MUX_INOUT8





IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT





IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B





IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA





IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO6





IOMUXC_PAD_GPIO_IO07__GPIO2_IO7





IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1





IOMUXC_PAD_GPIO_IO07__XBAR1_XBAR_INOUT43





IOMUXC_PAD_GPIO_IO07__GPT_MUX_INOUT3





IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK





IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B





IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL





IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO7





IOMUXC_PAD_GPIO_IO08__GPIO2_IO8





IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0





IOMUXC_PAD_GPIO_IO08__USDHC2_WP





IOMUXC_PAD_GPIO_IO08__GPT_MUX_INOUT2





IOMUXC_PAD_GPIO_IO08__TPM6_CH0





IOMUXC_PAD_GPIO_IO08__LPUART7_TX





IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA





IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO8





IOMUXC_PAD_GPIO_IO09__GPIO2_IO9





IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN





IOMUXC_PAD_GPIO_IO09__XBAR1_XBAR_INOUT44





IOMUXC_PAD_GPIO_IO09__GPT_MUX_INOUT0





IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK





IOMUXC_PAD_GPIO_IO09__LPUART7_RX





IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL





IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO9





IOMUXC_PAD_GPIO_IO10__GPIO2_IO10





IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT





IOMUXC_PAD_GPIO_IO10__XBAR1_XBAR_INOUT45





IOMUXC_PAD_GPIO_IO10__GPT_MUX_INOUT6





IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK





IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B





IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA





IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10





IOMUXC_PAD_GPIO_IO11__GPIO2_IO11





IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK





IOMUXC_PAD_GPIO_IO11__XBAR1_XBAR_INOUT46





IOMUXC_PAD_GPIO_IO11__GPT_MUX_INOUT9





IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK





IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B





IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL





IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11





IOMUXC_PAD_GPIO_IO12__GPIO2_IO12





IOMUXC_PAD_GPIO_IO12__TPM3_CH2





IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM2





IOMUXC_PAD_GPIO_IO12__FLEXIO1_FLEXIO12





IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0





IOMUXC_PAD_GPIO_IO12__LPUART8_TX





IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA





IOMUXC_PAD_GPIO_IO13__GPIO2_IO13





IOMUXC_PAD_GPIO_IO13__TPM4_CH2





IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM3





IOMUXC_PAD_GPIO_IO13__XBAR1_XBAR_INOUT47





IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN





IOMUXC_PAD_GPIO_IO13__LPUART8_RX





IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL





IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13





IOMUXC_PAD_GPIO_IO14__GPIO2_IO14





IOMUXC_PAD_GPIO_IO14__LPUART10_CTS_B





IOMUXC_PAD_GPIO_IO14__ECAT_SDA





IOMUXC_PAD_GPIO_IO14__XBAR1_XBAR_INOUT48





IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT





IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B





IOMUXC_PAD_GPIO_IO14__LPUART4_TX





IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14





IOMUXC_PAD_GPIO_IO15__GPIO2_IO15





IOMUXC_PAD_GPIO_IO15__LPUART10_RTS_B





IOMUXC_PAD_GPIO_IO15__ECAT_SCL





IOMUXC_PAD_GPIO_IO15__XBAR1_XBAR_INOUT8





IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK





IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B





IOMUXC_PAD_GPIO_IO15__LPUART4_RX





IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15





IOMUXC_PAD_GPIO_IO16__GPIO2_IO16





IOMUXC_PAD_GPIO_IO16__LPI2C3_SDA





IOMUXC_PAD_GPIO_IO16__CAN3_TX





IOMUXC_PAD_GPIO_IO16__EWM_OUT_B





IOMUXC_PAD_GPIO_IO16__LPUART11_TX





IOMUXC_PAD_GPIO_IO16__GPT_MUX_INOUT0





IOMUXC_PAD_GPIO_IO16__FLEXPWM4_PWMA0





IOMUXC_PAD_GPIO_IO16__XBAR1_XBAR_INOUT30





IOMUXC_PAD_GPIO_IO17__GPIO2_IO17





IOMUXC_PAD_GPIO_IO17__LPI2C3_SCL





IOMUXC_PAD_GPIO_IO17__CAN3_RX





IOMUXC_PAD_GPIO_IO17__LPI2C6_HREQ





IOMUXC_PAD_GPIO_IO17__LPUART11_RX





IOMUXC_PAD_GPIO_IO17__GPT_MUX_INOUT3





IOMUXC_PAD_GPIO_IO17__FLEXPWM4_PWMB0





IOMUXC_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31





IOMUXC_PAD_GPIO_IO17__XSPI1_IPP_IND_INTFA_B





IOMUXC_PAD_GPIO_IO18__GPIO2_IO18





IOMUXC_PAD_GPIO_IO18__LPI2C4_SDA





IOMUXC_PAD_GPIO_IO18__LPUART10_TX





IOMUXC_PAD_GPIO_IO18__LPI2C7_HREQ





IOMUXC_PAD_GPIO_IO18__LPUART11_CTS_B





IOMUXC_PAD_GPIO_IO18__GPT_MUX_INOUT6





IOMUXC_PAD_GPIO_IO18__FLEXPWM4_PWMA1





IOMUXC_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32





IOMUXC_PAD_GPIO_IO18__USB1_OTG_OC





IOMUXC_PAD_GPIO_IO19__GPIO2_IO19





IOMUXC_PAD_GPIO_IO19__LPI2C4_SCL





IOMUXC_PAD_GPIO_IO19__LPUART10_RX





IOMUXC_PAD_GPIO_IO19__LPI2C8_HREQ





IOMUXC_PAD_GPIO_IO19__LPUART11_RTS_B





IOMUXC_PAD_GPIO_IO19__GPT_MUX_INOUT9





IOMUXC_PAD_GPIO_IO19__FLEXPWM4_PWMB1





IOMUXC_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33





IOMUXC_PAD_GPIO_IO19__USB2_OTG_OC





IOMUXC_PAD_GPIO_IO20__GPIO2_IO20





IOMUXC_PAD_GPIO_IO20__PCIE1_CLKREQ_B





IOMUXC_PAD_GPIO_IO20__LPUART6_TX





IOMUXC_PAD_GPIO_IO20__LPI2C8_SDA





IOMUXC_PAD_GPIO_IO20__LPSPI4_PCS2





IOMUXC_PAD_GPIO_IO20__LPSPI3_PCS1





IOMUXC_PAD_GPIO_IO20__FLEXPWM4_PWMA2





IOMUXC_PAD_GPIO_IO20__XBAR1_XBAR_INOUT34





IOMUXC_PAD_GPIO_IO21__GPIO2_IO21





IOMUXC_PAD_GPIO_IO21__SAI2_TX_BCLK





IOMUXC_PAD_GPIO_IO21__LPUART6_RX





IOMUXC_PAD_GPIO_IO21__LPI2C8_SCL





IOMUXC_PAD_GPIO_IO21__LPSPI4_PCS1





IOMUXC_PAD_GPIO_IO21__LPI2C3_HREQ





IOMUXC_PAD_GPIO_IO21__FLEXPWM4_PWMB2





IOMUXC_PAD_GPIO_IO21__XBAR1_XBAR_INOUT35





IOMUXC_PAD_GPIO_IO22__GPIO2_IO22





IOMUXC_PAD_GPIO_IO22__SAI2_MCLK





IOMUXC_PAD_GPIO_IO22__LPUART6_CTS_B





IOMUXC_PAD_GPIO_IO22__XBAR1_XBAR_INOUT9





IOMUXC_PAD_GPIO_IO22__LPSPI4_PCS0





IOMUXC_PAD_GPIO_IO22__FLEXPWM3_PWMA3





IOMUXC_PAD_GPIO_IO22__FLEXPWM4_PWMA3





IOMUXC_PAD_GPIO_IO22__SINC4_EMCLK0





IOMUXC_PAD_GPIO_IO23__GPIO2_IO23





IOMUXC_PAD_GPIO_IO23__PCIE2_CLKREQ_B





IOMUXC_PAD_GPIO_IO23__LPUART6_RTS_B





IOMUXC_PAD_GPIO_IO23__XBAR1_XBAR_INOUT10





IOMUXC_PAD_GPIO_IO23__LPSPI4_SIN





IOMUXC_PAD_GPIO_IO23__FLEXPWM3_PWMB3





IOMUXC_PAD_GPIO_IO23__FLEXPWM4_PWMB3





IOMUXC_PAD_GPIO_IO23__SINC4_EMBIT0





IOMUXC_PAD_GPIO_IO24__GPIO2_IO24





IOMUXC_PAD_GPIO_IO24__SAI2_RX_BCLK





IOMUXC_PAD_GPIO_IO24__LPUART11_TX





IOMUXC_PAD_GPIO_IO24__LPI2C3_HREQ





IOMUXC_PAD_GPIO_IO24__LPSPI4_SOUT





IOMUXC_PAD_GPIO_IO24__SINC_FILTER_GLUE2_BREAK





IOMUXC_PAD_GPIO_IO24__FLEXPWM4_PWMX0





IOMUXC_PAD_GPIO_IO24__XBAR1_XBAR_INOUT36





IOMUXC_PAD_GPIO_IO25__GPIO2_IO25





IOMUXC_PAD_GPIO_IO25__SAI2_RX_SYNC





IOMUXC_PAD_GPIO_IO25__LPUART11_RX





IOMUXC_PAD_GPIO_IO25__LPI2C4_HREQ





IOMUXC_PAD_GPIO_IO25__LPSPI4_SCK





IOMUXC_PAD_GPIO_IO25__SINC_FILTER_GLUE1_BREAK





IOMUXC_PAD_GPIO_IO25__FLEXPWM4_PWMX1





IOMUXC_PAD_GPIO_IO25__XBAR1_XBAR_INOUT37





IOMUXC_PAD_GPIO_IO26__GPIO2_IO26





IOMUXC_PAD_GPIO_IO26__LPI2C5_SCL





IOMUXC_PAD_GPIO_IO26__LPUART12_TX





IOMUXC_PAD_GPIO_IO26__GPT_MUX_INOUT4





IOMUXC_PAD_GPIO_IO26__FLEXIO1_3_1_FLEXIO0





IOMUXC_PAD_GPIO_IO26__SAI2_RX_DATA0





IOMUXC_PAD_GPIO_IO26__FLEXPWM4_PWMX2





IOMUXC_PAD_GPIO_IO26__XBAR1_XBAR_INOUT38





IOMUXC_PAD_GPIO_IO27__GPIO2_IO27





IOMUXC_PAD_GPIO_IO27__LPI2C5_SDA





IOMUXC_PAD_GPIO_IO27__LPUART12_RX





IOMUXC_PAD_GPIO_IO27__GPT_MUX_INOUT5





IOMUXC_PAD_GPIO_IO27__FLEXIO1_3_1_FLEXIO1





IOMUXC_PAD_GPIO_IO27__SAI2_TX_DATA0





IOMUXC_PAD_GPIO_IO27__FLEXPWM4_PWMX3





IOMUXC_PAD_GPIO_IO27__SINC4_MOD_CLK0





IOMUXC_PAD_GPIO_IO28__GPIO2_IO28





IOMUXC_PAD_GPIO_IO28__LPI2C6_SCL





IOMUXC_PAD_GPIO_IO28__LPUART12_CTS_B





IOMUXC_PAD_GPIO_IO28__GPT_MUX_INOUT7





IOMUXC_PAD_GPIO_IO28__FLEXIO1_3_1_FLEXIO2





IOMUXC_PAD_GPIO_IO28__SAI2_TX_SYNC





IOMUXC_PAD_GPIO_IO28__FLEXPWM1_PWMX2





IOMUXC_PAD_GPIO_IO28__XBAR1_XBAR_INOUT4





IOMUXC_PAD_GPIO_IO29__GPIO2_IO29





IOMUXC_PAD_GPIO_IO29__LPI2C6_SDA





IOMUXC_PAD_GPIO_IO29__LPUART12_RTS_B





IOMUXC_PAD_GPIO_IO29__I3C2_SDA





IOMUXC_PAD_GPIO_IO29__FLEXIO1_3_1_FLEXIO3





IOMUXC_PAD_GPIO_IO29__FLEXPWM3_PWMX0





IOMUXC_PAD_GPIO_IO29__FLEXPWM1_PWMX3





IOMUXC_PAD_GPIO_IO29__XBAR1_XBAR_INOUT5





IOMUXC_PAD_GPIO_IO30__GPIO2_IO30





IOMUXC_PAD_GPIO_IO30__LPIT2_TRIGGER0





IOMUXC_PAD_GPIO_IO30__LPUART3_TX





IOMUXC_PAD_GPIO_IO30__I3C2_PUR





IOMUXC_PAD_GPIO_IO30__FLEXIO1_3_1_FLEXIO4





IOMUXC_PAD_GPIO_IO30__I3C2_PUR_B





IOMUXC_PAD_GPIO_IO30__FLEXPWM2_PWMX2





IOMUXC_PAD_GPIO_IO30__XBAR1_XBAR_INOUT6





IOMUXC_PAD_GPIO_IO31__GPIO2_IO31





IOMUXC_PAD_GPIO_IO31__LPIT2_TRIGGER1





IOMUXC_PAD_GPIO_IO31__LPUART3_RX





IOMUXC_PAD_GPIO_IO31__I3C2_SCL





IOMUXC_PAD_GPIO_IO31__FLEXIO1_3_1_FLEXIO5





IOMUXC_PAD_GPIO_IO31__FLEXPWM3_PWMX1





IOMUXC_PAD_GPIO_IO31__FLEXPWM2_PWMX3





IOMUXC_PAD_GPIO_IO31__XBAR1_XBAR_INOUT7





IOMUXC_PAD_GPIO_IO32__GPIO3_IO0





IOMUXC_PAD_GPIO_IO32__LPIT3_TRIGGER0





IOMUXC_PAD_GPIO_IO32__LPUART7_TX





IOMUXC_PAD_GPIO_IO32__GPT_MUX_INOUT8





IOMUXC_PAD_GPIO_IO32__FLEXIO1_3_1_FLEXIO6





IOMUXC_PAD_GPIO_IO32__FLEXPWM3_PWMA0





IOMUXC_PAD_GPIO_IO32__SINC_FILTER_GLUE2_BREAK





IOMUXC_PAD_GPIO_IO32__XBAR1_XBAR_INOUT8





IOMUXC_PAD_GPIO_IO33__GPIO3_IO1





IOMUXC_PAD_GPIO_IO33__LPIT3_TRIGGER1





IOMUXC_PAD_GPIO_IO33__LPUART7_RX





IOMUXC_PAD_GPIO_IO33__GPT_MUX_INOUT1





IOMUXC_PAD_GPIO_IO33__FLEXIO1_3_1_FLEXIO7





IOMUXC_PAD_GPIO_IO33__FLEXPWM3_PWMB0





IOMUXC_PAD_GPIO_IO33__SINC_FILTER_GLUE1_BREAK





IOMUXC_PAD_GPIO_IO33__XBAR1_XBAR_INOUT9





IOMUXC_PAD_GPIO_IO34__GPIO3_IO2





IOMUXC_PAD_GPIO_IO34__LPI2C7_SDA





IOMUXC_PAD_GPIO_IO34__CAN2_TX





IOMUXC_PAD_GPIO_IO34__ECAT_SDA





IOMUXC_PAD_GPIO_IO34__FLEXIO1_3_1_FLEXIO8





IOMUXC_PAD_GPIO_IO34__FLEXPWM3_PWMA1





IOMUXC_PAD_GPIO_IO34__FLEXPWM1_PWMX0





IOMUXC_PAD_GPIO_IO34__XBAR1_XBAR_INOUT10





IOMUXC_PAD_GPIO_IO35__GPIO3_IO3





IOMUXC_PAD_GPIO_IO35__LPI2C7_SCL





IOMUXC_PAD_GPIO_IO35__CAN2_RX





IOMUXC_PAD_GPIO_IO35__ECAT_SCL





IOMUXC_PAD_GPIO_IO35__FLEXIO1_3_1_FLEXIO9





IOMUXC_PAD_GPIO_IO35__FLEXPWM3_PWMB1





IOMUXC_PAD_GPIO_IO35__FLEXPWM1_PWMX1





IOMUXC_PAD_GPIO_IO35__XBAR1_XBAR_INOUT11





IOMUXC_PAD_GPIO_IO36__USDHC2_WP





IOMUXC_PAD_GPIO_IO36__FLEXIO1_3_1_FLEXIO10





IOMUXC_PAD_GPIO_IO36__FLEXPWM3_PWMA2





IOMUXC_PAD_GPIO_IO36__FLEXPWM2_PWMX0





IOMUXC_PAD_GPIO_IO36__XBAR1_XBAR_INOUT12





IOMUXC_PAD_GPIO_IO36__GPIO3_IO4





IOMUXC_PAD_GPIO_IO36__LPI2C8_SDA





IOMUXC_PAD_GPIO_IO36__CAN4_TX





IOMUXC_PAD_GPIO_IO37__GPIO3_IO5





IOMUXC_PAD_GPIO_IO37__LPI2C8_SCL





IOMUXC_PAD_GPIO_IO37__CAN4_RX





IOMUXC_PAD_GPIO_IO37__LPI2C5_HREQ





IOMUXC_PAD_GPIO_IO37__FLEXIO1_3_1_FLEXIO11





IOMUXC_PAD_GPIO_IO37__FLEXPWM3_PWMB2





IOMUXC_PAD_GPIO_IO37__FLEXPWM2_PWMX1





IOMUXC_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13





IOMUXC_PAD_GPIO_IO37__XSPI1_IPP_IND_INTFA_B





IOMUXC_PAD_GPIO_IO38__GPIO3_IO6





IOMUXC_PAD_GPIO_IO38__NETC_1588MUX_INOUT0





IOMUXC_PAD_GPIO_IO38__LPI2C3_SDA





IOMUXC_PAD_GPIO_IO38__LPIT3_TRIGGER2





IOMUXC_PAD_GPIO_IO38__FLEXIO1_3_1_FLEXIO12





IOMUXC_PAD_GPIO_IO38__LPUART3_CTS_B





IOMUXC_PAD_GPIO_IO38__FLEXPWM3_PWMX0





IOMUXC_PAD_GPIO_IO38__XBAR1_XBAR_INOUT14





IOMUXC_PAD_GPIO_IO39__GPIO3_IO7





IOMUXC_PAD_GPIO_IO39__NETC_1588MUX_INOUT1





IOMUXC_PAD_GPIO_IO39__LPI2C3_SCL





IOMUXC_PAD_GPIO_IO39__LPIT2_TRIGGER2





IOMUXC_PAD_GPIO_IO39__FLEXIO1_3_1_FLEXIO13





IOMUXC_PAD_GPIO_IO39__LPUART3_RTS_B





IOMUXC_PAD_GPIO_IO39__FLEXPWM3_PWMX1





IOMUXC_PAD_GPIO_IO39__XBAR1_XBAR_INOUT15





IOMUXC_PAD_GPIO_IO40__GPIO3_IO8





IOMUXC_PAD_GPIO_IO40__NETC_1588MUX_INOUT2





IOMUXC_PAD_GPIO_IO40__LPI2C7_SDA





IOMUXC_PAD_GPIO_IO40__LPUART4_TX





IOMUXC_PAD_GPIO_IO40__FLEXIO1_3_1_FLEXIO14





IOMUXC_PAD_GPIO_IO40__FLEXPWM3_PWMX2





IOMUXC_PAD_GPIO_IO40__FLEXPWM4_PWMX0





IOMUXC_PAD_GPIO_IO40__XBAR1_XBAR_INOUT16





IOMUXC_PAD_GPIO_IO41__GPIO3_IO9





IOMUXC_PAD_GPIO_IO41__NETC_1588MUX_INOUT3





IOMUXC_PAD_GPIO_IO41__LPI2C7_SCL





IOMUXC_PAD_GPIO_IO41__LPUART4_RX





IOMUXC_PAD_GPIO_IO41__FLEXIO1_3_1_FLEXIO15





IOMUXC_PAD_GPIO_IO41__LPI2C6_HREQ





IOMUXC_PAD_GPIO_IO41__FLEXPWM4_PWMX1





IOMUXC_PAD_GPIO_IO41__XBAR1_XBAR_INOUT17





IOMUXC_PAD_GPIO_IO42__GPIO3_IO10





IOMUXC_PAD_GPIO_IO42__SAI3_TX_BCLK





IOMUXC_PAD_GPIO_IO42__PDM_BIT_STREAM2





IOMUXC_PAD_GPIO_IO42__XBAR1_XBAR_INOUT11





IOMUXC_PAD_GPIO_IO42__LPUART3_TX





IOMUXC_PAD_GPIO_IO42__LPSPI4_PCS2





IOMUXC_PAD_GPIO_IO42__LPUART4_CTS_B





IOMUXC_PAD_GPIO_IO42__SINC4_EMCLK1





IOMUXC_PAD_GPIO_IO43__GPIO3_IO11





IOMUXC_PAD_GPIO_IO43__SAI3_MCLK





IOMUXC_PAD_GPIO_IO43__XBAR1_XBAR_INOUT12





IOMUXC_PAD_GPIO_IO43__LPUART3_RX





IOMUXC_PAD_GPIO_IO43__LPSPI3_PCS1





IOMUXC_PAD_GPIO_IO43__LPUART4_RTS_B





IOMUXC_PAD_GPIO_IO43__SINC4_EMBIT1





IOMUXC_PAD_GPIO_IO44__GPIO3_IO12





IOMUXC_PAD_GPIO_IO44__SAI3_RX_BCLK





IOMUXC_PAD_GPIO_IO44__PDM_BIT_STREAM1





IOMUXC_PAD_GPIO_IO44__LPUART9_TX





IOMUXC_PAD_GPIO_IO44__LPSPI5_PCS0





IOMUXC_PAD_GPIO_IO44__LPI2C3_SDA





IOMUXC_PAD_GPIO_IO44__TPM5_CH2





IOMUXC_PAD_GPIO_IO44__SINC_FILTER_GLUE4_BREAK





IOMUXC_PAD_GPIO_IO45__GPIO3_IO13





IOMUXC_PAD_GPIO_IO45__SAI3_RX_SYNC





IOMUXC_PAD_GPIO_IO45__PDM_BIT_STREAM3





IOMUXC_PAD_GPIO_IO45__LPUART9_RX





IOMUXC_PAD_GPIO_IO45__LPSPI5_SIN





IOMUXC_PAD_GPIO_IO45__LPI2C3_SCL





IOMUXC_PAD_GPIO_IO45__TPM6_CH2





IOMUXC_PAD_GPIO_IO45__SAI3_TX_DATA0





IOMUXC_PAD_GPIO_IO46__GPIO3_IO14





IOMUXC_PAD_GPIO_IO46__SAI3_RX_DATA0





IOMUXC_PAD_GPIO_IO46__PDM_BIT_STREAM0





IOMUXC_PAD_GPIO_IO46__LPUART9_CTS_B





IOMUXC_PAD_GPIO_IO46__LPSPI5_SOUT





IOMUXC_PAD_GPIO_IO46__LPI2C4_SDA





IOMUXC_PAD_GPIO_IO46__TPM3_CH1





IOMUXC_PAD_GPIO_IO46__EWM_OUT_B





IOMUXC_PAD_GPIO_IO47__GPIO3_IO15





IOMUXC_PAD_GPIO_IO47__SAI3_TX_DATA0





IOMUXC_PAD_GPIO_IO47__PDM_CLK





IOMUXC_PAD_GPIO_IO47__LPUART9_RTS_B





IOMUXC_PAD_GPIO_IO47__LPSPI5_SCK





IOMUXC_PAD_GPIO_IO47__LPI2C4_SCL





IOMUXC_PAD_GPIO_IO47__TPM4_CH1





IOMUXC_PAD_GPIO_IO47__SAI3_RX_BCLK





IOMUXC_PAD_GPIO_IO48__GPIO3_IO16





IOMUXC_PAD_GPIO_IO48__USDHC3_CLK





IOMUXC_PAD_GPIO_IO48__CAN5_TX





IOMUXC_PAD_GPIO_IO48__LPUART10_TX





IOMUXC_PAD_GPIO_IO48__TPM5_CH1





IOMUXC_PAD_GPIO_IO48__TPM6_EXTCLK





IOMUXC_PAD_GPIO_IO48__LPI2C5_SDA





IOMUXC_PAD_GPIO_IO48__SINC4_EMCLK2





IOMUXC_PAD_GPIO_IO49__GPIO3_IO17





IOMUXC_PAD_GPIO_IO49__USDHC3_CMD





IOMUXC_PAD_GPIO_IO49__CAN5_RX





IOMUXC_PAD_GPIO_IO49__LPUART10_RX





IOMUXC_PAD_GPIO_IO49__TPM6_CH1





IOMUXC_PAD_GPIO_IO49__XBAR1_XBAR_INOUT13





IOMUXC_PAD_GPIO_IO49__LPI2C5_SCL





IOMUXC_PAD_GPIO_IO49__SINC4_EMBIT2





IOMUXC_PAD_GPIO_IO50__GPIO3_IO18





IOMUXC_PAD_GPIO_IO50__USDHC3_DATA0





IOMUXC_PAD_GPIO_IO50__XBAR1_XBAR_INOUT14





IOMUXC_PAD_GPIO_IO50__LPUART10_CTS_B





IOMUXC_PAD_GPIO_IO50__TPM3_CH3





IOMUXC_PAD_GPIO_IO50__JTAG_MUX_TDO





IOMUXC_PAD_GPIO_IO50__LPSPI6_PCS1





IOMUXC_PAD_GPIO_IO50__SINC4_EMCLK3





IOMUXC_PAD_GPIO_IO51__GPIO3_IO19





IOMUXC_PAD_GPIO_IO51__USDHC3_DATA1





IOMUXC_PAD_GPIO_IO51__CAN2_TX





IOMUXC_PAD_GPIO_IO51__LPUART10_RTS_B





IOMUXC_PAD_GPIO_IO51__TPM4_CH3





IOMUXC_PAD_GPIO_IO51__JTAG_MUX_TCK





IOMUXC_PAD_GPIO_IO51__LPSPI7_PCS1





IOMUXC_PAD_GPIO_IO51__SINC4_EMBIT3





IOMUXC_PAD_GPIO_IO52__GPIO3_IO20





IOMUXC_PAD_GPIO_IO52__USDHC3_DATA2





IOMUXC_PAD_GPIO_IO52__PDM_BIT_STREAM1





IOMUXC_PAD_GPIO_IO52__LPSPI4_PCS2





IOMUXC_PAD_GPIO_IO52__TPM5_CH3





IOMUXC_PAD_GPIO_IO52__JTAG_MUX_TDI





IOMUXC_PAD_GPIO_IO52__LPSPI8_PCS1





IOMUXC_PAD_GPIO_IO52__SAI3_TX_SYNC





IOMUXC_PAD_GPIO_IO53__GPIO3_IO21





IOMUXC_PAD_GPIO_IO53__USDHC3_DATA3





IOMUXC_PAD_GPIO_IO53__CAN2_RX





IOMUXC_PAD_GPIO_IO53__LPSPI3_PCS1





IOMUXC_PAD_GPIO_IO53__TPM6_CH3





IOMUXC_PAD_GPIO_IO53__JTAG_MUX_TMS





IOMUXC_PAD_GPIO_IO53__LPSPI5_PCS1





IOMUXC_PAD_GPIO_IO53__SINC4_MOD_CLK1





IOMUXC_PAD_GPIO_IO54__GPIO3_IO22





IOMUXC_PAD_GPIO_IO54__NETC_1588MUX_INOUT4





IOMUXC_PAD_GPIO_IO54__CAN4_TX





IOMUXC_PAD_GPIO_IO54__LPIT3_TRIGGER2





IOMUXC_PAD_GPIO_IO54__LPSPI6_PCS1





IOMUXC_PAD_GPIO_IO54__TPM3_CH3





IOMUXC_PAD_GPIO_IO54__SINC3_EMCLK0





IOMUXC_PAD_GPIO_IO54__XBAR1_XBAR_INOUT18





IOMUXC_PAD_GPIO_IO55__GPIO3_IO23





IOMUXC_PAD_GPIO_IO55__NETC_1588MUX_INOUT5





IOMUXC_PAD_GPIO_IO55__CAN4_RX





IOMUXC_PAD_GPIO_IO55__LPIT2_TRIGGER2





IOMUXC_PAD_GPIO_IO55__LPSPI7_PCS1





IOMUXC_PAD_GPIO_IO55__TPM4_CH3





IOMUXC_PAD_GPIO_IO55__SINC3_EMBIT0





IOMUXC_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19





IOMUXC_PAD_GPIO_IO55__XSPI1_IPP_IND_INTFA_B





IOMUXC_PAD_GPIO_IO56__GPIO3_IO24





IOMUXC_PAD_GPIO_IO56__NETC_1588MUX_INOUT6





IOMUXC_PAD_GPIO_IO56__CAN5_TX





IOMUXC_PAD_GPIO_IO56__LPIT3_TRIGGER3





IOMUXC_PAD_GPIO_IO56__LPSPI8_PCS1





IOMUXC_PAD_GPIO_IO56__SAI3_TX_SYNC





IOMUXC_PAD_GPIO_IO56__SINC3_EMCLK1





IOMUXC_PAD_GPIO_IO56__XBAR1_XBAR_INOUT20





IOMUXC_PAD_GPIO_IO57__GPIO3_IO25





IOMUXC_PAD_GPIO_IO57__NETC_1588MUX_INOUT7





IOMUXC_PAD_GPIO_IO57__CAN5_RX





IOMUXC_PAD_GPIO_IO57__LPIT2_TRIGGER3





IOMUXC_PAD_GPIO_IO57__LPSPI5_PCS1





IOMUXC_PAD_GPIO_IO57__TPM6_CH3





IOMUXC_PAD_GPIO_IO57__SINC3_EMBIT1





IOMUXC_PAD_GPIO_IO57__ENET_REF_CLK_ROOT





IOMUXC_PAD_GPIO_IO57__XBAR1_XBAR_INOUT21





IOMUXC_PAD_GPIO_IO57__SAI3_RX_SYNC





IOMUXC_PAD_CCM_CLKO1__CLKO_1





IOMUXC_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8





IOMUXC_PAD_CCM_CLKO1__LPUART9_TX





IOMUXC_PAD_CCM_CLKO1__ECAT_LED_RUN





IOMUXC_PAD_CCM_CLKO1__TPM6_EXTCLK





IOMUXC_PAD_CCM_CLKO1__GPIO4_IO0





IOMUXC_PAD_CCM_CLKO1__SINC3_EMCLK2





IOMUXC_PAD_CCM_CLKO1__XBAR1_XBAR_INOUT22





IOMUXC_PAD_CCM_CLKO2__CLKO_2





IOMUXC_PAD_CCM_CLKO2__NETC_1588MUX_INOUT9





IOMUXC_PAD_CCM_CLKO2__LPUART9_RX





IOMUXC_PAD_CCM_CLKO2__ECAT_LED_ERR





IOMUXC_PAD_CCM_CLKO2__TPM5_CH1





IOMUXC_PAD_CCM_CLKO2__GPIO4_IO1





IOMUXC_PAD_CCM_CLKO2__SINC3_EMBIT2





IOMUXC_PAD_CCM_CLKO2__XBAR1_XBAR_INOUT23





IOMUXC_PAD_CCM_CLKO3__CLKO_3





IOMUXC_PAD_CCM_CLKO3__NETC_1588MUX_INOUT10





IOMUXC_PAD_CCM_CLKO3__CAN3_TX





IOMUXC_PAD_CCM_CLKO3__ECAT_LED_STATE_RUN





IOMUXC_PAD_CCM_CLKO3__TPM6_CH1





IOMUXC_PAD_CCM_CLKO3__GPIO4_IO2





IOMUXC_PAD_CCM_CLKO3__SINC3_EMCLK3





IOMUXC_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT





IOMUXC_PAD_CCM_CLKO3__XBAR1_XBAR_INOUT24





IOMUXC_PAD_CCM_CLKO4__CLKO_4





IOMUXC_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11





IOMUXC_PAD_CCM_CLKO4__CAN3_RX





IOMUXC_PAD_CCM_CLKO4__ECAT_RESET_OUT





IOMUXC_PAD_CCM_CLKO4__TPM5_CH3





IOMUXC_PAD_CCM_CLKO4__GPIO4_IO3





IOMUXC_PAD_CCM_CLKO4__SINC3_EMBIT3





IOMUXC_PAD_CCM_CLKO4__XBAR1_XBAR_INOUT25





IOMUXC_PAD_ETH2_MDC_GPIO1__NETC_EMDC





IOMUXC_PAD_ETH2_MDC_GPIO1__NETC_ETH2_SLV_MDC





IOMUXC_PAD_ETH2_MDC_GPIO1__I3C2_SCL





IOMUXC_PAD_ETH2_MDC_GPIO1__USB1_OTG_ID





IOMUXC_PAD_ETH2_MDC_GPIO1__FLEXIO2_FLEXIO0





IOMUXC_PAD_ETH2_MDC_GPIO1__GPIO6_IO0





IOMUXC_PAD_ETH2_MDC_GPIO1__FLEXPWM2_PWMX0





IOMUXC_PAD_ETH2_MDC_GPIO1__XBAR1_XBAR_INOUT30





IOMUXC_PAD_ETH2_MDIO_GPIO2__NETC_EMDIO





IOMUXC_PAD_ETH2_MDIO_GPIO2__NETC_ETH2_SLV_MDIO





IOMUXC_PAD_ETH2_MDIO_GPIO2__I3C2_SDA





IOMUXC_PAD_ETH2_MDIO_GPIO2__USB1_OTG_PWR





IOMUXC_PAD_ETH2_MDIO_GPIO2__FLEXIO2_FLEXIO1





IOMUXC_PAD_ETH2_MDIO_GPIO2__GPIO6_IO1





IOMUXC_PAD_ETH2_MDIO_GPIO2__FLEXPWM2_PWMX1





IOMUXC_PAD_ETH2_MDIO_GPIO2__XBAR1_XBAR_INOUT31





IOMUXC_PAD_ETH2_TXD3__NETC_PINMUX_ETH2_TXD3





IOMUXC_PAD_ETH2_TXD3__LPUART3_DCD_B





IOMUXC_PAD_ETH2_TXD3__CAN2_TX





IOMUXC_PAD_ETH2_TXD3__USB2_OTG_ID





IOMUXC_PAD_ETH2_TXD3__FLEXIO2_FLEXIO2





IOMUXC_PAD_ETH2_TXD3__GPIO6_IO2





IOMUXC_PAD_ETH2_TXD3__FLEXPWM2_PWMA0





IOMUXC_PAD_ETH2_TXD3__XBAR1_XBAR_INOUT32





IOMUXC_PAD_ETH2_TXD2__NETC_PINMUX_ETH2_TXD2





IOMUXC_PAD_ETH2_TXD2__ETH2_RMII_REF50_CLK





IOMUXC_PAD_ETH2_TXD2__CAN2_RX





IOMUXC_PAD_ETH2_TXD2__USB2_OTG_OC





IOMUXC_PAD_ETH2_TXD2__FLEXIO2_FLEXIO3





IOMUXC_PAD_ETH2_TXD2__GPIO6_IO3





IOMUXC_PAD_ETH2_TXD2__FLEXPWM2_PWMB0





IOMUXC_PAD_ETH2_TXD2__XBAR1_XBAR_INOUT33





IOMUXC_PAD_ETH2_TXD1__NETC_PINMUX_ETH2_TXD1





IOMUXC_PAD_ETH2_TXD1__LPUART3_RTS_B





IOMUXC_PAD_ETH2_TXD1__ECAT_CLK25





IOMUXC_PAD_ETH2_TXD1__USB1_OTG_OC





IOMUXC_PAD_ETH2_TXD1__FLEXIO2_FLEXIO4





IOMUXC_PAD_ETH2_TXD1__GPIO6_IO4





IOMUXC_PAD_ETH2_TXD1__FLEXPWM2_PWMA1





IOMUXC_PAD_ETH2_TXD1__XBAR1_XBAR_INOUT34





IOMUXC_PAD_ETH2_TXD0__NETC_PINMUX_ETH2_TXD0





IOMUXC_PAD_ETH2_TXD0__LPUART3_TX





IOMUXC_PAD_ETH2_TXD0__I3C2_PUR





IOMUXC_PAD_ETH2_TXD0__I3C2_PUR_B





IOMUXC_PAD_ETH2_TXD0__FLEXIO2_FLEXIO5





IOMUXC_PAD_ETH2_TXD0__GPIO6_IO5





IOMUXC_PAD_ETH2_TXD0__FLEXPWM2_PWMB1





IOMUXC_PAD_ETH2_TXD0__XBAR1_XBAR_INOUT35





IOMUXC_PAD_ETH2_TX_CTL__NETC_PINMUX_ETH2_TX_CTL





IOMUXC_PAD_ETH2_TX_CTL__LPUART3_DTR_B





IOMUXC_PAD_ETH2_TX_CTL__ECAT_LED_RUN





IOMUXC_PAD_ETH2_TX_CTL__FLEXIO2_FLEXIO6





IOMUXC_PAD_ETH2_TX_CTL__GPIO6_IO6





IOMUXC_PAD_ETH2_TX_CTL__FLEXPWM2_PWMA2





IOMUXC_PAD_ETH2_TX_CTL__XBAR1_XBAR_INOUT36





IOMUXC_PAD_ETH2_TX_CLK__NETC_PINMUX_ETH2_TX_CLK





IOMUXC_PAD_ETH2_TX_CLK__ECAT_LED_ERR





IOMUXC_PAD_ETH2_TX_CLK__FLEXIO2_FLEXIO7





IOMUXC_PAD_ETH2_TX_CLK__GPIO6_IO7





IOMUXC_PAD_ETH2_TX_CLK__FLEXPWM2_PWMB2





IOMUXC_PAD_ETH2_TX_CLK__XBAR1_XBAR_INOUT37





IOMUXC_PAD_ETH2_RX_CTL__NETC_PINMUX_ETH2_RX_CTL





IOMUXC_PAD_ETH2_RX_CTL__LPUART3_DSR_B





IOMUXC_PAD_ETH2_RX_CTL__ECAT_LED_STATE_RUN





IOMUXC_PAD_ETH2_RX_CTL__USB2_OTG_PWR





IOMUXC_PAD_ETH2_RX_CTL__FLEXIO2_FLEXIO8





IOMUXC_PAD_ETH2_RX_CTL__GPIO6_IO8





IOMUXC_PAD_ETH2_RX_CTL__FLEXPWM2_PWMA3





IOMUXC_PAD_ETH2_RX_CTL__SINC4_EMCLK0





IOMUXC_PAD_ETH2_RX_CLK__NETC_PINMUX_ETH2_RX_CLK





IOMUXC_PAD_ETH2_RX_CLK__LPUART3_RIN_B





IOMUXC_PAD_ETH2_RX_CLK__ECAT_RESET_OUT





IOMUXC_PAD_ETH2_RX_CLK__XBAR1_XBAR_INOUT38





IOMUXC_PAD_ETH2_RX_CLK__FLEXIO2_FLEXIO9





IOMUXC_PAD_ETH2_RX_CLK__GPIO6_IO9





IOMUXC_PAD_ETH2_RX_CLK__FLEXPWM2_PWMB3





IOMUXC_PAD_ETH2_RX_CLK__SINC4_EMBIT0





IOMUXC_PAD_ETH2_RXD0__NETC_PINMUX_ETH2_RXD0





IOMUXC_PAD_ETH2_RXD0__LPUART3_RX





IOMUXC_PAD_ETH2_RXD0__FLEXIO2_FLEXIO10





IOMUXC_PAD_ETH2_RXD0__GPIO6_IO10





IOMUXC_PAD_ETH2_RXD0__DIG_ENCODER2_DATA_EN





IOMUXC_PAD_ETH2_RXD0__XBAR1_XBAR_INOUT39





IOMUXC_PAD_ETH2_RXD1__NETC_PINMUX_ETH2_RXD1





IOMUXC_PAD_ETH2_RXD1__LPUART3_CTS_B





IOMUXC_PAD_ETH2_RXD1__LPTMR2_ALT0





IOMUXC_PAD_ETH2_RXD1__FLEXIO2_FLEXIO11





IOMUXC_PAD_ETH2_RXD1__GPIO6_IO11





IOMUXC_PAD_ETH2_RXD1__DIG_ENCODER2_DATA_CLK





IOMUXC_PAD_ETH2_RXD1__XBAR1_XBAR_INOUT40





IOMUXC_PAD_ETH2_RXD2__NETC_PINMUX_ETH2_RXD2





IOMUXC_PAD_ETH2_RXD2__LPTMR2_ALT1





IOMUXC_PAD_ETH2_RXD2__FLEXIO2_FLEXIO12





IOMUXC_PAD_ETH2_RXD2__GPIO6_IO12





IOMUXC_PAD_ETH2_RXD2__DIG_ENCODER2_DATA_OUT





IOMUXC_PAD_ETH2_RXD2__XBAR1_XBAR_INOUT41





IOMUXC_PAD_ETH2_RXD3__NETC_PINMUX_ETH2_RXD3





IOMUXC_PAD_ETH2_RXD3__LPTMR2_ALT2





IOMUXC_PAD_ETH2_RXD3__FLEXIO2_FLEXIO13





IOMUXC_PAD_ETH2_RXD3__GPIO6_IO13





IOMUXC_PAD_ETH2_RXD3__DIG_ENCODER2_DATA_IN





IOMUXC_PAD_ETH2_RXD3__XBAR1_XBAR_INOUT42





IOMUXC_PAD_ETH3_MDC_GPIO1__NETC_EMDC





IOMUXC_PAD_ETH3_MDC_GPIO1__LPUART4_DCD_B





IOMUXC_PAD_ETH3_MDC_GPIO1__NETC_ETH3_SLV_MDC





IOMUXC_PAD_ETH3_MDC_GPIO1__SAI4_TX_SYNC





IOMUXC_PAD_ETH3_MDC_GPIO1__FLEXIO2_FLEXIO14





IOMUXC_PAD_ETH3_MDC_GPIO1__GPIO6_IO14





IOMUXC_PAD_ETH3_MDC_GPIO1__FLEXPWM1_PWMX0





IOMUXC_PAD_ETH3_MDC_GPIO1__SINC4_MOD_CLK0





IOMUXC_PAD_ETH3_MDIO_GPIO2__NETC_EMDIO





IOMUXC_PAD_ETH3_MDIO_GPIO2__LPUART4_RIN_B





IOMUXC_PAD_ETH3_MDIO_GPIO2__NETC_ETH3_SLV_MDIO





IOMUXC_PAD_ETH3_MDIO_GPIO2__SAI4_TX_BCLK





IOMUXC_PAD_ETH3_MDIO_GPIO2__FLEXIO2_FLEXIO15





IOMUXC_PAD_ETH3_MDIO_GPIO2__GPIO6_IO15





IOMUXC_PAD_ETH3_MDIO_GPIO2__FLEXPWM1_PWMX1





IOMUXC_PAD_ETH3_MDIO_GPIO2__SINC4_MOD_CLK1





IOMUXC_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3





IOMUXC_PAD_ETH3_TXD3__XSPI_SLV_DATA7





IOMUXC_PAD_ETH3_TXD3__SAI4_TX_DATA0





IOMUXC_PAD_ETH3_TXD3__LPUART3_TX





IOMUXC_PAD_ETH3_TXD3__GPIO6_IO16





IOMUXC_PAD_ETH3_TXD3__FLEXPWM1_PWMA0





IOMUXC_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2





IOMUXC_PAD_ETH3_TXD2__ETH3_RMII_REF50_CLK





IOMUXC_PAD_ETH3_TXD2__XSPI_SLV_DATA6





IOMUXC_PAD_ETH3_TXD2__SAI4_RX_SYNC





IOMUXC_PAD_ETH3_TXD2__GPIO6_IO17





IOMUXC_PAD_ETH3_TXD2__FLEXPWM1_PWMB0





IOMUXC_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1





IOMUXC_PAD_ETH3_TXD1__LPUART4_RTS_B





IOMUXC_PAD_ETH3_TXD1__XSPI_SLV_DATA5





IOMUXC_PAD_ETH3_TXD1__SAI4_RX_BCLK





IOMUXC_PAD_ETH3_TXD1__GPIO6_IO18





IOMUXC_PAD_ETH3_TXD1__FLEXPWM1_PWMA1





IOMUXC_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0





IOMUXC_PAD_ETH3_TXD0__LPUART4_TX





IOMUXC_PAD_ETH3_TXD0__XSPI_SLV_DATA4





IOMUXC_PAD_ETH3_TXD0__SAI4_RX_DATA0





IOMUXC_PAD_ETH3_TXD0__GPIO6_IO19





IOMUXC_PAD_ETH3_TXD0__FLEXPWM1_PWMB1





IOMUXC_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL





IOMUXC_PAD_ETH3_TX_CTL__LPUART4_DTR_B





IOMUXC_PAD_ETH3_TX_CTL__XSPI_SLV_DQS





IOMUXC_PAD_ETH3_TX_CTL__SAI4_MCLK





IOMUXC_PAD_ETH3_TX_CTL__LPUART3_RX





IOMUXC_PAD_ETH3_TX_CTL__GPIO6_IO20





IOMUXC_PAD_ETH3_TX_CTL__FLEXPWM1_PWMA2





IOMUXC_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK





IOMUXC_PAD_ETH3_TX_CLK__XSPI_SLV_CLK





IOMUXC_PAD_ETH3_TX_CLK__SAI2_TX_SYNC





IOMUXC_PAD_ETH3_TX_CLK__LPUART3_CTS_B





IOMUXC_PAD_ETH3_TX_CLK__GPIO6_IO21





IOMUXC_PAD_ETH3_TX_CLK__FLEXPWM1_PWMB2





IOMUXC_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL





IOMUXC_PAD_ETH3_RX_CTL__LPUART4_DSR_B





IOMUXC_PAD_ETH3_RX_CTL__XSPI_SLV_CS





IOMUXC_PAD_ETH3_RX_CTL__SAI2_TX_BCLK





IOMUXC_PAD_ETH3_RX_CTL__XBAR1_XBAR_INOUT43





IOMUXC_PAD_ETH3_RX_CTL__GPIO6_IO22





IOMUXC_PAD_ETH3_RX_CTL__FLEXPWM1_PWMA3





IOMUXC_PAD_ETH3_RX_CTL__SINC4_EMCLK1





IOMUXC_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK





IOMUXC_PAD_ETH3_RX_CLK__LPUART4_CTS_B





IOMUXC_PAD_ETH3_RX_CLK__XSPI_SLV_DATA3





IOMUXC_PAD_ETH3_RX_CLK__SAI2_TX_DATA0





IOMUXC_PAD_ETH3_RX_CLK__XBAR1_XBAR_INOUT44





IOMUXC_PAD_ETH3_RX_CLK__GPIO6_IO23





IOMUXC_PAD_ETH3_RX_CLK__FLEXPWM1_PWMB3





IOMUXC_PAD_ETH3_RX_CLK__SINC4_EMBIT1





IOMUXC_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0





IOMUXC_PAD_ETH3_RXD0__LPUART4_RX





IOMUXC_PAD_ETH3_RXD0__XSPI_SLV_DATA2





IOMUXC_PAD_ETH3_RXD0__SAI2_RX_SYNC





IOMUXC_PAD_ETH3_RXD0__GPIO6_IO24





IOMUXC_PAD_ETH3_RXD0__DIG_ENCODER1_DATA_EN





IOMUXC_PAD_ETH3_RXD0__XBAR1_XBAR_INOUT45





IOMUXC_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1





IOMUXC_PAD_ETH3_RXD1__XSPI_SLV_DATA1





IOMUXC_PAD_ETH3_RXD1__SAI2_RX_BCLK





IOMUXC_PAD_ETH3_RXD1__LPUART3_RTS_B





IOMUXC_PAD_ETH3_RXD1__GPIO6_IO25





IOMUXC_PAD_ETH3_RXD1__DIG_ENCODER1_DATA_CLK





IOMUXC_PAD_ETH3_RXD1__XBAR1_XBAR_INOUT46





IOMUXC_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2





IOMUXC_PAD_ETH3_RXD2__MQS2_RIGHT





IOMUXC_PAD_ETH3_RXD2__XSPI_SLV_DATA0





IOMUXC_PAD_ETH3_RXD2__SAI2_RX_DATA0





IOMUXC_PAD_ETH3_RXD2__GPIO6_IO26





IOMUXC_PAD_ETH3_RXD2__DIG_ENCODER1_DATA_OUT





IOMUXC_PAD_ETH3_RXD2__XBAR1_XBAR_INOUT47





IOMUXC_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3





IOMUXC_PAD_ETH3_RXD3__MQS2_LEFT





IOMUXC_PAD_ETH3_RXD3__SAI2_MCLK





IOMUXC_PAD_ETH3_RXD3__GPIO6_IO27





IOMUXC_PAD_ETH3_RXD3__DIG_ENCODER1_DATA_IN





IOMUXC_PAD_ETH3_RXD3__XBAR1_XBAR_INOUT48





IOMUXC_PAD_ETH4_MDC_GPIO1__NETC_EMDC





IOMUXC_PAD_ETH4_MDC_GPIO1__ECAT_MDC





IOMUXC_PAD_ETH4_MDC_GPIO1__ECAT_CLK25





IOMUXC_PAD_ETH4_MDC_GPIO1__NETC_ETH4_SLV_MDC





IOMUXC_PAD_ETH4_MDC_GPIO1__FLEXIO1_3_2_FLEXIO12





IOMUXC_PAD_ETH4_MDC_GPIO1__GPIO6_IO28





IOMUXC_PAD_ETH4_MDC_GPIO1__FLEXPWM4_PWMX0





IOMUXC_PAD_ETH4_MDC_GPIO1__SINC4_MOD_CLK2





IOMUXC_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO





IOMUXC_PAD_ETH4_MDIO_GPIO2__ECAT_MDIO





IOMUXC_PAD_ETH4_MDIO_GPIO2__ENET_REF_CLK_ROOT





IOMUXC_PAD_ETH4_MDIO_GPIO2__NETC_ETH4_SLV_MDIO





IOMUXC_PAD_ETH4_MDIO_GPIO2__FLEXIO1_3_2_FLEXIO13





IOMUXC_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29





IOMUXC_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1





IOMUXC_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK





IOMUXC_PAD_ETH4_MDIO_GPIO2__XSPI2_IPP_IND_INTFA_B





IOMUXC_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK





IOMUXC_PAD_ETH4_TX_CLK__USDHC3_CLK





IOMUXC_PAD_ETH4_TX_CLK__XSPI2_A_SCLK





IOMUXC_PAD_ETH4_TX_CLK__ECAT_LED_ERR





IOMUXC_PAD_ETH4_TX_CLK__FLEXIO1_3_2_FLEXIO0





IOMUXC_PAD_ETH4_TX_CLK__GPIO6_IO30





IOMUXC_PAD_ETH4_TX_CLK__FLEXPWM4_PWMA0





IOMUXC_PAD_ETH4_TX_CLK__XBAR1_XBAR_INOUT30





IOMUXC_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL





IOMUXC_PAD_ETH4_TX_CTL__USDHC3_CMD





IOMUXC_PAD_ETH4_TX_CTL__XSPI2_A_SS0_B





IOMUXC_PAD_ETH4_TX_CTL__ECAT_RESET_OUT





IOMUXC_PAD_ETH4_TX_CTL__FLEXIO1_3_2_FLEXIO1





IOMUXC_PAD_ETH4_TX_CTL__GPIO6_IO31





IOMUXC_PAD_ETH4_TX_CTL__FLEXPWM4_PWMB0





IOMUXC_PAD_ETH4_TX_CTL__XBAR1_XBAR_INOUT31





IOMUXC_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0





IOMUXC_PAD_ETH4_TXD0__USDHC3_DATA0





IOMUXC_PAD_ETH4_TXD0__XSPI2_A_DATA0





IOMUXC_PAD_ETH4_TXD0__ECAT_LED_RUN





IOMUXC_PAD_ETH4_TXD0__FLEXIO1_3_2_FLEXIO2





IOMUXC_PAD_ETH4_TXD0__GPIO7_IO0





IOMUXC_PAD_ETH4_TXD0__FLEXPWM4_PWMA1





IOMUXC_PAD_ETH4_TXD0__XBAR1_XBAR_INOUT32





IOMUXC_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1





IOMUXC_PAD_ETH4_TXD1__USDHC3_DATA1





IOMUXC_PAD_ETH4_TXD1__XSPI2_A_DATA1





IOMUXC_PAD_ETH4_TXD1__ECAT_LED_STATE_RUN





IOMUXC_PAD_ETH4_TXD1__FLEXIO1_3_2_FLEXIO3





IOMUXC_PAD_ETH4_TXD1__GPIO7_IO1





IOMUXC_PAD_ETH4_TXD1__FLEXPWM4_PWMB1





IOMUXC_PAD_ETH4_TXD1__XBAR1_XBAR_INOUT33





IOMUXC_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2





IOMUXC_PAD_ETH4_TXD2__USDHC3_DATA2





IOMUXC_PAD_ETH4_TXD2__XSPI2_A_DATA2





IOMUXC_PAD_ETH4_TXD2__ECAT_CLK25





IOMUXC_PAD_ETH4_TXD2__FLEXIO1_3_2_FLEXIO4





IOMUXC_PAD_ETH4_TXD2__GPIO7_IO2





IOMUXC_PAD_ETH4_TXD2__FLEXPWM4_PWMA2





IOMUXC_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK





IOMUXC_PAD_ETH4_TXD2__XBAR1_XBAR_INOUT34





IOMUXC_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3





IOMUXC_PAD_ETH4_TXD3__USDHC3_DATA3





IOMUXC_PAD_ETH4_TXD3__XSPI2_A_DATA3





IOMUXC_PAD_ETH4_TXD3__FLEXIO1_3_2_FLEXIO5





IOMUXC_PAD_ETH4_TXD3__GPIO7_IO3





IOMUXC_PAD_ETH4_TXD3__FLEXPWM4_PWMB2





IOMUXC_PAD_ETH4_TXD3__XBAR1_XBAR_INOUT35





IOMUXC_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0





IOMUXC_PAD_ETH4_RXD0__XSPI2_A_DATA4





IOMUXC_PAD_ETH4_RXD0__FLEXIO1_3_2_FLEXIO6





IOMUXC_PAD_ETH4_RXD0__GPIO7_IO4





IOMUXC_PAD_ETH4_RXD0__FLEXPWM4_PWMA3





IOMUXC_PAD_ETH4_RXD0__SINC4_EMCLK2





IOMUXC_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1





IOMUXC_PAD_ETH4_RXD1__XSPI2_A_DATA5





IOMUXC_PAD_ETH4_RXD1__FLEXIO2_4_1_FLEXIO11





IOMUXC_PAD_ETH4_RXD1__FLEXIO1_3_2_FLEXIO7





IOMUXC_PAD_ETH4_RXD1__GPIO7_IO5





IOMUXC_PAD_ETH4_RXD1__FLEXPWM4_PWMB3





IOMUXC_PAD_ETH4_RXD1__SINC4_EMBIT2





IOMUXC_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2





IOMUXC_PAD_ETH4_RXD2__XSPI2_A_DATA6





IOMUXC_PAD_ETH4_RXD2__FLEXIO2_4_1_FLEXIO12





IOMUXC_PAD_ETH4_RXD2__FLEXIO1_3_2_FLEXIO8





IOMUXC_PAD_ETH4_RXD2__GPIO7_IO6





IOMUXC_PAD_ETH4_RXD2__DIG_ENCODER2_DATA_EN





IOMUXC_PAD_ETH4_RXD2__XBAR1_XBAR_INOUT4





IOMUXC_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3





IOMUXC_PAD_ETH4_RXD3__ENET_REF_CLK_ROOT





IOMUXC_PAD_ETH4_RXD3__XSPI2_A_DATA7





IOMUXC_PAD_ETH4_RXD3__FLEXIO2_4_1_FLEXIO13





IOMUXC_PAD_ETH4_RXD3__FLEXIO1_3_2_FLEXIO9





IOMUXC_PAD_ETH4_RXD3__GPIO7_IO7





IOMUXC_PAD_ETH4_RXD3__DIG_ENCODER2_DATA_CLK





IOMUXC_PAD_ETH4_RXD3__XBAR1_XBAR_INOUT5





IOMUXC_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL





IOMUXC_PAD_ETH4_RX_CTL__XSPI2_A_SS1_B





IOMUXC_PAD_ETH4_RX_CTL__FLEXIO2_4_1_FLEXIO14





IOMUXC_PAD_ETH4_RX_CTL__FLEXIO1_3_2_FLEXIO10





IOMUXC_PAD_ETH4_RX_CTL__GPIO7_IO8





IOMUXC_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT





IOMUXC_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6





IOMUXC_PAD_ETH4_RX_CTL__XSPI2_INTFA





IOMUXC_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK





IOMUXC_PAD_ETH4_RX_CLK__XSPI2_A_DQS





IOMUXC_PAD_ETH4_RX_CLK__FLEXIO2_4_1_FLEXIO15





IOMUXC_PAD_ETH4_RX_CLK__FLEXIO1_3_2_FLEXIO11





IOMUXC_PAD_ETH4_RX_CLK__GPIO7_IO9





IOMUXC_PAD_ETH4_RX_CLK__DIG_ENCODER2_DATA_IN





IOMUXC_PAD_ETH4_RX_CLK__XBAR1_XBAR_INOUT7





IOMUXC_PAD_ETH0_TXD0__NETC_PINMUX_ETH0_TXD0





IOMUXC_PAD_ETH0_TXD0__ECAT_PT0_TXD0





IOMUXC_PAD_ETH0_TXD0__FLEXIO4_FLEXIO0





IOMUXC_PAD_ETH0_TXD0__GPIO5_IO0





IOMUXC_PAD_ETH0_TXD1__NETC_PINMUX_ETH0_TXD1





IOMUXC_PAD_ETH0_TXD1__ECAT_PT0_TXD1





IOMUXC_PAD_ETH0_TXD1__FLEXIO4_FLEXIO1





IOMUXC_PAD_ETH0_TXD1__GPIO5_IO1





IOMUXC_PAD_ETH0_TX_EN__NETC_PINMUX_ETH0_TX_EN





IOMUXC_PAD_ETH0_TX_EN__ECAT_PT0_TX_EN





IOMUXC_PAD_ETH0_TX_EN__FLEXIO4_FLEXIO2





IOMUXC_PAD_ETH0_TX_EN__GPIO5_IO2





IOMUXC_PAD_ETH0_TX_CLK__NETC_PINMUX_ETH0_TX_CLK





IOMUXC_PAD_ETH0_TX_CLK__ECAT_PT0_TX_CLK





IOMUXC_PAD_ETH0_TX_CLK__FLEXIO4_FLEXIO3





IOMUXC_PAD_ETH0_TX_CLK__GPIO5_IO3





IOMUXC_PAD_ETH0_RXD0__NETC_PINMUX_ETH0_RXD0





IOMUXC_PAD_ETH0_RXD0__ECAT_PT0_RXD0





IOMUXC_PAD_ETH0_RXD0__FLEXIO4_FLEXIO4





IOMUXC_PAD_ETH0_RXD0__GPIO5_IO4





IOMUXC_PAD_ETH0_RXD1__NETC_PINMUX_ETH0_RXD1





IOMUXC_PAD_ETH0_RXD1__ECAT_PT0_RXD1





IOMUXC_PAD_ETH0_RXD1__FLEXIO4_FLEXIO5





IOMUXC_PAD_ETH0_RXD1__GPIO5_IO5





IOMUXC_PAD_ETH0_RX_DV__NETC_PINMUX_ETH0_RX_DV





IOMUXC_PAD_ETH0_RX_DV__ECAT_PT0_RX_DV





IOMUXC_PAD_ETH0_RX_DV__FLEXIO4_FLEXIO6





IOMUXC_PAD_ETH0_RX_DV__GPIO5_IO6





IOMUXC_PAD_ETH0_TXD2__NETC_PINMUX_ETH0_TXD2





IOMUXC_PAD_ETH0_TXD2__ECAT_PT0_TXD2





IOMUXC_PAD_ETH0_TXD2__ETH0_RMII_REF50_CLK





IOMUXC_PAD_ETH0_TXD2__FLEXIO4_FLEXIO7





IOMUXC_PAD_ETH0_TXD2__GPIO5_IO7





IOMUXC_PAD_ETH0_TXD3__NETC_PINMUX_ETH0_TXD3





IOMUXC_PAD_ETH0_TXD3__ECAT_PT0_TXD3





IOMUXC_PAD_ETH0_TXD3__FLEXIO4_FLEXIO8





IOMUXC_PAD_ETH0_TXD3__GPIO5_IO8





IOMUXC_PAD_ETH0_RXD2__NETC_PINMUX_ETH0_RXD2





IOMUXC_PAD_ETH0_RXD2__ECAT_PT0_RXD2





IOMUXC_PAD_ETH0_RXD2__FLEXIO4_FLEXIO9





IOMUXC_PAD_ETH0_RXD2__GPIO5_IO9





IOMUXC_PAD_ETH0_RXD3__NETC_PINMUX_ETH0_RXD3





IOMUXC_PAD_ETH0_RXD3__ECAT_PT0_RXD3





IOMUXC_PAD_ETH0_RXD3__FLEXIO4_FLEXIO10





IOMUXC_PAD_ETH0_RXD3__GPIO5_IO10





IOMUXC_PAD_ETH0_RX_CLK__NETC_PINMUX_ETH0_RX_CLK





IOMUXC_PAD_ETH0_RX_CLK__ECAT_PT0_RX_CLK





IOMUXC_PAD_ETH0_RX_CLK__FLEXIO4_FLEXIO11





IOMUXC_PAD_ETH0_RX_CLK__GPIO5_IO11





IOMUXC_PAD_ETH0_RX_ER__NETC_PINMUX_ETH0_RX_ER





IOMUXC_PAD_ETH0_RX_ER__ECAT_PT0_RX_ER





IOMUXC_PAD_ETH0_RX_ER__FLEXIO4_FLEXIO12





IOMUXC_PAD_ETH0_RX_ER__GPIO5_IO12





IOMUXC_PAD_ETH0_TX_ER__NETC_PINMUX_ETH0_TX_ER





IOMUXC_PAD_ETH0_TX_ER__ECAT_LINK_ACT0





IOMUXC_PAD_ETH0_TX_ER__FLEXIO4_FLEXIO13





IOMUXC_PAD_ETH0_TX_ER__GPIO5_IO13





IOMUXC_PAD_ETH0_CRS__NETC_PINMUX_ETH0_CRS





IOMUXC_PAD_ETH0_CRS__ECAT_LINK0





IOMUXC_PAD_ETH0_CRS__NETC_EMDC





IOMUXC_PAD_ETH0_CRS__FLEXIO4_FLEXIO14





IOMUXC_PAD_ETH0_CRS__GPIO5_IO14





IOMUXC_PAD_ETH0_CRS__XBAR1_XBAR_INOUT8





IOMUXC_PAD_ETH0_CRS__SINC_FILTER_GLUE2_BREAK





IOMUXC_PAD_ETH0_COL__NETC_PINMUX_ETH0_COL





IOMUXC_PAD_ETH0_COL__ECAT_LINK1





IOMUXC_PAD_ETH0_COL__NETC_EMDIO





IOMUXC_PAD_ETH0_COL__FLEXIO4_FLEXIO15





IOMUXC_PAD_ETH0_COL__GPIO5_IO15





IOMUXC_PAD_ETH0_COL__XBAR1_XBAR_INOUT9





IOMUXC_PAD_ETH0_COL__SINC_FILTER_GLUE1_BREAK





IOMUXC_PAD_ETH1_TXD0__NETC_PINMUX_ETH1_TXD0





IOMUXC_PAD_ETH1_TXD0__ECAT_PT1_TXD0





IOMUXC_PAD_ETH1_TXD0__ENCODER_DIAG0





IOMUXC_PAD_ETH1_TXD0__FLEXIO3_FLEXIO0





IOMUXC_PAD_ETH1_TXD0__GPIO5_IO16





IOMUXC_PAD_ETH1_TXD1__NETC_PINMUX_ETH1_TXD1





IOMUXC_PAD_ETH1_TXD1__ECAT_PT1_TXD1





IOMUXC_PAD_ETH1_TXD1__ENCODER_DIAG1





IOMUXC_PAD_ETH1_TXD1__FLEXIO3_FLEXIO1





IOMUXC_PAD_ETH1_TXD1__GPIO5_IO17





IOMUXC_PAD_ETH1_TX_EN__NETC_PINMUX_ETH1_TX_EN





IOMUXC_PAD_ETH1_TX_EN__ECAT_PT1_TX_EN





IOMUXC_PAD_ETH1_TX_EN__ENCODER_DIAG2





IOMUXC_PAD_ETH1_TX_EN__FLEXIO3_FLEXIO2





IOMUXC_PAD_ETH1_TX_EN__GPIO5_IO18





IOMUXC_PAD_ETH1_TX_CLK__NETC_PINMUX_ETH1_TX_CLK





IOMUXC_PAD_ETH1_TX_CLK__ECAT_PT1_TX_CLK





IOMUXC_PAD_ETH1_TX_CLK__ENCODER_DIAG3





IOMUXC_PAD_ETH1_TX_CLK__FLEXIO3_FLEXIO3





IOMUXC_PAD_ETH1_TX_CLK__GPIO5_IO19





IOMUXC_PAD_ETH1_RXD0__NETC_PINMUX_ETH1_RXD0





IOMUXC_PAD_ETH1_RXD0__ECAT_PT1_RXD0





IOMUXC_PAD_ETH1_RXD0__ENCODER_DIAG4





IOMUXC_PAD_ETH1_RXD0__FLEXIO3_FLEXIO4





IOMUXC_PAD_ETH1_RXD0__GPIO5_IO20





IOMUXC_PAD_ETH1_RXD1__NETC_PINMUX_ETH1_RXD1





IOMUXC_PAD_ETH1_RXD1__ECAT_PT1_RXD1





IOMUXC_PAD_ETH1_RXD1__ENCODER_DIAG5





IOMUXC_PAD_ETH1_RXD1__FLEXIO3_FLEXIO5





IOMUXC_PAD_ETH1_RXD1__GPIO5_IO21





IOMUXC_PAD_ETH1_RX_DV__NETC_PINMUX_ETH1_RX_DV





IOMUXC_PAD_ETH1_RX_DV__ECAT_PT1_RX_DV





IOMUXC_PAD_ETH1_RX_DV__ENCODER_DIAG6





IOMUXC_PAD_ETH1_RX_DV__FLEXIO3_FLEXIO6





IOMUXC_PAD_ETH1_RX_DV__GPIO5_IO22





IOMUXC_PAD_ETH1_TXD2__NETC_PINMUX_ETH1_TXD2





IOMUXC_PAD_ETH1_TXD2__ECAT_PT1_TXD2





IOMUXC_PAD_ETH1_TXD2__ETH1_RMII_REF50_CLK





IOMUXC_PAD_ETH1_TXD2__ENCODER_DIAG7





IOMUXC_PAD_ETH1_TXD2__FLEXIO3_FLEXIO7





IOMUXC_PAD_ETH1_TXD2__GPIO5_IO23





IOMUXC_PAD_ETH1_TXD3__NETC_PINMUX_ETH1_TXD3





IOMUXC_PAD_ETH1_TXD3__ECAT_PT1_TXD3





IOMUXC_PAD_ETH1_TXD3__ENCODER_DIAG8





IOMUXC_PAD_ETH1_TXD3__FLEXIO3_FLEXIO8





IOMUXC_PAD_ETH1_TXD3__GPIO5_IO24





IOMUXC_PAD_ETH1_RXD2__NETC_PINMUX_ETH1_RXD2





IOMUXC_PAD_ETH1_RXD2__ECAT_PT1_RXD2





IOMUXC_PAD_ETH1_RXD2__ENCODER_DIAG9





IOMUXC_PAD_ETH1_RXD2__FLEXIO3_FLEXIO9





IOMUXC_PAD_ETH1_RXD2__GPIO5_IO25





IOMUXC_PAD_ETH1_RXD3__NETC_PINMUX_ETH1_RXD3





IOMUXC_PAD_ETH1_RXD3__ECAT_PT1_RXD3





IOMUXC_PAD_ETH1_RXD3__ENCODER_DIAG10





IOMUXC_PAD_ETH1_RXD3__FLEXIO3_FLEXIO10





IOMUXC_PAD_ETH1_RXD3__GPIO5_IO26





IOMUXC_PAD_ETH1_RX_CLK__NETC_PINMUX_ETH1_RX_CLK





IOMUXC_PAD_ETH1_RX_CLK__ECAT_PT1_RX_CLK





IOMUXC_PAD_ETH1_RX_CLK__ENCODER_DIAG11





IOMUXC_PAD_ETH1_RX_CLK__FLEXIO3_FLEXIO11





IOMUXC_PAD_ETH1_RX_CLK__GPIO5_IO27





IOMUXC_PAD_ETH1_RX_ER__NETC_PINMUX_ETH1_RX_ER





IOMUXC_PAD_ETH1_RX_ER__ECAT_PT1_RX_ER





IOMUXC_PAD_ETH1_RX_ER__ENCODER_DIAG12





IOMUXC_PAD_ETH1_RX_ER__FLEXIO3_FLEXIO12





IOMUXC_PAD_ETH1_RX_ER__GPIO5_IO28





IOMUXC_PAD_ETH1_TX_ER__NETC_PINMUX_ETH1_TX_ER





IOMUXC_PAD_ETH1_TX_ER__ECAT_LINK_ACT1





IOMUXC_PAD_ETH1_TX_ER__ENCODER_DIAG13





IOMUXC_PAD_ETH1_TX_ER__FLEXIO3_FLEXIO13





IOMUXC_PAD_ETH1_TX_ER__GPIO5_IO29





IOMUXC_PAD_ETH1_CRS__NETC_PINMUX_ETH1_CRS





IOMUXC_PAD_ETH1_CRS__ECAT_MDC





IOMUXC_PAD_ETH1_CRS__NETC_EMDC





IOMUXC_PAD_ETH1_CRS__ENCODER_DIAG14





IOMUXC_PAD_ETH1_CRS__FLEXIO3_FLEXIO14





IOMUXC_PAD_ETH1_CRS__GPIO5_IO30





IOMUXC_PAD_ETH1_CRS__XBAR1_XBAR_INOUT10





IOMUXC_PAD_ETH1_CRS__SINC_FILTER_GLUE1_BREAK





IOMUXC_PAD_ETH1_COL__NETC_PINMUX_ETH1_COL





IOMUXC_PAD_ETH1_COL__ECAT_MDIO





IOMUXC_PAD_ETH1_COL__NETC_EMDIO





IOMUXC_PAD_ETH1_COL__ENCODER_DIAG15





IOMUXC_PAD_ETH1_COL__FLEXIO3_FLEXIO15





IOMUXC_PAD_ETH1_COL__GPIO5_IO31





IOMUXC_PAD_ETH1_COL__XBAR1_XBAR_INOUT11





IOMUXC_PAD_ETH1_COL__SINC_FILTER_GLUE2_BREAK





IOMUXC_PAD_SD1_CLK__USDHC1_CLK





IOMUXC_PAD_SD1_CLK__SAI4_TX_BCLK





IOMUXC_PAD_SD1_CLK__CAN4_TX





IOMUXC_PAD_SD1_CLK__NETC_1588MUX_INOUT0





IOMUXC_PAD_SD1_CLK__FLEXIO2_4_1_FLEXIO0





IOMUXC_PAD_SD1_CLK__GPIO4_IO8





IOMUXC_PAD_SD1_CLK__FLEXPWM3_PWMX0





IOMUXC_PAD_SD1_CLK__SINC1_EMCLK0





IOMUXC_PAD_SD1_CMD__USDHC1_CMD





IOMUXC_PAD_SD1_CMD__SAI4_RX_BCLK





IOMUXC_PAD_SD1_CMD__CAN4_RX





IOMUXC_PAD_SD1_CMD__NETC_1588MUX_INOUT1





IOMUXC_PAD_SD1_CMD__FLEXIO2_4_1_FLEXIO1





IOMUXC_PAD_SD1_CMD__GPIO4_IO9





IOMUXC_PAD_SD1_CMD__FLEXPWM3_PWMX1





IOMUXC_PAD_SD1_CMD__SINC1_EMBIT0





IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0





IOMUXC_PAD_SD1_DATA0__SAI4_RX_SYNC





IOMUXC_PAD_SD1_DATA0__CAN5_TX





IOMUXC_PAD_SD1_DATA0__NETC_1588MUX_INOUT2





IOMUXC_PAD_SD1_DATA0__FLEXIO2_4_1_FLEXIO2





IOMUXC_PAD_SD1_DATA0__GPIO4_IO10





IOMUXC_PAD_SD1_DATA0__FLEXPWM3_PWMX2





IOMUXC_PAD_SD1_DATA0__SINC1_EMCLK1





IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1





IOMUXC_PAD_SD1_DATA1__SAI4_TX_SYNC





IOMUXC_PAD_SD1_DATA1__CAN5_RX





IOMUXC_PAD_SD1_DATA1__NETC_1588MUX_INOUT3





IOMUXC_PAD_SD1_DATA1__FLEXIO2_4_1_FLEXIO3





IOMUXC_PAD_SD1_DATA1__GPIO4_IO11





IOMUXC_PAD_SD1_DATA1__FLEXPWM3_PWMA3





IOMUXC_PAD_SD1_DATA1__SINC1_EMBIT1





IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2





IOMUXC_PAD_SD1_DATA2__SAI4_TX_DATA0





IOMUXC_PAD_SD1_DATA2__PMIC_READY





IOMUXC_PAD_SD1_DATA2__NETC_1588MUX_INOUT4





IOMUXC_PAD_SD1_DATA2__FLEXIO2_4_1_FLEXIO4





IOMUXC_PAD_SD1_DATA2__GPIO4_IO12





IOMUXC_PAD_SD1_DATA2__FLEXPWM3_PWMB3





IOMUXC_PAD_SD1_DATA2__SINC1_EMCLK2





IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3





IOMUXC_PAD_SD1_DATA3__SAI4_RX_DATA0





IOMUXC_PAD_SD1_DATA3__NETC_1588MUX_INOUT5





IOMUXC_PAD_SD1_DATA3__FLEXIO2_4_1_FLEXIO5





IOMUXC_PAD_SD1_DATA3__GPIO4_IO13





IOMUXC_PAD_SD1_DATA3__FLEXPWM3_PWMA2





IOMUXC_PAD_SD1_DATA3__SINC1_EMBIT2





IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4





IOMUXC_PAD_SD1_DATA4__SAI2_RX_DATA0





IOMUXC_PAD_SD1_DATA4__NETC_1588MUX_INOUT6





IOMUXC_PAD_SD1_DATA4__FLEXIO2_4_1_FLEXIO6





IOMUXC_PAD_SD1_DATA4__GPIO4_IO14





IOMUXC_PAD_SD1_DATA4__FLEXPWM3_PWMB2





IOMUXC_PAD_SD1_DATA4__SINC1_EMCLK3





IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5





IOMUXC_PAD_SD1_DATA5__SAI2_TX_DATA0





IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B





IOMUXC_PAD_SD1_DATA5__NETC_1588MUX_INOUT7





IOMUXC_PAD_SD1_DATA5__FLEXIO2_4_1_FLEXIO7





IOMUXC_PAD_SD1_DATA5__GPIO4_IO15





IOMUXC_PAD_SD1_DATA5__FLEXPWM3_PWMA1





IOMUXC_PAD_SD1_DATA5__SINC1_EMBIT3





IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6





IOMUXC_PAD_SD1_DATA6__SAI2_TX_BCLK





IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B





IOMUXC_PAD_SD1_DATA6__NETC_1588MUX_INOUT8





IOMUXC_PAD_SD1_DATA6__FLEXIO2_4_1_FLEXIO8





IOMUXC_PAD_SD1_DATA6__GPIO4_IO16





IOMUXC_PAD_SD1_DATA6__FLEXPWM3_PWMB1





IOMUXC_PAD_SD1_DATA6__SINC1_MOD_CLK0





IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7





IOMUXC_PAD_SD1_DATA7__SAI2_RX_SYNC





IOMUXC_PAD_SD1_DATA7__USDHC1_WP





IOMUXC_PAD_SD1_DATA7__NETC_1588MUX_INOUT9





IOMUXC_PAD_SD1_DATA7__FLEXIO2_4_1_FLEXIO9





IOMUXC_PAD_SD1_DATA7__GPIO4_IO17





IOMUXC_PAD_SD1_DATA7__FLEXPWM3_PWMA0





IOMUXC_PAD_SD1_DATA7__SINC1_MOD_CLK1





IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE





IOMUXC_PAD_SD1_STROBE__SAI2_TX_SYNC





IOMUXC_PAD_SD1_STROBE__NETC_1588MUX_INOUT10





IOMUXC_PAD_SD1_STROBE__FLEXIO2_4_1_FLEXIO10





IOMUXC_PAD_SD1_STROBE__GPIO4_IO18





IOMUXC_PAD_SD1_STROBE__FLEXPWM3_PWMB0





IOMUXC_PAD_SD1_STROBE__SINC1_MOD_CLK2





IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT





IOMUXC_PAD_SD2_VSELECT__SAI4_MCLK





IOMUXC_PAD_SD2_VSELECT__USDHC2_WP





IOMUXC_PAD_SD2_VSELECT__NETC_1588MUX_INOUT10





IOMUXC_PAD_SD2_VSELECT__FLEXIO2_4_1_FLEXIO11





IOMUXC_PAD_SD2_VSELECT__GPIO4_IO19





IOMUXC_PAD_SD2_VSELECT__EXT_CLK1





IOMUXC_PAD_SD2_VSELECT__XBAR1_XBAR_INOUT12





IOMUXC_PAD_XSPI1_DATA0__XSPI1_A_DATA0





IOMUXC_PAD_XSPI1_DATA0__SAI2_RX_SYNC





IOMUXC_PAD_XSPI1_DATA0__XSPI_SLV_DATA0





IOMUXC_PAD_XSPI1_DATA0__FLEXIO1_3_3_FLEXIO0





IOMUXC_PAD_XSPI1_DATA0__GPIO7_IO16





IOMUXC_PAD_XSPI1_DATA1__XSPI1_A_DATA1





IOMUXC_PAD_XSPI1_DATA1__SAI2_TX_SYNC





IOMUXC_PAD_XSPI1_DATA1__XSPI_SLV_DATA1





IOMUXC_PAD_XSPI1_DATA1__FLEXIO1_3_3_FLEXIO1





IOMUXC_PAD_XSPI1_DATA1__GPIO7_IO17





IOMUXC_PAD_XSPI1_DATA2__XSPI1_A_DATA2





IOMUXC_PAD_XSPI1_DATA2__SAI2_TX_DATA0





IOMUXC_PAD_XSPI1_DATA2__XSPI_SLV_DATA2





IOMUXC_PAD_XSPI1_DATA2__FLEXIO1_3_3_FLEXIO2





IOMUXC_PAD_XSPI1_DATA2__GPIO7_IO18





IOMUXC_PAD_XSPI1_DATA3__XSPI1_A_DATA3





IOMUXC_PAD_XSPI1_DATA3__SAI2_RX_DATA0





IOMUXC_PAD_XSPI1_DATA3__SAI2_MCLK





IOMUXC_PAD_XSPI1_DATA3__XSPI_SLV_DATA3





IOMUXC_PAD_XSPI1_DATA3__FLEXIO1_3_3_FLEXIO3





IOMUXC_PAD_XSPI1_DATA3__GPIO7_IO19





IOMUXC_PAD_XSPI1_DATA4__XSPI1_A_DATA4





IOMUXC_PAD_XSPI1_DATA4__SAI4_RX_SYNC





IOMUXC_PAD_XSPI1_DATA4__XSPI_SLV_DATA4





IOMUXC_PAD_XSPI1_DATA4__FLEXIO1_3_3_FLEXIO4





IOMUXC_PAD_XSPI1_DATA4__GPIO7_IO20





IOMUXC_PAD_XSPI1_DATA5__XSPI1_A_DATA5





IOMUXC_PAD_XSPI1_DATA5__SAI4_TX_SYNC





IOMUXC_PAD_XSPI1_DATA5__XSPI_SLV_DATA5





IOMUXC_PAD_XSPI1_DATA5__FLEXIO1_3_3_FLEXIO5





IOMUXC_PAD_XSPI1_DATA5__GPIO7_IO21





IOMUXC_PAD_XSPI1_DATA6__XSPI1_A_DATA6





IOMUXC_PAD_XSPI1_DATA6__SAI4_TX_DATA0





IOMUXC_PAD_XSPI1_DATA6__XSPI_SLV_DATA6





IOMUXC_PAD_XSPI1_DATA6__FLEXIO1_3_3_FLEXIO6





IOMUXC_PAD_XSPI1_DATA6__GPIO7_IO22





IOMUXC_PAD_XSPI1_DATA7__XSPI1_A_DATA7





IOMUXC_PAD_XSPI1_DATA7__SAI4_RX_DATA0





IOMUXC_PAD_XSPI1_DATA7__SAI4_MCLK





IOMUXC_PAD_XSPI1_DATA7__XSPI_SLV_DATA7





IOMUXC_PAD_XSPI1_DATA7__FLEXIO1_3_3_FLEXIO7





IOMUXC_PAD_XSPI1_DATA7__GPIO7_IO23





IOMUXC_PAD_XSPI1_DQS__XSPI1_A_DQS





IOMUXC_PAD_XSPI1_DQS__SAI2_TX_BCLK





IOMUXC_PAD_XSPI1_DQS__XSPI_SLV_DQS





IOMUXC_PAD_XSPI1_DQS__FLEXIO1_3_3_FLEXIO8





IOMUXC_PAD_XSPI1_DQS__GPIO7_IO24





IOMUXC_PAD_XSPI1_SCLK__XSPI1_A_SCLK





IOMUXC_PAD_XSPI1_SCLK__SAI4_TX_BCLK





IOMUXC_PAD_XSPI1_SCLK__XSPI_SLV_CLK





IOMUXC_PAD_XSPI1_SCLK__FLEXIO1_3_3_FLEXIO9





IOMUXC_PAD_XSPI1_SCLK__GPIO7_IO25





IOMUXC_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B





IOMUXC_PAD_XSPI1_SS0_B__SAI4_RX_BCLK





IOMUXC_PAD_XSPI1_SS0_B__XSPI_SLV_CS





IOMUXC_PAD_XSPI1_SS0_B__FLEXIO1_3_3_FLEXIO10





IOMUXC_PAD_XSPI1_SS0_B__GPIO7_IO26





IOMUXC_PAD_XSPI1_SS1_B__XSPI1_A_SS1_B





IOMUXC_PAD_XSPI1_SS1_B__SAI2_RX_BCLK





IOMUXC_PAD_XSPI1_SS1_B__FLEXPWM3_PWMX3





IOMUXC_PAD_XSPI1_SS1_B__FLEXIO1_3_3_FLEXIO11





IOMUXC_PAD_XSPI1_SS1_B__GPIO7_IO27





IOMUXC_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0





IOMUXC_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK





IOMUXC_PAD_XSPI1_SS1_B__XSPI1_IPP_IND_INTFA_B





IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B





IOMUXC_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL





IOMUXC_PAD_SD2_CD_B__I3C2_SCL





IOMUXC_PAD_SD2_CD_B__NETC_1588MUX_INOUT9





IOMUXC_PAD_SD2_CD_B__FLEXIO2_4_2_FLEXIO0





IOMUXC_PAD_SD2_CD_B__GPIO4_IO20





IOMUXC_PAD_SD2_CD_B__XBAR1_XBAR_INOUT13





IOMUXC_PAD_SD2_CD_B__SINC2_EMCLK0





IOMUXC_PAD_SD2_CLK__USDHC2_CLK





IOMUXC_PAD_SD2_CLK__NETC_PINMUX_ETH4_TX_CLK





IOMUXC_PAD_SD2_CLK__I3C2_SDA





IOMUXC_PAD_SD2_CLK__NETC_1588MUX_INOUT8





IOMUXC_PAD_SD2_CLK__FLEXIO2_4_2_FLEXIO1





IOMUXC_PAD_SD2_CLK__GPIO4_IO21





IOMUXC_PAD_SD2_CLK__OBSERVE0





IOMUXC_PAD_SD2_CLK__SINC2_EMBIT0





IOMUXC_PAD_SD2_CMD__USDHC2_CMD





IOMUXC_PAD_SD2_CMD__NETC_PINMUX_ETH4_TX_CTL





IOMUXC_PAD_SD2_CMD__I3C2_PUR





IOMUXC_PAD_SD2_CMD__I3C2_PUR_B





IOMUXC_PAD_SD2_CMD__FLEXIO2_4_2_FLEXIO2





IOMUXC_PAD_SD2_CMD__GPIO4_IO22





IOMUXC_PAD_SD2_CMD__OBSERVE1





IOMUXC_PAD_SD2_CMD__SINC2_EMCLK1





IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0





IOMUXC_PAD_SD2_DATA0__NETC_PINMUX_ETH4_TXD0





IOMUXC_PAD_SD2_DATA0__CAN2_TX





IOMUXC_PAD_SD2_DATA0__NETC_1588MUX_INOUT7





IOMUXC_PAD_SD2_DATA0__FLEXIO2_4_2_FLEXIO3





IOMUXC_PAD_SD2_DATA0__GPIO4_IO23





IOMUXC_PAD_SD2_DATA0__OBSERVE2





IOMUXC_PAD_SD2_DATA0__SINC2_EMBIT1





IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1





IOMUXC_PAD_SD2_DATA1__NETC_PINMUX_ETH4_TXD1





IOMUXC_PAD_SD2_DATA1__CAN2_RX





IOMUXC_PAD_SD2_DATA1__NETC_1588MUX_INOUT6





IOMUXC_PAD_SD2_DATA1__FLEXIO2_4_2_FLEXIO4





IOMUXC_PAD_SD2_DATA1__GPIO4_IO24





IOMUXC_PAD_SD2_DATA1__XBAR1_XBAR_INOUT14





IOMUXC_PAD_SD2_DATA1__SINC2_EMCLK2





IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2





IOMUXC_PAD_SD2_DATA2__NETC_PINMUX_ETH4_TXD2





IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT





IOMUXC_PAD_SD2_DATA2__NETC_1588MUX_INOUT5





IOMUXC_PAD_SD2_DATA2__FLEXIO2_4_2_FLEXIO5





IOMUXC_PAD_SD2_DATA2__GPIO4_IO25





IOMUXC_PAD_SD2_DATA2__XBAR1_XBAR_INOUT15





IOMUXC_PAD_SD2_DATA2__SINC2_EMBIT2





IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3





IOMUXC_PAD_SD2_DATA3__NETC_PINMUX_ETH4_TXD3





IOMUXC_PAD_SD2_DATA3__MQS2_LEFT





IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT0





IOMUXC_PAD_SD2_DATA3__FLEXIO2_4_2_FLEXIO6





IOMUXC_PAD_SD2_DATA3__GPIO4_IO26





IOMUXC_PAD_SD2_DATA3__XBAR1_XBAR_INOUT16





IOMUXC_PAD_SD2_DATA3__SINC2_EMCLK3





IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B





IOMUXC_PAD_SD2_RESET_B__NETC_PINMUX_ETH4_RXD0





IOMUXC_PAD_SD2_RESET_B__NETC_1588MUX_INOUT4





IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT1





IOMUXC_PAD_SD2_RESET_B__FLEXIO2_4_2_FLEXIO7





IOMUXC_PAD_SD2_RESET_B__GPIO4_IO27





IOMUXC_PAD_SD2_RESET_B__XBAR1_XBAR_INOUT17





IOMUXC_PAD_SD2_RESET_B__SINC2_EMBIT3





IOMUXC_PAD_SD2_GPIO0__USDHC2_WP





IOMUXC_PAD_SD2_GPIO0__NETC_PINMUX_ETH4_RXD1





IOMUXC_PAD_SD2_GPIO0__NETC_1588MUX_INOUT3





IOMUXC_PAD_SD2_GPIO0__FLEXIO2_4_2_FLEXIO8





IOMUXC_PAD_SD2_GPIO0__GPIO4_IO28





IOMUXC_PAD_SD2_GPIO0__XBAR1_XBAR_INOUT18





IOMUXC_PAD_SD2_GPIO0__SINC2_MOD_CLK1





IOMUXC_PAD_SD2_GPIO1__LPTMR2_ALT2





IOMUXC_PAD_SD2_GPIO1__NETC_PINMUX_ETH4_RXD2





IOMUXC_PAD_SD2_GPIO1__ECAT_CLK25





IOMUXC_PAD_SD2_GPIO1__NETC_1588MUX_INOUT2





IOMUXC_PAD_SD2_GPIO1__FLEXIO2_4_2_FLEXIO9





IOMUXC_PAD_SD2_GPIO1__GPIO4_IO29





IOMUXC_PAD_SD2_GPIO1__XBAR1_XBAR_INOUT19





IOMUXC_PAD_SD2_GPIO1__SINC2_MOD_CLK0





IOMUXC_PAD_SD2_GPIO2__NETC_PINMUX_ETH4_RXD3





IOMUXC_PAD_SD2_GPIO2__CAN5_TX





IOMUXC_PAD_SD2_GPIO2__NETC_1588MUX_INOUT1





IOMUXC_PAD_SD2_GPIO2__FLEXIO2_4_2_FLEXIO10





IOMUXC_PAD_SD2_GPIO2__GPIO4_IO30





IOMUXC_PAD_SD2_GPIO2__XBAR1_XBAR_INOUT20





IOMUXC_PAD_SD2_GPIO2__SINC2_MOD_CLK2





IOMUXC_PAD_SD2_GPIO3__NETC_PINMUX_ETH4_RX_CLK





IOMUXC_PAD_SD2_GPIO3__CAN5_RX





IOMUXC_PAD_SD2_GPIO3__NETC_1588MUX_INOUT0





IOMUXC_PAD_SD2_GPIO3__FLEXIO2_4_2_FLEXIO11





IOMUXC_PAD_SD2_GPIO3__GPIO4_IO31





IOMUXC_PAD_SD2_GPIO3__XBAR1_XBAR_INOUT21





IOMUXC_PAD_SD2_GPIO3__SINC_FILTER_GLUE2_BREAK





IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL





IOMUXC_PAD_I2C1_SCL__I3C1_SCL





IOMUXC_PAD_I2C1_SCL__LPUART1_DCD_B





IOMUXC_PAD_I2C1_SCL__TPM2_CH0





IOMUXC_PAD_I2C1_SCL__SAI1_RX_SYNC





IOMUXC_PAD_I2C1_SCL__GPIO1_IO0





IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA





IOMUXC_PAD_I2C1_SDA__I3C1_SDA





IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B





IOMUXC_PAD_I2C1_SDA__TPM2_CH1





IOMUXC_PAD_I2C1_SDA__SAI1_RX_BCLK





IOMUXC_PAD_I2C1_SDA__GPIO1_IO1





IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL





IOMUXC_PAD_I2C2_SCL__I3C1_PUR





IOMUXC_PAD_I2C2_SCL__LPUART2_DCD_B





IOMUXC_PAD_I2C2_SCL__TPM2_CH2





IOMUXC_PAD_I2C2_SCL__GPT1_CLK





IOMUXC_PAD_I2C2_SCL__GPIO1_IO2





IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B





IOMUXC_PAD_I2C2_SCL__LPIT1_TRIGGER0





IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA





IOMUXC_PAD_I2C2_SDA__LPI2C1_HREQ





IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B





IOMUXC_PAD_I2C2_SDA__TPM2_CH3





IOMUXC_PAD_I2C2_SDA__SAI1_MCLK





IOMUXC_PAD_I2C2_SDA__GPIO1_IO3





IOMUXC_PAD_I2C2_SDA__EWM_OUT_B





IOMUXC_PAD_I2C2_SDA__LPIT1_TRIGGER1





IOMUXC_PAD_UART1_RXD__LPUART1_RX





IOMUXC_PAD_UART1_RXD__S400_UART_RX





IOMUXC_PAD_UART1_RXD__LPSPI2_SIN





IOMUXC_PAD_UART1_RXD__TPM1_CH0





IOMUXC_PAD_UART1_RXD__GPT1_CAPTURE1





IOMUXC_PAD_UART1_RXD__GPIO1_IO4





IOMUXC_PAD_UART1_TXD__LPUART1_TX





IOMUXC_PAD_UART1_TXD__S400_UART_TX





IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0





IOMUXC_PAD_UART1_TXD__TPM1_CH1





IOMUXC_PAD_UART1_TXD__GPT1_COMPARE1





IOMUXC_PAD_UART1_TXD__GPIO1_IO5





IOMUXC_PAD_UART2_RXD__LPUART2_RX





IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B





IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT





IOMUXC_PAD_UART2_RXD__TPM1_CH2





IOMUXC_PAD_UART2_RXD__SAI1_MCLK





IOMUXC_PAD_UART2_RXD__GPIO1_IO6





IOMUXC_PAD_UART2_RXD__GPT1_CLK





IOMUXC_PAD_UART2_RXD__LPIT1_TRIGGER2





IOMUXC_PAD_UART2_TXD__LPUART2_TX





IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B





IOMUXC_PAD_UART2_TXD__LPSPI2_SCK





IOMUXC_PAD_UART2_TXD__TPM1_CH3





IOMUXC_PAD_UART2_TXD__GPIO1_IO7





IOMUXC_PAD_PDM_CLK__PDM_CLK





IOMUXC_PAD_PDM_CLK__MQS1_LEFT





IOMUXC_PAD_PDM_CLK__LPTMR1_ALT0





IOMUXC_PAD_PDM_CLK__GPIO1_IO8





IOMUXC_PAD_PDM_CLK__CAN1_TX





IOMUXC_PAD_PDM_CLK__EWM_OUT_B





IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0





IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT





IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1





IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK





IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT1





IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO9





IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX





IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1





IOMUXC_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI





IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1





IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK





IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT2





IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10





IOMUXC_PAD_PDM_BIT_STREAM1__EXT_CLK1





IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC





IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA1





IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0





IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B





IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT





IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11





IOMUXC_PAD_SAI1_TXFS__EWM_OUT_B





IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK





IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B





IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN





IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B





IOMUXC_PAD_SAI1_TXC__CAN1_RX





IOMUXC_PAD_SAI1_TXC__GPIO1_IO12





IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA0





IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B





IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK





IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B





IOMUXC_PAD_SAI1_TXD0__CAN1_TX





IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13





IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA0





IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK





IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT





IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B





IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT





IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14





IOMUXC_PAD_SAI1_RXD0__LPIT1_TRIGGER3





IOMUXC_PAD_WDOG_ANY__WDOG_ANY





IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1





IOMUXC_PAD_WDOG_ANY__GPIO1_IO15





IOMUXC_PAD_MUX_MODE_MASK





IOMUXC_PAD_MUX_MODE_SHIFT





IOMUXC_PAD_MUX_MODE(x)





IOMUXC_PAD_SION_MASK





IOMUXC_PAD_SION_SHIFT





IOMUXC_PAD_SION(x)





IOMUXC_PAD_DSE_MASK





IOMUXC_PAD_DSE_SHIFT





IOMUXC_PAD_DSE(x)





IOMUXC_PAD_FSEL1_MASK





IOMUXC_PAD_FSEL1_SHIFT





IOMUXC_PAD_FSEL1(x)





IOMUXC_PAD_PU_MASK





IOMUXC_PAD_PU_SHIFT





IOMUXC_PAD_PU(x)





IOMUXC_PAD_PD_MASK





IOMUXC_PAD_PD_SHIFT





IOMUXC_PAD_PD(x)





IOMUXC_PAD_OD_MASK





IOMUXC_PAD_OD_SHIFT





IOMUXC_PAD_OD(x)





IOMUXC_PAD_HYS_MASK





IOMUXC_PAD_HYS_SHIFT





IOMUXC_PAD_HYS(x)





IOMUXC_PAD_APC_MASK





IOMUXC_PAD_APC_SHIFT





IOMUXC_PAD_APC(x)





FSL_COMPONENT_ID





IRQSTEER: Interrupt Request Steering Driver#


irqsteer_data_t *IRQSTEER_GetIrqsteerData(int32_t instIdx)

Get the IRQSTEER data(some SoC information). 
This function gets the specified IRQSTEER data.

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 







int32_t IRQSTEER_GetInstIdxByIRQ(IRQn_Type irq)

Find the IRQSTEER instance index by IRQ number. 
This function iterates through all IRQSTEER instances to find which instance owns the given IRQ number. Supports instances with different interrupt counts.

Parameters:

irq – System interrupt number. 


Returns:
Instance index if found, -1 if not found. 






void IRQSTEER_Init(int32_t instIdx)

Initializes the IRQSTEER module. 
This function enables the clock gate for the specified IRQSTEER.

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 







void IRQSTEER_Deinit(int32_t instIdx)

Deinitializes an IRQSTEER instance for operation. 
The clock gate for the specified IRQSTEER is disabled.

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 







void IRQSTEER_EnableInterrupt(int32_t instIdx, IRQn_Type irq)

Enables an interrupt source. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
irq – Interrupt(system interrupt number) to be routed. The interrupt must be an IRQSTEER source. 







void IRQSTEER_DisableInterrupt(int32_t instIdx, IRQn_Type irq)

Disables an interrupt source. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
irq – Interrupt source number. The interrupt must be an IRQSTEER source. 







static inline bool IRQSTEER_InterruptIsEnabled(int32_t instIdx, IRQn_Type irq)

Check if an interrupt source is enabled. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
irq – Interrupt to be queried. The interrupt must be an IRQSTEER source. 


Returns:
true if the interrupt is not masked, false otherwise. 






static inline void IRQSTEER_SetInterrupt(int32_t instIdx, IRQn_Type irq, bool set)

Sets/Forces an interrupt. 

Note
This function is not affected by the function IRQSTEER_DisableInterrupt and IRQSTEER_EnableInterrupt. 


Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
irq – Interrupt to be set/forced. The interrupt must be an IRQSTEER source. 
set – Switcher of the interrupt set/force function. “true” means to set. “false” means not (normal operation). 







static inline void IRQSTEER_EnableMasterInterrupt(int32_t instIdx, uint32_t outputChanIdx)

Enables a master interrupt. By default, all the master interrupts are enabled. 

For example, to enable the interrupt sources of master 1: 
IRQSTEER_EnableMasterInterrupt(IRQSTEERM33_INST, 1);


 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Master index of interrupt sources to be routed, options available in enumeration ::irqsteer_int_master_t.







static inline void IRQSTEER_DisableMasterInterrupt(int32_t instIdx, uint32_t outputChanIdx)

Disables a master interrupt. 

For example, to disable the interrupt sources of master 1: 
IRQSTEER_DisableMasterInterrupt(IRQSTEER_M4_0, kIRQSTEER_InterruptMaster1);


 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Master index of interrupt sources to be disabled, options available in enumeration ::irqsteer_int_master_t.







static inline bool IRQSTEER_IsInterruptSet(int32_t instIdx, IRQn_Type irq)

Checks the status of one specific IRQSTEER interrupt. 

For example, to check whether interrupt from output 0 of Display 1 is set: 
if (IRQSTEER_IsInterruptSet(IRQSTEER_DISPLAY1_INT_OUT0)
{
    ...
}


 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
irq – Interrupt source status to be checked. The interrupt must be an IRQSTEER source. 


Returns:
The interrupt status. “true” means interrupt set. “false” means not.






static inline bool IRQSTEER_IsMasterInterruptSet(int32_t instIdx)

Checks the status of IRQSTEER master interrupt. The master interrupt status represents at least one interrupt is asserted or not among ALL interrupts. 

Note
The master interrupt status is not affected by the function IRQSTEER_DisableMasterInterrupt. 


Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 


Returns:
The master interrupt status. “true” means at least one interrupt set. “false” means not. 






IRQn_Type IRQSTEER_GetMasterNextInterrupt(int32_t instIdx, uint32_t outputChanIdx)

Gets the next interrupt source (currently set) of one specific master. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Master index of interrupt sources, options available in enumeration ::irqsteer_int_master_t. 


Returns:
The current set next interrupt source number of one specific master(output channel). Return IRQSTEER_INT_Invalid if no interrupt set. 






uint32_t IRQSTEER_GetMasterIrqCount(int32_t instIdx, uint32_t outputChanIdx)

Get the number of interrupt for a given master. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Master index of interrupt sources, options available in enumeration ::irqsteer_int_master_t. 


Returns:
Number of interrupts for a given master. 






uint64_t IRQSTEER_GetMasterInterruptsStatus(int32_t instIdx, uint32_t outputChanIdx)

Get the status of the interrupts a master is in charge of. 
What this function does is it takes the CHn_STATUS registers associated with the interrupts a master is in charge of and puts them in 64-bit variable. The order they are put in the 64-bit variable is the following: CHn_STATUS[i] : CHn_STATUS[i + 1], where CHn_STATUS[i + 1] is placed in the least significant half of the 64-bit variable. Assuming a master is in charge of 64 interrupts, the user may use the result of this function as such: BIT(i) & IRQSTEER_GetMasterInterrupts() to check if interrupt i is asserted.

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Index of IRQSTEER output channel. 


Returns:
64-bit variable containing the status of the interrupts a master is in charge of. 






static inline uint64_t IRQSTEER_GetGroupInterruptStatus(int32_t instIdx, uint32_t outputChanIdx)

Gets the status of IRQSTEER group interrupt. The group interrupt status represents all the interrupt status within the group specified. This API aims for facilitating the status return of one set of interrupts. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIndex – Index of the interrupt group(output channel) status to get. 


Returns:
The mask of the group interrupt status. Bit[n] set means the source with bit offset n in group intGroupIndex of IRQSTEER is asserted. 






void IRQSTEER_CommonIRQHandler(int32_t instIdx, uint32_t outputChanIdx)

Common IRQSTEER interrupt handler. 

Parameters:

instIdx – base address index in IRQSTEER peripheral base array. 
outputChanIdx – Master index of interrupt sources. ref “int”. 







FSL_IRQSTEER_DRIVER_VERSION

Version 2.0.1. 




IRQSTEER_CHANNEL_OFFSET





IRQSTEER_INT_SRC_REG_WIDTH





IRQSTEER_AGGREGATED_INT_NUM_PER_GRP





IRQSTEER_SLICE





IRQSTEER_CTRL_STRIDE_OFF(regNum, stepIdx)

Use irq channel 1, CHAN_MASK29 register as an example: irq channel 1, CHAN_MASK29 register offset: irqChanIdx = 1, regIdx = 29, regNum = 30 (irqChanIdx * IRQSTEER_CHANNEL_OFFSET) + IRQSTEER_CTRL_STRIDE_OFF(regNum, 0) + 0x4 * (regIdx) + 0x4 = (1 * 0x10000) + (30 * 4 * 0) + 0x4 * 29 + 0x4 = 0x10000 + 0 + 0x74 + 0x4 = 0x10078 




IRQSTEER_CHAN_MASK(irqChanIdx, regIdx, regNum)





IRQSTEER_CHAN_SET(irqChanIdx, regIdx, regNum)





IRQSTEER_CHAN_STATUS(irqChanIdx, regIdx, regNum)





IRQSTEER_CHAN_MINTDIS(irqChanIdx, regNum)





IRQSTEER_CHAN_MSTRSTAT(irqChanIdx, regNum)





IRQSTEER_GEN_REG_IDX(regNum, inputIdx)





IRQSTEER_IRQ_OFFSET





IRQSTEER_OUTPUT_CHAN_MAX_NUM





struct irqsteer_info_t


#include <fsl_irqsteer.h>
Find the instance index from base address and register offset mappings. 




struct irqsteer_data_t





Common Driver#


FSL_COMMON_DRIVER_VERSION

common driver version. 




DEBUG_CONSOLE_DEVICE_TYPE_NONE

No debug console. 




DEBUG_CONSOLE_DEVICE_TYPE_UART

Debug console based on UART. 




DEBUG_CONSOLE_DEVICE_TYPE_LPUART

Debug console based on LPUART. 




DEBUG_CONSOLE_DEVICE_TYPE_LPSCI

Debug console based on LPSCI. 




DEBUG_CONSOLE_DEVICE_TYPE_USBCDC

Debug console based on USBCDC. 




DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM

Debug console based on FLEXCOMM. 




DEBUG_CONSOLE_DEVICE_TYPE_IUART

Debug console based on i.MX UART. 




DEBUG_CONSOLE_DEVICE_TYPE_VUSART

Debug console based on LPC_VUSART. 




DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART

Debug console based on LPC_USART. 




DEBUG_CONSOLE_DEVICE_TYPE_SWO

Debug console based on SWO. 




DEBUG_CONSOLE_DEVICE_TYPE_QSCI

Debug console based on QSCI. 




MIN(a, b)

Computes the minimum of a and b. 




MAX(a, b)

Computes the maximum of a and b. 




UINT16_MAX

Max value of uint16_t type. 




UINT32_MAX

Max value of uint32_t type. 




UINTPTR_SIZE





UINT64_H(X)

Macro to get upper 32 bits of a 64-bit value 




UINT64_L(X)

Macro to get lower 32 bits of a 64-bit value 




MCUX_MASK_INVERT_8(mask)

8-bit mask inversion. 




MCUX_MASK_INVERT_16(mask)

16-bit mask inversion. 




MCUX_MASK_INVERT_32(mask)

32-bit mask inversion for completeness. 




MCUX_REG_WRITE8(reg, value)

8-bit register write macro 




MCUX_REG_WRITE16(reg, value)

16-bit register write macro 




MCUX_REG_WRITE32(reg, value)

32-bit register write macro 




MCUX_REG_READ8(reg)

8-bit register read macro 




MCUX_REG_READ16(reg)

16-bit register read macro 




MCUX_REG_READ32(reg)

32-bit register read macro 




MCUX_REG_BIT_SET8(reg, mask)

8-bit register bit set macro 




MCUX_REG_BIT_SET16(reg, mask)

16-bit register bit set macro 




MCUX_REG_BIT_SET32(reg, mask)

32-bit register bit set macro 




MCUX_REG_BIT_CLEAR8(reg, mask)

8-bit register bit clear macro 




MCUX_REG_BIT_CLEAR16(reg, mask)

16-bit register bit clear macro 




MCUX_REG_BIT_CLEAR32(reg, mask)

32-bit register bit clear macro 




MCUX_REG_BIT_GET8(reg, mask)

8-bit register bit get macro 




MCUX_REG_BIT_GET16(reg, mask)

16-bit register bit get macro 




MCUX_REG_BIT_GET32(reg, mask)

32-bit register bit get macro 




MCUX_REG_MODIFY8(reg, mask, value)

32-bit register read-modify-write macro 




MCUX_REG_MODIFY16(reg, mask, value)

16-bit register read-modify-write macro 




MCUX_REG_MODIFY32(reg, mask, value)

32-bit register read-modify-write macro 




SDK_ATOMIC_LOCAL_ADD(addr, val)

Add value val from the variable at address address. 




SDK_ATOMIC_LOCAL_SUB(addr, val)

Subtract value val to the variable at address address. 




SDK_ATOMIC_LOCAL_SET(addr, bits)

Set the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_CLEAR(addr, bits)

Clear the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)

Toggle the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)

For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits. 




SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)

For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false . 




SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)

For the variable at address address, set as newValue value and return old value. 




USEC_TO_COUNT(us, clockFreqInHz)

Macro to convert a microsecond period to raw count value 




COUNT_TO_USEC(count, clockFreqInHz)

Macro to convert a raw count value to microsecond 




MSEC_TO_COUNT(ms, clockFreqInHz)

Macro to convert a millisecond period to raw count value 




COUNT_TO_MSEC(count, clockFreqInHz)

Macro to convert a raw count value to millisecond 




SDK_ISR_EXIT_BARRIER





SDK_ALIGN(var, alignbytes)

Macro to define a variable with alignbytes alignment 




SDK_L1DCACHE_ALIGN(var)

Macro to define a variable with L1 d-cache line size alignment 




SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L2 cache line size alignment
Macro to change a value to a given size aligned value (rounded up) 




SDK_SIZEALIGN_UP(var, alignbytes)

Macro to change a value to a given size aligned value (rounded up), the wrapper of SDK_SIZEALIGN 




SDK_SIZEALIGN_DOWN(var, alignbytes)

Macro to change a value to a given size aligned value (rounded down) 




SDK_IS_ALIGNED(var, alignbytes)

Macro to check if a value is aligned to a given size 




AT_NONCACHEABLE_SECTION(var)

Define a variable var, and place it in non-cacheable section. 




AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)

Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. 




AT_NONCACHEABLE_SECTION_INIT(var)

Define a variable var with initial value, and place it in non-cacheable section. 




AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)

Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. 




MCUX_CS





AT_CACHE_LINE_SECTION(var)

Define a variable var, which is cache line size aligned and be placed in CacheLineData section. 




AT_CACHE_LINE_SECTION_INIT(var)

Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section. 




CACHE_LINE_DATA





AT_QUICKACCESS_SECTION_CODE(func)

Place function in a section which can be accessed quickly by core. 




AT_QUICKACCESS_SECTION_DATA(var)

Place data in a section which can be accessed quickly by core. 




AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)

Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes. 




MCUX_RAMFUNC

Function attribute to place function in RAM. For example, to place function my_func in ram, use like: 
MCUX_RAMFUNC my_func







RAMFUNCTION_SECTION_CODE(func)

Place function in ram. 




MCUX_DEPRECATED

Deprecated APIs. 




MCUX_DEPRECATED_MACRO

Deprecated macros. 




MCUX_EXPERIMENTAL

Experimental APIs. 




MCUX_EXPERIMENTAL_MACRO

Experimental macros. 




enum _status_groups

Status group numbers. 
Values:


enumerator kStatusGroup_Generic

Group number for generic status codes. 




enumerator kStatusGroup_FLASH

Group number for FLASH status codes. 




enumerator kStatusGroup_LPSPI

Group number for LPSPI status codes. 




enumerator kStatusGroup_FLEXIO_SPI

Group number for FLEXIO SPI status codes. 




enumerator kStatusGroup_DSPI

Group number for DSPI status codes. 




enumerator kStatusGroup_FLEXIO_UART

Group number for FLEXIO UART status codes. 




enumerator kStatusGroup_FLEXIO_I2C

Group number for FLEXIO I2C status codes. 




enumerator kStatusGroup_LPI2C

Group number for LPI2C status codes. 




enumerator kStatusGroup_UART

Group number for UART status codes. 




enumerator kStatusGroup_I2C

Group number for UART status codes. 




enumerator kStatusGroup_LPSCI

Group number for LPSCI status codes. 




enumerator kStatusGroup_LPUART

Group number for LPUART status codes. 




enumerator kStatusGroup_SPI

Group number for SPI status code. 




enumerator kStatusGroup_XRDC

Group number for XRDC status code. 




enumerator kStatusGroup_SEMA42

Group number for SEMA42 status code. 




enumerator kStatusGroup_SDHC

Group number for SDHC status code 




enumerator kStatusGroup_SDMMC

Group number for SDMMC status code 




enumerator kStatusGroup_SAI

Group number for SAI status code 




enumerator kStatusGroup_MCG

Group number for MCG status codes. 




enumerator kStatusGroup_SCG

Group number for SCG status codes. 




enumerator kStatusGroup_SDSPI

Group number for SDSPI status codes. 




enumerator kStatusGroup_FLEXIO_I2S

Group number for FLEXIO I2S status codes 




enumerator kStatusGroup_FLEXIO_MCULCD

Group number for FLEXIO LCD status codes 




enumerator kStatusGroup_FLASHIAP

Group number for FLASHIAP status codes 




enumerator kStatusGroup_FLEXCOMM_I2C

Group number for FLEXCOMM I2C status codes 




enumerator kStatusGroup_I2S

Group number for I2S status codes 




enumerator kStatusGroup_IUART

Group number for IUART status codes 




enumerator kStatusGroup_CSI

Group number for CSI status codes 




enumerator kStatusGroup_MIPI_DSI

Group number for MIPI DSI status codes 




enumerator kStatusGroup_SDRAMC

Group number for SDRAMC status codes. 




enumerator kStatusGroup_POWER

Group number for POWER status codes. 




enumerator kStatusGroup_ENET

Group number for ENET status codes. 




enumerator kStatusGroup_PHY

Group number for PHY status codes. 




enumerator kStatusGroup_TRGMUX

Group number for TRGMUX status codes. 




enumerator kStatusGroup_SMARTCARD

Group number for SMARTCARD status codes. 




enumerator kStatusGroup_LMEM

Group number for LMEM status codes. 




enumerator kStatusGroup_QSPI

Group number for QSPI status codes. 




enumerator kStatusGroup_DMA

Group number for DMA status codes. 




enumerator kStatusGroup_EDMA

Group number for EDMA status codes. 




enumerator kStatusGroup_DMAMGR

Group number for DMAMGR status codes. 




enumerator kStatusGroup_FLEXCAN

Group number for FlexCAN status codes. 




enumerator kStatusGroup_LTC

Group number for LTC status codes. 




enumerator kStatusGroup_FLEXIO_CAMERA

Group number for FLEXIO CAMERA status codes. 




enumerator kStatusGroup_LPC_SPI

Group number for LPC_SPI status codes. 




enumerator kStatusGroup_LPC_USART

Group number for LPC_USART status codes. 




enumerator kStatusGroup_DMIC

Group number for DMIC status codes. 




enumerator kStatusGroup_SDIF

Group number for SDIF status codes. 




enumerator kStatusGroup_SPIFI

Group number for SPIFI status codes. 




enumerator kStatusGroup_OTP

Group number for OTP status codes. 




enumerator kStatusGroup_MCAN

Group number for MCAN status codes. 




enumerator kStatusGroup_CAAM

Group number for CAAM status codes. 




enumerator kStatusGroup_ECSPI

Group number for ECSPI status codes. 




enumerator kStatusGroup_USDHC

Group number for USDHC status codes. 




enumerator kStatusGroup_LPC_I2C

Group number for LPC_I2C status codes. 




enumerator kStatusGroup_DCP

Group number for DCP status codes. 




enumerator kStatusGroup_MSCAN

Group number for MSCAN status codes. 




enumerator kStatusGroup_ESAI

Group number for ESAI status codes. 




enumerator kStatusGroup_FLEXSPI

Group number for FLEXSPI status codes. 




enumerator kStatusGroup_MMDC

Group number for MMDC status codes. 




enumerator kStatusGroup_PDM

Group number for MIC status codes. 




enumerator kStatusGroup_SDMA

Group number for SDMA status codes. 




enumerator kStatusGroup_ICS

Group number for ICS status codes. 




enumerator kStatusGroup_SPDIF

Group number for SPDIF status codes. 




enumerator kStatusGroup_LPC_MINISPI

Group number for LPC_MINISPI status codes. 




enumerator kStatusGroup_HASHCRYPT

Group number for Hashcrypt status codes 




enumerator kStatusGroup_LPC_SPI_SSP

Group number for LPC_SPI_SSP status codes. 




enumerator kStatusGroup_I3C

Group number for I3C status codes 




enumerator kStatusGroup_LPC_I2C_1

Group number for LPC_I2C_1 status codes. 




enumerator kStatusGroup_NOTIFIER

Group number for NOTIFIER status codes. 




enumerator kStatusGroup_DebugConsole

Group number for debug console status codes. 




enumerator kStatusGroup_SEMC

Group number for SEMC status codes. 




enumerator kStatusGroup_ApplicationRangeStart

Starting number for application groups. 




enumerator kStatusGroup_IAP

Group number for IAP status codes 




enumerator kStatusGroup_SFA

Group number for SFA status codes 




enumerator kStatusGroup_SPC

Group number for SPC status codes. 




enumerator kStatusGroup_PUF

Group number for PUF status codes. 




enumerator kStatusGroup_TOUCH_PANEL

Group number for touch panel status codes 




enumerator kStatusGroup_VBAT

Group number for VBAT status codes 




enumerator kStatusGroup_XSPI

Group number for XSPI status codes 




enumerator kStatusGroup_PNGDEC

Group number for PNGDEC status codes 




enumerator kStatusGroup_JPEGDEC

Group number for JPEGDEC status codes 




enumerator kStatusGroup_AUDMIX

Group number for AUDMIX status codes 




enumerator kStatusGroup_HAL_GPIO

Group number for HAL GPIO status codes. 




enumerator kStatusGroup_HAL_UART

Group number for HAL UART status codes. 




enumerator kStatusGroup_HAL_TIMER

Group number for HAL TIMER status codes. 




enumerator kStatusGroup_HAL_SPI

Group number for HAL SPI status codes. 




enumerator kStatusGroup_HAL_I2C

Group number for HAL I2C status codes. 




enumerator kStatusGroup_HAL_FLASH

Group number for HAL FLASH status codes. 




enumerator kStatusGroup_HAL_PWM

Group number for HAL PWM status codes. 




enumerator kStatusGroup_HAL_RNG

Group number for HAL RNG status codes. 




enumerator kStatusGroup_HAL_I2S

Group number for HAL I2S status codes. 




enumerator kStatusGroup_HAL_ADC_SENSOR

Group number for HAL ADC SENSOR status codes. 




enumerator kStatusGroup_TIMERMANAGER

Group number for TiMER MANAGER status codes. 




enumerator kStatusGroup_SERIALMANAGER

Group number for SERIAL MANAGER status codes. 




enumerator kStatusGroup_LED

Group number for LED status codes. 




enumerator kStatusGroup_BUTTON

Group number for BUTTON status codes. 




enumerator kStatusGroup_EXTERN_EEPROM

Group number for EXTERN EEPROM status codes. 




enumerator kStatusGroup_SHELL

Group number for SHELL status codes. 




enumerator kStatusGroup_MEM_MANAGER

Group number for MEM MANAGER status codes. 




enumerator kStatusGroup_LIST

Group number for List status codes. 




enumerator kStatusGroup_OSA

Group number for OSA status codes. 




enumerator kStatusGroup_COMMON_TASK

Group number for Common task status codes. 




enumerator kStatusGroup_MSG

Group number for messaging status codes. 




enumerator kStatusGroup_SDK_OCOTP

Group number for OCOTP status codes. 




enumerator kStatusGroup_SDK_FLEXSPINOR

Group number for FLEXSPINOR status codes. 




enumerator kStatusGroup_CODEC

Group number for codec status codes. 




enumerator kStatusGroup_ASRC

Group number for codec status ASRC. 




enumerator kStatusGroup_OTFAD

Group number for codec status codes. 




enumerator kStatusGroup_SDIOSLV

Group number for SDIOSLV status codes. 




enumerator kStatusGroup_MECC

Group number for MECC status codes. 




enumerator kStatusGroup_ENET_QOS

Group number for ENET_QOS status codes. 




enumerator kStatusGroup_LOG

Group number for LOG status codes. 




enumerator kStatusGroup_I3CBUS

Group number for I3CBUS status codes. 




enumerator kStatusGroup_QSCI

Group number for QSCI status codes. 




enumerator kStatusGroup_ELEMU

Group number for ELEMU status codes. 




enumerator kStatusGroup_QUEUEDSPI

Group number for QSPI status codes. 




enumerator kStatusGroup_POWER_MANAGER

Group number for POWER_MANAGER status codes. 




enumerator kStatusGroup_IPED

Group number for IPED status codes. 




enumerator kStatusGroup_ELS_PKC

Group number for ELS PKC status codes. 




enumerator kStatusGroup_CSS_PKC

Group number for CSS PKC status codes. 




enumerator kStatusGroup_HOSTIF

Group number for HOSTIF status codes. 




enumerator kStatusGroup_CLIF

Group number for CLIF status codes. 




enumerator kStatusGroup_BMA

Group number for BMA status codes. 




enumerator kStatusGroup_NETC

Group number for NETC status codes. 




enumerator kStatusGroup_ELE

Group number for ELE status codes. 




enumerator kStatusGroup_GLIKEY

Group number for GLIKEY status codes. 




enumerator kStatusGroup_AON_POWER

Group number for AON_POWER status codes. 




enumerator kStatusGroup_AON_COMMON

Group number for AON_COMMON status codes. 




enumerator kStatusGroup_ENDAT3

Group number for ENDAT3 status codes. 




enumerator kStatusGroup_HIPERFACE

Group number for HIPERFACE status codes. 




enumerator kStatusGroup_NPX

Group number for NPX status codes. 




enumerator kStatusGroup_ELA_CSEC

Group number for ELA_CSEC status codes. 




enumerator kStatusGroup_FLEXIO_T_FORMAT

Group number for T-format status codes. 




enumerator kStatusGroup_FLEXIO_A_FORMAT

Group number for A-format status codes. 




enumerator kStatusGroup_LPC_QSPI

Group number for LPC QSPI status codes. 




enumerator kStatusGroup_EVENT_CTRL

Group number for Event controller status codes. 







Generic status return codes. 
Values:


enumerator kStatus_Success

Generic status for Success. 




enumerator kStatus_Fail

Generic status for Fail. 




enumerator kStatus_ReadOnly

Generic status for read only failure. 




enumerator kStatus_OutOfRange

Generic status for out of range access. 




enumerator kStatus_InvalidArgument

Generic status for invalid argument check. 




enumerator kStatus_Timeout

Generic status for timeout. 




enumerator kStatus_NoTransferInProgress

Generic status for no transfer in progress. 




enumerator kStatus_Busy

Generic status for module is busy. 




enumerator kStatus_NoData

Generic status for no data is found for the operation. 






typedef int32_t status_t

Type used for all status and error return values. 




void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size. 
This is provided to support the dynamically allocated memory used in cache-able region. 

Parameters:

size – The length required to malloc. 
alignbytes – The alignment size. 


Return values:
The – allocated memory. 






void SDK_Free(void *ptr)

Free memory. 

Parameters:

ptr – The memory to be release. 







void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer. 

Parameters:

delayTime_us – Delay time in unit of microsecond. 
coreClock_Hz – Core clock frequency with Hz. 







void IRQSTEER_EnableInterrupt(int32_t irqsteerInstIdx, IRQn_Type interrupt)





void IRQSTEER_DisableInterrupt(int32_t irqsteerInstIdx, IRQn_Type interrupt)





int32_t IRQSTEER_GetInstIdxByIRQ(IRQn_Type irq)





static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt. 
Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number. 


Return values:

kStatus_Success – Interrupt enabled successfully 
kStatus_Fail – Failed to enable the interrupt 







static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt. 
Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number. 


Return values:

kStatus_Success – Interrupt disabled successfully 
kStatus_Fail – Failed to disable the interrupt 







static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to Enable. 
priNum – Priority number set to interrupt controller register. 


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to set. 
priNum – Priority number set to interrupt controller register.


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The flag which IRQ to clear.


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ. 
Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:
Current primask value. 






static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ. 
Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ(). 







static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)





static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)





FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ

Macro to use the default weak IRQ handler in drivers. 




MAKE_STATUS(group, code)

Construct a status code value from a group and code number. 




MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers. 
The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).
| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0






ARRAY_SIZE(x)

Computes the number of elements in an array. 




SUPPRESS_FALL_THROUGH_WARNING()

For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement. 




MSDK_REG_SECURE_ADDR(x)

Convert the register address to the one used in secure mode. 




MSDK_REG_NONSECURE_ADDR(x)

Convert the register address to the one used in non-secure mode. 




MSDK_HAS_DWT_CYCCNT

The chip supports DWT CYCCNT or not. 




MSDK_INVALID_IRQ_HANDLER

Invalid IRQ handler address. 




LPI2C: Low Power Inter-Integrated Circuit Driver#


void LPI2C_DriverIRQHandler(uint32_t instance)

LPI2C driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPI2C.

Parameters:

instance – LPI2C instance. 







FSL_LPI2C_DRIVER_VERSION

LPI2C driver version. 





LPI2C status return codes. 
Values:


enumerator kStatus_LPI2C_Busy

The master is already performing a transfer. 




enumerator kStatus_LPI2C_Idle

The slave driver is idle. 




enumerator kStatus_LPI2C_Nak

The slave device sent a NAK in response to a byte. 




enumerator kStatus_LPI2C_FifoError

FIFO under run or overrun. 




enumerator kStatus_LPI2C_BitError

Transferred bit was not seen on the bus. 




enumerator kStatus_LPI2C_ArbitrationLost

Arbitration lost error. 




enumerator kStatus_LPI2C_PinLowTimeout

SCL or SDA were held low longer than the timeout. 




enumerator kStatus_LPI2C_NoTransferInProgress

Attempt to abort a transfer when one is not in progress. 




enumerator kStatus_LPI2C_DmaRequestFail

DMA request failed. 




enumerator kStatus_LPI2C_Timeout

Timeout polling status flags. 






IRQn_Type const kLpi2cMasterIrqs[]

Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs. 




IRQn_Type const kLpi2cSlaveIrqs[]





lpi2c_master_isr_t s_lpi2cMasterIsr

Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs. 




void *s_lpi2cMasterHandle[]

Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs. 




uint32_t LPI2C_GetInstance(LPI2C_Type *base)

Returns an instance number given a base address. 
If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

base – The LPI2C peripheral base address. 


Returns:
LPI2C instance number starting from 0. 






I2C_RETRY_TIMES

Retry times for waiting flag. 




LPI2C Master Driver#


void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)

Provides a default configuration for the LPI2C master peripheral. 
This function provides the following default configuration for the LPI2C master peripheral: 
masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t. 







void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C master peripheral. 
This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The LPI2C peripheral base address. 
masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







void LPI2C_MasterDeinit(LPI2C_Type *base)

Deinitializes the LPI2C master peripheral. 
This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)

Configures LPI2C master data match feature. 

Parameters:

base – The LPI2C peripheral base address. 
matchConfig – Settings for the data match feature. 







status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)

Convert provided flags to status code, and clear any errors if present. 

Parameters:

base – The LPI2C peripheral base address. 
status – Current status flags value that will be checked. 


Return values:

kStatus_Success – 
kStatus_LPI2C_PinLowTimeout – 
kStatus_LPI2C_ArbitrationLost – 
kStatus_LPI2C_Nak – 
kStatus_LPI2C_FifoError – 







status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)

Make sure the bus isn’t already busy. 
A busy bus is allowed if we are the one driving it.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

kStatus_Success – 
kStatus_LPI2C_Busy – 







static inline void LPI2C_MasterReset(LPI2C_Type *base)

Performs a software reset. 
Restores the LPI2C master peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as master. 

Parameters:

base – The LPI2C peripheral base address. 
enable – Pass true to enable or false to disable the specified LPI2C as master. 







static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C master status flags. 
A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_lpi2c_master_flags



Parameters:

base – The LPI2C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C master status flag state. 
The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag


Attempts to clear other flags has no effect.

See also
_lpi2c_master_flags. 



Parameters:

base – The LPI2C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags(). 







static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C master interrupt requests. 
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C master interrupt requests. 
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C master interrupt requests. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)

Enables or disables LPI2C master DMA requests. 

Parameters:

base – The LPI2C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 







static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)

Gets LPI2C master transmit data register address for DMA transfer. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The LPI2C Master Transmit Data Register address. 






static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)

Gets LPI2C master receive data register address for DMA transfer. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The LPI2C Master Receive Data Register address. 






static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)

Sets the watermarks for LPI2C master FIFOs. 

Parameters:

base – The LPI2C peripheral base address. 
txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated. 
rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated. 







static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of words in the LPI2C master FIFOs. 

Parameters:

base – The LPI2C peripheral base address. 
txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required. 







void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)

Sets the I2C bus frequency for master transactions. 
The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note
Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.


Parameters:

base – The LPI2C peripheral base address. 
sourceClock_Hz – LPI2C functional clock frequency in Hertz. 
baudRate_Hz – Requested bus frequency in Hertz. 







static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle. 
Requires the master mode to be enabled.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a START signal and slave address on the I2C bus. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The LPI2C peripheral base address. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 







static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a repeated START signal and slave address on the I2C bus. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note
This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The LPI2C peripheral base address. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 







status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)

Performs a polling send transfer on the I2C bus. 
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

base – The LPI2C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Return values:

kStatus_Success – Data was sent successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or over run. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterStop(LPI2C_Type *base)

Sends a STOP signal on the I2C bus. 
This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C bus. 

Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.


Parameters:

base – The LPI2C peripheral base address. 
transfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C master non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 







status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 







void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The LPI2C peripheral base address. 
lpi2cMasterHandle – Pointer to the LPI2C master driver handle. 







enum _lpi2c_master_flags

LPI2C master peripheral flags. 
The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag


All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kLPI2C_MasterTxReadyFlag

Transmit data flag 




enumerator kLPI2C_MasterRxReadyFlag

Receive data flag 




enumerator kLPI2C_MasterEndOfPacketFlag

End Packet flag 




enumerator kLPI2C_MasterStopDetectFlag

Stop detect flag 




enumerator kLPI2C_MasterNackDetectFlag

NACK detect flag 




enumerator kLPI2C_MasterArbitrationLostFlag

Arbitration lost flag 




enumerator kLPI2C_MasterFifoErrFlag

FIFO error flag 




enumerator kLPI2C_MasterPinLowTimeoutFlag

Pin low timeout flag 




enumerator kLPI2C_MasterDataMatchFlag

Data match flag 




enumerator kLPI2C_MasterBusyFlag

Master busy flag 




enumerator kLPI2C_MasterBusBusyFlag

Bus busy flag 




enumerator kLPI2C_MasterClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kLPI2C_MasterIrqFlags

IRQ sources enabled by the non-blocking transactional API. 




enumerator kLPI2C_MasterErrorFlags

Errors to check for. 






enum _lpi2c_direction

Direction of master and slave transfers. 
Values:


enumerator kLPI2C_Write

Master transmit. 




enumerator kLPI2C_Read

Master receive. 






enum _lpi2c_master_pin_config

LPI2C pin configuration. 
Values:


enumerator kLPI2C_2PinOpenDrain

LPI2C Configured for 2-pin open drain mode 




enumerator kLPI2C_2PinOutputOnly

LPI2C Configured for 2-pin output only mode (ultra-fast mode) 




enumerator kLPI2C_2PinPushPull

LPI2C Configured for 2-pin push-pull mode 




enumerator kLPI2C_4PinPushPull

LPI2C Configured for 4-pin push-pull mode 




enumerator kLPI2C_2PinOpenDrainWithSeparateSlave

LPI2C Configured for 2-pin open drain mode with separate LPI2C slave 




enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave

LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave 




enumerator kLPI2C_2PinPushPullWithSeparateSlave

LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave 




enumerator kLPI2C_4PinPushPullWithInvertedOutput

LPI2C Configured for 4-pin push-pull mode(inverted outputs) 






enum _lpi2c_host_request_source

LPI2C master host request selection. 
Values:


enumerator kLPI2C_HostRequestExternalPin

Select the LPI2C_HREQ pin as the host request input 




enumerator kLPI2C_HostRequestInputTrigger

Select the input trigger as the host request input 






enum _lpi2c_host_request_polarity

LPI2C master host request pin polarity configuration. 
Values:


enumerator kLPI2C_HostRequestPinActiveLow

Configure the LPI2C_HREQ pin active low 




enumerator kLPI2C_HostRequestPinActiveHigh

Configure the LPI2C_HREQ pin active high 






enum _lpi2c_data_match_config_mode

LPI2C master data match configuration modes. 
Values:


enumerator kLPI2C_MatchDisabled

LPI2C Match Disabled 




enumerator kLPI2C_1stWordEqualsM0OrM1

LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 




enumerator kLPI2C_AnyWordEqualsM0OrM1

LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 




enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1

LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 




enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1

LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 




enumerator kLPI2C_1stWordAndM1EqualsM0AndM1

LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 




enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1

LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 






enum _lpi2c_master_transfer_flags

Transfer option flags. 

Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field. 

Values:


enumerator kLPI2C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal. 




enumerator kLPI2C_TransferNoStartFlag

Don’t send a start condition, address, and sub address 




enumerator kLPI2C_TransferNoStopFlag

Don’t send a stop condition. 






typedef enum _lpi2c_direction lpi2c_direction_t

Direction of master and slave transfers. 




typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t

LPI2C pin configuration. 




typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t

LPI2C master host request selection. 




typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t

LPI2C master host request pin polarity configuration. 




typedef struct _lpi2c_master_config lpi2c_master_config_t

Structure with settings to initialize the LPI2C master module. 
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t

LPI2C master data match configuration modes. 




typedef struct _lpi2c_match_config lpi2c_data_match_config_t

LPI2C master data match configuration structure. 




typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t

LPI2C master descriptor of the transfer. 




typedef struct _lpi2c_master_handle lpi2c_master_handle_t

LPI2C master handle of the transfer. 




typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)

Master completion callback function pointer type. 
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:
The LPI2C peripheral base address. 

Param handle:
Pointer to the LPI2C master driver handle. 

Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)

Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs. 




struct _lpi2c_master_config


#include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C master module. 
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableMaster

Whether to enable master mode. 




bool enableDoze

Whether master is enabled in doze mode. 




bool debugEnable

Enable transfers to continue when halted in debug mode. 




bool ignoreAck

Whether to ignore ACK/NACK. 




lpi2c_master_pin_config_t pinConfig

The pin configuration option. 




uint32_t baudRate_Hz

Desired baud rate in Hertz. 




uint32_t busIdleTimeout_ns

Bus idle timeout in nanoseconds. Set to 0 to disable. 




uint32_t pinLowTimeout_ns

Pin low timeout in nanoseconds. Set to 0 to disable. 




uint8_t sdaGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. 




uint8_t sclGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. 




struct _lpi2c_master_config hostRequest

Host request options. 







struct _lpi2c_match_config


#include <fsl_lpi2c.h>
LPI2C master data match configuration structure. 

Public Members


lpi2c_data_match_config_mode_t matchMode

Data match configuration setting. 




bool rxDataMatchOnly

When set to true, received data is ignored until a successful match. 




uint32_t match0

Match value 0. 




uint32_t match1

Match value 1. 







struct _lpi2c_master_transfer


#include <fsl_lpi2c.h>
Non-blocking transfer descriptor structure. 
This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. 

Public Members


uint32_t flags

Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers. 




uint16_t slaveAddress

The 7-bit slave address. 




lpi2c_direction_t direction

Either kLPI2C_Read or kLPI2C_Write. 




uint32_t subaddress

Sub address. Transferred MSB first. 




size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes. 




void *data

Pointer to data to transfer. 




size_t dataSize

Number of bytes to transfer. 







struct _lpi2c_master_handle


#include <fsl_lpi2c.h>
Driver handle for master non-blocking APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


uint8_t state

Transfer state machine current state. 




uint16_t remainingBytes

Remaining byte count in current state. 




uint8_t *buf

Buffer pointer for current state. 




uint16_t commandBuffer[6]

LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] 




lpi2c_master_transfer_t transfer

Copy of the current transfer info. 




lpi2c_master_transfer_callback_t completionCallback

Callback function pointer. 




void *userData

Application data passed to callback. 




uint16_t chunkSize

Remaining byte count in current chunk. 







struct hostRequest


Public Members


bool enable

Enable host request. 




lpi2c_host_request_source_t source

Host request source. 




lpi2c_host_request_polarity_t polarity

Host request pin polarity. 







LPI2C Master DMA Driver#


void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)

Create a new handle for the LPI2C master DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.
For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C master driver handle. 
rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I2C bus. 
The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 







status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress. 







status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 


Return values:

kStatus_Success – A transaction was successfully aborted. 
kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress. 







typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t

LPI2C master EDMA handle of the transfer. 




typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)

Master DMA completion callback function pointer type. 
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:
The LPI2C peripheral base address. 

Param handle:
Handle associated with the completed transfer. 

Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _lpi2c_master_edma_handle


#include <fsl_lpi2c_edma.h>
Driver handle for master DMA APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


LPI2C_Type *base

LPI2C base pointer. 




bool isBusy

Transfer state machine current state. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




uint16_t commandBuffer[20U]

LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words] 




lpi2c_master_transfer_t transfer

Copy of the current transfer info. 




lpi2c_master_edma_transfer_callback_t completionCallback

Callback function pointer. 




void *userData

Application data passed to callback. 




edma_handle_t *rx

Handle for receive DMA channel. 




edma_handle_t *tx

Handle for transmit DMA channel. 




edma_tcd_t tcds[3]

Software TCD. Three are allocated to provide enough room to align to 32-bytes. 







LPI2C Slave Driver#


void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)

Provides a default configuration for the LPI2C slave peripheral. 
This function provides the following default configuration for the LPI2C slave peripheral: 
slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;



After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t. 







void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C slave peripheral. 
This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

base – The LPI2C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time. 







void LPI2C_SlaveDeinit(LPI2C_Type *base)

Deinitializes the LPI2C slave peripheral. 
This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_SlaveReset(LPI2C_Type *base)

Performs a software reset of the LPI2C slave peripheral. 

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as slave. 

Parameters:

base – The LPI2C peripheral base address. 
enable – Pass true to enable or false to disable the specified LPI2C as slave. 







static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C slave status flags. 
A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_lpi2c_slave_flags



Parameters:

base – The LPI2C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C status flag state. 
The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag


Attempts to clear other flags has no effect.

See also
_lpi2c_slave_flags. 



Parameters:

base – The LPI2C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags(). 







static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C slave interrupt requests. 
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C slave interrupt requests. 
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C slave interrupt requests. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)

Enables or disables the LPI2C slave peripheral DMA requests. 

Parameters:

base – The LPI2C peripheral base address. 
enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request. 
enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable. 
enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable. 







static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle. 
Requires the slave mode to be enabled.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. 
Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

base – The LPI2C peripheral base address. 
ackOrNack – Pass true for an ACK or false for a NAK. 







static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)

Enables or disables ACKSTALL. 
When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

base – The LPI2C peripheral base address. 
enable – True will enable ACKSTALL,false will disable ACKSTALL. 







static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)

Returns the slave address sent by the I2C master. 
This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits. 






status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)

Performs a polling send transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 
actualTxSize – [out] 


Returns:
Error or success status returned by API. 






status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)

Performs a polling receive transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 
actualRxSize – [out] 


Returns:
Error or success status returned by API. 






void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C slave non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers. 
Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 
eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.


Return values:

kStatus_Success – Slave transfers were successfully started. 
kStatus_LPI2C_Busy – Slave transfers have already been started on this handle. 







status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to i2c_slave_handle_t structure. 
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – 







void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Aborts the slave non-blocking transfers. 

Note
This API could be called at any time to stop slave for handling the bus events. 


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 







void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 







enum _lpi2c_slave_flags

LPI2C slave peripheral flags. 
The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag


All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note
These enumerations are meant to be OR’d together to form a bit mask. 

Values:


enumerator kLPI2C_SlaveTxReadyFlag

Transmit data flag 




enumerator kLPI2C_SlaveRxReadyFlag

Receive data flag 




enumerator kLPI2C_SlaveAddressValidFlag

Address valid flag 




enumerator kLPI2C_SlaveTransmitAckFlag

Transmit ACK flag 




enumerator kLPI2C_SlaveRepeatedStartDetectFlag

Repeated start detect flag 




enumerator kLPI2C_SlaveStopDetectFlag

Stop detect flag 




enumerator kLPI2C_SlaveBitErrFlag

Bit error flag 




enumerator kLPI2C_SlaveFifoErrFlag

FIFO error flag 




enumerator kLPI2C_SlaveAddressMatch0Flag

Address match 0 flag 




enumerator kLPI2C_SlaveAddressMatch1Flag

Address match 1 flag 




enumerator kLPI2C_SlaveGeneralCallFlag

General call flag 




enumerator kLPI2C_SlaveBusyFlag

Master busy flag 




enumerator kLPI2C_SlaveBusBusyFlag

Bus busy flag 




enumerator kLPI2C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kLPI2C_SlaveIrqFlags

IRQ sources enabled by the non-blocking transactional API. 




enumerator kLPI2C_SlaveErrorFlags

Errors to check for. 






enum _lpi2c_slave_address_match

LPI2C slave address match options. 
Values:


enumerator kLPI2C_MatchAddress0

Match only address 0. 




enumerator kLPI2C_MatchAddress0OrAddress1

Match either address 0 or address 1. 




enumerator kLPI2C_MatchAddress0ThroughAddress1

Match a range of slave addresses from address 0 through address 1. 






enum _lpi2c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 

Values:


enumerator kLPI2C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start. 




enumerator kLPI2C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role). 




enumerator kLPI2C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kLPI2C_SlaveTransmitAckEvent

Callback needs to either transmit an ACK or NACK. 




enumerator kLPI2C_SlaveRepeatedStartEvent

A repeated start was detected. 




enumerator kLPI2C_SlaveCompletionEvent

A stop was detected, completing the transfer. 




enumerator kLPI2C_SlaveAllEvents

Bit mask of all available events. 






typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t

LPI2C slave address match options. 




typedef struct _lpi2c_slave_config lpi2c_slave_config_t

Structure with settings to initialize the LPI2C slave module. 
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 





typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t

LPI2C slave transfer structure. 




typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t

LPI2C slave handle structure. 




typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:
Base address for the LPI2C instance on which the event occurred. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _lpi2c_slave_config


#include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C slave module. 
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableSlave

Enable slave mode. 




uint8_t address0

Slave’s 7-bit address. 




uint8_t address1

Alternate slave 7-bit address. 




lpi2c_slave_address_match_t addressMatchMode

Address matching options. 




bool filterDozeEnable

Enable digital glitch filter in doze mode. 




bool filterEnable

Enable digital glitch filter. 




bool enableGeneralCall

Enable general call address matching. 




struct _lpi2c_slave_config sclStall

SCL stall enable options. 




bool ignoreAck

Continue transfers after a NACK is detected. 




bool enableReceivedAddressRead

Enable reading the address received address as the first byte of data. 




uint32_t sdaGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable. 




uint32_t sclGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable. 




uint32_t dataValidDelay_ns

Width in nanoseconds of the data valid delay. 




uint32_t clockHoldTime_ns

Width in nanoseconds of the clock hold time. 







struct _lpi2c_slave_transfer


#include <fsl_lpi2c.h>
LPI2C slave transfer structure. 

Public Members


lpi2c_slave_transfer_event_t event

Reason the callback is being invoked. 




uint8_t receivedAddress

Matching address send by master. 




uint8_t *data

Transfer buffer 




size_t dataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent. 




size_t transferredCount

Number of bytes actually transferred since start or last repeated start. 







struct _lpi2c_slave_handle


#include <fsl_lpi2c.h>
LPI2C slave handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


lpi2c_slave_transfer_t transfer

LPI2C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




uint32_t eventMask

Mask of enabled events. 




uint32_t transferredCount

Count of bytes transferred. 




lpi2c_slave_transfer_callback_t callback

Callback function called at transfer event. 




void *userData

Callback parameter passed to callback. 







struct sclStall


Public Members


bool enableAck

Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall. 




bool enableTx

Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer. 




bool enableRx

Enables SCL clock stretching when receive data flag is set during a slave-receive transfer. 




bool enableAddress

Enables SCL clock stretching when the address valid flag is asserted. 







LPIT: Low-Power Interrupt Timer#


void LPIT_Init(LPIT_Type *base, const lpit_config_t *config)

Ungates the LPIT clock and configures the peripheral for a basic operation. 
This function issues a software reset to reset all channels and registers except the Module Control register.

Note
This API should be called at the beginning of the application using the LPIT driver.


Parameters:

base – LPIT peripheral base address. 
config – Pointer to the user configuration structure. 







void LPIT_Deinit(LPIT_Type *base)

Disables the module and gates the LPIT clock. 

Parameters:

base – LPIT peripheral base address. 







void LPIT_GetDefaultConfig(lpit_config_t *config)

Fills in the LPIT configuration structure with default settings. 
The default values are: 
config->enableRunInDebug = false;
config->enableRunInDoze = false;


 

Parameters:

config – Pointer to the user configuration structure. 







status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl_params_t *chnlSetup)

Sets up an LPIT channel based on the user’s preference. 
This function sets up the operation mode to one of the options available in the enumeration lpit_timer_modes_t. It sets the trigger source as either internal or external, trigger selection and the timers behaviour when a timeout occurs. It also chains the timer if a prior timer if requested by the user.

Parameters:

base – LPIT peripheral base address. 
channel – Channel that is being configured. 
chnlSetup – Configuration parameters. 







static inline void LPIT_EnableInterrupts(LPIT_Type *base, uint32_t mask)

Enables the selected PIT interrupts. 

Parameters:

base – LPIT peripheral base address. 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t







static inline void LPIT_DisableInterrupts(LPIT_Type *base, uint32_t mask)

Disables the selected PIT interrupts. 

Parameters:

base – LPIT peripheral base address. 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t







static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type *base)

Gets the enabled LPIT interrupts. 

Parameters:

base – LPIT peripheral base address.


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lpit_interrupt_enable_t






static inline uint32_t LPIT_GetStatusFlags(LPIT_Type *base)

Gets the LPIT status flags. 

Parameters:

base – LPIT peripheral base address.


Returns:
The status flags. This is the logical OR of members of the enumeration lpit_status_flags_t






static inline void LPIT_ClearStatusFlags(LPIT_Type *base, uint32_t mask)

Clears the LPIT status flags. 

Parameters:

base – LPIT peripheral base address. 
mask – The status flags to clear. This is a logical OR of members of the enumeration lpit_status_flags_t







static inline void LPIT_SetTimerPeriod(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count. 
Timers begin counting down from the value set by this function until it reaches 0, at which point it generates an interrupt and loads this register value again. Writing a new value to this register does not restart the timer. Instead, the value is loaded after the timer expires.

Note
User can call the utility macros provided in fsl_common.h to convert to ticks.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 
ticks – Timer period in units of ticks. 







static inline void LPIT_SetTimerValue(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count. 
In the Dual 16-bit Periodic Counter mode, the counter will load and then the lower 16-bits will decrement down to zero, which will assert the output pre-trigger. The upper 16-bits will then decrement down to zero, which will negate the output pre-trigger and set the timer interrupt flag.

Note
Set TVAL register to 0 or 1 is invalid in compare mode.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 
ticks – Timer period in units of ticks. 







static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type *base, lpit_chnl_t channel)

Reads the current timer counting value. 
This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note
User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number.


Returns:
Current timer counting value in ticks. 






static inline void LPIT_StartTimer(LPIT_Type *base, lpit_chnl_t channel)

Starts the timer counting. 
After calling this function, timers load the period value and count down to 0. When the timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.

Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 







static inline void LPIT_StopTimer(LPIT_Type *base, lpit_chnl_t channel)

Stops the timer counting. 

Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 







FSL_LPIT_DRIVER_VERSION

Version 2.1.3 




enum _lpit_chnl

List of LPIT channels. 

Note
Actual number of available channels is SoC-dependent 

Values:


enumerator kLPIT_Chnl_0

LPIT channel number 0 




enumerator kLPIT_Chnl_1

LPIT channel number 1 




enumerator kLPIT_Chnl_2

LPIT channel number 2 




enumerator kLPIT_Chnl_3

LPIT channel number 3 






enum _lpit_timer_modes

Mode options available for the LPIT timer. 
Values:


enumerator kLPIT_PeriodicCounter

Use the all 32-bits, counter loads and decrements to zero 




enumerator kLPIT_DualPeriodicCounter

Counter loads, lower 16-bits decrement to zero, then upper 16-bits decrement 




enumerator kLPIT_TriggerAccumulator

Counter loads on first trigger and decrements on each trigger 




enumerator kLPIT_InputCapture

Counter loads with 0xFFFFFFFF, decrements to zero. It stores the inverse of the current value when a input trigger is detected 






enum _lpit_trigger_select

Trigger options available. 
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual. 
Values:


enumerator kLPIT_Trigger_TimerChn0

Channel 0 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn1

Channel 1 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn2

Channel 2 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn3

Channel 3 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn4

Channel 4 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn5

Channel 5 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn6

Channel 6 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn7

Channel 7 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn8

Channel 8 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn9

Channel 9 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn10

Channel 10 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn11

Channel 11 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn12

Channel 12 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn13

Channel 13 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn14

Channel 14 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn15

Channel 15 is selected as a trigger source 






enum _lpit_trigger_source

Trigger source options available. 
Values:


enumerator kLPIT_TriggerSource_External

Use external trigger input 




enumerator kLPIT_TriggerSource_Internal

Use internal trigger 






enum _lpit_interrupt_enable

List of LPIT interrupts. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 

Values:


enumerator kLPIT_Channel0TimerInterruptEnable

Channel 0 Timer interrupt 




enumerator kLPIT_Channel1TimerInterruptEnable

Channel 1 Timer interrupt 




enumerator kLPIT_Channel2TimerInterruptEnable

Channel 2 Timer interrupt 




enumerator kLPIT_Channel3TimerInterruptEnable

Channel 3 Timer interrupt 






enum _lpit_status_flags

List of LPIT status flags. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 

Values:


enumerator kLPIT_Channel0TimerFlag

Channel 0 Timer interrupt flag 




enumerator kLPIT_Channel1TimerFlag

Channel 1 Timer interrupt flag 




enumerator kLPIT_Channel2TimerFlag

Channel 2 Timer interrupt flag 




enumerator kLPIT_Channel3TimerFlag

Channel 3 Timer interrupt flag 






typedef enum _lpit_chnl lpit_chnl_t

List of LPIT channels. 

Note
Actual number of available channels is SoC-dependent 





typedef enum _lpit_timer_modes lpit_timer_modes_t

Mode options available for the LPIT timer. 




typedef enum _lpit_trigger_select lpit_trigger_select_t

Trigger options available. 
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual. 




typedef enum _lpit_trigger_source lpit_trigger_source_t

Trigger source options available. 




typedef enum _lpit_interrupt_enable lpit_interrupt_enable_t

List of LPIT interrupts. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 





typedef enum _lpit_status_flags lpit_status_flags_t

List of LPIT status flags. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 





typedef struct _lpit_chnl_params lpit_chnl_params_t

Structure to configure the channel timer. 




typedef struct _lpit_config lpit_config_t

LPIT configuration structure. 
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash. 




static void LPIT_ResetStateDelay(void)

Short wait for LPIT state reset. 
After clear or set LPIT_EN, there should be delay longer than 4 LPIT functional clock. 




static inline void LPIT_Reset(LPIT_Type *base)

Performs a software reset on the LPIT module. 
This resets all channels and registers except the Module Control Register.

Parameters:

base – LPIT peripheral base address. 







LPIT_RESET_STATE_DELAY

Delay used in LPIT_Reset. 
The macro value should be larger than 4 * core clock / LPIT peripheral clock. 




struct _lpit_chnl_params


#include <fsl_lpit.h>
Structure to configure the channel timer. 

Public Members


bool chainChannel

true: Timer chained to previous timer; false: Timer not chained 




lpit_timer_modes_t timerMode

Timers mode of operation. 




lpit_trigger_select_t triggerSelect

Trigger selection for the timer 




lpit_trigger_source_t triggerSource

Decides if we use external or internal trigger. 




bool enableReloadOnTrigger

true: Timer reloads when a trigger is detected; false: No effect 




bool enableStopOnTimeout

true: Timer will stop after timeout; false: does not stop after timeout 




bool enableStartOnTrigger

true: Timer starts when a trigger is detected; false: decrement immediately 







struct _lpit_config


#include <fsl_lpit.h>
LPIT configuration structure. 
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash. 

Public Members


bool enableRunInDebug

true: Timers run in debug mode; false: Timers stop in debug mode 




bool enableRunInDoze

true: Timers run in doze mode; false: Timers stop in doze mode 







LPSPI: Low Power Serial Peripheral Interface#


LPSPI Peripheral driver#


void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the LPSPI master. 

Parameters:

base – LPSPI peripheral address. 
masterConfig – Pointer to structure lpspi_master_config_t. 
srcClock_Hz – Module source input clock in Hertz 







void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)

Sets the lpspi_master_config_t structure to default values. 
This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example: 
lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);


 

Parameters:

masterConfig – pointer to lpspi_master_config_t structure 







void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)

LPSPI slave configuration. 

Parameters:

base – LPSPI peripheral address. 
slaveConfig – Pointer to a structure lpspi_slave_config_t. 







void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)

Sets the lpspi_slave_config_t structure to default values. 
This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example: 
lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);


 

Parameters:

slaveConfig – pointer to lpspi_slave_config_t structure. 







void LPSPI_Deinit(LPSPI_Type *base)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. 

Parameters:

base – LPSPI peripheral address. 







void LPSPI_Reset(LPSPI_Type *base)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API. 

Parameters:

base – LPSPI peripheral address. 







uint32_t LPSPI_GetInstance(LPSPI_Type *base)

Get the LPSPI instance from peripheral base address. 

Parameters:

base – LPSPI peripheral base address. 


Returns:
LPSPI instance. 






static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)

Enables the LPSPI peripheral and sets the MCR MDIS to 0. 

Parameters:

base – LPSPI peripheral address. 
enable – Pass true to enable module, false to disable module. 







static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)

Gets the LPSPI status flag state. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI status(in SR register). 






static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)

Gets the LPSPI Tx FIFO size. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Tx FIFO size. 






static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)

Gets the LPSPI Rx FIFO size. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Rx FIFO size. 






static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)

Gets the LPSPI Tx FIFO count. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The number of words in the transmit FIFO. 






static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)

Gets the LPSPI Rx FIFO count. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The number of words in the receive FIFO. 






static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)

Clears the LPSPI status flag. 
This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage: 
LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);




Parameters:

base – LPSPI peripheral address. 
statusFlags – The status flag used from type _lpspi_flags. 







static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)





static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI interrupts. 
This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );



Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable. 







static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI interrupts. 
LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );



Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable. 







static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI DMA request. 
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);




Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_dma_enable. 







static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI DMA request. 
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 
SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);




Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_dma_enable. 







static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Transmit Data Register address for a DMA operation. 
This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Transmit Data Register address. 






static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Receive Data Register address for a DMA operation. 
This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Receive Data Register address. 






bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)

Check the argument for transfer . 

Parameters:

base – LPSPI peripheral address. 
transfer – the transfer struct to be used. 
isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer 


Returns:
Return true for right and false for wrong. 






static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)

Configures the LPSPI for either master or slave. 
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

base – LPSPI peripheral address. 
mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t. 







static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)

Configures the peripheral chip select used for the transfer. 

Parameters:

base – LPSPI peripheral address. 
select – LPSPI Peripheral Chip Select (PCS) configuration. 







static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)

Set the PCS signal to continuous or uncontinuous mode. 

Note
In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).


Parameters:

base – LPSPI peripheral address. 
IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. 







static inline bool LPSPI_IsMaster(LPSPI_Type *base)

Returns whether the LPSPI module is in master mode. 

Parameters:

base – LPSPI peripheral address. 


Returns:
Returns true if the module is in master mode or false if the module is in slave mode. 






static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)

Flushes the LPSPI FIFOs. 

Parameters:

base – LPSPI peripheral address. 
flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. 
flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. 







static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)

Sets the transmit and receive FIFO watermark values. 
This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

base – LPSPI peripheral address. 
txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 
rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 







static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)

Configures all LPSPI peripheral chip select polarities simultaneously. 
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific. 
LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);




Parameters:

base – LPSPI peripheral address. 
mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity. 







static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)

Configures the frame size. 
The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.
Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

base – LPSPI peripheral address. 
frameSize – The frame size in number of bits. 







uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)

Sets the LPSPI baud rate in bits per second. 
This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address. 
baudRate_Bps – The desired baud rate in bits per second. 
srcClock_Hz – Module source input clock in Hertz. 
tcrPrescaleValue – The TCR prescale value needed to program the TCR. 


Returns:
The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled. 






void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values). 
This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.
The delay names are available in type lpspi_delay_type_t.
The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address. 
scaler – The 8-bit delay value 0x00 to 0xFF (255). 
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t. 







uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values). 
This function configures the SCK to PCS delay, PCS to SCK delay, or the delay between transfers. The delay names are available in type lpspi_delay_type_t.
The function calculates the value needed for the desired delay parameter and returns the actual calculated delay. An exact delay match may not be possible, in which case the closest match is calculated without going below the desired delay value. If the input exceeds the maximum capability, the maximum supported delay is returned.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address. 
delayTimeInNanoSec – The desired delay value in nanoseconds. 
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t. 
srcClock_Hz – Module source input clock in Hertz. 


Returns:
Actual calculated delay value in nanoseconds. 






static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)

Writes data into the transmit data buffer. 
This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

base – LPSPI peripheral address. 
data – The data word to be sent. 







static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)

Reads data from the data buffer. 
This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The data read from the data buffer. 






void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)

Set up the dummy data. 

Parameters:

base – LPSPI peripheral address. 
dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated. 







void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)

Initializes the LPSPI master handle. 
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address. 
handle – LPSPI handle pointer to lpspi_master_handle_t. 
callback – DSPI callback. 
userData – callback function parameter. 







status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)

LPSPI master transfer data using a polling method. 
This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using an interrupt method. 
This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)

Gets the master transfer remaining bytes. 
This function gets the master transfer remaining bytes.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the non-blocking transaction. 


Returns:
status of status_t. 






void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI master abort transfer which uses an interrupt method. 
This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 







void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI Master IRQ handler function. 
This function processes the LPSPI transmit and receive IRQ.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 







void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)

Initializes the LPSPI slave handle. 
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address. 
handle – LPSPI handle pointer to lpspi_slave_handle_t. 
callback – DSPI callback. 
userData – callback function parameter. 







status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfer data using an interrupt method. 
This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes. 
This function gets the slave transfer remaining bytes.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the non-blocking transaction. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI slave aborts a transfer which uses an interrupt method. 
This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 







void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI Slave IRQ handler function. 
This function processes the LPSPI transmit and receives an IRQ.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 







bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)

Wait for tx FIFO to be empty. 
This function wait the tx fifo empty

Parameters:

base – LPSPI peripheral address. 


Returns:
true for the tx FIFO is ready, false is not. 






void LPSPI_DriverIRQHandler(uint32_t instance)

LPSPI driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPSPI.

Parameters:

instance – LPSPI instance. 







FSL_LPSPI_DRIVER_VERSION

LPSPI driver version. 





Status for the LPSPI driver. 
Values:


enumerator kStatus_LPSPI_Busy

LPSPI transfer is busy. 




enumerator kStatus_LPSPI_Error

LPSPI driver error. 




enumerator kStatus_LPSPI_Idle

LPSPI is idle. 




enumerator kStatus_LPSPI_OutOfRange

LPSPI transfer out Of range. 




enumerator kStatus_LPSPI_Timeout

LPSPI timeout polling status flags. 






enum _lpspi_flags

LPSPI status flags in SPIx_SR register. 
Values:


enumerator kLPSPI_TxDataRequestFlag

Transmit data flag 




enumerator kLPSPI_RxDataReadyFlag

Receive data flag 




enumerator kLPSPI_WordCompleteFlag

Word Complete flag 




enumerator kLPSPI_FrameCompleteFlag

Frame Complete flag 




enumerator kLPSPI_TransferCompleteFlag

Transfer Complete flag 




enumerator kLPSPI_TransmitErrorFlag

Transmit Error flag (FIFO underrun) 




enumerator kLPSPI_ReceiveErrorFlag

Receive Error flag (FIFO overrun) 




enumerator kLPSPI_DataMatchFlag

Data Match flag 




enumerator kLPSPI_ModuleBusyFlag

Module Busy flag 




enumerator kLPSPI_AllStatusFlag

Used for clearing all w1c status flags 






enum _lpspi_interrupt_enable

LPSPI interrupt source. 
Values:


enumerator kLPSPI_TxInterruptEnable

Transmit data interrupt enable 




enumerator kLPSPI_RxInterruptEnable

Receive data interrupt enable 




enumerator kLPSPI_WordCompleteInterruptEnable

Word complete interrupt enable 




enumerator kLPSPI_FrameCompleteInterruptEnable

Frame complete interrupt enable 




enumerator kLPSPI_TransferCompleteInterruptEnable

Transfer complete interrupt enable 




enumerator kLPSPI_TransmitErrorInterruptEnable

Transmit error interrupt enable(FIFO underrun) 




enumerator kLPSPI_ReceiveErrorInterruptEnable

Receive Error interrupt enable (FIFO overrun) 




enumerator kLPSPI_DataMatchInterruptEnable

Data Match interrupt enable 




enumerator kLPSPI_AllInterruptEnable

All above interrupts enable. 






enum _lpspi_dma_enable

LPSPI DMA source. 
Values:


enumerator kLPSPI_TxDmaEnable

Transmit data DMA enable 




enumerator kLPSPI_RxDmaEnable

Receive data DMA enable 






enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration. 
Values:


enumerator kLPSPI_Master

LPSPI peripheral operates in master mode. 




enumerator kLPSPI_Slave

LPSPI peripheral operates in slave mode. 






enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure). 
Values:


enumerator kLPSPI_Pcs0

PCS[0] 




enumerator kLPSPI_Pcs1

PCS[1] 




enumerator kLPSPI_Pcs2

PCS[2] 




enumerator kLPSPI_Pcs3

PCS[3] 






enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration. 
Values:


enumerator kLPSPI_PcsActiveHigh

PCS Active High (idles low) 




enumerator kLPSPI_PcsActiveLow

PCS Active Low (idles high) 






enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity. 
Values:


enumerator kLPSPI_Pcs0ActiveLow

Pcs0 Active Low (idles high). 




enumerator kLPSPI_Pcs1ActiveLow

Pcs1 Active Low (idles high). 




enumerator kLPSPI_Pcs2ActiveLow

Pcs2 Active Low (idles high). 




enumerator kLPSPI_Pcs3ActiveLow

Pcs3 Active Low (idles high). 




enumerator kLPSPI_PcsAllActiveLow

Pcs0 to Pcs5 Active Low (idles high). 






enum _lpspi_clock_polarity

LPSPI clock polarity configuration. 
Values:


enumerator kLPSPI_ClockPolarityActiveHigh

CPOL=0. Active-high LPSPI clock (idles low) 




enumerator kLPSPI_ClockPolarityActiveLow

CPOL=1. Active-low LPSPI clock (idles high) 






enum _lpspi_clock_phase

LPSPI clock phase configuration. 
Values:


enumerator kLPSPI_ClockPhaseFirstEdge

CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge. 




enumerator kLPSPI_ClockPhaseSecondEdge

CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge. 






enum _lpspi_shift_direction

LPSPI data shifter direction options. 
Values:


enumerator kLPSPI_MsbFirst

Data transfers start with most significant bit. 




enumerator kLPSPI_LsbFirst

Data transfers start with least significant bit. 






enum _lpspi_host_request_select

LPSPI Host Request select configuration. 
Values:


enumerator kLPSPI_HostReqExtPin

Host Request is an ext pin. 




enumerator kLPSPI_HostReqInternalTrigger

Host Request is an internal trigger. 






enum _lpspi_match_config

LPSPI Match configuration options. 
Values:


enumerator kLPSI_MatchDisabled

LPSPI Match Disabled. 




enumerator kLPSI_1stWordEqualsM0orM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordEqualsM0orM1

LPSPI Match Enabled. 




enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1

LPSPI Match Enabled. 




enumerator kLPSI_1stWordAndM1EqualsM0andM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordAndM1EqualsM0andM1

LPSPI Match Enabled. 






enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration. 
Values:


enumerator kLPSPI_SdiInSdoOut

LPSPI SDI input, SDO output. 




enumerator kLPSPI_SdiInSdiOut

LPSPI SDI input, SDI output. 




enumerator kLPSPI_SdoInSdoOut

LPSPI SDO input, SDO output. 




enumerator kLPSPI_SdoInSdiOut

LPSPI SDO input, SDI output. 






enum _lpspi_data_out_config

LPSPI data output configuration. 
Values:


enumerator kLpspiDataOutRetained

Data out retains last value when chip select is de-asserted 




enumerator kLpspiDataOutTristate

Data out is tristated when chip select is de-asserted 






enum _lpspi_transfer_width

LPSPI transfer width configuration. 
Values:


enumerator kLPSPI_SingleBitXfer

1-bit shift at a time, data out on SDO, in on SDI (normal mode) 




enumerator kLPSPI_TwoBitXfer

2-bits shift out on SDO/SDI and in on SDO/SDI 




enumerator kLPSPI_FourBitXfer

4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] 






enum _lpspi_delay_type

LPSPI delay type selection. 
Values:


enumerator kLPSPI_PcsToSck

PCS-to-SCK delay. 




enumerator kLPSPI_LastSckToPcs

Last SCK edge to PCS delay. 




enumerator kLPSPI_BetweenTransfer

Delay between transfers. 






enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags. 
Values:


enumerator kLPSPI_MasterPcs0

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal 




enumerator kLPSPI_MasterPcs1

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal 




enumerator kLPSPI_MasterPcs2

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal 




enumerator kLPSPI_MasterPcs3

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal 




enumerator kLPSPI_MasterPcsContinuous

Is PCS signal continuous 




enumerator kLPSPI_MasterByteSwap

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. 








enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags. 
Values:


enumerator kLPSPI_SlavePcs0

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal 




enumerator kLPSPI_SlavePcs1

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal 




enumerator kLPSPI_SlavePcs2

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal 




enumerator kLPSPI_SlavePcs3

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal 




enumerator kLPSPI_SlaveByteSwap

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. 








enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine. 
Values:


enumerator kLPSPI_Idle

Nothing in the transmitter/receiver. 




enumerator kLPSPI_Busy

Transfer queue is not finished. 




enumerator kLPSPI_Error

Transfer error. 






typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration. 




typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure). 




typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration. 




typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration. 




typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration. 




typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options. 




typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration. 




typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options. 




typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration. 




typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration. 




typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration. 




typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection. 




typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure. 




typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure. 




typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs. 




typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs. 




typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type. 

Param base:
LPSPI peripheral address. 

Param handle:
Pointer to the handle for the LPSPI master. 

Param status:
Success or error code describing whether the transfer is completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type. 

Param base:
LPSPI peripheral address. 

Param handle:
Pointer to the handle for the LPSPI slave. 

Param status:
Success or error code describing whether the transfer is completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure. 




volatile uint8_t g_lpspiDummyData[]

Global variable for dummy data value setting. 




LPSPI_DUMMY_DATA

LPSPI dummy data if no Tx data. 
Dummy data used for tx if there is not txData. 




SPI_RETRY_TIMES

Retry times for waiting flag. 




LPSPI_MASTER_PCS_SHIFT

LPSPI master PCS shift macro , internal used. 




LPSPI_MASTER_PCS_MASK

LPSPI master PCS shift macro , internal used. 




LPSPI_SLAVE_PCS_SHIFT

LPSPI slave PCS shift macro , internal used. 




LPSPI_SLAVE_PCS_MASK

LPSPI slave PCS shift macro , internal used. 




struct _lpspi_master_config


#include <fsl_lpspi.h>
LPSPI master configuration structure. 

Public Members


uint32_t baudRate

Baud Rate for LPSPI. 




uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096. 




lpspi_clock_polarity_t cpol

Clock polarity. 




lpspi_clock_phase_t cpha

Clock phase. 




lpspi_shift_direction_t direction

MSB or LSB data shift direction. 




uint32_t pcsToSckDelayInNanoSec

PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




uint32_t lastSckToPcsDelayInNanoSec

Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




uint32_t betweenTransferDelayInNanoSec

After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (PCS). 




lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low 




lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers. 




lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated). 




bool enableInputDelay

Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length. 







struct _lpspi_slave_config


#include <fsl_lpspi.h>
LPSPI slave configuration structure. 

Public Members


uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096. 




lpspi_clock_polarity_t cpol

Clock polarity. 




lpspi_clock_phase_t cpha

Clock phase. 




lpspi_shift_direction_t direction

MSB or LSB data shift direction. 




lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (pcs) 




lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low 




lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers. 




lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated). 







struct _lpspi_transfer


#include <fsl_lpspi.h>
LPSPI master/slave transfer structure. 

Public Members


const uint8_t *txData

Send buffer. 




uint8_t *rxData

Receive buffer. 




volatile size_t dataSize

Transfer bytes. 




uint32_t configFlags

Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave. 







struct _lpspi_master_handle


#include <fsl_lpspi.h>
LPSPI master transfer handle structure used for transactional API. 

Public Members


volatile bool isPcsContinuous

Is PCS continuous in transfer. 




volatile bool writeTcrInIsr

A flag that whether should write TCR in ISR. 




volatile bool isByteSwap

A flag that whether should byte swap. 




volatile bool isTxMask

A flag that whether TCR[TXMSK] is set. 




volatile uint16_t bytesPerFrame

Number of bytes in each frame 




volatile uint16_t frameSize

Backup of TCR[FRAMESZ] 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




uint32_t txBuffIfNull

Used if the txData is NULL. 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




lpspi_master_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 







struct _lpspi_slave_handle


#include <fsl_lpspi.h>
LPSPI slave transfer handle structure used for transactional API. 

Public Members


volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




volatile uint32_t errorCount

Error count for slave transfer. 




lpspi_slave_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 







LPSPI eDMA Driver#


FSL_LPSPI_EDMA_DRIVER_VERSION

LPSPI EDMA driver version. 




DMA_MAX_TRANSFER_COUNT

DMA max transfer size. 




typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t

Forward declaration of the _lpspi_master_edma_handle typedefs. 




typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t

Forward declaration of the _lpspi_slave_edma_handle typedefs. 




typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type. 

Param base:
LPSPI peripheral base address. 

Param handle:
Pointer to the handle for the LPSPI master. 

Param status:
Success or error code describing whether the transfer completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type. 

Param base:
LPSPI peripheral base address. 

Param handle:
Pointer to the handle for the LPSPI slave. 

Param status:
Success or error code describing whether the transfer completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI master eDMA handle. 
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

base – LPSPI peripheral base address. 
handle – LPSPI handle pointer to lpspi_master_edma_handle_t. 
callback – LPSPI callback. 
userData – callback function parameter. 
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t. 
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t. 







status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA. 
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)

LPSPI master config transfer parameter while using eDMA. 
This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master. 


Return values:

kStatus_Success – Execution successfully. 
kStatus_LPSPI_Busy – The LPSPI device is busy. 


Returns:
Indicates whether LPSPI master transfer was successful or not. 






status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA without configs. 
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure, config field is not uesed. 


Return values:

kStatus_Success – Execution successfully. 
kStatus_LPSPI_Busy – The LPSPI device is busy. 
kStatus_InvalidArgument – The transfer structure is invalid. 


Returns:
Indicates whether LPSPI master transfer was successful or not. 






void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)

LPSPI master aborts a transfer which is using eDMA. 
This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 







status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)

Gets the master eDMA transfer remaining bytes. 
This function gets the master eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the EDMA transaction. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI slave eDMA handle. 
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.
(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

base – LPSPI peripheral base address. 
handle – LPSPI handle pointer to lpspi_slave_edma_handle_t. 
callback – LPSPI callback. 
userData – callback function parameter. 
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t. 
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t. 







status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfers data using eDMA. 
This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)

LPSPI slave aborts a transfer which is using eDMA. 
This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 







status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)

Gets the slave eDMA transfer remaining bytes. 
This function gets the slave eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the eDMA transaction. 


Returns:
status of status_t. 






struct _lpspi_master_edma_handle


#include <fsl_lpspi_edma.h>
LPSPI master eDMA transfer handle structure used for transactional API. 

Public Members


volatile bool isPcsContinuous

Is PCS continuous in transfer. 




volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




volatile uint8_t bytesLastRead

Bytes for last read RDR. 




volatile bool isThereExtraRxBytes

Is there extra RX byte. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




edma_tcd_t *lastTimeTCD

Pointer to the lastTime TCD 




bool isMultiDMATransmit

Is there multi DMA transmit 




volatile uint8_t dmaTransmitTime

DMA Transfer times. 




uint32_t lastTimeDataBytes

DMA transmit last Time data Bytes 




uint32_t dataBytesEveryTime

Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT 




edma_transfer_config_t transferConfigRx

Config of DMA rx channel. 




edma_transfer_config_t transferConfigTx

Config of DMA tx channel. 




uint32_t txBuffIfNull

Used if there is not txData for DMA purpose. 




uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose. 




uint32_t transmitCommand

Used to write TCR for DMA purpose. 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




lpspi_master_edma_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 




edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff 




edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg buff 




edma_tcd_t lpspiSoftwareTCD[3]

SoftwareTCD, internal used 







struct _lpspi_slave_edma_handle


#include <fsl_lpspi_edma.h>
LPSPI slave eDMA transfer handle structure used for transactional API. 

Public Members


volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




volatile uint8_t bytesLastRead

Bytes for last read RDR. 




volatile bool isThereExtraRxBytes

Is there extra RX byte. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




uint32_t txBuffIfNull

Used if there is not txData for DMA purpose. 




uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose. 




volatile uint8_t state

LPSPI transfer state. 




uint32_t errorCount

Error count for slave transfer. 




lpspi_slave_edma_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 




edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff 




edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg 




edma_tcd_t lpspiSoftwareTCD[2]

SoftwareTCD, internal used 







LPTMR: Low-Power Timer#


void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)

Ungates the LPTMR clock and configures the peripheral for a basic operation. 

Note
This API should be called at the beginning of the application using the LPTMR driver.


Parameters:

base – LPTMR peripheral base address 
config – A pointer to the LPTMR configuration structure. 







void LPTMR_Deinit(LPTMR_Type *base)

Gates the LPTMR clock. 

Parameters:

base – LPTMR peripheral base address 







void LPTMR_GetDefaultConfig(lptmr_config_t *config)

Fills in the LPTMR configuration structure with default settings. 
The default values are as follows. 
config->timerMode = kLPTMR_TimerModeTimeCounter;
config->pinSelect = kLPTMR_PinSelectInput_0;
config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
config->enableFreeRunning = false;
config->bypassPrescaler = true;
config->prescalerClockSource = kLPTMR_PrescalerClock_1;
config->value = kLPTMR_Prescale_Glitch_0;


 

Parameters:

config – A pointer to the LPTMR configuration structure. 







static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)

Enables the selected LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t







static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)

Disables the selected LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address 
mask – The interrupts to disable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t. 







static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)

Gets the enabled LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lptmr_interrupt_enable_t






static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)

Gets the LPTMR status flags. 

Parameters:

base – LPTMR peripheral base address


Returns:
The status flags. This is the logical OR of members of the enumeration lptmr_status_flags_t






static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)

Clears the LPTMR status flags. 

Parameters:

base – LPTMR peripheral base address 
mask – The status flags to clear. This is a logical OR of members of the enumeration lptmr_status_flags_t. 







static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)

Sets the timer period in units of count. 
Timers counts from 0 until it equals the count value set here. The count value is written to the CMR register.

Note

The TCF flag is set with the CNR equals the count provided here and then increments.
Call the utility macros provided in the fsl_common.h to convert to ticks.




Parameters:

base – LPTMR peripheral base address 
ticks – A timer period in units of ticks 







static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)

Reads the current timer counting value. 
This function returns the real-time timer counting value in a range from 0 to a timer period.

Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.


Parameters:

base – LPTMR peripheral base address


Returns:
The current counter value in ticks 






static inline void LPTMR_StartTimer(LPTMR_Type *base)

Starts the timer. 
After calling this function, the timer counts up to the CMR register value. Each time the timer reaches the CMR value and then increments, it generates a trigger pulse and sets the timeout interrupt flag. An interrupt is also triggered if the timer interrupt is enabled.

Parameters:

base – LPTMR peripheral base address 







static inline void LPTMR_StopTimer(LPTMR_Type *base)

Stops the timer. 
This function stops the timer and resets the timer’s counter register.

Parameters:

base – LPTMR peripheral base address 







FSL_LPTMR_DRIVER_VERSION

Driver Version 




enum _lptmr_pin_select

LPTMR pin selection used in pulse counter mode. 
Values:


enumerator kLPTMR_PinSelectInput_0

Pulse counter input 0 is selected 




enumerator kLPTMR_PinSelectInput_1

Pulse counter input 1 is selected 




enumerator kLPTMR_PinSelectInput_2

Pulse counter input 2 is selected 




enumerator kLPTMR_PinSelectInput_3

Pulse counter input 3 is selected 






enum _lptmr_pin_polarity

LPTMR pin polarity used in pulse counter mode. 
Values:


enumerator kLPTMR_PinPolarityActiveHigh

Pulse Counter input source is active-high 




enumerator kLPTMR_PinPolarityActiveLow

Pulse Counter input source is active-low 






enum _lptmr_timer_mode

LPTMR timer mode selection. 
Values:


enumerator kLPTMR_TimerModeTimeCounter

Time Counter mode 




enumerator kLPTMR_TimerModePulseCounter

Pulse Counter mode 






enum _lptmr_prescaler_glitch_value

LPTMR prescaler/glitch filter values. 
Values:


enumerator kLPTMR_Prescale_Glitch_0

Prescaler divide 2, glitch filter does not support this setting 




enumerator kLPTMR_Prescale_Glitch_1

Prescaler divide 4, glitch filter 2 




enumerator kLPTMR_Prescale_Glitch_2

Prescaler divide 8, glitch filter 4 




enumerator kLPTMR_Prescale_Glitch_3

Prescaler divide 16, glitch filter 8 




enumerator kLPTMR_Prescale_Glitch_4

Prescaler divide 32, glitch filter 16 




enumerator kLPTMR_Prescale_Glitch_5

Prescaler divide 64, glitch filter 32 




enumerator kLPTMR_Prescale_Glitch_6

Prescaler divide 128, glitch filter 64 




enumerator kLPTMR_Prescale_Glitch_7

Prescaler divide 256, glitch filter 128 




enumerator kLPTMR_Prescale_Glitch_8

Prescaler divide 512, glitch filter 256 




enumerator kLPTMR_Prescale_Glitch_9

Prescaler divide 1024, glitch filter 512 




enumerator kLPTMR_Prescale_Glitch_10

Prescaler divide 2048 glitch filter 1024 




enumerator kLPTMR_Prescale_Glitch_11

Prescaler divide 4096, glitch filter 2048 




enumerator kLPTMR_Prescale_Glitch_12

Prescaler divide 8192, glitch filter 4096 




enumerator kLPTMR_Prescale_Glitch_13

Prescaler divide 16384, glitch filter 8192 




enumerator kLPTMR_Prescale_Glitch_14

Prescaler divide 32768, glitch filter 16384 




enumerator kLPTMR_Prescale_Glitch_15

Prescaler divide 65536, glitch filter 32768 






enum _lptmr_prescaler_clock_select

LPTMR prescaler/glitch filter clock select. 

Note
Clock connections are SoC-specific 

Values:




enum _lptmr_interrupt_enable

List of the LPTMR interrupts. 
Values:


enumerator kLPTMR_TimerInterruptEnable

Timer interrupt enable 






enum _lptmr_status_flags

List of the LPTMR status flags. 
Values:


enumerator kLPTMR_TimerCompareFlag

Timer compare flag 






typedef enum _lptmr_pin_select lptmr_pin_select_t

LPTMR pin selection used in pulse counter mode. 




typedef enum _lptmr_pin_polarity lptmr_pin_polarity_t

LPTMR pin polarity used in pulse counter mode. 




typedef enum _lptmr_timer_mode lptmr_timer_mode_t

LPTMR timer mode selection. 




typedef enum _lptmr_prescaler_glitch_value lptmr_prescaler_glitch_value_t

LPTMR prescaler/glitch filter values. 




typedef enum _lptmr_prescaler_clock_select lptmr_prescaler_clock_select_t

LPTMR prescaler/glitch filter clock select. 

Note
Clock connections are SoC-specific 





typedef enum _lptmr_interrupt_enable lptmr_interrupt_enable_t

List of the LPTMR interrupts. 




typedef enum _lptmr_status_flags lptmr_status_flags_t

List of the LPTMR status flags. 




typedef struct _lptmr_config lptmr_config_t

LPTMR config structure. 
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash. 




static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)

Enable or disable timer DMA request. 
Toggles CSR[TDRE] on the LPTMR side only: when enabled, every compare event (CSR[TCF]=1) raises an LPTMR DMA request line which is auto-cleared after the DMA controller services it.

Note
LPTMR runs on a low-power clock that is asynchronous to the EDMA bus clock. On some EDMA IP variants the channel has TWO gates that must BOTH be opened for an LPTMR request to be accepted: the base hardware request gate (ERQ, opened by EDMA_EnableChannelRequest()) and an extra asynchronous-request gate (opened by EDMA_EnableAsyncRequest() on EDMA4; the classic EDMA + DMAMUX combination does not need this).


Parameters:

base – base LPTMR peripheral base address 
enable – Switcher of timer DMA feature. “true” means to enable, “false” means to disable. 







struct _lptmr_config


#include <fsl_lptmr.h>
LPTMR config structure. 
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash. 

Public Members


lptmr_timer_mode_t timerMode

Time counter mode or pulse counter mode 




lptmr_pin_select_t pinSelect

LPTMR pulse input pin select; used only in pulse counter mode 




lptmr_pin_polarity_t pinPolarity

LPTMR pulse input pin polarity; used only in pulse counter mode 




bool enableFreeRunning

True: enable free running, counter is reset on overflow False: counter is reset when the compare flag is set 




bool bypassPrescaler

True: bypass prescaler; false: use clock from prescaler 




lptmr_prescaler_clock_select_t prescalerClockSource

LPTMR clock source 




lptmr_prescaler_glitch_value_t value

Prescaler or glitch filter value 







LPUART:  Low Power Universal Asynchronous Receiver/Transmitter Driver#


LPUART Driver#


static inline void LPUART_SoftwareReset(LPUART_Type *base)

Resets the LPUART using software. 
This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

base – LPUART peripheral base address. 







status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)

Initializes an LPUART instance with the user configuration structure and the peripheral clock. 
This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART. 
lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);




Parameters:

base – LPUART peripheral base address. 
config – Pointer to a user-defined configuration structure. 
srcClock_Hz – LPUART clock source frequency in HZ. 


Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source. 
kStatus_Success – LPUART initialize succeed 







status_t LPUART_Deinit(LPUART_Type *base)

Deinitializes a LPUART instance. 
This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

base – LPUART peripheral base address. 


Return values:

kStatus_Success – Deinit is success. 
kStatus_LPUART_Timeout – Timeout during deinit. 







void LPUART_GetDefaultConfig(lpuart_config_t *config)

Gets the default configuration structure. 
This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

config – Pointer to a configuration structure. 







status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the LPUART instance baudrate. 
This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. 
LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);




Parameters:

base – LPUART peripheral base address. 
baudRate_Bps – LPUART baudrate to be set. 
srcClock_Hz – LPUART clock source frequency in HZ. 


Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source. 
kStatus_Success – Set baudrate succeeded. 







void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)

Enable 9-bit data mode for LPUART. 
This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

base – LPUART peripheral base address. 
enable – true to enable, flase to disable. 







static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)

Set the LPUART address. 
This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note
Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.


Parameters:

base – LPUART peripheral base address. 
address1 – LPUART slave address1. 
address2 – LPUART slave address2. 







static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)

Enable the LPUART match address feature. 

Parameters:

base – LPUART peripheral base address. 
match1 – true to enable match address1, false to disable. 
match2 – true to enable match address2, false to disable. 







static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the rx FIFO watermark. 

Parameters:

base – LPUART peripheral base address. 
water – Rx FIFO watermark. 







static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the tx FIFO watermark. 

Parameters:

base – LPUART peripheral base address. 
water – Tx FIFO watermark. 







static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. 
This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

handle – LPUART handle pointer. 
enable – true to enable, false to disable. 







uint32_t LPUART_GetStatusFlags(LPUART_Type *base)

Gets LPUART status flags. 
This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty: 
if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}




Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART status flags which are ORed by the enumerators in the _lpuart_flags. 






status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)

Clears status flags with a provided mask. 
This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

base – LPUART peripheral base address. 
mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask. 


Return values:

kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware. 
kStatus_Success – Status in the mask are cleared. 


Returns:
0 succeed, others failed. 






void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)

Enables LPUART interrupts according to a provided mask. 
This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt: 
LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);




Parameters:

base – LPUART peripheral base address. 
mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable. 







void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)

Disables LPUART interrupts according to a provided mask. 
This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt: 
LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);




Parameters:

base – LPUART peripheral base address. 
mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable. 







uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)

Gets enabled LPUART interrupts. 
This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled: 
uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}




Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable. 






static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)

Gets the LPUART data register address. 
This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART data register addresses which are used both by the transmitter and receiver. 






static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter DMA request. 
This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver DMA. 
This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







uint32_t LPUART_GetInstance(LPUART_Type *base)

Get the LPUART instance from peripheral base address. 

Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART instance. 






static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter. 
This function enables or disables the LPUART transmitter.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver. 
This function enables or disables the LPUART receiver.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)

Writes to the transmitter register. 
This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

base – LPUART peripheral base address. 
data – Data write to the TX register. 







static inline uint8_t LPUART_ReadByte(LPUART_Type *base)

Reads the receiver register. 
This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

base – LPUART peripheral base address. 


Returns:
Data read from data register. 






static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)

Gets the rx FIFO data count. 

Parameters:

base – LPUART peripheral base address. 


Returns:
rx FIFO data count. 






static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)

Gets the tx FIFO data count. 

Parameters:

base – LPUART peripheral base address. 


Returns:
tx FIFO data count. 






void LPUART_SendAddress(LPUART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode. 

Parameters:

base – LPUART peripheral base address. 
address – LPUART slave address. 







status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)

Writes to the transmitter register using a blocking method. 
This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

base – LPUART peripheral base address. 
data – Start address of the data to write. 
length – Size of the data to write. 


Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully wrote all data. 







status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)

Writes to the transmitter register using a blocking method in 9bit or 10bit mode. 

Note
This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.


Parameters:

base – LPUART peripheral base address. 
data – Start address of the data to write. 
length – Size of the data to write. 


Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully wrote all data. 







status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)

Reads the receiver data register using a blocking method. 
This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

base – LPUART peripheral base address. 
data – Start address of the buffer to store the received data. 
length – Size of the buffer. 


Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data. 
kStatus_LPUART_NoiseError – Noise error happened while receiving data. 
kStatus_LPUART_FramingError – Framing error happened while receiving data. 
kStatus_LPUART_ParityError – Parity error happened while receiving data. 
kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully received all data. 







status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)

Reads the receiver data register in 9bit or 10bit mode. 

Note
This function only support 9bit or 10bit transfer.


Parameters:

base – LPUART peripheral base address. 
data – Start address of the buffer to store the received data by 16bit, only 10bit is valid. 
length – Size of the buffer. 


Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data. 
kStatus_LPUART_NoiseError – Noise error happened while receiving data. 
kStatus_LPUART_FramingError – Framing error happened while receiving data. 
kStatus_LPUART_ParityError – Parity error happened while receiving data. 
kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully received all data. 







void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)

Initializes the LPUART handle. 
This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.
The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
callback – Callback function. 
userData – User data. 







status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method. 
This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note
The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.


Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART transfer structure, see lpuart_transfer_t. 


Return values:

kStatus_Success – Successfully start the data transmission. 
kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer. 
This function sets up the RX ring buffer to a specific UART handle.
When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note
When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.


Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. 
ringBufferSize – size of the ring buffer. 







void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer. 
This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)

Get the length of received data in RX ring buffer. 

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 


Returns:
Length of received data in RX ring buffer. 






void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data transmit. 
This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been sent out to bus. 
This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Send bytes count. 


Return values:

kStatus_NoTransferInProgress – No send in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method. 
This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART transfer structure, see uart_transfer_t. 
receivedBytes – Bytes received from the ring buffer directly. 


Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue. 
kStatus_LPUART_RxBusy – Previous receive request is not finished. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data receiving. 
This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received. 
This function gets the number of bytes that have been received.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Receive bytes count. 


Return values:

kStatus_NoTransferInProgress – No receive in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)

LPUART IRQ handle function. 
This function handles the LPUART transmit and receive IRQ request.

Parameters:

base – LPUART peripheral base address. 
irqHandle – LPUART handle pointer. 







void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)

LPUART Error IRQ handle function. 
This function handles the LPUART error IRQ request.

Parameters:

base – LPUART peripheral base address. 
irqHandle – LPUART handle pointer. 







void LPUART_DriverIRQHandler(uint32_t instance)

LPUART driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPUART.

Parameters:

instance – LPUART instance. 







FSL_LPUART_DRIVER_VERSION

LPUART driver version. 





Error codes for the LPUART driver. 
Values:


enumerator kStatus_LPUART_TxBusy

TX busy 




enumerator kStatus_LPUART_RxBusy

RX busy 




enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle. 




enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle. 




enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large 




enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large 




enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear 




enumerator kStatus_LPUART_Error

Error happens on LPUART. 




enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun. 




enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun. 




enumerator kStatus_LPUART_NoiseError

LPUART noise error. 




enumerator kStatus_LPUART_FramingError

LPUART framing error. 




enumerator kStatus_LPUART_ParityError

LPUART parity error. 




enumerator kStatus_LPUART_BaudrateNotSupport

Baudrate is not support in current clock source 




enumerator kStatus_LPUART_IdleLineDetected

IDLE flag. 




enumerator kStatus_LPUART_Timeout

LPUART times out. 






enum _lpuart_parity_mode

LPUART parity mode. 
Values:


enumerator kLPUART_ParityDisabled

Parity disabled 




enumerator kLPUART_ParityEven

Parity enabled, type even, bit setting: PE|PT = 10 




enumerator kLPUART_ParityOdd

Parity enabled, type odd, bit setting: PE|PT = 11 






enum _lpuart_data_bits

LPUART data bits count. 
Values:


enumerator kLPUART_EightDataBits

Eight data bit 




enumerator kLPUART_SevenDataBits

Seven data bit 






enum _lpuart_stop_bit_count

LPUART stop bit count. 
Values:


enumerator kLPUART_OneStopBit

One stop bit 




enumerator kLPUART_TwoStopBit

Two stop bits 






enum _lpuart_transmit_cts_source

LPUART transmit CTS source. 
Values:


enumerator kLPUART_CtsSourcePin

CTS resource is the LPUART_CTS pin. 




enumerator kLPUART_CtsSourceMatchResult

CTS resource is the match result. 






enum _lpuart_transmit_cts_config

LPUART transmit CTS configure. 
Values:


enumerator kLPUART_CtsSampleAtStart

CTS input is sampled at the start of each character. 




enumerator kLPUART_CtsSampleAtIdle

CTS input is sampled when the transmitter is idle 






enum _lpuart_transmit_rts_polarity

LPUART transmitter RTS polarity. 
Values:


enumerator kLPUART_RtsPolarityLow

Transmitter RTS is active low. 




enumerator kLPUART_RtsPolarityHigh

Transmitter RTS is active high. 






enum _lpuart_idle_type_select

LPUART idle flag type defines when the receiver starts counting. 
Values:


enumerator kLPUART_IdleTypeStartBit

Start counting after a valid start bit. 




enumerator kLPUART_IdleTypeStopBit

Start counting after a stop bit. 






enum _lpuart_idle_config

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set. 
Values:


enumerator kLPUART_IdleCharacter1

the number of idle characters. 




enumerator kLPUART_IdleCharacter2

the number of idle characters. 




enumerator kLPUART_IdleCharacter4

the number of idle characters. 




enumerator kLPUART_IdleCharacter8

the number of idle characters. 




enumerator kLPUART_IdleCharacter16

the number of idle characters. 




enumerator kLPUART_IdleCharacter32

the number of idle characters. 




enumerator kLPUART_IdleCharacter64

the number of idle characters. 




enumerator kLPUART_IdleCharacter128

the number of idle characters. 






enum _lpuart_interrupt_enable

LPUART interrupt configuration structure, default settings all disabled. 
This structure contains the settings for all LPUART interrupt configurations. 
Values:


enumerator kLPUART_LinBreakInterruptEnable

LIN break detect. bit 7 




enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge. bit 6 




enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty. bit 23 




enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete. bit 22 




enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full. bit 21 




enumerator kLPUART_IdleLineInterruptEnable

Idle line. bit 20 




enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun. bit 27 




enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag. bit 26 




enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag. bit 25 




enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag. bit 24 




enumerator kLPUART_Match1InterruptEnable

Parity error flag. bit 15 




enumerator kLPUART_Match2InterruptEnable

Parity error flag. bit 14 




enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow. bit 9 




enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow. bit 8 




enumerator kLPUART_AllInterruptEnable







enum _lpuart_flags

LPUART status flags. 
This provides constants for the LPUART status flags for use in the LPUART functions. 
Values:


enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty. bit 23 




enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete. bit 22 




enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full. bit 21 




enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected. bit 20 




enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register. bit 19 




enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18 




enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 




enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection. bit 16 




enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31 




enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected. bit 30 




enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 




enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1. bit 15 




enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2. bit 14 




enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty. bit 7 




enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty. bit 6 




enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred. bit 1 




enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred. bit 0 




enumerator kLPUART_AllClearFlags





enumerator kLPUART_AllFlags







typedef enum _lpuart_parity_mode lpuart_parity_mode_t

LPUART parity mode. 




typedef enum _lpuart_data_bits lpuart_data_bits_t

LPUART data bits count. 




typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t

LPUART stop bit count. 




typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t

LPUART transmit CTS source. 




typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t

LPUART transmit CTS configure. 




typedef enum _lpuart_transmit_rts_polarity lpuart_transmit_rts_polarity_t

LPUART transmitter RTS polarity. 




typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t

LPUART idle flag type defines when the receiver starts counting. 




typedef enum _lpuart_idle_config lpuart_idle_config_t

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set. 




typedef struct _lpuart_config lpuart_config_t

LPUART configuration structure. 




typedef struct _lpuart_transfer lpuart_transfer_t

LPUART transfer structure. 




typedef struct _lpuart_handle lpuart_handle_t





typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function. 




typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)





void *s_lpuartHandle[]





const IRQn_Type s_lpuartTxIRQ[]





lpuart_isr_t s_lpuartIsr[]





UART_RETRY_TIMES

Retry times for waiting flag. 




struct _lpuart_config


#include <fsl_lpuart.h>
LPUART configuration structure. 

Public Members


uint32_t baudRate_Bps

LPUART baud rate 




lpuart_parity_mode_t parityMode

Parity mode, disabled (default), even, odd 




lpuart_data_bits_t dataBitsCount

Data bits count, eight (default), seven 




bool isMsb

Data bits order, LSB (default), MSB 




lpuart_stop_bit_count_t stopBitCount

Number of stop bits, 1 stop bit (default) or 2 stop bits 




uint8_t txFifoWatermark

TX FIFO watermark 




uint8_t rxFifoWatermark

RX FIFO watermark 




bool enableRxRTS

RX RTS enable 




bool enableTxRTS

TX RTS enable 




bool enableTxCTS

TX CTS enable 




lpuart_transmit_cts_source_t txCtsSource

TX CTS source 




lpuart_transmit_cts_config_t txCtsConfig

TX CTS configure 




lpuart_transmit_rts_polarity_t txRtsPolarity

TX RTS polarity 




uint8_t rtsWatermark

RTS watermark 




lpuart_idle_type_select_t rxIdleType

RX IDLE type. 




lpuart_idle_config_t rxIdleConfig

RX IDLE configuration. 




bool enableTx

Enable TX 




bool enableRx

Enable RX 




bool swapTxdRxd

Swap TXD and RXD pins 




bool inverseTxd

Transmit Data Inversion - Setting true reverses the polarity of the transmitted data output 







struct _lpuart_transfer


#include <fsl_lpuart.h>
LPUART transfer structure. 

Public Members


size_t dataSize

The byte count to be transfer. 







struct _lpuart_handle


#include <fsl_lpuart.h>
LPUART handle structure. 

Public Members


volatile size_t txDataSize

Size of the remaining data to send. 




size_t txDataSizeAll

Size of the data to send out. 




volatile size_t rxDataSize

Size of the remaining data to receive. 




size_t rxDataSizeAll

Size of the data to receive. 




size_t rxRingBufferSize

Size of the ring buffer. 




volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer. 




volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer. 




lpuart_transfer_callback_t callback

Callback function. 




void *userData

LPUART callback function parameter. 




volatile uint8_t txState

TX transfer state. 




volatile uint8_t rxState

RX transfer state. 




bool isSevenDataBits

Seven data bits flag. 




bool is16bitData

16bit data bits flag, only used for 9bit or 10bit data 







union __unnamed68__


Public Members


uint8_t *data

The buffer of data to be transfer. 




uint8_t *rxData

The buffer to receive data. 




uint16_t *rxData16

The buffer to receive data. 




const uint8_t *txData

The buffer of data to be sent. 




const uint16_t *txData16

The buffer of data to be sent. 







union __unnamed70__


Public Members


const uint8_t *volatile txData

Address of remaining data to send. 




const uint16_t *volatile txData16

Address of remaining data to send. 







union __unnamed72__


Public Members


uint8_t *volatile rxData

Address of remaining data to receive. 




uint16_t *volatile rxData16

Address of remaining data to receive. 







union __unnamed74__


Public Members


uint8_t *rxRingBuffer

Start address of the receiver ring buffer. 




uint16_t *rxRingBuffer16

Start address of the receiver ring buffer. 







LPUART eDMA Driver#


void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the LPUART handle which is used in transactional functions. 

Note
This function disables all LPUART interrupts.


Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 
callback – Callback function. 
userData – User data. 
txEdmaHandle – User requested DMA handle for TX DMA transfer. 
rxEdmaHandle – User requested DMA handle for RX DMA transfer. 







status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Sends data using eDMA. 
This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART eDMA transfer structure. See lpuart_transfer_t. 


Return values:

kStatus_Success – if succeed, others failed. 
kStatus_LPUART_TxBusy – Previous transfer on going. 
kStatus_InvalidArgument – Invalid argument. 







status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Receives data using eDMA. 
This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 
xfer – LPUART eDMA transfer structure, see lpuart_transfer_t. 


Return values:

kStatus_Success – if succeed, others fail. 
kStatus_LPUART_RxBusy – Previous transfer ongoing. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the sent data using eDMA. 
This function aborts the sent data using eDMA.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 







void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the received data using eDMA. 
This function aborts the received data using eDMA.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 







status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the LPUART TX register. 
This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Send bytes count. 


Return values:

kStatus_NoTransferInProgress – No send in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of received bytes. 
This function gets the number of received bytes.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Receive bytes count. 


Return values:

kStatus_NoTransferInProgress – No receive in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)

LPUART eDMA IRQ handle function. 
This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application. 

Note
This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.


Parameters:

base – LPUART peripheral base address. 
lpuartEdmaHandle – LPUART handle pointer. 







FSL_LPUART_EDMA_DRIVER_VERSION

LPUART EDMA driver version. 




typedef struct _lpuart_edma_handle lpuart_edma_handle_t





typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function. 




struct _lpuart_edma_handle


#include <fsl_lpuart_edma.h>
LPUART eDMA handle. 

Public Members


lpuart_edma_transfer_callback_t callback

Callback function. 




void *userData

LPUART callback function parameter. 




size_t rxDataSizeAll

Size of the data to receive. 




size_t txDataSizeAll

Size of the data to send out. 




edma_handle_t *txEdmaHandle

The eDMA TX channel used. 




edma_handle_t *rxEdmaHandle

The eDMA RX channel used. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




volatile uint8_t txState

TX transfer state. 




volatile uint8_t rxState

RX transfer state 







MCM: Miscellaneous Control Module#


FSL_MCM_DRIVER_VERSION

MCM driver version. 





Enum _mcm_interrupt_flag. Interrupt status flag mask. . 
Values:


enumerator kMCM_CacheWriteBuffer

Cache Write Buffer Error Enable. 




enumerator kMCM_ParityError

Cache Parity Error Enable. 




enumerator kMCM_FPUInvalidOperation

FPU Invalid Operation Interrupt Enable. 




enumerator kMCM_FPUDivideByZero

FPU Divide-by-zero Interrupt Enable. 




enumerator kMCM_FPUOverflow

FPU Overflow Interrupt Enable. 




enumerator kMCM_FPUUnderflow

FPU Underflow Interrupt Enable. 




enumerator kMCM_FPUInexact

FPU Inexact Interrupt Enable. 




enumerator kMCM_FPUInputDenormalInterrupt

FPU Input Denormal Interrupt Enable. 






typedef union _mcm_buffer_fault_attribute mcm_buffer_fault_attribute_t

The union of buffer fault attribute. 




typedef union _mcm_lmem_fault_attribute mcm_lmem_fault_attribute_t

The union of LMEM fault attribute. 




static inline void MCM_EnableCrossbarRoundRobin(MCM_Type *base, bool enable)

Enables/Disables crossbar round robin. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable crossbar round robin.

true Enable crossbar round robin.
false disable crossbar round robin. 









static inline void MCM_EnableInterruptStatus(MCM_Type *base, uint32_t mask)

Enables the interrupt. 

Parameters:

base – MCM peripheral base address. 
mask – Interrupt status flags mask(_mcm_interrupt_flag). 







static inline void MCM_DisableInterruptStatus(MCM_Type *base, uint32_t mask)

Disables the interrupt. 

Parameters:

base – MCM peripheral base address. 
mask – Interrupt status flags mask(_mcm_interrupt_flag). 







static inline uint16_t MCM_GetInterruptStatus(MCM_Type *base)

Gets the Interrupt status . 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_ClearCacheWriteBufferErroStatus(MCM_Type *base)

Clears the Interrupt status . 

Parameters:

base – MCM peripheral base address. 







static inline uint32_t MCM_GetBufferFaultAddress(MCM_Type *base)

Gets buffer fault address. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_GetBufferFaultAttribute(MCM_Type *base, mcm_buffer_fault_attribute_t *bufferfault)

Gets buffer fault attributes. 

Parameters:

base – MCM peripheral base address. 
bufferfault – Structure to store the result. 







static inline uint32_t MCM_GetBufferFaultData(MCM_Type *base)

Gets buffer fault data. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type *base, bool enable)

Limit code cache peripheral write buffering. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable limit code cache peripheral write buffering.

true Enable limit code cache peripheral write buffering.
false disable limit code cache peripheral write buffering. 









static inline void MCM_BypassFixedCodeCacheMap(MCM_Type *base, bool enable)

Bypass fixed code cache map. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable bypass fixed code cache map.

true Enable bypass fixed code cache map.
false disable bypass fixed code cache map. 









static inline void MCM_EnableCodeBusCache(MCM_Type *base, bool enable)

Enables/Disables code bus cache. 

Parameters:

base – MCM peripheral base address. 
enable – Used to disable/enable code bus cache.

true Enable code bus cache.
false disable code bus cache. 









static inline void MCM_ForceCodeCacheToNoAllocation(MCM_Type *base, bool enable)

Force code cache to no allocation. 

Parameters:

base – MCM peripheral base address. 
enable – Used to force code cache to allocation or no allocation.

true Force code cache to no allocation.
false Force code cache to allocation. 









static inline void MCM_EnableCodeCacheWriteBuffer(MCM_Type *base, bool enable)

Enables/Disables code cache write buffer. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable code cache write buffer.

true Enable code cache write buffer.
false Disable code cache write buffer. 









static inline void MCM_ClearCodeBusCache(MCM_Type *base)

Clear code bus cache. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_EnablePcParityFaultReport(MCM_Type *base, bool enable)

Enables/Disables PC Parity Fault Report. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable PC Parity Fault Report.

true Enable PC Parity Fault Report.
false disable PC Parity Fault Report. 









static inline void MCM_EnablePcParity(MCM_Type *base, bool enable)

Enables/Disables PC Parity. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable PC Parity.

true Enable PC Parity.
false disable PC Parity. 









static inline void MCM_LockConfigState(MCM_Type *base)

Lock the configuration state. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_EnableCacheParityReporting(MCM_Type *base, bool enable)

Enables/Disables cache parity reporting. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable cache parity reporting.

true Enable cache parity reporting.
false disable cache parity reporting. 









static inline uint32_t MCM_GetLmemFaultAddress(MCM_Type *base)

Gets LMEM fault address. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_GetLmemFaultAttribute(MCM_Type *base, mcm_lmem_fault_attribute_t *lmemFault)

Get LMEM fault attributes. 

Parameters:

base – MCM peripheral base address. 
lmemFault – Structure to store the result. 







static inline uint64_t MCM_GetLmemFaultData(MCM_Type *base)

Gets LMEM fault data. 

Parameters:

base – MCM peripheral base address. 







MCM_LMFATR_TYPE_MASK





MCM_LMFATR_MODE_MASK





MCM_LMFATR_BUFF_MASK





MCM_LMFATR_CACH_MASK





MCM_ISCR_STAT_MASK





FSL_COMPONENT_ID





union _mcm_buffer_fault_attribute


#include <fsl_mcm.h>
The union of buffer fault attribute. 

Public Members


uint32_t attribute

Indicates the faulting attributes, when a properly-enabled cache write buffer error interrupt event is detected. 




struct _mcm_buffer_fault_attribute._mcm_buffer_fault_attribut attribute_memory






struct _mcm_buffer_fault_attribut


Public Members


uint32_t busErrorDataAccessType

Indicates the type of cache write buffer access. 




uint32_t busErrorPrivilegeLevel

Indicates the privilege level of the cache write buffer access. 




uint32_t busErrorSize

Indicates the size of the cache write buffer access. 




uint32_t busErrorAccess

Indicates the type of system bus access. 




uint32_t busErrorMasterID

Indicates the crossbar switch bus master number of the captured cache write buffer bus error. 




uint32_t busErrorOverrun

Indicates if another cache write buffer bus error is detected. 









union _mcm_lmem_fault_attribute


#include <fsl_mcm.h>
The union of LMEM fault attribute. 

Public Members


uint32_t attribute

Indicates the attributes of the LMEM fault detected. 




struct _mcm_lmem_fault_attribute._mcm_lmem_fault_attribut attribute_memory






struct _mcm_lmem_fault_attribut


Public Members


uint32_t parityFaultProtectionSignal

Indicates the features of parity fault protection signal. 




uint32_t parityFaultMasterSize

Indicates the parity fault master size. 




uint32_t parityFaultWrite

Indicates the parity fault is caused by read or write. 




uint32_t backdoorAccess

Indicates the LMEM access fault is initiated by core access or backdoor access. 




uint32_t parityFaultSyndrome

Indicates the parity fault syndrome. 




uint32_t overrun

Indicates the number of faultss. 









MSGINTR: Message Unit#


MSGINTR Driver#


MU: Messaging Unit#


void MU_Init(MU_Type *base)

Initializes the MU module. 
This function enables the MU clock only.

Parameters:

base – MU peripheral base address. 







void MU_Deinit(MU_Type *base)

De-initializes the MU module. 
This function disables the MU clock only.

Parameters:

base – MU peripheral base address. 







static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register. 
This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.
while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.



Parameters:

base – MU peripheral base address. 
regIndex – TX register index, see mu_msg_reg_index_t. 
msg – Message to send. 







status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message. 
This function waits until the TX register is empty and sends the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and returns kStatus_Timeout.

Parameters:

base – MU peripheral base address. 
regIndex – MU message register, see mu_msg_reg_index_t. 
msg – Message to send.


Return values:

kStatus_Success – Message sent successfully. 
kStatus_Timeout – Timeout occurred while waiting for TX register to be empty. 


Returns:
status_t 






static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register. 
This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.
uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.



Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 


Returns:
The received message. 






status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue)

Blocks to receive a message with timeout protection. 
This function waits until the RX register is full and receives the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.
This function provides the same blocking behavior as MU_ReceiveMsg() but with additional timeout protection to prevent system hangs if the other core becomes unresponsive or if hardware issues occur.

Note
Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that this function includes timeout protection while MU_ReceiveMsg() waits indefinitely.


Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 
readValue – Pointer to store the received message.


Return values:

kStatus_Success – Message received successfully. 
kStatus_InvalidArgument – Invalid readValue pointer. 
kStatus_Timeout – Timeout occurred while waiting for RX register to be full. 


Returns:
status_t 






uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message (infinite wait, no timeout protection). 
This function waits until the RX register is full and receives the message. This function will wait indefinitely until a message is received.

Note
Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that MU_ReceiveMsgTimeout() includes timeout protection while this function waits indefinitely.


Warning
This function does not include timeout protection and may cause system hangs if the other core becomes unresponsive. For applications requiring timeout protection, use MU_ReceiveMsgTimeout() instead.


Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 


Returns:
The received message. 






static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side. 
This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.
while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.



Parameters:

base – MU peripheral base address. 
flags – The 3-bit MU flags to set. 







status_t MU_SetFlags(MU_Type *base, uint32_t flags)

brief Blocks setting the 3-bit MU flags reflect on the other MU side.
This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

return status_t retval kStatus_Success Flags were set successfully. retval kStatus_Timeout Timeout occurred while waiting for flags to update. 

Parameters:

base – MU peripheral base address. 
flags – The 3-bit MU flags to set.







static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side. 
This function gets the current 3-bit MU flags on the current side.

Parameters:

base – MU peripheral base address. 


Returns:
flags Current value of the 3-bit flags. 






uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags. 
This function returns the bit mask of the MU status flags. See _mu_status_flags.
uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}


If there are more than 4 general purpose interrupts, use MU_GetGeneralPurposeStatusFlags.

Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU status flags, see _mu_status_flags. 






static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts. 
This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU IRQs pending. 






static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)

Clears the specific MU status flags. 
This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.
Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);


If there are more than 4 general purpose interrupts, use MU_ClearGeneralPurposeStatusFlags.

Parameters:

base – MU peripheral base address. 
flags – Bit mask of the MU status flags. See _mu_status_flags. Only the following flags can be cleared by software (if applicable for particular device), other flags are cleared by hardware:

kMU_GenInt0Flag
kMU_GenInt1Flag
kMU_GenInt2Flag
kMU_GenInt3Flag
kMU_MuResetInterruptFlag
kMU_OtherSideEnterRunInterruptFlag
kMU_OtherSideEnterHaltInterruptFlag
kMU_OtherSideEnterWaitInterruptFlag
kMU_OtherSideEnterStopInterruptFlag
kMU_OtherSideEnterPowerDownInterruptFlag
kMU_ResetAssertInterruptFlag
kMU_HardwareResetInterruptFlag 









static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)

Enables the specific MU interrupts. 
This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.
   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);


If there are more than 4 general purpose interrupts, use MU_EnableGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable. 







static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)

Disables the specific MU interrupts. 
This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.
   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);


If there are more than 4 general purpose interrupts, use MU_DisableGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable. 







status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts)

Triggers interrupts to the other core. 
This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}


If there are more than 4 general purpose interrupts, use MU_TriggerGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. 


Return values:

kStatus_Success – Interrupts have been triggered successfully. 
kStatus_Fail – Previous interrupts have not been accepted. 







static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Enables the MU general purpose interrupts. 
This function enables the MU general purpose interrupts. The interrupts to enable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_EnableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to enable general purpose interrupt 0 and 3, use like this: 
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);




Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU general purpose interrupts, see mu_general_purpose_interrupt_t. 







static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Disables the MU general purpose interrupts. 
This function disables the MU general purpose interrupts. The interrupts to disable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_DisableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to disable general purpose interrupt 0 and 3, use like this: 
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);




Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU general purpose interrupts. see mu_general_purpose_interrupt_t. 







static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)

Gets the MU general purpose interrupt status flags. 
This function returns the bit mask of the MU general purpose interrupt status flags. MU_GetStatusFlags can only get general purpose interrupt status 0~3, this function can get all general purpose interrupts status.
This example shows to check whether general purpose interrupt 0 and 3 happened.
uint32_t flags;
flags = MU_GetGeneralPurposeStatusFlags(base);
if (kMU_GeneralPurposeInterrupt0 & flags)
{
}
if (kMU_GeneralPurposeInterrupt3 & flags)
{
}



Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU general purpose interrupt status flags. 






static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)

Clear the MU general purpose interrupt status flags. 
This function clears the specific MU general purpose interrupt status flags. The flags to clear should be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.
Example to clear general purpose interrupt 0 and general interrupt 1 pending flags. 
MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);




Parameters:

base – MU peripheral base address. 
flags – Bit mask of the MU general purpose interrupt status flags. See mu_general_purpose_interrupt_t. 







static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags in reverse numerical order. 
This function return the RX status flags in reverse order. Note: RFn bits of SR[3-0](mu status register) are mapped in ascending numerical order: RF0 -> SR[0] RF1 -> SR[1] RF2 -> SR[2] RF3 -> SR[3] This function will return these bits in reverse numerical order(RF3->RF1) to comply with MU_GetRxStatusFlags() of mu driver. See MU_GetRxStatusFlags() from drivers/mu/fsl_mu.h
status_reg = MU_GetRxStatusFlags(base);



Parameters:

base – MU peripheral base address. 


Returns:
MU RX status flags in reverse order 






status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Triggers general purpose interrupts to the other core. 
This function triggers the specific general purpose interrupts to the other core. The interrupts to trigger are passed in as bit mask. See mu_general_purpose_interrupt_t. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
status_t status;
status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2);

if (kStatus_Success != status)
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}



Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the interrupts to trigger. See mu_general_purpose_interrupt_t. 


Return values:

kStatus_Success – Interrupts have been triggered successfully. 
kStatus_Fail – Previous interrupts have not been accepted. 







void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)

Boots the other core. 
This function boots the other core with a boot configuration.

Parameters:

base – MU peripheral base address. 
mode – The other core boot mode. 







void MU_HoldOtherCoreReset(MU_Type *base)

Holds the other core reset. 
This function causes the other core to be held in reset following any reset event.

Parameters:

base – MU peripheral base address. 







static inline status_t MU_ResetBothSides(MU_Type *base)

Resets the MU for both A side and B side. 
This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations if waiting for the other side to come out of reset takes too long.

Note
For some platforms, only MU side A could use this function, check reference manual for details. 


Parameters:

base – MU peripheral base address. 


Return values:

kStatus_Success – The MU was reset successfully. 
kStatus_Timeout – Timeout occurred while waiting for the other side to come out of reset.


Returns:
status_t 






status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)

Hardware reset the other core. 
This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout if waiting for the other core to enter or exit reset takes too long.
Example 1: Reset the other core, and no hold reset 
MU_HardwareResetOtherCore(MU_A, true, false, bootMode);


 In this example, the core at MU side B will reset with the specified boot mode.
Example 2: Reset the other core and hold it, then boot the other core later. Here the other core enters reset, and the reset is hold 
MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);


 Current core boot the other core when necessary. MU_BootOtherCore(MU_A, bootMode);




Note
The feature waitReset, holdReset, and bootMode might be not supported for some platforms. waitReset is only available for platforms that FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not defined as 0.


Parameters:

base – MU peripheral base address. 
waitReset – Wait the other core enters reset. Only work when there is CSSR0[RAIP].

true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked.
false: Don’t wait the reset. 


holdReset – Hold the other core reset or not. Only work when there is CCR0[RSTH].

true: Hold the other core in reset, this function returns directly when the other core enters reset.
false: Don’t hold the other core in reset, this function waits until the other core out of reset. 


bootMode – Boot mode of the other core, if holdReset is true, this parameter is useless.


Return values:

kStatus_Success – The other core was reset successfully. 
kStatus_Timeout – Timeout occurred while waiting for the other core to enter or exit reset. 


Returns:
status_t 






FSL_MU_DRIVER_VERSION

MU driver version. 




enum _mu_status_flags

MU status flags. 
Values:


enumerator kMU_Tx0EmptyFlag

TX0 empty. 




enumerator kMU_Tx1EmptyFlag

TX1 empty. 




enumerator kMU_Tx2EmptyFlag

TX2 empty. 




enumerator kMU_Tx3EmptyFlag

TX3 empty. 




enumerator kMU_Rx0FullFlag

RX0 full. 




enumerator kMU_Rx1FullFlag

RX1 full. 




enumerator kMU_Rx2FullFlag

RX2 full. 




enumerator kMU_Rx3FullFlag

RX3 full. 




enumerator kMU_GenInt0Flag

General purpose interrupt 0 pending. 




enumerator kMU_GenInt1Flag

General purpose interrupt 1 pending. 




enumerator kMU_GenInt2Flag

General purpose interrupt 2 pending. 




enumerator kMU_GenInt3Flag

General purpose interrupt 3 pending. 




enumerator kMU_RxFullPendingFlag

Any RX full flag is pending. 




enumerator kMU_TxEmptyPendingFlag

Any TX empty flag is pending. 




enumerator kMU_GenIntPendingFlag

Any general interrupt flag is pending. 




enumerator kMU_EventPendingFlag

MU event pending. 




enumerator kMU_FlagsUpdatingFlag

MU flags update is on-going. 




enumerator kMU_MuInResetFlag

MU of any side is in reset. 




enumerator kMU_MuResetInterruptFlag

The other side initializes MU reset. 






enum _mu_interrupt_enable

MU interrupt source to enable. 
Values:


enumerator kMU_Tx0EmptyInterruptEnable

TX0 empty. 




enumerator kMU_Tx1EmptyInterruptEnable

TX1 empty. 




enumerator kMU_Tx2EmptyInterruptEnable

TX2 empty. 




enumerator kMU_Tx3EmptyInterruptEnable

TX3 empty. 




enumerator kMU_Rx0FullInterruptEnable

RX0 full. 




enumerator kMU_Rx1FullInterruptEnable

RX1 full. 




enumerator kMU_Rx2FullInterruptEnable

RX2 full. 




enumerator kMU_Rx3FullInterruptEnable

RX3 full. 




enumerator kMU_GenInt0InterruptEnable

General purpose interrupt 0. 




enumerator kMU_GenInt1InterruptEnable

General purpose interrupt 1. 




enumerator kMU_GenInt2InterruptEnable

General purpose interrupt 2. 




enumerator kMU_GenInt3InterruptEnable

General purpose interrupt 3. 




enumerator kMU_MuResetInterruptEnable

The other side initializes MU reset. 






enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core. 
Values:


enumerator kMU_GenInt0InterruptTrigger

General purpose interrupt 0. 




enumerator kMU_GenInt1InterruptTrigger

General purpose interrupt 1. 




enumerator kMU_GenInt2InterruptTrigger

General purpose interrupt 2. 




enumerator kMU_GenInt3InterruptTrigger

General purpose interrupt 3. 






enum _mu_msg_reg_index

MU message register index. 
Values:


enumerator kMU_MsgReg0

Message register 0. 




enumerator kMU_MsgReg1

Message register 1. 




enumerator kMU_MsgReg2

Message register 2. 




enumerator kMU_MsgReg3

Message register 3. 






enum _mu_general_purpose_interrupt

MU general purpose interrupts. 
Values:


enumerator kMU_GeneralPurposeInterrupt0

General purpose interrupt 0 




enumerator kMU_GeneralPurposeInterrupt1

General purpose interrupt 1 




enumerator kMU_GeneralPurposeInterrupt2

General purpose interrupt 2 




enumerator kMU_GeneralPurposeInterrupt3

General purpose interrupt 3 






typedef enum _mu_msg_reg_index mu_msg_reg_index_t

MU message register index. 




typedef enum _mu_general_purpose_interrupt mu_general_purpose_interrupt_t

MU general purpose interrupts. 




MU_CORE_INTR(intr)





MU_MISC_INTR(intr)





MU_TX_INTR(intr)





MU_RX_INTR(intr)





MU_GI_INTR(intr)





MU_GET_CORE_INTR(intrs)





MU_GET_TX_INTR(intrs)





MU_GET_RX_INTR(intrs)





MU_GET_GI_INTR(intrs)





MU_CORE_FLAG(flag)





MU_STAT_FLAG(flag)





MU_TX_FLAG(flag)





MU_RX_FLAG(flag)





MU_GI_FLAG(flag)





MU_GET_CORE_FLAG(flags)





MU_GET_STAT_FLAG(flags)





MU_GET_TX_FLAG(flags)





MU_GET_RX_FLAG(flags)





MU_GET_GI_FLAG(flags)





MU1_BUSY_POLL_COUNT

Maximum polling iterations for MU waiting loops. 
This parameter defines the maximum number of iterations for any polling loop in the MU code before timing out and returning an error.
It applies to all waiting loops in MU driver, such as waiting for TX register to be empty or waiting for RX register to be full.
This is a count of loop iterations, not a time-based value.
If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if a core becomes unresponsive. 




MX943_RST_driver#


typedef SRC_XSPR_Type src_mix_slice_t

SRC power region mix slice register structure 




typedef SRC_MEM_Type src_mem_slice_t

SRC power region memory slice register structure 




typedef SRC_GEN_Type src_generic_t

SRC general register structure 




rst_line_info_t const g_rstLineInfo[]

Reset line information 




uint32_t RST_SystemGetResetReason(void)

Get system reset reason
This function allows caller to get reset reason from SRESR (SRC recent event status register).

Returns:
Returns system reset reason captured by SRES (SRC Reset Events Status) register. Defaults to reset reason as POR if SRES bits are cleared. 






void RST_SystemClearResetReason(uint32_t resetReason)

Clear system reset reason

This function allows caller to clear given resetReason in SRESR (SRC recent event status register). 

Parameters:

resetReason – [in] Reset reason identifier







void RST_SystemRequestReset(void)

Request system reset
This function allows caller to request system reset. 




RST_NUM_REASONS





RST_REASON_CM33_LOCKUP





RST_REASON_CM33_SWREQ





RST_REASON_CM7_0_LOCKUP





RST_REASON_CM7_0_SWREQ





RST_REASON_FCCU





RST_REASON_JTAG_SW





RST_REASON_ELE





RST_REASON_TEMPSENSE





RST_REASON_WDOG1





RST_REASON_WDOG2





RST_REASON_WDOG3





RST_REASON_WDOG4





RST_REASON_WDOG5





RST_REASON_JTAG





RST_REASON_WDOG6





RST_REASON_WDOG7





RST_REASON_WDOG8





RST_REASON_WO_NETC





RST_REASON_CM33_S_LOCKUP





RST_REASON_CM33_S_SWREQ





RST_REASON_CM7_1_LOCKUP





RST_REASON_CM7_1_SWREQ





RST_REASON_CM33_EXC





RST_REASON_UNUSED0





RST_REASON_UNUSED1





RST_REASON_UNUSED2





RST_REASON_UNUSED3





RST_REASON_UNUSED4





RST_REASON_UNUSED5





RST_REASON_UNUSED6





RST_REASON_UNUSED7





RST_REASON_POR





RST_LINE_CTRL_DEASSERT





RST_LINE_CTRL_ASSERT





RST_LINE_CTRL_TOGGLE





RST_LINE_CTRL_UNKNOWN





RST_NUM_LINE





RST_LINE_A55C0_NCPUPORESET





RST_LINE_A55C0_NCORERESET





RST_LINE_A55C1_NCPUPORESET





RST_LINE_A55C1_NCORERESET





RST_LINE_A55C2_NCPUPORESET





RST_LINE_A55C2_NCORERESET





RST_LINE_A55C3_NCPUPORESET





RST_LINE_A55C3_NCORERESET





RST_LINE_A55P_NPRESET





RST_LINE_A55P_NSPORESET





RST_LINE_A55P_NSRESET





RST_LINE_A55P_NATRESET





RST_LINE_A55P_NGICRESET





RST_LINE_A55P_NPERIPHRESET





RST_LINE_DDRPHY_PRESETN





RST_LINE_DDRPHY_RESETN





RST_LINE_DISP0_RESETN





RST_LINE_DISP1_RESETN





RST_LINE_LVDS_RESETN





RST_LINE_USB1PHY_RESETN





RST_LINE_USB2PHY_RESETN





RST_LINE_PCIE1PHY_RESETN





RST_LINE_PCIE2PHY_RESETN





RST_LINE_ENETPHY_PCS_RESETN





RST_LINE_ECAT_IP_RESETN





RST_LINE_V2X_RESETB





RST_LINE_BISS_RESETN





RST_LINE_ENDAT3_RESETN





RST_LINE_ENDAT2_RESETN





RST_LINE_HIPERFACE_RESETN





RST_LINE_ANAMIX





RST_LINE_AONMIX_TOP





RST_LINE_AONMIX_M33





RST_LINE_AONMIX_ELE





RST_LINE_BBSMMIX





RST_LINE_M71MIX





RST_LINE_CCMSRCGPCMIX





RST_LINE_CORTEXAMIX_CORE0





RST_LINE_CORTEXAMIX_CORE1





RST_LINE_CORTEXAMIX_CORE2





RST_LINE_CORTEXAMIX_CORE3





RST_LINE_CORTEXAMIX_PLATFORM





RST_LINE_DDRMIX_TOP





RST_LINE_DDRMIX_PHY





RST_LINE_DISPLAYMIX





RST_LINE_M70MIX





RST_LINE_HSIOMIX_TOP





RST_LINE_HSIOMIX_WAON





RST_LINE_NETCMIX





RST_LINE_NETCMIX_M33





RST_LINE_NETCMIX_WDOG_7_8





RST_LINE_NOCMIX





RST_LINE_NOCMIX_WDOG_3_4





RST_LINE_NPUMIX





RST_LINE_WAKEUPMIX_TOP





RST_LINE_WAKEUPMIX_JTAG





RST_LINE_WAKEUPMIX_WDOG_5





RST_LINE_WAKEUPMIX_WDOG_6





SRC_MIX_BASE_PTRS





A55_HDSK_ACK_CTRL_CNT_MODE_MASK





A55_HDSK_ACK_CTRL_CNT_MODE_MASK





A55_HDSK_ACK_CTRL_CNT_MODE





FUNC_STAT_PSW_STAT_MASK





FUNC_STAT_MEM_STAT_MASK





AUTHEN_CTRL_LPM_MODE_MASK





AUTHEN_CTRL_WHITELIST_SHIFT





SLICE_SW_CTRL_PDN_SOFT_MASK





struct rst_line_info_t


#include <fsl_reset.h>
Structure for reset line details 

Public Members


uint32_t lineMask

Reset line control mask register 




__IO uint32_t * lineReg
Reset line control register 




uint32_t statMask

Reset line status mask 




__I uint32_t * statReg
Reset line status register 




bool assertLow

Assert signal (low/high) 




uint32_t toggleUsec

Delay during reset toggle 







NETC driver#



Status code for the NETC module. 
Values:


enumerator kStatus_NETC_RxFrameEmpty

Rx BD ring empty. 




enumerator kStatus_NETC_RxTsrResp

Rx timestamp reference response 




enumerator kStatus_NETC_RxFrameError

Rx frame error. 




enumerator kStatus_NETC_TxFrameOverLen

Tx frame over length. 




enumerator kStatus_NETC_LackOfResource

Lack of resources to configure certain features. 




enumerator kStatus_NETC_Unsupported

Unsupported operation/feature. 




enumerator kStatus_NETC_RxHRZeroFrame

Rx frame host reason is zero 




enumerator kStatus_NETC_RxHRNotZeroFrame

Rx frame host reason is not zero 




enumerator kStatus_NETC_NotFound

No entry found in hardware tables 




enumerator kStatus_NETC_EntryExists

An entry already exists in hardware tables 






enum _netc_ep_event

Defines the common interrupt event for callback use. 
Values:


enumerator kNETC_EPRxEvent

EP Rx interrupt event. 




enumerator kNETC_EPTxEvent

EP Tx interrupt event. 






enum _netc_ep_tx_status

Status for the transmit buffer descriptor. 
Values:


enumerator kNETC_EPTxSuccess

Success transmission. 




enumerator kNETC_EPTxProgramErr

Error exists in either the Tx BD, the Tx ring registers, or both. 




enumerator kNETC_EPTxTsdDrop

The time defined in TX_START expired before frame could be transmitted. 




enumerator kNETC_EPTxFrameSizeErr

Frame size error. 




enumerator kNETC_EPTxNullAddr

Null address. 




enumerator kNETC_EPTxInvalidLength

Invalid frame/buffer/chain length. 




enumerator kNETC_EPTxSrcMacSpoofingDetect

Source MAC address spoofing detected. 




enumerator kNETC_EPTxPortRestDrop

Frame dropped due to port reset. 




enumerator kNETC_EPTxPortDisableDrop

Frame dropped due to port disable. 




enumerator kNETC_EPTxVlanTpidDrop

VLAN TPID not allowed. 




enumerator kNETC_EPTxSmsoParamErr

Programming error in buffer descriptor used for direct switch enqueue. 




enumerator kNETC_EPTxFrameGateErr

Frame too large for time gating window. 




enumerator kNETC_EPTxAxiReadErr

AXI read error. 




enumerator kNETC_EPTxAxiWriteErr

AXI write error. 




enumerator kNETC_EPTxMultiBitECCErr

Frame not transmitted(dropped) due to a multi-bit ECC error detected. 




enumerator kNETC_EPTxParityErr

Parity error. 




enumerator kNETC_EPTxSwCongestion

Frame dropped due to switch congestion. 






enum _netc_vlan_tpid_select

Ethernet VLAN Tag protocol identifier. 
Values:


enumerator kNETC_StanCvlan

0x8100. 




enumerator kNETC_StanSvlan

0x88A8. 




enumerator kNETC_CustomVlan1

CVLANR1[ETYPE] 




enumerator kNETC_CustomVlan2

CVLANR2[ETYPE] 






enum _netc_packet_type

Ethernet packet type enumerator. 
Values:


enumerator kNETC_PacketUnicast





enumerator kNETC_PacketMulticast





enumerator kNETC_PacketBroadcast







enum _netc_host_reason

Host reason. 
Values:


enumerator kNETC_RegularFrame





enumerator kNETC_IngressMirror





enumerator kNETC_MACLearning





enumerator kNETC_TimestampResp





enumerator kNETC_SoftwareDefHR0





enumerator kNETC_SoftwareDefHR1





enumerator kNETC_SoftwareDefHR2





enumerator kNETC_SoftwareDefHR3





enumerator kNETC_SoftwareDefHR4





enumerator kNETC_SoftwareDefHR5





enumerator kNETC_SoftwareDefHR6





enumerator kNETC_SoftwareDefHR7







enum _netc_msix_vector_ctrl

MSIX vector control field. 
Values:


enumerator kNETC_MsixIntrMaskBit

MSIX vector control interrupt mask bit. 






enum _netc_tx_ext_flags

METC Extension Transmit Buffer Descriptor Extension flags field. 
Values:


enumerator kNETC_TxExtVlanInsert

Enable VLAN insert. 




enumerator kNETC_TxExtTwoStepTs

Enable two-step timestamp offload. 






typedef enum _netc_ep_event netc_ep_event_t

Defines the common interrupt event for callback use. 




typedef enum _netc_ep_tx_status netc_ep_tx_status_t

Status for the transmit buffer descriptor. 




typedef struct _netc_vlan netc_vlan_t

VLAN tag struct. 




typedef enum _netc_vlan_tpid_select netc_vlan_tpid_select_t

Ethernet VLAN Tag protocol identifier. 




typedef enum _netc_packet_type netc_packet_type_t

Ethernet packet type enumerator. 




typedef enum _netc_host_reason netc_host_reason_t

Host reason. 




typedef struct _ep_buffer_struct netc_buffer_struct_t

Buffer structure. Driver can send/receive one frame spread across multiple buffers. 




typedef struct _ep_frame_struct netc_frame_struct_t

Frame structure for single Tx/Rx frame. 




typedef struct _netc_frame_attr_struct netc_frame_attr_t

Frame attribute struct. 




typedef struct _netc_tx_frame_info_struct netc_tx_frame_info_t

Frame attribute structure. 




typedef enum _netc_msix_vector_ctrl netc_msix_vector_ctrl_t

MSIX vector control field. 




typedef struct _netc_msix_entry netc_msix_entry_t

NETC MSIX entry structure. 




typedef enum _netc_tx_ext_flags netc_tx_ext_flags_t

METC Extension Transmit Buffer Descriptor Extension flags field. 




FSL_NETC_DRIVER_VERSION

Driver Version. 




NETC_ADDR_LOW_32BIT(x)

Macro to divides an address into a low 32 bits and a possible high 32 bits. 




NETC_ADDR_HIGH_32BIT(x)





struct _netc_vlan


#include <fsl_netc.h>
VLAN tag struct. 

Public Members


uint32_t vid

Vlan Identifier. 




uint32_t dei

Drop Eligible indicator. 




uint32_t pcp

Priority. 




uint32_t tpid

Tag protocol identifier. 







struct _ep_buffer_struct


#include <fsl_netc.h>
Buffer structure. Driver can send/receive one frame spread across multiple buffers. 

Public Members


void *buffer

Buffer address. 




uint16_t length

Buffer data length. 







struct _ep_frame_struct


#include <fsl_netc.h>
Frame structure for single Tx/Rx frame. 

Public Members


netc_buffer_struct_t *buffArray

Buffer array. Tx: [in]App sets, Rx: [in/out]App sets prepared array, driver sets back received buffers array. 




uint16_t length

Buffer array length. Tx: [in]App sets, Rx: [in/out]App sets prepared array length, driver sets back received buffers array length. 







struct _netc_frame_attr_struct


#include <fsl_netc.h>
Frame attribute struct. 

Public Members


bool isTsAvail

Rx frame timestamp is available or not. 




bool isVlanExtracted

Rx frame VLAN header is available or not. 




uint32_t timestamp

The timestamp of this Rx frame. 







struct _netc_tx_frame_info_struct


#include <fsl_netc.h>
Frame attribute structure. 

Public Members


bool isTsAvail

Tx frame timestamp is available or not. 




uint32_t timestamp

The timestamp of this Tx frame, valid when isTsAvail is true. 




void *context

Private context provided by the user. 




netc_ep_tx_status_t status

Transmit status. 







struct _netc_msix_entry


#include <fsl_netc.h>
NETC MSIX entry structure. 

Public Members


uint64_t msgAddr

Message address. 




uint32_t msgData

Message data. 




uint32_t control

Vector control, netc_msix_vector_ctrl_t. 







Abbreviation in NETC driver#


API layer#


NETC Endpoint (EP) Driver#


Endpoint (EP) Generic Configuration#


typedef struct _ep_handle ep_handle_t

Endpoint handle. 




typedef status_t (*ep_reclaim_cb_t)(ep_handle_t *handle, uint8_t ring, netc_tx_frame_info_t *frameInfo, void *userData)

Callback for reclaimed tx frames. 




typedef void *(*ep_rx_alloc_cb_t)(ep_handle_t *handle, uint8_t ring, uint32_t length, void *userData)

Defines the EP Rx memory buffer alloc function pointer. 




typedef void (*ep_rx_free_cb_t)(ep_handle_t *handle, uint8_t ring, void *address, void *userData)

Defines the EP Rx memory buffer free function pointer. 




typedef status_t (*ep_get_link_status_cb_t)(ep_handle_t *handle, uint8_t *link)

Callback for getting link status. 




typedef status_t (*ep_get_link_speed_cb_t)(ep_handle_t *handle, netc_hw_mii_speed_t *speed, netc_hw_mii_duplex_t *duplex)

Callback for getting link speed. 




typedef status_t (*ep_preinit_vsi_cb_t)(netc_enetc_hw_t *hw, netc_hw_si_idx_t si)

Callback for vsi pre-init. 




typedef struct _ep_config ep_config_t

Configuration for the endpoint handle. 




typedef struct _ep_config_const ep_config_const_t

Configuration constant in handle. 




status_t EP_Init(ep_handle_t *handle, uint8_t *macAddr, const ep_config_t *config, const netc_bdr_config_t *bdrConfig)

Initialize the endpoint with specified station interface. 
Each station interface needs to call this API. In the case of a virtual station interface it’s necessary that the physical station interface has been initialized beforehand.

Parameters:

handle – 
macAddr – Primary MAC address 
config – The user configuration 
bdrConfig – Array of buffer configurations (for each queue/ring) 


Returns:
status_t 






status_t EP_Deinit(ep_handle_t *handle)

De-initialize the endpoint. 

Parameters:

handle – 


Returns:
status_t 






status_t EP_GetDefaultConfig(ep_config_t *config)

Get the default configuration. 

Parameters:

config – 


Returns:
status_t 






status_t EP_Up(ep_handle_t *handle, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)

Enable MAC transmission/reception To be called when the PHY link is up. 

Parameters:

handle – 
speed – 
duplex – 


Returns:
status_t 






status_t EP_Down(ep_handle_t *handle)

Disable MAC transmission/reception To be called when the PHY link is down. 

Note
Must ensure all active Tx rings finish current transmission before call this API.


Parameters:

handle – 


Returns:
status_t 






status_t EP_SetPrimaryMacAddr(ep_handle_t *handle, uint8_t *macAddr)

Set the Primary MAC address. 

Parameters:

handle – 
macAddr – 


Returns:
status_t 






static inline void EP_SetPortSpeed(ep_handle_t *handle, uint16_t pSpeed)

Set EP port speed. 

Parameters:

handle – 
pSpeed – 







struct _ep_config


#include <fsl_netc_endpoint.h>
Configuration for the endpoint handle. 

Public Members


netc_hw_si_idx_t si

Station interface index. 




netc_hw_enetc_si_config_t siConfig

Station interface configuration. 




uint8_t txPrioToTC[8]

Tx BD ring priority to Tx traffic class queue index mapping, range in TC0 ~ TC7. 




netc_port_tx_tc_config_t txTcCfg[8]

Tx traffic class related configuration, vaild only on ENETC 0. 




netc_ep_psfp_config_t psfpCfg

PSFP configuration,cover the ISI key construction profile and port ingress stream identification configuration. 




bool enOuterAsInner

Enable use outer VLAN tag as the inner tag if only one tag is found. 




netc_enetc_native_vlan_config_t rxOuterVLANCfg

Port outer native VLAN config. 




netc_enetc_native_vlan_config_t rxInnerVLANCfg

Port inner native VLAN config. 




netc_enetc_parser_config_t parserCfg

ENETC parser configuration. 




uint32_t pauseOnThr

ENETC Port pause ON threshold value, value 0 means disables pause generation. 




uint32_t pauseOffThr

ENETC Port pause OFF threshold value, value 0 means disables pause generation. 




netc_msix_entry_t *msixEntry

MSIX table entry array. 




uint8_t entryNum

MSIX entry number. 




uint8_t cmdBdEntryIdx

MSIX entry index of command BD ring interrupt. 




uint8_t siComEntryIdx

MSIX entry index of PSI-VSI communication interrupt. 




uint8_t timerSyncEntryIdx

MSIX entry index of timer synchronous state change interrupt. 




ep_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx frames. 




void *userData

User data, return in callback. 




bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver. 




bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver. 




bool rxZeroCopy

Enable/Disable zero-copy receive mode. 




ep_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx. 




ep_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx. 




ep_preinit_vsi_cb_t preinitVsi

Callback function to pre-init VSI 




netc_cmd_bdr_config_t cmdBdrConfig

Command BD ring configuration. 







struct _ep_config_const


#include <fsl_netc_endpoint.h>
Configuration constant in handle. 

Public Members


netc_hw_si_idx_t si

Station interface index. 




uint8_t rxRingUse

Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings. 




uint8_t txRingUse

Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0. 




uint8_t rxBdrGroupNum

Rx BD ring group number, range in 0 ~ 2. 




uint8_t ringPerBdrGroup

The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero. 




bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver. 




bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver. 




bool rxZeroCopy

Enable/Disable zero-copy receive mode. 




uint8_t entryNum

MSIX entry number. 




ep_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx frames. 




void *userData

User data, return in callback. 




ep_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx. 




ep_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx. 







struct _ep_handle


#include <fsl_netc_endpoint.h>
Handle for the endpoint Private internal data. 

Public Members


netc_enetc_hw_t hw

Hardware register map resource. 




netc_enetc_cap_t capability

ENETC capability. 




ep_config_const_t cfg

Endpoint configuration constant. 




uint8_t ringShift

Endpoint Tx ring shift. 




netc_rx_bdr_t rxBdRing[1]

Receive buffer descriptor ring. 




netc_tx_bdr_t txBdRing[1]

Transmit buffer descriptor ring. 




netc_cmd_bdr_t cmdBdRing

Command BD ring handle for endpoint. 




uint8_t unicastHashCount[64]

Unicast hash index collisions counter. 




uint8_t multicastHashCount[64]

Multicast hash index collisions counter. 




uint8_t vlanHashCount[64]

VLAN hash index collisions counter. 




uint8_t macFilterCount[64]

mac address filter index collisions counter. 




uint8_t vlanFilterCount[64]

vlan address filter index collisions counter. 




ep_get_link_status_cb_t getLinkStatus

Callback to get link status 




ep_get_link_speed_cb_t getLinkSpeed

Callback to get link speed 




uint16_t vsiBitMapNotifyLinkStatus

VSI bit map for link status notify 




uint16_t vsiBitMapNotifyLinkSpeed

VSI bit map for link speed notify 







struct port


Public Members


netc_port_ethmac_t ethMac

Ethernet MAC configuration. 




netc_port_common_t common

Port common configuration. 




bool enableTg

Enable port time gate scheduling. 




bool enPseudoMacTxPad

Enable pseudo MAC Port Transmit Padding, will pad the frame to a minimum of 60 bytes and append 4 octets of FCS. 







Endpoint (EP) data path#


typedef struct _netc_ep_ipf_config netc_ep_ipf_config_t

Port Ingress Filter config. 




typedef struct _netc_ep_psfp_config netc_ep_psfp_config_t

PSFP config. 




struct _netc_ep_ipf_config


#include <fsl_netc_endpoint.h>
Port Ingress Filter config. 

Public Members


netc_ipf_config_t dosCfg

Configuration for L2/3 DOS. 




netc_port_ipf_config_t portConfig

Configuration for port connected to enetc peripheral. 







struct _netc_ep_psfp_config


#include <fsl_netc_endpoint.h>
PSFP config. 




Endpoint (EP) Interrupt Module#


enum _ep_interrupt_flag

Interrupt enable/disable flags. 
The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER 
Values:


enumerator kNETC_EPPSIResetInterruptEnable





enumerator kNETC_EPPSIMsgRxInterruptEnable







typedef enum _ep_interrupt_flag ep_interrupt_flag_t

Interrupt enable/disable flags. 
The value of the enumerator is not necessary match the bit in register. All interrupts in Endpoint are merged into this enum except the BDR specific interrupt. TODO SITMRIER 




static inline void EP_CleanTxIntrFlags(ep_handle_t *handle, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)

Clean the SI transmit interrupt flags. 

Parameters:

handle – The EP handle. 
txFrameIntrMask – IPV value to be mapped, bit x represents ring x. 
txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x. 







static inline void EP_CleanRxIntrFlags(ep_handle_t *handle, uint32_t rxIntrMask)

Clean the SI receive interrupt flags. 

Parameters:

handle – The EP handle. 
rxIntrMask – Rx interrupt bit mask, bit x represents ring x. 







status_t EP_MsixSetGlobalMask(ep_handle_t *handle, bool mask)

Set the global MSIX mask status. 
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.

Parameters:

handle – The EP handle 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t EP_MsixSetEntryMask(ep_handle_t *handle, uint8_t entryIdx, bool mask)

Set the MSIX entry mask status for specified entry. 
This function masks/unmasks MSIX message for specified entry.

Parameters:

handle – The EP handle 
entryIdx – The entry index in the table. 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t EP_MsixGetPendingStatus(ep_handle_t *handle, uint8_t pbaIdx, uint64_t *status)

Get the MSIX pending status in MSIX PBA table. 
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.

Parameters:

handle – The EP handle 
pbaIdx – The index of PBA array with 64-bit unit. 
status – Pending status bit mask, bit n for entry n. 


Returns:
status_t 






Endpoint (EP) Table Management Module#


status_t EP_CmdBDRInit(ep_handle_t *handle, const netc_cmd_bdr_config_t *config)

Initialize endpoint command BD ring. 

Parameters:

handle – 
config – The command BD ring configuration 


Returns:
status_t 






status_t EP_CmdBDRDeinit(ep_handle_t *handle)

Deinit endpoint command BD ring. 

Parameters:

handle – 


Returns:
status_t 






Endpoint (EP) PSI/VSI#


void EP_PsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)

PSI enables/disables specified interrupt. 

Parameters:

handle – The EP handle. 
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 
enable – Enable/Disable the interrupt. 







uint32_t EP_PsiGetStatus(ep_handle_t *handle)

PSI gets interrupt event flag status. 

Parameters:

handle – The EP handle. 


Returns:
The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 






void EP_PsiClearStatus(ep_handle_t *handle, uint32_t mask)

PSI clears interrupt event flag. 

Parameters:

handle – The EP handle. 
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 







status_t EP_PsiSendMsg(ep_handle_t *handle, uint16_t msg, netc_vsi_number_t vsi)

PSI sends message to specified VSI(s) 

Parameters:

handle – The EP handle. 
msg – The message to be sent. 
vsi – The VSI number. 


Returns:
status_t 






bool EP_PsiCheckTxBusy(ep_handle_t *handle, netc_vsi_number_t vsi)

PSI checks Tx busy flag which should be cleaned when VSI receive the message data. 

Parameters:

handle – The EP handle. 
vsi – The VSI number. 


Returns:
The busy status of specified VSI. 






status_t EP_PsiSetRxBuffer(ep_handle_t *handle, netc_vsi_number_t vsi, uint64_t buffAddr)

PSI sets Rx buffer to receive message from specified VSI. 

Note
The buffer memory size should be big enough for the message data from VSI


Parameters:

handle – The EP handle. 
vsi – The VSI number. 
buffAddr – The buffer address to store message data from VSI. 







status_t EP_PsiGetRxMsg(ep_handle_t *handle, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)

PSI gets Rx message from specified VSI. 

Parameters:

handle – The EP handle. 
vsi – The VSI number. 
msgInfo – The Rx message information. 







void EP_VsiEnableInterrupt(ep_handle_t *handle, uint32_t mask, bool enable)

Enable VSI interrupt. 

Parameters:

handle – The EP handle. 
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together. 
enable – Enable/Disable interrupt. 







uint32_t EP_VsiGetStatus(ep_handle_t *handle)

Get VSI interrupt status. 

Parameters:

handle – The EP handle. 


Returns:
A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together. 






void EP_VsiClearStatus(ep_handle_t *handle, uint32_t mask)

Clear VSI interrupt status. 

Parameters:

handle – The EP handle. 
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together. 







status_t EP_VsiSendMsg(ep_handle_t *handle, uint64_t msgAddr, uint32_t msgLen)

VSI sends message to PSI. 

Parameters:

handle – The EP handle. 
msgAddr – Address to store message ready to be sent, must be 64 bytes aligned. 
msgLen – The message length, must be 32 bytes aligned. 


Returns:
status_t 






void EP_VsiCheckTxStatus(ep_handle_t *handle, netc_vsi_msg_tx_status_t *status)

Check VSI Tx status. 

Parameters:

handle – The EP handle. 
status – The VSI Tx status structure. 







status_t EP_VsiReceiveMsg(ep_handle_t *handle, uint16_t *msg)

VSI receives message from PSI. 

Parameters:

handle – The EP handle. 
msg – The message from PSI. 


Returns:
status_t 






Endpoint (EP) Ingress data path configuration#


static inline status_t EP_RxParserConfig(ep_handle_t *handle, netc_port_parser_config_t *config)

Configure Parser in Receive Data Path. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t EP_RxVlanCInit(ep_handle_t *handle, const netc_vlan_classify_config_t *config)

Configure the customer vlan type. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t EP_RxVlanCConfigPort(ep_handle_t *handle, netc_port_vlan_classify_config_t *config)

Configure the Accepted Vlan. 

Parameters:

handle – 
config – 


Returns:
status_t 






status_t EP_RxIPFInit(ep_handle_t *handle, netc_ep_ipf_config_t *config)

Enable / Disable Ingress Port Filtering. 
Applied for both Switch and ENETC

Parameters:

handle – 
config – IPF general features 


Returns:
status_t 






static inline uint32_t EP_RxIPFGetTableRemainWordNum(ep_handle_t *handle)

Get remaining available word number (words size is 6 bytes) of the ingress Port Filter Table. 

Note
This is a ternary match table, and the entries can vary in size, from 2 to 14 words.


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxIPFAddTableEntry(ep_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)

Add an entry for the ingress Port Filter Table. 
This function do an add & query with return hardware id which can be used as future query / delete / update.

Parameters:

handle – 
config – IPF instance configuaration 
entryID – The table entry ID read out 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxIPFUpdateTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)

Update entry in the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxIPFDelTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry for the ingress Port Filter Table. 

Parameters:

handle – 
entryID – The table entry ID 


Returns:
status_t 






status_t EP_RxIPFResetMatchCounter(ep_handle_t *handle, uint32_t entryID)

Reset the counter of an ingress port filter entry. 

Parameters:

handle – 
entryID – The table entry ID 


Returns:
status_t 






status_t EP_RxIPFGetMatchedCount(ep_handle_t *handle, uint32_t entryID, uint64_t *count)

Get the matched count for entry in IPF. 

Parameters:

handle – 
entryID – The table entry ID 
count – A count of how many times this entry has been matched. 


Returns:
status_t 






static inline status_t EP_RxPSFPInit(ep_handle_t *handle, const netc_ep_psfp_config_t *config)

Init the ENETC PSFP, inlcude. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline uint32_t EP_RxPSFPGetISITableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of stream identification table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Filter, table.


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddISITableEntry(ep_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)

Add an entry into the stream identification table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelISITableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t EP_RxPSFPGetISTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of ingress stream table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)

Add an entry into the ingress stream table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPUpdateISTableEntry(ep_handle_t *handle, netc_tb_is_config_t *config)

Update an entry in the ingress stream table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelISTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 






static inline uint32_t EP_RxPSFPGetISFTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of ingress stream filter table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification table.


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddISFTableEntry(ep_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)

Add an entry into the ingress stream filter table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPUpdateISFTableEntry(ep_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)

Update an entry into the ingress stream filter table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelISFTableEntry(ep_handle_t *handle, uint32_t entryID)

Del an entry into the stream filter table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 






static inline uint32_t EP_RxPSFPGetRPTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of Rate Policer table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Add entry to Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Update entry in Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPAddOrUpdateRPTableEntry(ep_handle_t *handle, netc_tb_rp_config_t *config)

Add or update entry in Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelRPTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry in the Rate Policer table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 






status_t EP_RxPSFPGetRPStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)

Get statistic of specified Rate Policer entry. 

Parameters:

handle – 
entryID – 
statis – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t EP_RxPSFPGetISCTableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of ingress stream count table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddISCTableEntry(ep_handle_t *handle, uint32_t entryID)

Add entry in ingress stream count table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPGetISCStatistic(ep_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)

Get ingress stream count statistic. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPResetISCStatistic(ep_handle_t *handle, uint32_t entryID)

Reset the count of the ingress stream count. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t EP_RxPSFPGetSGITableRemainEntryNum(ep_handle_t *handle)

Get remaining available entry number of stream gate instance table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)

Add entry in stream gate instance table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPUpdateSGITableEntry(ep_handle_t *handle, netc_tb_sgi_config_t *config)

Update entry in stream gate instance table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelSGITableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry in stream gate instance table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPGetSGIState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state)

Get state of the stream gate instance for specified entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t EP_RxPSFPGetSGCLTableRemainWordNum(ep_handle_t *handle)

Get remaining available words number of Stream Gate Control List table. 

Note
This is a dynamic bounded index table, and number of words required for a stream gate control list is 1+N/2 where N is number of gate time slots in the stream gate control list. The remaining word should be greater than the want added entry size


Parameters:

handle – 


Returns:
uint32_t 






status_t EP_RxPSFPAddSGCLTableEntry(ep_handle_t *handle, netc_tb_sgcl_gcl_t *config)

Add entry into Stream Gate Control List Table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPDelSGCLTableEntry(ep_handle_t *handle, uint32_t entryID)

Delete entry of Stream Gate Control List Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPGetSGCLGateList(ep_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)

Get Stream Gate Control List Table entry gate control list. 

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxPSFPGetSGCLState(ep_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)

Get state (ref count) for Stream Gate Control List table entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxL2MFInit(ep_handle_t *handle, netc_si_l2mf_config_t *config)

Init the L2 MAC Filter for a specified SI. 

Parameters:

handle – EP handle 
config – The L2 MAC Filter configuration 


Returns:
status_t 






status_t EP_RxL2MFAddHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)

Add entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement. 

Parameters:

handle – EP handle 
type – Unicast or multicast MAC address 
macAddr – MAC address to be added in filter table 


Returns:
status_t 






status_t EP_RxL2MFDelHashEntry(ep_handle_t *handle, netc_packet_type_t type, uint8_t *macAddr)

Delete entry into the MAC address hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement. 

Parameters:

handle – EP handle 
type – Unicast or multicast MAC address 
macAddr – MAC address to be deleted from filter table 


Returns:
status_t 






status_t EP_RxL2MFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint8_t *macAddr)

Add entry into the MAC filter exact match table. 
The entry is associated to the current Station Interface

Parameters:

handle – 
idx – Index in the entry table 
macAddr – MAC address for filter 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxL2MFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)

Delete entry into the MAC filter exact match table. 

Parameters:

handle – EP handle 
idx – Index in the entry table 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxL2VFInit(ep_handle_t *handle, netc_si_l2vf_config_t *config)

For VLAN filter, use inner vlan tag or outer vlan tag. 

Parameters:

handle – 
config – 


Returns:
status_t 






status_t EP_RxL2VFAddHashEntry(ep_handle_t *handle, uint16_t vlanId)

Add entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement. 

Parameters:

handle – 
vlanId – VLAN identifier for filter 


Returns:
status_t 






status_t EP_RxL2VFDelHashEntry(ep_handle_t *handle, uint16_t vlanId)

Delete entry into the VLAN hash filter with given MAC address Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement. 

Parameters:

handle – 
vlanId – VLAN identifier for filter 


Returns:
status_t 






status_t EP_RxL2VFAddEMTableEntry(ep_handle_t *handle, uint32_t idx, uint16_t vlanId, netc_vlan_tpid_select_t tpid)

Add entry into the MAC filter exact match table. 
The entry is associated to the current Station Interface

Parameters:

handle – 
idx – Index in the entry table 
vlanId – VLAN identifier 
tpid – VLAN TPID 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_RxL2VFDelEMTableEntry(ep_handle_t *handle, uint32_t idx)

Delete entry into the VLAN filter exact match table. 

Parameters:

handle – 
idx – Index in the entry table 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline status_t EP_RxMapVlanToIpv(ep_handle_t *handle, netc_vlan_t vlan, uint8_t ipv)

Set the received Frame vlan to IPV mapping. 

Parameters:

handle – 
vlan – Frame VLAN tag. 
ipv – The IPV value to be mapped. 


Returns:
status_t 






static inline status_t EP_RxMapIpvToRing(ep_handle_t *handle, uint8_t ipv, uint8_t ring)

Set the IPV to Rx ring mapping. 

Parameters:

handle – 
ipv – IPV value to be mapped. 
ring – The Rx BD ring index to be mapped. 


Returns:
status_t 






static inline status_t EP_RxSetDefaultBDRGroup(ep_handle_t *handle, netc_hw_enetc_si_rxr_group groupIdx)

Set the default used receive Rx BD ring group. 

Note
The IPV mapped ring index is the relative index inside the default used group.


Parameters:

handle – 
groupIdx – The default Rx group index. 


Returns:
status_t 






Endpoint (EP) Statistic Module#


enum _ep_flags

Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR. 
Values:


enumerator kNETC_EPTimerSyncedFlag





enumerator kNETC_EPICMBlockedFlag





enumerator kNETC_EPWakeOnLANActiveFlag







typedef enum _ep_flags ep_flags_t

Status/interrupt detect flags merged to same set of enum. TODO SITMRIDR. 




static inline status_t EP_GetPortDiscardStatistic(ep_handle_t *handle, bool useTx, netc_port_discard_statistic_t *statistic)

Get the ENETC port discard statistic and reason. 
Get the discarded count of frames and its reasons.

Parameters:

handle – 
useTx – true - Tx port. false - Rx port. 
statistic – pointer to the statistic data 


Returns:
status_t 






static inline status_t EP_ClearPortDiscardReason(ep_handle_t *handle, bool useTx, uint32_t reason0, uint32_t reason1)

Clean the EP Port Rx discard reason. Set the related bits to 1 to clear the specific reasons. 

Parameters:

handle – 
useTx – true - Tx port. false - Rx port. 
reason0 – 
reason1 – 


Returns:
status_t 






static inline uint32_t EP_GetPortTGSListStatus(ep_handle_t *handle)

Get EP port time gate scheduling gate list status. 

Parameters:

handle – 


Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t






Endpoint (EP) Egress data path configuration#


status_t EP_TxTGSConfigAdminGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *config)

Config the Time Gate Scheduling entry admin gate control list. 
This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_TxPortTGSEnable(ep_handle_t *handle, bool enable, uint8_t gateState)

Enable the EP port time gate scheduling. 

Parameters:

handle – 
enable – 
gateState – 


Returns:
status_t 






status_t EP_TxtTGSGetOperGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)

Get Time Gate Scheduling entry operation gate control list. 
This function is used to read the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t EP_TxTrafficClassConfig(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config)

Config the TC (traffic class) property. 

Parameters:

handle – 
tcIdx – 
config – 


Returns:
status_t 






static inline void EP_TxTcConfigPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const bool enable)

Config Preemption for each port TC (traffic class) 

Parameters:

handle – 
tcIdx – 
enable – 







static inline void EP_TxGetTcPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, bool *enabled)

Get Preemption configuration for each port TC (traffic class) 

Parameters:

handle – 
tcIdx – 
enabled – 







static inline void EP_TxPortEthMacConfigPreemption(ep_handle_t *handle, const netc_port_preemption_config *config)

Configure Preemption control configuration for an ethernet MAC. 

Parameters:

handle – 
config – 







static inline void EP_TxPortGetEthMacPreemption(ep_handle_t *handle, netc_port_preemption_config *config, netc_port_phy_mac_preemption_status_t *status)

Get Preemption configuration from ethernet MAC port. 

Parameters:

handle – 
config – 
status – 







Endpoint (EP) Transmit/Receive#


enum _ep_rx_flags

Values:


enumerator kEP_RX_RSS_VALID

Request timestamp. 




enumerator kEP_RX_VLAN_VALID

Specifiy frame departure time. 




enumerator kEP_RX_TIMESTAMP_VALID

Enable port masquerading. 






enum _ep_tx_opt_flags

Values:


enumerator kEP_TX_OPT_REQ_TS

Request timestamp (IEEE 1588 PTP two-step timestamp). 




enumerator kEP_TX_OPT_VLAN_INSERT

Enable VLAN insert. 




enumerator kEP_TX_OPT_START_TIME

Specifiy frame departure time. 






typedef enum _ep_rx_flags ep_rx_flags_t





typedef enum _ep_tx_opt_flags ep_tx_opt_flags





typedef struct _ep_tx_offload netc_tx_offload_t





typedef struct _ep_tx_opt ep_tx_opt





status_t EP_SendFrameCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, netc_frame_struct_t *frame, void *context, netc_tx_bd_t *txDesc, bool txCacheMaintain)

Common part for transfer regular frame or Switch management frame. 

Note
This function is internal used. Please use EP_SendFrame() or SWT_SendFrame() API to send frames.


Parameters:

handle – 
txBdRing – The Transmit buffer descriptor ring handle 
hwRing – The hardware Tx ring index 
frame – The frame descriptor pointer 
context – Private context provided back by ep_reclaim_cb_t 
txDesc – Point to the Transmits BD Description array. 
txCacheMaintain – Enable/Disable Tx buffer Cache Maintain. 


Return values:
status_t – 






status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, void *context, ep_tx_opt *opt)

Transmits a frame for specified ring. This API is zero-copy and requires the ep_reclaim_cb_t to be called to free the transmitted frame. 

Parameters:

handle – 
ring – The ring index 
frame – The frame descriptor pointer 
context – Private context provided back by ep_reclaim_cb_t 
opt – Additional tx options. If NULL, default is tx timestamping enabled, no start time and no masquerading. 


Return values:
status_t – 






static inline void EP_WaitUnitilTxComplete(ep_handle_t *handle, uint8_t ring)

Wait until the EP Tx ring has completed the transfer. 

Note
Only call after EP_SendFrame() to do a no-interrupt transfer


Parameters:

handle – 
ring – The ring index 







netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle, netc_tx_bdr_t *txBdRing, uint8_t hwRing, bool enCallback)

Common part of Reclaim tx descriptors for regular frame or Switch management frame. 

Note
This function is internal used. Please use EP_ReclaimTxDescriptor() or SWT_ReclaimTxDescriptor() API to Reclaim tx descriptors.


Parameters:

handle – 
txBdRing – The Transmit buffer descriptor ring handle 
hwRing – The hardware Tx ring index 
enCallback – Enable/Disable call the Tx Reclaim callback functions. 







void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring)

Reclaim tx descriptors. This function is used to update the tx descriptor status and get the tx timestamp. For each reclaimed transmit frame the ep_reclaim_cb_t is called. 
This is called after being notified of a transmit completion from ISR. It runs until there are no more frames to be reclaimed in the BD ring.

Parameters:

handle – 
ring – The ring index 







status_t EP_ReceiveFrameCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr, bool rxCacheMaintain)

Common part of receives one frame with zero copy from specified ring. 

Note
This function is internal used. Please use EP_ReceiveFrame() or SWT_ReceiveFrame() API.


Parameters:

handle – 
rxBdRing – Rx BD ring handle 
ring – Ring index 
frame – Frame buffer point 
attr – Frame attribute pointer 
rxCacheMaintain – Enable/Disable Rx buffer Cache maintain 


Returns:
status_t 






status_t EP_ReceiveFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *frame, netc_frame_attr_t *attr)

Receives one frame with zero copy from specified ring. 

Note
The sufficient rx frame data structure MUST be provided by appliction.


Parameters:

handle – 
ring – The ring index 
frame – The frame descriptor pointer 
attr – Frame attribute pointer 


Returns:
kStatus_Success Successfully receive a regular frame 

Returns:
kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_ReceiveFrame()

Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response 

Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty 

Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped 

Returns:
kStatus_InvalidArgument Rx BD ring index is out of range 

Returns:
kStatus_NETC_LackOfResource Appliction provided buffer is not enough 






void EP_DropFrame(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring)

Drop one frame. 

Note
This function is internal used.


Parameters:

handle – 
rxBdRing – Rx BD ring handle 
ring – Ring index 







status_t EP_ReceiveFrameCopyCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr, bool rxCacheMaintain)

Common part of receive regular frame or Switch management frame which will be copied in the provided buffer. 

Note
This function is internal used. Please use EP_ReceiveFrameCopy() or SWT_ReceiveFrameCopy() API.


Parameters:

handle – 
rxBdRing – Rx BD ring handle 
ring – Ring index 
buffer – Buffer address 
length – Buffer length 
attr – Frame attribute pointer 
rxCacheMaintain – Enable/Disable Rx buffer Cache maintain 


Returns:
status_t 






status_t EP_ReceiveFrameCopy(ep_handle_t *handle, uint8_t ring, void *buffer, uint32_t length, netc_frame_attr_t *attr)

Receives one frame which will be copied in the provided buffer from specified ring. 

Note
The buffer size MUST be queried using EP_GetRxFrameSize() beforehand.


Parameters:

handle – 
ring – Ring index 
buffer – Buffer address 
length – Buffer length 
attr – Frame attribute pointer 


Returns:
kStatus_Success Successfully receive a regular frame 

Returns:
kStatus_InvalidArgument Rx BD ring index is out of range 






status_t EP_GetRxFrameSizeCommon(ep_handle_t *handle, netc_rx_bdr_t *rxBdRing, uint32_t *length)

Common part of get pending frame size API for regular frame or Switch management frame. 

Note
This function is internal used. Please use EP_GetRxFrameSize() or SWT_GetRxFrameSize() API.


Parameters:

handle – 
rxBdRing – Rx BD ring handle 
length – The length of the valid frame received. 


Returns:
status_t 






status_t EP_GetRxFrameSize(ep_handle_t *handle, uint8_t ring, uint32_t *length)

Gets the size of the pending frame in the specified receive ring buffer. 

Note
Frame size without FCS


Parameters:

handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init. 
ring – The ring index 
length – The length of the valid frame received. 


Returns:
kStatus_Success Successfully get the length of a regular frame 

Returns:
kStatus_NETC_RxHRNotZeroFrame Frame in Rx BD ring is management frame, need call SWT_GetRxFrameSize() to get frame size 

Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response 

Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty 

Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped 

Returns:
kStatus_InvalidArgument Rx BD ring index is out of range 






struct _ep_tx_offload


Public Members


bool lso

Large send offload. 




bool l4Checksum

L4 checksum offload. 




bool ipv4Checksum

IPv4 checksum offload. 




uint32_t lsoMaxSegSize

Large send offload maximum segment size. 




uint32_t l4Type

L4 type. 1-UDP, 2-TCP. 




uint32_t l3Type

L3 type. 0-IPv4, 1-IPv6. 




uint32_t l3HeaderSize

L3 IP header size in units of 32-bit words. 




uint32_t l3Start

Offset of the IPv4/IPv6 header in units of bytes. 







struct _ep_tx_opt


Public Members


uint32_t flags

A bitmask of ep_tx_opt_flags 




uint32_t timestamp

Departure timestamp, used if kEP_TX_OPT_START_TIME is set 




netc_enetc_vlan_tag_t vlan

VLAN tag which will be inserted, used if kEP_TX_OPT_VLAN_INSERT is set 







Hardware layer#


enum _netc_hw_enetc_idx

ENETC index enumerator. 
Values:


enumerator kNETC_ENETC0

ENETC hardware 0 




enumerator kNETC_ENETC1

ENETC hardware 0 






enum _netc_hw_switch_idx

SWITCH index enumerator. 
Values:


enumerator kNETC_SWITCH0

SWITCH hardware 0 






enum _netc_hw_port_idx

Port Resource for the NETC module. 
Values:


enumerator kNETC_ENETC0Port

MAC port for ENETC0 




enumerator kNETC_ENETC1Port

Pseudo MAC port for ENETC1 




enumerator kNETC_SWITCH0Port0

MAC port0 for SWITCH 




enumerator kNETC_SWITCH0Port1

MAC port1 for SWITCH 




enumerator kNETC_SWITCH0Port2

MAC port2 for SWITCH 




enumerator kNETC_SWITCH0Port3

MAC port3 for SWITCH 




enumerator kNETC_SWITCH0Port4

Pseudo port4 for SWITCH 






enum _netc_hw_tc_idx

Traffic class enumerator. 
Values:


enumerator kNETC_TxTC4

Traffic class 4 




enumerator kNETC_TxTC5

Traffic class 5 




enumerator kNETC_TxTC6

Traffic class 6 




enumerator kNETC_TxTC7

Traffic class 7 




enumerator kNETC_TxTC0

Traffic class 0 




enumerator kNETC_TxTC1

Traffic class 1 




enumerator kNETC_TxTC2

Traffic class 2 




enumerator kNETC_TxTC3

Traffic class 3 






enum _netc_hw_bdr_idx

Enumeration for the ENETC SI BDR identifier. 
Values:


enumerator kNETC_BDR0





enumerator kNETC_BDR1





enumerator kNETC_BDR2





enumerator kNETC_BDR3





enumerator kNETC_BDR4





enumerator kNETC_BDR5





enumerator kNETC_BDR6





enumerator kNETC_BDR7





enumerator kNETC_BDR8





enumerator kNETC_BDR9





enumerator kNETC_BDR10





enumerator kNETC_BDR11





enumerator kNETC_BDR12





enumerator kNETC_BDR13







enum _netc_hw_swt_cbdr_idx

Switch command BD ring index enumerator. 
Values:


enumerator kNETC_SWTCBDR0

Switch command BD ring 0 




enumerator kNETC_SWTCBDR1

Switch command BD ring 1 






enum _netc_hw_classs_queue_idx

Enumerator for ETM class queue identifier. 
Values:


enumerator kNETC_ClassQueue0

ETM Class Queue 0 




enumerator kNETC_ClassQueue1

ETM Class Queue 1 




enumerator kNETC_ClassQueue2

ETM Class Queue 2 




enumerator kNETC_ClassQueue3

ETM Class Queue 3 




enumerator kNETC_ClassQueue4

ETM Class Queue 4 




enumerator kNETC_ClassQueue5

ETM Class Queue 5 




enumerator kNETC_ClassQueue6

ETM Class Queue 6 




enumerator kNETC_ClassQueue7

ETM Class Queue 7 






enum _netc_hw_congestion_group_idx

Enumerator for the ETM congestion group. 
Values:


enumerator kNETC_CongGroup0





enumerator kNETC_CongGroup1







enum _netc_hw_mii_mode

Defines the MII/RGMII mode for data interface between the MAC and the PHY. 
Values:


enumerator kNETC_XgmiiMode

XGMII mode for data interface. 




enumerator kNETC_MiiMode

MII mode for data interface. 




enumerator kNETC_GmiiMode

GMII mode for data interface. 




enumerator kNETC_RmiiMode

RMII mode for data interface. 




enumerator kNETC_RgmiiMode

RGMII mode for data interface. 




enumerator kNETC_SgmiiMode

SGMII mode for data interface. 






enum _netc_hw_mii_speed

Defines the speed for the *MII data interface. 
Values:


enumerator kNETC_MiiSpeed10M

Speed 10 Mbps. 




enumerator kNETC_MiiSpeed100M

Speed 100 Mbps. 




enumerator kNETC_MiiSpeed1000M

Speed 1000 Mbps. 




enumerator kNETC_MiiSpeed2500M

Speed 2500 Mbps. 




enumerator kNETC_MiiSpeed5G

Speed 5Gbps. 




enumerator kNETC_MiiSpeed10G

Speed 10Gbps Mbps. 






enum _netc_hw_mii_duplex

Defines the half or full duplex for the MII data interface. 
Values:


enumerator kNETC_MiiHalfDuplex

Half duplex mode. 




enumerator kNETC_MiiFullDuplex

Full duplex mode. 






typedef enum _netc_hw_enetc_idx netc_hw_enetc_idx_t

ENETC index enumerator. 




typedef enum _netc_hw_switch_idx netc_hw_switch_idx_t

SWITCH index enumerator. 




typedef enum _netc_hw_port_idx netc_hw_port_idx_t

Port Resource for the NETC module. 




typedef enum _netc_hw_tc_idx netc_hw_tc_idx_t

Traffic class enumerator. 




typedef enum _netc_hw_bdr_idx netc_hw_bdr_idx_t

Enumeration for the ENETC SI BDR identifier. 




typedef enum _netc_hw_swt_cbdr_idx netc_hw_swt_cbdr_idx_t

Switch command BD ring index enumerator. 




typedef enum _netc_hw_classs_queue_idx netc_hw_etm_class_queue_idx_t

Enumerator for ETM class queue identifier. 




typedef enum _netc_hw_congestion_group_idx netc_hw_congestion_group_idx_t

Enumerator for the ETM congestion group. 




typedef enum _netc_hw_mii_mode netc_hw_mii_mode_t

Defines the MII/RGMII mode for data interface between the MAC and the PHY. 




typedef enum _netc_hw_mii_speed netc_hw_mii_speed_t

Defines the speed for the *MII data interface. 




typedef enum _netc_hw_mii_duplex netc_hw_mii_duplex_t

Defines the half or full duplex for the MII data interface. 




typedef struct _netc_psfp_kc_profile netc_isi_kc_rule_t

NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes. 




typedef struct _netc_vlan_classify_config netc_vlan_classify_config_t

NETC Vlan classification config. 




typedef struct _netc_qos_classify_profile netc_qos_classify_profile_t

NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map) 




typedef struct _netc_ipf_config netc_ipf_config_t

NETC Ingress Filter config. 




typedef struct _netc_func netc_func_t

Register groups for the PCIe function. 




typedef struct _netc_port_hw netc_port_hw_t

Register groups for the Port/Link hardware. 




typedef struct _netc_enetc_hw netc_enetc_hw_t

Register group for the ENETC peripheral hardware. 




typedef struct _netc_timer_hw netc_timer_hw_t

Register group for the Timer peripheral hardware. 




typedef struct _netc_mdio_hw netc_mdio_hw_t

Register group for both EMDIO and port external MDIO. 




getSiInstance(si)

Get SI information from netc_hw_si_idx_t. 
The ENETC instance of this SI. 




getSiIdx(si)

The actaul index in the netc_hw_si_idx_t. 




NETC_MSIX_TABLE_OFFSET

MSIX table address offset. 




NETC_MSIX_TABLE_PBA_OFFSET

MSIX PBA address offset. 




NETC_NANOSECOND_ONE_SECOND

Nanosecond in one second. 




struct _netc_psfp_kc_profile


#include <fsl_netc.h>
NETC PSFP kc profile configuration, the key size (not include the spmp and portp) is up to 16 bytes. 

Public Members


bool etp

2 Byte Ethertype field present in the key 




bool sqtp

1 Byte Sequence Tag present in the key 




bool ipcpp

inner VLAN header’s PCP field present in the key 




bool ividp

inner VLAN ID present in the key 




bool opcpp

outer VLAN header’s PCP field present in the key 




bool ovidp

outer VLAN ID present in the key 




bool smacp

6 bytes of source MAC address present in the key 




bool dmacp

6 bytes of destination MAC address present in the key 




bool spmp

switch port masquerading flag present in the key 




bool portp

source port present in the key 




bool valid

Key Construction is valid 







struct _netc_vlan_classify_config


#include <fsl_netc.h>
NETC Vlan classification config. 

Public Members


bool enableCustom1

Enable/Disable custom0 ether type 




uint16_t custom1EtherType

Ethertype 




bool enableCustom2

Enable/Disable custom0 ether type 




uint16_t custom2EtherType

Ethertype 




uint16_t preStandRTAGType

802.1CB draft 2.0 R-TAG Ethertype value. PSRTAGETR. Only applicable for switch 







struct _netc_qos_classify_profile


#include <fsl_netc.h>
NETC Qos Classification profile file (vlan PCP/DEI to IPV/DR map) 

Public Members


uint8_t ipv[16]

Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped IPV for Qos. 




uint8_t dr[16]

Index is created from PCP (3 bits) + DEI (1 bit) field. Value is the mapped DR for QoS. 







struct _netc_ipf_config


#include <fsl_netc.h>
NETC Ingress Filter config. 

Public Members


bool l2DiscardMCSmac

DOSL2CR. Discard received frames with Multicast SMAC address 




bool l2DiscardSmacEquDmac

DOSL2CR. Discard received frames with SMAC = DMAC 




bool l3DiscardSipEquDip

DOSL3CR. Discard IPV3/IPV6 source address == destination address 







struct _netc_func


#include <fsl_netc_hw.h>
Register groups for the PCIe function. 




struct _netc_port_hw


#include <fsl_netc_hw.h>
Register groups for the Port/Link hardware. 

Public Members


NETC_PORT_Type *port

Port Address 







struct _netc_enetc_hw


#include <fsl_netc_hw.h>
Register group for the ENETC peripheral hardware. 

Public Members


netc_func_t func

PCIE function register 




NETC_ENETC_Type *base

Base register of ENETC module 




NETC_SW_ENETC_Type *common

Common register of ENETC module 




netc_port_hw_t portGroup

Port register group 




ENETC_GLOBAL_Type *global

Global NETC address 




ENETC_SI_Type *si

Station Interfce for the P/V SI 




netc_msix_entry_t *msixTable

MSIX table address 







struct _netc_timer_hw


#include <fsl_netc_hw.h>
Register group for the Timer peripheral hardware. 

Public Members


ENETC_PCI_TYPE0_Type *func

PCIE function register 




ENETC_PF_TMR_Type *base

Base register address for timer module 




ENETC_GLOBAL_Type *global

Global NETC register address 




netc_msix_entry_t *msixTable

MSIX table address 







struct _netc_mdio_hw


#include <fsl_netc_hw.h>
Register group for both EMDIO and port external MDIO. 

Public Members


__IO uint32_t EMDIO_CFG
External MDIO configuration register, offset: 0x1C00 




__IO uint32_t EMDIO_CTL
External MDIO interface control register, offset: 0x1C04 




__IO uint32_t EMDIO_DATA
External MDIO interface data register, offset: 0x1C08 




__IO uint32_t EMDIO_ADDR
External MDIO register address register, offset: 0x1C0C 




__I uint32_t EMDIO_STAT
External MDIO status register, offset: 0x1C10 




__IO uint32_t PHY_STATUS_CFG
PHY status configuration register, offset: 0x1C20 




__IO uint32_t PHY_STATUS_CTL
PHY status control register, offset: 0x1C24 




__I uint32_t PHY_STATUS_DATA
PHY status data register, offset: 0x1C28 




__IO uint32_t PHY_STATUS_ADDR
PHY status register address register, offset: 0x1C2C 




__IO uint32_t PHY_STATUS_EVENT
PHY status event register, offset: 0x1C30 




__IO uint32_t PHY_STATUS_MASK
PHY status mask register, offset: 0x1C34 







struct payload


Public Members


uint8_t lbMask

Payload Last Byte Mask 




uint8_t fbMask

Payload First Byte Mask 




uint8_t byteOffset

Payload Byte Offset where field extraction begins 




uint8_t numBytes

Specify the size (numBytes + 1) of the payload key field 




uint8_t pfp

Payload field Present 







union __unnamed191__


Public Members


ENETC_PCI_TYPE0_Type *pf

PSI function 




ENETC_VF_PCI_TYPE0_Type *vf

VSI function 







union __unnamed193__


Public Members


NETC_ETH_LINK_Type *eth

MAC Port Address 







Hardware Common Functions#


static inline uint16_t EP_IncreaseIndex(uint16_t index, uint32_t max)





uint16_t NETC_SIGetVsiIndex(netc_vsi_number_t vsi)

Get the VSI index. 

Parameters:

vsi – The VSI number. 







static inline void NETC_IPFInit(NETC_SW_ENETC_Type *base, const netc_ipf_config_t *config)

Set layer2/3 Dos configuration. 

Parameters:

base – 
config – 







void NETC_PSFPKcProfileInit(NETC_SW_ENETC_Type *base, const netc_isi_kc_rule_t *rule, bool enKcPair1)

Initialize the Ingress Stream Identification Key construction rule profiles. 

Parameters:

base – 
rule – 
enKcPair1 – 


Returns:
void 






void NETC_RxVlanCInit(NETC_SW_ENETC_Type *base, const netc_vlan_classify_config_t *config, bool enRtag)

Initialize the customer vlan type. 

Parameters:

base – 
config – 
enRtag – 


Returns:
void 






void NETC_RxQosCInit(NETC_SW_ENETC_Type *base, const netc_qos_classify_profile_t *profile, bool enProfile1)

Initialize the ingress QoS classification. 

Parameters:

base – 
profile – 
enProfile1 – 







Hardware ENETC#


typedef struct _netc_enetc_vlan_tag_t netc_enetc_vlan_tag_t

ENETC Port outer/inner VLAN tag. 




typedef struct _netc_enetc_discard_statistic netc_enetc_port_discard_statistic_t

PORT discard count statistic. 




typedef struct _netc_enetc_native_vlan_config_t netc_enetc_native_vlan_config_t

ENETC Port outer/inner native VLAN config. 




typedef struct _netc_enetc_parser_config_t netc_enetc_parser_config_t

ENETC parser configuration. 




typedef struct _netc_enetc_cap netc_enetc_cap_t

ENETC capability. 




static inline bool NETC_EnetcHasManagement(NETC_ENETC_Type *base)

Check whether ENETC has switch management capability. 

Parameters:

base – NETC peripheral base address. 


Returns:
true or false 






void NETC_EnetcGetCapability(NETC_ENETC_Type *base, netc_enetc_cap_t *capability)

Get ENETC capability. 

Parameters:

base – NETC peripheral base address. 
capability – Pointer to capability structure. 







void NETC_EnetcSetSIMacAddr(NETC_ENETC_Type *base, uint8_t si, uint8_t *macAddr)

Set MAC address for specified VSI of ENETC. 

Parameters:

base – 
macAddr – 







status_t NETC_EnetcConfigureSI(NETC_ENETC_Type *base, uint8_t si, const netc_hw_enetc_si_config_t *psConfig)

Configure SI. 

Parameters:

base – ENETC peripheral base address. 
si – The SI number 
psConfig – The SI configuration 


Returns:
status_t 






status_t NETC_EnetcSetMsixEntryNum(NETC_ENETC_Type *base, uint8_t si, uint32_t msixNum)

Set SI MSIX table entry number. 

Parameters:

base – ENETC peripheral base address. 
si – The SI number. 
msixNum – The MSIX table entry number. 


Returns:
status_t 






static inline void NETC_EnetcEnableSI(NETC_ENETC_Type *base, uint8_t si, bool enable)

Enable/Disable specified SI. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
enable – Enable/Disable SI from ENETC layer. 







void NETC_EnetcGetPortDiscardStatistic(NETC_ENETC_Type *base, netc_enetc_port_discard_statistic_t *statistic)

Get ENETC discard statistic data. 

Parameters:

base – ENETC peripheral base address. 
statistic – Statistic data. 







void NETC_EnetcEnablePromiscuous(NETC_ENETC_Type *base, uint8_t si, bool enableUCPromis, bool enableMCPromis)

Enable MAC promiscuous mode. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
enableUCPromis – Enable unicast frame promiscuous. 
enableMCPromis – Enable multicast frame promiscuous. 







void NETC_EnetcConfigureVlanFilter(NETC_ENETC_Type *base, uint8_t si, netc_si_l2vf_config_t *config)

Configure VLAN filter. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
config – Enable untagged VLAN frame promiscuous. 







void NETC_EnetcAddMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)

Add the hash filter for the MAC address. 
Hardware layer will not maitain the counter of the hash filter. API layer shall cover this requirement.

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
type – Unicast or multicast frame type. 
hashIndex – The calculated hash index of MAC address. 







void NETC_EnetcDelMacAddrHash(NETC_ENETC_Type *base, uint8_t si, netc_packet_type_t type, uint8_t hashIndex)

Remove the hash filter for the MAC address. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
type – Unicast or multicast frame type. 
hashIndex – The calculated hash index of MAC address. 







void NETC_EnetcAddVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)

Add the hash filter for the VLAN. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
hashIndex – The calculated hash index of MAC address. 







void NETC_EnetcDelVlanHash(NETC_ENETC_Type *base, uint8_t si, uint8_t hashIndex)

Remove the hash filter for the VLAN. 

Parameters:

base – ENETC peripheral base address. 
si – SI index. 
hashIndex – The calculated hash index of MAC address. 







static inline status_t NETC_EnetcPortEnableTSD(NETC_ENETC_Type *base, netc_hw_tc_idx_t tcIdx, bool isEnable)

Enable / Disable ENETC Port Time Specific Departure (TSD) feature. 
It can’t work with QBV CBS

Parameters:

base – 
tcIdx – 
isEnable – 


Returns:
status_t 






static inline void NETC_EnetcPortSetNativeVLAN(NETC_ENETC_Type *base, const netc_enetc_native_vlan_config_t *config, bool isOuter)

Set ENETC Rx native outer/inner VLAN. 
It is used for classification when untagged frames are received by the port.

Parameters:

base – 
config – 
isOunter – 







static inline void NETC_EnetcSetParser(NETC_ENETC_Type *base, const netc_enetc_parser_config_t *config)

Set ENETC Parser configuration. 
PARCSCR and PARCE0CR - PARCE3CR.

Parameters:

base – 
config – 







static inline void NETC_EnetcEnableWakeOnLan(NETC_ENETC_Type *base, bool isEnable)

Enable / Disable ENETC Wake-on-LAN mode. 
Only available on ENETC 0

Parameters:

base – 
isEnable – 


Returns:
status_t 






struct _netc_enetc_vlan_tag_t


#include <fsl_netc.h>
ENETC Port outer/inner VLAN tag. 

Public Members


uint16_t pcp

Priority code point 




uint16_t dei

Drop eligible indicator 




uint16_t vid

VLAN identifier 




netc_vlan_tpid_select_t tpid

Tag protocol identifier 







struct _netc_enetc_discard_statistic


#include <fsl_netc.h>
PORT discard count statistic. 

Public Members


uint32_t ingressDR[4]

Discard count for port ingress congestion different DR 




uint32_t broadcastReject

Broadcast frame drops count due to all SI enable broadcast reject 




uint32_t smacPruning

Frames discard count due to port MAC source address pruning 




uint32_t unicastMacFilt

Unicast frame discard count due to port MAC filtering 




uint32_t multicastMacFilt

Multicast frame discard count due to MAC filtering 




uint32_t unicastVlanFilt

Unicast frame discard count due to VLAN filtering 




uint32_t multicastVlanFilt

Multicast frame discard count due to VLAN filtering 




uint32_t boradcastVlanFilt

Broadcast frame discard count due to VLAN filtering 







struct _netc_enetc_native_vlan_config_t


#include <fsl_netc.h>
ENETC Port outer/inner native VLAN config. 

Public Members


bool enUnderZeroVid

Enable use the port default VLAN VID when the VID in the packet’s is zero 




bool enUnderNoVlan

Enable use the port default VLAN VID when the VLAN tag is not present 




netc_enetc_vlan_tag_t vlanTag

Port native outer/inner VLAN tag, valid when enUnderZeroVid or enUnderNoVlan is true 







struct _netc_enetc_parser_config_t


#include <fsl_netc.h>
ENETC parser configuration. 

Public Members


bool disL3Checksum

Disable Layer 3 IPv4 Header checksum validation. 




bool disL4Checksum

Disable Layer 4 TCP and UDP checksum validation. 







struct _netc_enetc_cap


#include <fsl_netc_hw_enetc.h>
ENETC capability. 

Public Members


bool funcSafety

Support for safety capability. 




bool wol

Support for Wake-on-LAN in low-power mode. 




bool rss

Support for RSS. 




bool tsd

Support for time specific departure. 




bool rfs

Support for RFS. 




uint32_t ipvNum

IPV number. 




uint32_t vsiNum

VSI number. 




uint32_t msixNum

MSIX table vector/entry number. 




uint32_t tcsNum

Traffic class number. 




uint16_t uchNum

Unicast hash entry number. 




uint16_t mchNum

Multicast hash entry number. 




uint16_t rxBdrNum

Rx BD ring number. 




uint16_t txBdrNum

Tx BD ring number. 







struct custEtype


Public Members


uint16_t etype

Custom Ethertype value. Upon detecting this ether type the associated code point will be mapped to the parse summary as a Non IP code point. 




bool en

Enables the detection and mapping. 




uint8_t cp

This value is mapped to the parse summary as a Non IP code point. 







Hardware Port#


enum _netc_port_tgsl_status

Port time gate scheduling gate list status. 
Values:


enumerator kNETC_OperListActive

Port operational gate control list is active. 




enumerator kNETC_AdminListPending

Administrative gate control list is pending (configured but not installed yet). 






enum _netc_port_discard_tpye

Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function. 
Values:


enumerator kNETC_RxDiscard

Discarded frames in the receive port datapath processing pipeline. 




enumerator kNETC_TxDiscard

Discarded frames in the egress datapath processing pipeline, only for switch. 




enumerator kNETC_BridgeDiscard

Discarded frames in the bridge forwarding processing function, only for switch. 






enum _netc_port_tpidlist

Defines Port TPID acceptance. 
Values:


enumerator kNETC_OuterStanCvlan

Accept outer Standard C-VLAN 0x8100. 




enumerator kNETC_OuterStanSvlan

Accept outer Standard S-VLAN 0x88A8. 




enumerator kNETC_OuterCustomVlan1

Accept outer Custom VLAN as defined by CVLANR1[ETYPE]. 




enumerator kNETC_OuterCustomVlan2

Accept outer Custom VLAN as defined by CVLANR2[ETYPE]. 




enumerator kNETC_InnerStanCvlan

Accept inner Standard C-VLAN 0x8100. 




enumerator kNETC_InnerStanSvlan

Accept inner Standard S-VLAN 0x88A8. 




enumerator kNETC_InnerCustomVlan1

Accept inner Custom VLAN as defined by CVLANR1[ETYPE]. 




enumerator kNETC_InnerCustomVlan2

Accept inner Custom VLAN as defined by CVLANR2[ETYPE]. 






enum _netc_port_ts_select

Defines port timestamp selection. 
Values:


enumerator kNETC_SyncTime

Synchronized time. 




enumerator kNETC_FreeRunningTime

Free running time. 






enum _netc_hw_preemption_mode

Port MAC preemption mode. 
Values:


enumerator kNETC_PreemptDisable

Frame preemption is not enabled 




enumerator kNETC_PreemptOn64B

Frame preemption is enabled, but transmit only preempts frames on 64B boundaries 




enumerator kNETC_PreemptOn4B

Frame preemption is enabled, but transmit only preempts frames on 4B boundaries 






enum _netc_hw_raf_size

Port MAC Remote Additional Fragment Size. 
Values:


enumerator kNETC_RafSize64

Additional Fragment Size of 64 octets 




enumerator kNETC_RafSize128

Additional Fragment Size of 128 octets 




enumerator kNETC_RafSize256

Additional Fragment Size of 256 octets 




enumerator kNETC_RafSize512

Additional Fragment Size of 512 octets 






enum _netc_tc_sdu_type

Type of PDU/SDU (Protocol/Service Data Unit). 

Note
Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:

PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes
MPDU = add rxMacsecBco/txMacsecBco bytes
MSDU = minus 16B (12B MAC Header + 4B FCS) 



Values:


enumerator kNETC_PDU

Physical Layer PDU, Preamble, IFG, SFD along with MPDU. Not supported if cut-through frames are expected 




enumerator kNETC_MPDU

MAC PDU, MAC Header, MSDU and FCS 




enumerator kNETC_MSDU

MAC SDU, MPDU minus 12B MAC Header and 4B FCS. Not supported if cut-through frames are expected 






enum _netc_port_sg_ogc_mode

Defines the Port’s Stream Gate Open Gate Check mode. 
Values:


enumerator kNETC_SGCheckSFD

Check whether frame SFD is within the open gate interval. 




enumerator kNETC_SGCheckEntire

Check whether the entire frame is within the open gate interval. 






enum _netc_port_intr_flags

Values:


enumerator kNETC_TxEmptyFlag

Tx FIFO empty flag. 




enumerator kNETC_RxEmptyFlag

Rx FIFO empty flag. 




enumerator kNETC_TxOverflowFlag

Tx overflow flag. 




enumerator kNETC_TxUnderflowFlag

Tx underflow flag. 




enumerator kNETC_RxOverflowFlag

Rx overflow flag. 




enumerator kNETC_MagicPacketFlag

Magic packet detection indication flag. 




enumerator kNETC_TxClkStopFlag

Tx clock stop detection flag. 




enumerator kNETC_RxClkStopFlag

Rx clock stop detection flag. 




enumerator kNETC_SpeedDuplexChangeFlag

Speed/Duplex Change flag 




enumerator kNETC_MacMergeSMDErrFlag

MAC merge frame SMD error received event flag 




enumerator kNETC_MacMergeAssemblyErrFlag

MAC merge frame assembly error event flag 






enum _netc_port_loopback_mode_t

Defines the port MAC frame loopback mode. 
Values:


enumerator kNETC_PortLpbWithExtTxClk

Port MAC frame loopback with external Tx clock. 




enumerator kNETC_PortLpbWithIntTxClk

Port MAC frame loopback with internal Tx clock. 






typedef enum _netc_port_tgsl_status netc_port_tgsl_status_t

Port time gate scheduling gate list status. 




typedef enum _netc_port_discard_tpye netc_port_discard_tpye_t

Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function. 




typedef enum _netc_port_tpidlist netc_port_tpidlist_t

Defines Port TPID acceptance. 




typedef enum _netc_port_ts_select netc_port_ts_select_t

Defines port timestamp selection. 




typedef struct _netc_port_qos_mode netc_port_qos_mode_t

Port Qos mode. 




typedef struct _netc_port_parser_config netc_port_parser_config_t

Port Parser config. 




typedef struct _netc_port_tg_config netc_port_tg_config_t

Port time gate config. 




typedef struct _netc_port_tg_preemption_config netc_port_tg_preemption_config

Port time gate config when used with Frame Preemption. 




typedef enum _netc_hw_preemption_mode netc_hw_preemption_mode_t

Port MAC preemption mode. 




typedef enum _netc_hw_raf_size netc_hw_raf_size_t

Port MAC Remote Additional Fragment Size. 




typedef struct _netc_port_preemption_config netc_port_preemption_config

Frame Preemption Portconfig. 




typedef struct _netc_port_tc_cbs_config netc_port_tc_cbs_config_t

Configuration for the Credit Based Shaped for port TC. 

Note
The 802.1Qav bandwidth availability parameters is is calculated as follows:

idleSlope (bits) = portTxRate * bwWeight / 100
sendSlope (bits) = portTxRate * (100 - bwWeight) / 100
lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100
hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.
hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits) 







typedef enum _netc_tc_sdu_type netc_tc_sdu_type_t

Type of PDU/SDU (Protocol/Service Data Unit). 

Note
Overhead values which adding to the transmitted frame of Length are specified by Port SDU config as follows:

PPDU = add rxPpduBco/txPpduBco + rxMacsecBco/txMacsecBco bytes
MPDU = add rxMacsecBco/txMacsecBco bytes
MSDU = minus 16B (12B MAC Header + 4B FCS) 







typedef struct _netc_port_tc_sdu_config netc_port_tc_sdu_config_t





typedef struct _netc_port_tx_tc_config netc_port_tx_tc_config_t

Configuration for the port Tx Traffic Class. 




typedef struct _netc_port_discard_statistic netc_port_discard_statistic_t

Switch or ENETC port Tx/Rx/Bridge discard statistic / reason. 




typedef struct _netc_port_vlan_classify_config netc_port_vlan_classify_config_t

Port accepted Vlan classification config. 




typedef struct _netc_port_qos_classify_configs netc_port_qos_classify_config_t

Port Qos Classification Config. 




typedef struct _netc_port_ipf_config_t netc_port_ipf_config_t

Port Ingress Filter Config. 




typedef struct _netc_port_psfp_isi_config netc_port_psfp_isi_config

PSFP port config. 
Port ingress stream identification config

Note
The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows

RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID
RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID
RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID 







typedef struct _netc_port_ethmac netc_port_ethmac_t





typedef enum _netc_port_sg_ogc_mode netc_port_sg_ogc_mode_t

Defines the Port’s Stream Gate Open Gate Check mode. 




typedef struct _netc_port_common netc_port_common_t

Port common configuration. 




typedef enum _netc_port_intr_flags netc_port_intr_flags_t





typedef enum _netc_port_loopback_mode_t netc_port_loopback_mode_t

Defines the port MAC frame loopback mode. 




status_t NETC_PortConfig(NETC_PORT_Type *base, const netc_port_common_t *config)

Configure specified PORT. 

Parameters:

base – NETC port module base address. 
config – Port configuration structure. 


Returns:
status_t 






void NETC_PortSetMacAddr(NETC_PORT_Type *base, const uint8_t *macAddr)

Set the MAC address. 

Parameters:

handle – 
macAddr – 







bool NETC_PortIsPseudo(NETC_PORT_Type *base)

Check whether this port a pseudo MAC port. 

Parameters:

base – PORT peripheral base address. 







void NETC_PortGetDiscardStatistic(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, netc_port_discard_statistic_t *statistic)

Get specified PORT discard counter. 

Parameters:

base – NETC port module base address. 
discardType – Port discard type. 
statistic – pointer to the statistic data 







void NETC_PortClearDiscardReason(NETC_PORT_Type *base, netc_port_discard_tpye_t discardType, uint32_t reason0, uint32_t reason1)

Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons. 

Parameters:

base – NETC port module base address. 
discardType – Port discard type. 
reason0 – 
reason1 – 







static inline uint32_t NETC_PortGetTGSListStatus(NETC_PORT_Type *base)

Get port time gate scheduling gate list status. 

Parameters:

base – NETC port module base address. 


Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t






void NETC_PortEthMacGracefulStop(NETC_PORT_Type *base)

Do graceful stop for Port Ethernet MAC receive/transmit. 

Parameters:

base – NETC port module base address. 







static inline void NETC_PortSetSpeed(NETC_PORT_Type *base, uint16_t pSpeed)

Set port speed. 

Parameters:

base – NETC port module base address. 
pSpeed – Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable. 







NETC_PORT_MIN_FRAME_SIZE

The port supported minimum/maximum frame size. 




NETC_PORT_MAX_FRAME_SIZE





struct _netc_port_qos_mode


#include <fsl_netc.h>
Port Qos mode. 

Public Members


uint8_t qosVlanMap

Transmit QoS to VLAN PCP Mapping Profile index, only active on switch port 




uint8_t vlanQosMap

Receive VLAN PCP/DE to QoS Mapping Profile index, only active on switch port 




uint8_t defaultIpv

Port default IPV 




uint8_t defaultDr

Port default DR 




bool enVlanInfo

Enable use VLAN info to determine IPV and DR (base on VLANIPVMPaR0/1 and VLANDRMPaR) 




bool vlanTagSelect

True: Outer VLAN, False: Innner VLAN. Active when enVlanInfo is true 







struct _netc_port_parser_config


#include <fsl_netc.h>
Port Parser config. 

Public Members


uint8_t l2PloadCount

L2 payload fields size in bytes 




bool enableL3Parser

Enable/Disable parser for L3 




uint8_t l3PayloadCount

L3 payload fields size in bytes 




bool enableL4Parser

Enable/Disable parser for L4 




uint8_t l4PayloadCount

L4 payload fields size in bytes 







struct _netc_port_tg_config


#include <fsl_netc.h>
Port time gate config. 

Public Members


uint16_t advOffset

Advance time offset in ns. 




uint32_t holdSkew

Hold-Skew in ns, not effective on ports connected to a pseudo-MAC 







struct _netc_port_tg_preemption_config


#include <fsl_netc.h>
Port time gate config when used with Frame Preemption. 

Public Members


uint16_t holdAdvance

the amount of time in ns prior to the Set-And-Hold-MAC time slot for asserting a Hold request. Used with frame Preemption. 




uint16_t releaseAdvance

the amount of time in ns prior to the Set-And-Release-MAC time slot for asserting a Release request. Used with Frame Preemption. 







struct _netc_port_preemption_config


#include <fsl_netc.h>
Frame Preemption Portconfig. 

Public Members


bool enMergeVerify

Enable verify the merged preemption frame, need to enable when preemptMode is not zero 




uint8_t mergeVerifyTime

The nominal wait time between verification attempts in milliseconds, range in 1 ~ 128 




netc_hw_preemption_mode_t preemptMode

When set to not zero, PMAC frames may be preempted by EMAC frames 




netc_hw_raf_size_t raf_size

Additional Fragment Size. Indicates the smallest sized fragments that can be sent on Tx 




bool PreemptionActive

Local preemption active. Indicates whether preemption is active for this port. This bit will be set if preemption is both enabled and has completed the verification process 







struct _netc_port_tc_cbs_config


#include <fsl_netc.h>
Configuration for the Credit Based Shaped for port TC. 

Note
The 802.1Qav bandwidth availability parameters is is calculated as follows:

idleSlope (bits) = portTxRate * bwWeight / 100
sendSlope (bits) = portTxRate * (100 - bwWeight) / 100
lowCredit (bits) = tcMaxFrameSize * (100 - bwWeight) / 100
hiCredit (bits) calculation formula depends on the traffic class, Please refer to the Reference manual.
hiCredit (credits) = (enetClockFrequency / portTxRate) * 100 * hiCredit (bits) 




Public Members


uint8_t bwWeight

Percentage units of the port transmit rate and the credit-based shaper (range from 0 ~ 100), the sum of all traffic class credit-based shaper’s bandwidth cannot exceed 100 




uint32_t hiCredit

The maximum allowed accumulation of credits when conflicting transfers occur, in credit units ((enetClockFrequency / portTxRate) * 100) 







struct _netc_port_tc_sdu_config


Public Members


bool enTxMaxSduCheck

Enable Tx Max SDU check for Store and Forward frames, the frame which greater than maxSduSized wiil be discarded, Cut-Through frames will always perform Max SDU check 




netc_tc_sdu_type_t sduType

Specifies the type of PDU/SDU whose length is being validated as seen on the link 




uint16_t maxSduSized

Transmit Maximum SDU size in bytes, the dequeued frame will be discarded when it SDU size exceeds this value 







struct _netc_port_tx_tc_config


#include <fsl_netc.h>
Configuration for the port Tx Traffic Class. 

Public Members


bool enPreemption

Frames from traffic class are transmitted on the preemptable MAC, not supported on internal port (ENETC 1 port and Switch port 4) 




bool enTcGate

Enable the traffic class gate when no gate control list is operational, or when time gate scheduling is disabled. 




bool enableTsd

Enable Time Specific Departure traffic class, only applicable to ENETC 




bool enableCbs

Enable Credit based shaper for traffic class 




netc_port_tc_cbs_config_t cbsCfg

Configure transmit traffic class credit based shaper (PTC0CBSR0/PTC0CBSR1) if enableCbs set to ture 







struct _netc_port_discard_statistic


#include <fsl_netc.h>
Switch or ENETC port Tx/Rx/Bridge discard statistic / reason. 

Public Members


uint32_t count

Count of discarded frames. PRXDCR, PTXDCR or BPDCR. 




uint32_t reason0

Discard Reason. Find bit detail from PT/RXDCRR0 or BPDCRR0. 




uint32_t reason1

Discard Reason. Find bit detail from PT/RXDCRR1 or BPDCRR1. 







struct _netc_port_vlan_classify_config


#include <fsl_netc.h>
Port accepted Vlan classification config. 

Public Members


uint8_t innerMask

Bitmap identifying which TPIDs are acceptable as Inner VLAN tag. See PTAR 




uint8_t outerMask

Bitmap identifying which TPIDs are acceptable as Outter VLAN tag. See PTAR 







struct _netc_port_qos_classify_configs


#include <fsl_netc.h>
Port Qos Classification Config. 

Public Members


uint8_t vlanQosMap

Receive VLAN PCP/DE to QoS Mapping Profile index 




uint8_t defaultIpv

Port default IPV 




uint8_t defaultDr

Port default DR 




bool enVlanInfo

Enable use VLAN info to determine IPV and DR ,base on VLAN to IPV map (VLANIPVMPaR0/1) and VLAN to DR map (VLANDRMPaR) 




bool vlanTagSelect

True: Use received Outer VLAN, False: Use received Innner VLAN. Active when enVlanInfo is true 







struct _netc_port_ipf_config_t


#include <fsl_netc.h>
Port Ingress Filter Config. 

Public Members


bool enL2Dos

Enable port L2 Ethernet DoS Protection 




bool enL3Dos

Enable port L3 IP DoS Protection 




bool enIPFTable

Enable port IPF lookup 







struct _netc_port_psfp_isi_config


#include <fsl_netc.h>
PSFP port config. 
Port ingress stream identification config

Note
The first stream identification find IS_EID has higher precedence value than the second, and the priority of the IS_EID found by the IPF is specified by the IPF entry RRR bit. The possible orderings are as follows

RRR = 00b : IPF > enKC0 > enKC1 > defaultISEID
RRR = 01b : enKC0 > IPF > enKC1 > defaultISEID
RRR = 10b : enKC0 > enKC1 > IPF > defaultISEID 




Public Members


uint16_t defaultISEID

Default Ingress Stream Entry ID, has lower precedence value than ISI entry and IPF entry defined IS_EID. 0xFFFF means NULL 




bool enKC1

Enable do the second stream identification with key construction rule 1 or rule 3 




bool enKC0

Enable do the first stream identification with key construction rule 0 or rule 2 




bool kcPair

Indicates which Key Construction pair to use for this port, false - user pair0. true - use pair1 only applicable for Switch 







struct _netc_port_ethmac


Public Members


bool enableRevMii

Enable RevMII mode. 




netc_port_ts_select_t txTsSelect

Tx timestamp clock source. 




bool isTsPointPhy

True: Timestamp is captured based on PHY SFD detect pulse on Rx and Tx for 2-step timestamping. False: Based on SFD detect at boundary of MAC merge layer and pins/protocol gaskets. 




netc_hw_mii_mode_t miiMode

MII mode. 




netc_hw_mii_speed_t miiSpeed

MII Speed. 




netc_hw_mii_duplex_t miiDuplex

MII duplex. 




bool enTxPad

Enable ETH MAC Tx Padding, which will pad the frame to a minimum of 60 bytes and append 4 octets of FCS. 




uint8_t rxMinFrameSize

Receive Minimum Frame Length size in bytes, range in 18 ~ 64, received frames shorter than 18B are discarded silently. Both for express MAC and preemptable MAC. 




uint16_t rxMaxFrameSize

Receive Maximum Frame Length size in bytes, up to 2000, received frames that exceed this stated maximum are truncated. Both for express MAC and preemptable MAC. 




netc_port_preemption_config PreemptionConfig

Frame Preemption configuration 




bool rgmiiClkStop

True: RGMII transmit clock is stoppable during low power idle. False: It’s not stoppable. 




bool enableHalfDuplexFlowCtrl

Enable/Disable half-duplex flow control. 




uint16_t maxBackPressOn

Maximum amount of time backpressure can stay asserted before stopping to prevent excess defer on link partner, in byte times. 




uint16_t minBackPressOff

Minimum amount of time backpressure will stay off after reaching the ON max, before backpressure can reassert after checking if icm_pause_notification is still or again asserted, in byte times. 




uint32_t txWakeupTimeCycleEEE

Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) required by the PHY to wait before transmitting a new frame after the application has indicated it wants to end the low power state. 




uint32_t txSleepTimeCycleEEE

Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) where Tx is idle before mac transmits low power EEE. A value of 0 does not activate low power EEE transmission. 







struct _netc_port_common


#include <fsl_netc.h>
Port common configuration. 

Public Members


netc_port_vlan_classify_config_t acceptTpid

Port acceptable VLAN tpid configure. 




netc_port_ts_select_t rxTsSelect

Eth MAC Rx or pseudo MAC Tx timestamp clock source 




uint16_t pSpeed

Transmit Port Speed = 10Mbps * (pSpeed+1), Used by ETS, Qbu and to determine if cut-through is permissable 




uint8_t rxMacsecBco

Port receive MACSec byte count overhead which due to MACSec encapsulation 




uint8_t rxPpduBco

Port receive PPDU Byte count overhead which includes IPG, SFD and Preamble 




uint8_t txMacsecBco

Port transmit MACSec byte count overhead which due to MACSec encapsulation 




uint8_t txPpduBco

Port transmit PPDU Byte count overhead which includes IPG, SFD and Preamble 




netc_port_sg_ogc_mode_t ogcMode

Stream Gate Open Gate Check mode, 0b is check whether SFD is within the open gate interval, 1b is check whether the entire frame is within the open gate interval 




uint32_t pDelay

Link propagation delay in ns 




uint8_t macAddr[6]

Port MAC address, used for Switch egress frame modification action or ENETC SI0 primary MAC address 




netc_port_qos_classify_config_t qosMode

Port Rx Qos Classification config 




netc_port_ipf_config_t ipfCfg

Port ingress port filter configuration 




netc_port_tg_config_t timeGate

Port Tx time gate config 




netc_port_parser_config_t parser

Port Rx Parser config 







Hardware Port MAC#


enum _netc_port_phy_mac_type

Defines the Ethernet MAC physical port type. 
Values:


enumerator kNETC_ExpressMAC

The MAC which handles express traffic when frame preemption is enabled or handles all traffic when frame preemption is disabled. 




enumerator kNETC_PreemptableMAC

The MAC which handles preemptive traffic when frame preemption is enabled. 






enum _netc_port_preemption_verify_status

Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016. 
Values:


enumerator kNETC_VerifyDisable

Verification is disabled 




enumerator kNETC_VerifyInProgress

Verification is in progress 




enumerator kNETC_VerifySuccess

Verification was successful 




enumerator kNETC_VerifyFaile

Verification failed 




enumerator kNETC_VerifyUndefined

Verification is in an undefined state 






typedef enum _netc_port_phy_mac_type netc_port_phy_mac_type_t

Defines the Ethernet MAC physical port type. 




typedef enum _netc_port_preemption_verify_status netc_port_preemption_verify_status_t

Definesthe state of the mac merge sublayer with respect to verification as defined in IEEE Std 802.3br-2016. 




typedef struct _netc_port_phy_mac_preemption_status netc_port_phy_mac_preemption_status_t

Port MAC preemption Status. 




typedef struct _netc_port_phy_mac_traffic_statistic netc_port_phy_mac_traffic_statistic_t

Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups. 




typedef struct _netc_port_phy_mac_discard_statistic netc_port_phy_mac_discard_statistic_t

Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups. 




typedef struct _netc_port_phy_mac_preemption_statistic netc_port_phy_mac_preemption_statistic_t

Ethernet physical MAC port preemption (Tx/Rx) related statistics counters. 




typedef struct _netc_port_pseudo_mac_traffic_statistic netc_port_pseudo_mac_traffic_statistic_t

Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters. 




uint32_t NETC_GetPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType)

Get port MAC interrupt flags. 

Parameters:

base – NETC ETH link base register. 
mac – MAC type. 







void NETC_ClearPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask)

Clear port MAC interrupt flags. 

Parameters:

base – NETC ETH link base register. 
mac – MAC type. 
mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask. 







void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask, bool enable)

Enable/Disable port MAC interrupts. 

Parameters:

base – NETC ETH link base register. 
mac – MAC type. 
mask – Bit mask of interrupts to enable. See netc_port_intr_flags_t for the set of constants that should be OR’d together to form the bit mask. 
enable – Enable/Disable interrupts. 







status_t NETC_PortEnableLoopback(NETC_ETH_LINK_Type *base, netc_port_loopback_mode_t loopMode, bool enable)

Enable/Disable Loopback for specified MAC. 

Parameters:

base – 
loopMode – 
enable – 


Returns:
status_t 






static inline netc_hw_mii_mode_t NETC_PortGetMIIMode(NETC_ETH_LINK_Type *base)

Get ethernet MAC port MII mode. 

Parameters:

base – Ethernet MAC port peripheral base address. 


Returns:
netc_hw_mii_mode_t 






status_t NETC_PortSetMII(NETC_ETH_LINK_Type *base, netc_hw_mii_mode_t miiMode, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)

Configure ethernet MAC interface mode, speed and duplex for specified PORT. 

Parameters:

base – Ethernet MAC port peripheral base address. 
miiMode – The Ethernet MAC MII mode. 
speed – The Ethernet MAC speed. 
duplex – The Ethernet MAC duplex. 


Returns:
status_t 






status_t NETC_PortSetMaxFrameSize(NETC_ETH_LINK_Type *base, uint16_t size)

Set the maximum supported received frame size. 

Parameters:

base – Ethernet MAC port peripheral base address. 
size – Maximum frame size to set. 


Returns:
status_t 






status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_t *config)

Configure ethernet MAC for specified PORT. Set the MII mode, speed/duplex, reverse mode, etc. 

Parameters:

base – Ethernet MAC port peripheral base address. 
config – The Ethernet MAC configuration. 


Returns:
status_t 






static inline void NETC_PortConfigEthMacPreemption(NETC_ETH_LINK_Type *base, const netc_port_preemption_config *config)

Configure ethernet MAC for Frame preemption on specified PORT. 

Parameters:

base – Ethernet MAC port peripheral base address. 
config – The Ethernet MAC configuration. 


Returns:
status_t 






static inline void NETC_PortSoftwareResetEthMac(NETC_ETH_LINK_Type *base)

Do software reset for Ethernet MAC. 

Note
This can reset all statistic counters.


Parameters:

base – PORT MAC peripheral base address. 







static inline void NETC_PortGetPhyMacPreemptionStatus(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_status_t *status)

Get Ethernet MAC preemption status. 

Parameters:

base – PORT MAC peripheral base address. 
status – Point to the buffer which store status. 







static inline void NETC_PortGetPhyMacPreemptionControl(NETC_ETH_LINK_Type *base, netc_port_preemption_config *config)

Get Ethernet MAC preemption control parameters. 

Parameters:

base – PORT MAC peripheral base address. 
config – Pointer to the NETC port preemption configuration. 







void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)

Get Ethernet MAC Tx Traffic Statistics . 

Parameters:

base – PORT MAC peripheral base address. 
macType – Express MAC or Preemptable MAC. 
status – Point to the buffer which store statistics. 







void NETC_PortGetPhyMacRxStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_traffic_statistic_t *statistic)

Get Ethernet MAC Rx Traffic Statistics . 

Parameters:

base – PORT MAC peripheral base address. 
macType – Express MAC or Preemptable MAC. 
status – Point to the buffer which store statistics. 







void NETC_PortGetPhyMacDiscardStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, netc_port_phy_mac_discard_statistic_t *statistic)

Get Ethernet MAC Rx/Tx Drops/Errors Statistics . 

Parameters:

base – PORT MAC peripheral base address. 
macType – Express MAC or Preemptable MAC. 
status – Point to the buffer which store statistics. 







void NETC_PortGetPhyMacPreemptionStatistic(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_statistic_t *statistic)

Get Ethernet Preemptable MAC preemption Statistics . 

Parameters:

base – PORT MAC peripheral base address. 
status – Point to the buffer which store statistics. 







status_t NETC_PortConfigTxIpgPreamble(NETC_ETH_LINK_Type *base, uint8_t preambleCnt, uint8_t ipgLen)

Configure the port MAC flexible preamble and IPG length. 

Parameters:

base – PORT MAC peripheral base address. 
preambleCnt – Flexible Preamble Count. Valid values are 1 to 7(default). 
ipgLen – Transmit inter-packet gap value. Valid values are 4 to 24(default) with 12 being default. 


Returns:
status_t 






struct _netc_port_phy_mac_preemption_status


#include <fsl_netc.h>
Port MAC preemption Status. 

Public Members


bool mergeActive

Transmit preemption is active or not 




netc_port_preemption_verify_status_t verifyStatus

Transmit preemption is active or not 







struct _netc_port_phy_mac_traffic_statistic


#include <fsl_netc.h>
Ethernet MAC physical port traffic (Tx/Rx) statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups. 

Public Members


uint64_t totalOctet

Count of MAC received/transmitted good/error Ethernet octets. 




uint64_t validOctet

Count of MAC received/transmitted good Ethernet octets. 




uint64_t pauseFrame

Count of MAC received/transmitted valid PAUSE frames. 




uint64_t validFrame

Count of MAC received/transmitted valid frames. 




uint64_t vlanFrame

Count of MAC received/transmitted valid VLAN tagged frames. 




uint64_t unicastFrame

Count of MAC received/transmitted valid unicast frames. 




uint64_t multicastFrame

Count of MAC received/transmitted valid multicast frames. 




uint64_t boradcastFrame

Count of MAC received/transmitted valid broadcast frames. 




uint64_t totalPacket

Count of MAC received/transmitted good/error packets. 




uint64_t rxMinPacket

Count of MAC received min to 63-octet packets. 




uint64_t total64BPacket

Count of MAC received/transmitted 64 octet packets. 




uint64_t total65To127BPacket

Count of MAC received/transmitted 65 to 127 octet packets. 




uint64_t total128To255BPacket

Count of MAC received/transmitted 128 to 255 octet packets. 




uint64_t total256To511BPacket

Count of MAC received/transmitted 256 to 511 octet packets. 




uint64_t total511To1023BPacket

Count of MAC received/transmitted 512 to 1023 octet packets. 




uint64_t total1024To1522BPacket

Count of MAC received/transmitted 1024 to 1522 octet packets. 




uint64_t total1523ToMaxBPacket

Count of MAC received/transmitted 1523 to Max octet packets. 




uint64_t controlPacket

Count of MAC received/transmitted control packets. 







struct _netc_port_phy_mac_discard_statistic


#include <fsl_netc.h>
Ethernet MAC physical port frame discard/errors status statistics counters, when enable frame preemption, one physical MAC will be divided into a pMAC and a eMAC and statistics counters will also have two groups. 

Public Members


uint64_t rxError

Count of MAC received error frames. 




uint64_t rxUndersized

Count of MAC received undersized frames. 




uint64_t rxOversized

Count of MAC received oversized frames. 




uint64_t rxErrorFCS

Count of MAC received check sequence (FCS) error frames. 




uint64_t rxFragment

Count of MAC frames which is shorter than the MIN length and received with a wrong FCS/CRC. 




uint64_t rxJabber

Count of MAC frames which is larger than the MAX length and received with a wrong FCS/CRC. 




uint64_t rxDiscard

Count of MAC drops frame. 




uint64_t rxDiscardNoTruncated

Count of MAC non-truncated drops frame. 




uint64_t txErrorFCS

Count of MAC transmitted bad FCS frames. 




uint64_t txUndersized

Count of MAC transmitted less than 64B with good FCS frames. 







struct _netc_port_phy_mac_preemption_statistic


#include <fsl_netc.h>
Ethernet physical MAC port preemption (Tx/Rx) related statistics counters. 

Public Members


uint32_t rxReassembledFrame

Count of MAC frames that were successfully reassembled and delivered to the MAC. 




uint32_t rxReassembledError

Count of MAC frames with reassembly errors. 




uint32_t rxMPacket

Count of the number of additional mPackets received due to preemption. 




uint32_t rxSMDError

Count of received MAC frames / MAC frame fragments rejected due to unknown SMD. 




uint32_t txPreemptionReq

Count of the number of tx preemption HOLD requests. 




uint32_t txMPacket

Count of the number of additional mPackets transmitted due to preemption. 







struct _netc_port_pseudo_mac_traffic_statistic


#include <fsl_netc.h>
Ethernet pseudo MAC port traffic (Tx/Rx) statistics counters. 

Public Members


uint64_t totalOctet

Count of MAC received/transmitted octets. 




uint64_t unicastFrame

Count of MAC received/transmitted unicast frames. 




uint64_t multicastFrame

Count of MAC received/transmitted multicast frames. 




uint64_t boradcastFrame

Count of MAC received/transmitted broadcast frames . 







Hardware Port Rx#


static inline void NETC_PortSetParser(NETC_PORT_Type *base, const netc_port_parser_config_t *config)

Set port Parser. 

Parameters:

base – PORT peripheral base address. 
config – The port Parser configuration. 







static inline void NETC_PortSetVlanClassify(NETC_PORT_Type *base, const netc_port_vlan_classify_config_t *config)

Set port acceptable VLAN. 

Parameters:

base – PORT peripheral base address. 
config – The port acceptable vlan classification configuration. 







static inline status_t NETC_PortSetQosClassify(NETC_PORT_Type *base, const netc_port_qos_classify_config_t *config)

Set port Qos Classification. 

Parameters:

base – PORT peripheral base address. 
config – The port QoS classification configuration. 


Returns:
status_t 






static inline void NETC_PortSetIPF(NETC_PORT_Type *base, const netc_port_ipf_config_t *config)

Set port ingress filter. 

Parameters:

base – PORT peripheral base address. 
config – The port ingress filter configuration. 







static inline void NETC_PortSetISI(NETC_PORT_Type *base, const netc_port_psfp_isi_config *config)

Set port Ingress stream identification. 

Parameters:

base – PORT peripheral base address. 
config – The port Ingress stream identification configuration. 







Hardware Port Tx#


static inline status_t NETC_PortConfigTGS(NETC_PORT_Type *base, const netc_port_tg_config_t *config)

Configure the port time gating Scheduling. 

Parameters:

base – 
config – 


Returns:
status_t 






status_t NETC_PortConfigTcCBS(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_cbs_config_t *config)

Config the Credit-Based Shaper (CBS) for specified Port Traffic Class. 

Parameters:

base – 
tcIdx – 
config – 


Returns:
status_t 






static inline status_t NETC_PortConfigTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const netc_port_tc_sdu_config_t *config)

Config the max Transmit max SDU for specified Port Traffic Class. 

Parameters:

base – 
tcIdx – 
config – 


Returns:
status_t 






static inline status_t NETC_PortGetTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, netc_port_tc_sdu_config_t *config)

Read the max Transmit max SDU for specified Port Traffic Class. 

Parameters:

base – 
tcIdx – 
config – 


Returns:
status_t 






static inline void NETC_PortConfigTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const bool enable)

Config Frame Preemption for specified Port Traffic Class. 

Parameters:

base – NETC PORT base peripheral address 
tcIdx – traffic class index 
enable – enable/disable feature on traffic class 







static inline void NETC_PortGetTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, bool *enabled)

Get Frame Preemption configuration for specified Port Traffic Class. 

Parameters:

base – NETC PORT base peripheral address 
tcIdx – traffic class index 
enabled – port tx traffic class enabled flag 







static inline void NETC_PortGetTGSFPConfig(NETC_PORT_Type *base, netc_port_tg_preemption_config *config)

Get the port time gating Scheduling configuration specifc for when used with Frame Preemption. 

Parameters:

base – NETC PORT base peripheral address 
config – 







Hardware Station Interface(SI)#


NETC_SI_TXDESCRIP_RD_FL(n)

Defines for read format. 




NETC_SI_TXDESCRIP_RD_TSE_MASK





NETC_SI_TXDESCRIP_RD_TXSTART(n)





NETC_SI_TXDESCRIP_RD_L3START(n)





NETC_SI_TXDESCRIP_RD_IPCS(n)





NETC_SI_TXDESCRIP_RD_L3HDRSIZE(n)





NETC_SI_TXDESCRIP_RD_L3T(n)





NETC_SI_TXDESCRIP_RD_L4T(n)





NETC_SI_TXDESCRIP_RD_L4CS(n)





NETC_SI_TXDESCRIP_RD_LSO(n)





NETC_SI_TXDESCRIP_RD_LSO_MASK





enum _netc_hw_enetc_si_vlan_type

VLAN Ethertypes. 
Values:


enumerator kNETC_ENETC_StanCVlan

Standard C-VLAN 0x8100. 




enumerator kNETC_ENETC_StanSVlan

Standard S-VLAN 0x88A8. 




enumerator kNETC_ENETC_CustomVlan1

Custom VLAN as defined by CVLANR1[ETYPE]. 




enumerator kNETC_ENETC_CustomVlan2

Custom VLAN as defined by CVLANR2[ETYPE]. 






enum _netc_hw_enetc_si_rxr_group

SI receive BD ring group index. 
Values:


enumerator kNETC_SiBDRGroupOne

SI Rx BD ring group index one. 




enumerator kNETC_SiBDRGroupTwo

SI Rx BD ring group index two. 






enum _netc_tx_bdr_flags

Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation. 
Values:


enumerator kNETC_TxBDRSystemBusErrorFlag





enumerator kNETC_TxBDRBusyFlag





enumerator kNETC_TxBDRStatusFlagsMask







enum _netc_rx_bdr_flags

Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation. 
Values:


enumerator kNETC_RxBDRSystemBusErrorFlag





enumerator kNETC_RxBDREmptyFlag







enum _netc_psi_msg_flags_t

PSI message interrupt type. 
Values:


enumerator kNETC_PsiRxMsgFromVsi1Flag

Message receive interrupt enable, initiated by VSI1. 




enumerator kNETC_PsiRxMsgFromVsi2Flag

Message receive interrupt enable, initiated by VSI2. 




enumerator kNETC_PsiRxMsgFromVsi3Flag

Message receive interrupt enable, initiated by VSI3. 




enumerator kNETC_PsiFLRFromVsi1Flag

Function level reset interrupt enable, initiated by VSI1. 






enum _netc_vsi_msg_flags

VSI message interrupt flags. 
Values:


enumerator kNETC_VsiMsgTxFlag

Message sent to PSI has completed and response received. 




enumerator kNETC_VsiMsgRxFlag

Message received from PSI. 






enum _netc_vsi_number

VSI number bit map, VSI1 starts from bit1. 
Values:


enumerator kNETC_Vsi1





enumerator kNETC_Vsi2





enumerator kNETC_Vsi3







enum _enetc_si_bdr_priority

ENETC Station Interface BD Ring priority enumeration. 
Values:


enumerator kNETC_SIBdrPriorityLowest





enumerator kNETC_SIBdrPriority0





enumerator kNETC_SIBdrPriority1





enumerator kNETC_SIBdrPriority2





enumerator kNETC_SIBdrPriority3





enumerator kNETC_SIBdrPriority4





enumerator kNETC_SIBdrPriority5





enumerator kNETC_SIBdrPriority6





enumerator kNETC_SIBdrPriority7





enumerator kNETC_SIBdrPriorityHighest







typedef enum _netc_hw_enetc_si_vlan_type netc_hw_enetc_si_vlan_type

VLAN Ethertypes. 




typedef enum _netc_hw_enetc_si_rxr_group netc_hw_enetc_si_rxr_group

SI receive BD ring group index. 




typedef struct _netc_hw_enetc_si_config netc_hw_enetc_si_config_t

Station Interface configuration. 




typedef struct _netc_si_l2mf_config netc_si_l2mf_config_t

L2 Mac Filter Configuration for SI. 




typedef struct _netc_si_l2vf_config netc_si_l2vf_config_t

L2 VLAN Filter Configuration for SI. 




typedef struct _netc_si_discard_statistic netc_si_discard_statistic_t

SI frame drop statistic struct. 




typedef struct _netc_si_traffic_statistic netc_si_traffic_statistic_t

SI traffic statistic struct. 




typedef struct _netc_si_config netc_si_config_t

SI Configuration. 




typedef union _netc_tx_bd netc_tx_bd_t

Transmit Buffer Descriptor format. 
A union type cover the BD used as Standard/Extended/WriteBack format. 




typedef union _netc_rx_bd netc_rx_bd_t

Receive Buffer Descriptor format. 




typedef struct _netc_tx_bdr_config netc_tx_bdr_config_t

Configuration for the SI Tx Buffer Descriptor Ring Configuration. 




typedef struct _netc_tx_bdr netc_tx_bdr_t

Transmit BD ring handler data structure. 




typedef enum _netc_tx_bdr_flags netc_tx_bdr_flags_t

Status/Interrupts flags for the TX BDR. Each flag get its own bit thus it support bit AND/OR operation. 




typedef struct _netc_rx_bdr_config netc_rx_bdr_config_t

Configuration for the SI Rx Buffer Descriptor Ring Configuration. 




typedef struct _netc_rx_bdr netc_rx_bdr_t

Receive BD ring handler data structure. 




typedef enum _netc_rx_bdr_flags netc_rx_bdr_flags_t

Status/Interrupts flags for the RX BDR. Each flag get its own bit thus it support bit AND/OR operation. 




typedef struct _netc_bdr_config netc_bdr_config_t

Configuration for the buffer descriptors ring. 




typedef enum _netc_psi_msg_flags_t netc_psi_msg_flags_t

PSI message interrupt type. 




typedef enum _netc_vsi_msg_flags netc_vsi_msg_flags_t

VSI message interrupt flags. 




typedef enum _netc_vsi_number netc_vsi_number_t

VSI number bit map, VSI1 starts from bit1. 




typedef struct _netc_psi_rx_msg netc_psi_rx_msg_t

PSI receive message information. 




typedef struct _netc_vsi_msg_tx_status netc_vsi_msg_tx_status_t

VSI message transmit status. 




typedef enum _enetc_si_bdr_priority enetc_si_bdr_priority_t

ENETC Station Interface BD Ring priority enumeration. 




static inline void NETC_ClearTxDescriptor(netc_tx_bd_t *txDesc)





static inline void NETC_CopyTxDescriptor(netc_tx_bd_t *txDescDst, netc_tx_bd_t *txDescSrc)





static inline void NETC_SIEnable(ENETC_SI_Type *base, bool enable)

Enable the Station Interface(SI) 

Parameters:

base – 







static inline void NETC_SIRxRingEnable(ENETC_SI_Type *base, uint8_t ring, bool enable)

Enable the specified Rx BD ring. 

Parameters:

base – 
ring – The ring index. 
base – Enable/Disable the ring. 







static inline void NETC_SIEnablePromisc(ENETC_SI_Type *base, netc_packet_type_t type, bool enable)

Enable/Disable unicast/multicast/boardcast promisc mode for specified SI. 

Parameters:

base – 
type – 
enable – 







static inline void NETC_SISetTxProducer(ENETC_SI_Type *base, uint8_t ring, uint16_t producer)

Set producer index of specified Tx BD ring. 

Parameters:

base – SI base address. 
ring – BD ring index. 
producer – The producer index of specified ring. 







static inline uint16_t NETC_SIGetTxConsumer(ENETC_SI_Type *base, uint8_t ring)

Get consumer index of specified Tx BD ring. 

Parameters:

base – SI base address. 
ring – BD ring index. 


Returns:
consumer The consumer index of specified ring. 






static inline void NETC_SISetRxConsumer(ENETC_SI_Type *base, uint8_t ring, uint16_t consumer)

Set consumer index of specified Rx BD ring. 

Parameters:

base – SI base address. 
ring – BD ring index. 
consumer – The consumer index of specified ring. 







static inline uint16_t NETC_SIGetRxProducer(ENETC_SI_Type *base, uint8_t ring)

Get producer index of specified Rx BD ring. 

Parameters:

base – SI base address. 
ring – BD ring index. 


Returns:
producer The producer index of specified ring. 






status_t NETC_SIConfigTxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_tx_bdr_config_t *bdrConfig)

Configure the Transmit Buffer Descriptor Ring for specified SI. 

Parameters:

base – SI base address. 
ring – BD ring index. 
bdrConfig – The BD ring configuration. 


Returns:
status_t 






status_t NETC_SIConfigRxBDR(ENETC_SI_Type *base, uint8_t ring, const netc_rx_bdr_config_t *bdrConfig)

Configure the Rx Buffer Descriptor Ring for specified SI. 

Parameters:

base – SI base address. 
ring – BD ring index. 
bdrConfig – The BD ring configuration. 


Returns:
status_t 






static inline void NETC_SIMapVlanToIpv(ENETC_SI_Type *base, uint8_t pcpDei, uint8_t ipv)

Enable the mapping of VLAN to IPV. 

Parameters:

base – SI base address. 
pcpDei – The VLAN tag pcp dei value (use NETC_VLAN_PCP_DEI_VALUE macro). 
ipv – The IPV value for this VLAN mapping. 







static inline void NETC_SIEnableVlanToIpv(ENETC_SI_Type *base, bool enable)

Enable the mapping of VLAN to IPV. 

Parameters:

base – SI base address. 
enable – Whether enable mapping. 


Returns:
status_t 






static inline void NETC_SIMapIpvToRing(ENETC_SI_Type *base, uint8_t ipv, uint8_t ring)

Set the IPV to ring mapping. 

Parameters:

base – SI base address. 
ipv – IPV value to be mapped. 
ring – The Rx BD ring index to be mapped. 


Returns:
status_t 






static inline void NETC_SISetRxBDRGroup(ENETC_SI_Type *base, uint8_t groupNum, uint8_t ringPerGroup)

Set the group of Rx BD ring. 

Parameters:

base – SI base address. 
groupNum – Total group number. 
ringPerGroup – Rings per group. 


Returns:
status_t 






static inline void NETC_SISetDefaultRxBDRGroup(ENETC_SI_Type *base, netc_hw_enetc_si_rxr_group groupIdx)

Set the default used receive Rx BD ring group. 

Note
The IPV mapped ring index is the relative index inside the default used group.


Parameters:

base – SI base address. 
groupNum – The default Rx group index. 


Returns:
status_t 






static inline void NETC_SICleanTxIntrFlags(ENETC_SI_Type *base, uint16_t txFrameIntrMask, uint16_t txThresIntrMask)

Clean the SI transmit interrupt flags. 

Parameters:

base – SI base address. 
txFrameIntrMask – IPV value to be mapped, bit x represents ring x. 
txThresIntrMask – The Rx BD ring index to be mapped, bit x represents ring x. 







static inline void NETC_SICleanRxIntrFlags(ENETC_SI_Type *base, uint32_t rxIntrMask)

Clean the SI receive interrupt flags. 

Parameters:

base – SI base address. 
rxIntrMask – Rx interrupt bit mask, bit x represents ring x. 







void NETC_SIPsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)

PSI enables/disables specified interrupt. 

Parameters:

base – SI base address. 
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 
enable – Enable/Disable the interrupt. 







static inline uint32_t NETC_SIPsiGetStatus(ENETC_SI_Type *base)

PSI gets interrupt event flag status. 

Parameters:

base – SI base address. 


Returns:
The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 






static inline void NETC_SIPsiClearStatus(ENETC_SI_Type *base, uint32_t mask)

PSI clears interrupt event flag. 

Parameters:

base – SI base address. 
mask – The interrupt mask, refer to netc_psi_msg_flags_t which should be OR’d together. 







status_t NETC_SIPsiSendMsg(ENETC_SI_Type *base, uint16_t msg, netc_vsi_number_t vsi)

PSI sends message to specified VSI(s) 

Parameters:

base – SI base address. 
msg – The message to be sent. 
vsi – The VSI number. 


Returns:
status_t 






static inline bool NETC_SIPsiCheckTxBusy(ENETC_SI_Type *base, netc_vsi_number_t vsi)

PSI checks Tx busy flag which should be cleaned when VSI receive the message data. 

Parameters:

base – SI base address. 
vsi – The VSI number. 


Returns:
The busy status of specified VSI. 






status_t NETC_SIPsiSetRxBuffer(ENETC_SI_Type *base, netc_vsi_number_t vsi, uint64_t buffAddr)

PSI sets Rx buffer to receive message from specified VSI. 

Note
The buffer memory size should be big enough for the message data from VSI


Parameters:

base – SI base address. 
vsi – The VSI number. 
buffAddr – The buffer address to store message data from VSI, must be 64 bytes aligned. 


Returns:
status_t 






status_t NETC_SIPsiGetRxMsg(ENETC_SI_Type *base, netc_vsi_number_t vsi, netc_psi_rx_msg_t *msgInfo)

PSI gets Rx message from specified VSI. 

Parameters:

base – SI base address. 
vsi – The VSI number. 
msgInfo – The Rx message information. 







void NETC_SIVsiEnableInterrupt(ENETC_SI_Type *base, uint32_t mask, bool enable)

Enable VSI interrupt. 

Parameters:

base – SI base address. 
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together. 
enable – Enable/Disable interrupt. 







static inline uint32_t NETC_SIVsiGetStatus(ENETC_SI_Type *base)

Get VSI interrupt status. 

Parameters:

base – SI base address. 


Returns:
A bitmask composed of netc_vsi_msg_flags_t enumerators OR’d together. 






static inline void NETC_SIVsiClearStatus(ENETC_SI_Type *base, uint32_t mask)

Clear VSI interrupt status. 

Parameters:

base – SI base address. 
mask – The interrupt mask, see netc_vsi_msg_flags_t which should be OR’d together. 







status_t NETC_SIVsiSendMsg(ENETC_SI_Type *base, uint64_t msgAddr, uint32_t msgLen)

VSI sends message to PSI. 

Parameters:

base – SI base address. 
msgAddr – Address to store message ready to be sent, must be 64 bytes aligned. 
msgLen – The message length, must be 32 bytes aligned. 


Returns:
status_t 






void NETC_SIVsiCheckTxStatus(ENETC_SI_Type *base, netc_vsi_msg_tx_status_t *status)

Check VSI Tx status. 

Parameters:

base – SI base address. 
status – The VSI Tx status structure. 







status_t NETC_SIVsiReceiveMsg(ENETC_SI_Type *base, uint16_t *msg)

VSI receives message from PSI. 

Parameters:

base – SI base address. 
msg – The message from PSI. 


Returns:
status_t 






void NETC_SIGetDiscardStatistic(ENETC_SI_Type *base, netc_si_discard_statistic_t *statistic)

Get the discard statistic from SI layer. 

Parameters:

base – SI base address. 
statistic – The statistic data. 







void NETC_SIGetTrafficStatistic(ENETC_SI_Type *base, netc_si_traffic_statistic_t *statistic)

Get the traffic statistic from SI layer. 

Parameters:

base – SI base address. 
statistic – The statistic data. 







NETC_VLAN_PCP_DEI_VALUE(pcp, dei)

Macro to cover VLAN PCP, DEI value to internal used pcpDei value. 




struct _netc_hw_enetc_si_config


#include <fsl_netc.h>
Station Interface configuration. 

Public Members


uint8_t bandWeight

Station interface traffic class bandwidth weight 




uint8_t vlanCtrl

VLAN Ethertypes can be inserted by the SI driver, set with OR of netc_hw_enetc_si_vlan_type. 




bool antiSpoofEnable

Anti-spoofing enable 




bool vlanInsertEnable

Software SI-based VLAN Insertion enable, avtive when enSIBaseVlan is true 




bool vlanExtractEnable

SI-based VLAN removed from frame enable, avtive when enSIBaseVlan is true 




bool sourcePruneEnable

Source pruning enable 




uint8_t rxRingUse

Number of Rx Rings to be used, when enable Rx ring group, this equal to the sum of all Rx group rings. 




uint8_t txRingUse

Number of Tx Rings to be used, note that when SI is Switch management ENETC SI, the number not include Tx ring 0. 




bool valnToIpvEnable

Enable the VLAN PCP/DEI value (use NETC_VLAN_PCP_DEI_VALUE marco) to internal priority value mapping. 




uint8_t rxBdrGroupNum

Rx BD ring group number, range in 0 ~ 2. 




uint8_t ringPerBdrGroup

The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero. 




netc_hw_enetc_si_rxr_group defaultRxBdrGroup

The selected Rx BD ring group, active when rxBdrGroupNum not equal zero. 




uint8_t vlanToIpvMap[16]

Frame VLAN pcp|dei to IPV mapping, active when valnToIpvEnable is true. 




uint8_t ipvToRingMap[8]

BD ring used within the default Rx BD ring group for IPV n, active when rxBdrGroupNum not equal zero. 




uint8_t vsiTcToTC[8]

Maps the VSI traffic class to transmit traffic class, done after the ENETC txPrio to TC mapping, only available for VSI. 




bool enSIBaseVlan

Enable use SI-based VLAN information. 




netc_enetc_vlan_tag_t siBaseVlan

SI-based VLAN information, active when enSIBaseVlan is true. 







struct _netc_si_l2mf_config


#include <fsl_netc.h>
L2 Mac Filter Configuration for SI. 

Public Members


bool macUCPromis

Enable/Disable MAC unicast promiscuous. 




bool macMCPromis

Enable/Disable MAC multicast promiscuous. 




bool rejectUC

Reject Unicast. 




bool rejectMC

Reject Multicast. 




bool rejectBC

Reject Broadcast. 







struct _netc_si_l2vf_config


#include <fsl_netc.h>
L2 VLAN Filter Configuration for SI. 

Public Members


bool acceptUntagged

Accept/Reject untagged frame. 




bool enPromis

Enable/Disable VLAN promiscuous. 




bool useOuterVlanTag

Use outer/inner VLAN tag for filtering. 







struct _netc_si_discard_statistic


#include <fsl_netc.h>
SI frame drop statistic struct. 

Public Members


uint32_t programError

Due to programming error ( non-existing BD ring or non-existing group, or SI disabled or BD ring disabled). 




uint32_t busError

Due to system bus error. 




uint32_t lackBD[14]

Due to lack of Rx BDs available. 







struct _netc_si_traffic_statistic


#include <fsl_netc.h>
SI traffic statistic struct. 




struct _netc_si_config


#include <fsl_netc.h>
SI Configuration. 

Public Members


uint32_t tcBWWeight

SI traffic class bandwidth weight. 







union _netc_tx_bd


#include <fsl_netc.h>
Transmit Buffer Descriptor format. 
A union type cover the BD used as Standard/Extended/WriteBack format. 

Public Members


struct _netc_tx_bd standard





struct _netc_tx_bd ext





struct _netc_tx_bd writeback





uint64_t dword[2]








union _netc_rx_bd


#include <fsl_netc.h>
Receive Buffer Descriptor format. 

Public Members


struct _netc_rx_bd standard





struct _netc_rx_bd writeback





struct _netc_rx_bd ext








struct _netc_tx_bdr_config


#include <fsl_netc.h>
Configuration for the SI Tx Buffer Descriptor Ring Configuration. 

Public Members


uint32_t len

Size of BD ring which shall be multiple of 8 BD. 




netc_tx_bd_t *bdArray

BDR base address which shall be 128 bytes aligned. 




netc_tx_frame_info_t *dirtyArray

Tx cleanup ring. 




bool enIntr

Enable/Disable completion interrupt. 




bool enThresIntr

Enable/Disable threshold interrupt. 




bool enCoalIntr

Enable/Disable interrupt coalescing. 




uint32_t intrThreshold

Interrupt coalescing packet threshold. 




uint32_t intrTimerThres

Interrupt coalescing timer threshold, specified in NETC clock cycles. 




uint8_t msixEntryIdx

MSIX entry index of Tx ring interrupt. 




bool isVlanInsert

Enable/Disable VLAN insert offload. 




bool isUserCRC

Enable/Disable user provided the CRC32 - FCS at end of frame. 




uint8_t wrrWeight

Weight used for arbitration when rings have same priority. 




uint8_t priority

Priority of the Tx BDR. 







struct _netc_tx_bdr


#include <fsl_netc.h>
Transmit BD ring handler data structure. 

Public Members


netc_tx_bd_t *bdBase

Tx BDR base address. 




netc_tx_frame_info_t *dirtyBase

Tx cleanup ring base address. 




uint16_t producerIndex

Current index for transmit. 




uint16_t cleanIndex

Current index for tx cleaning. 




uint32_t len

Length of this BD ring. 




uint8_t enableInterrupt

Interrupt flag for this BD ring. 







struct _netc_rx_bdr_config


#include <fsl_netc.h>
Configuration for the SI Rx Buffer Descriptor Ring Configuration. 

Public Members


bool extendDescEn

False - Use 16Bytes standard BD. True - Use 32Bytes extended BD. 




netc_rx_bd_t *bdArray

BD ring base address which shall be 128 bytes aligned. 




uint32_t len

BD ring length in the unit of 16Bytes standard BD. Shall be multiple of 8/16 for standard/exteneded BD. 




uint64_t *buffAddrArray

Rx buffers array with BD length(half of BD length if use exteneded BD). 




uint16_t buffSize

Size of all Rx buffers in this BD ring. 




bool enThresIntr

Enable/Disable threshold interrupt. 




bool enCoalIntr

Enable/Disable interrupt coalescing. 




uint32_t intrThreshold

Interrupt coalescing packet threshold. 




uint32_t intrTimerThres

Interrupt coalescing timer threshold, specified in NETC clock cycles. 




uint8_t msixEntryIdx

MSIX entry index of Rx ring interrupt. 




bool disVlanPresent

Disable/Enable VLAN in BD. 




bool enVlanExtract

Enable/Disable VLAN extract. 




bool isKeepCRC

Whether user provided the CRC32 - FCS at end of frame. 




bool congestionMode

False - lossy. True - lossless. 




bool enHeaderAlign

Enable/disable +2B alignment to frame. 







struct _netc_rx_bdr


#include <fsl_netc.h>
Receive BD ring handler data structure. 

Public Members


netc_rx_bd_t *bdBase

Rx BDR base address. 




bool extendDesc

Use extended buffer descriptor. 




uint16_t index

Current index for read. 




uint32_t len

Length of this BD ring, unit of 16Bytes standard BD. 




uint64_t *buffArray

Rx buffers array of this ring. 




uint32_t buffSize

Rx buffers size for all BDs in this ring. 







struct _netc_bdr_config


#include <fsl_netc.h>
Configuration for the buffer descriptors ring. 

Public Members


netc_rx_bdr_config_t *rxBdrConfig

Receive buffer ring configuration array. 




netc_tx_bdr_config_t *txBdrConfig

Transmit buffer ring configuration array. 







struct _netc_psi_rx_msg


#include <fsl_netc.h>
PSI receive message information. 

Public Members


uint8_t *msgBuff

The buffer address application set before receiving message. 




uint32_t msgLen

Received message length. 







struct _netc_vsi_msg_tx_status


#include <fsl_netc.h>
VSI message transmit status. 

Public Members


bool txBusy

The VSI Tx busy flag, become idle when the PSI receive and clear the related status. 




bool isTxErr

Tx error flag. 




uint16_t msgCode

The error code or user-defined content. 







struct standard


Public Members


uint64_t addr

Address of the buffer. Little Endian. 




uint16_t bufLen

Length of buffer specifying effective number of bytes. 




uint16_t frameLen

Length of Frame. 




uint32_t flags

Flags qualified setting. 




uint32_t enableInterrupt

Whether enable interrupt on complete of BD. 




uint32_t isExtended

Extended BD format flag. 




uint32_t isFinal

Final BD flag. 







struct ext


Public Members


uint32_t timestamp

IEEE1588 PTP one-step timestamp. 




uint32_t __pad0__

Ignore 2-bit MSB. 




uint16_t tpid

VLAN TPID type, see netc_vlan_tpid_select_t. 




uint16_t vid

VLAN ID. 




uint16_t dei

VLAN DEI. 




uint16_t pcp

VLAN PCP. 




uint8_t eFlags

Tx extension flags. 




uint8_t isFinal

Final BD flag. 







struct writeback


Public Members


uint32_t timestamp

Timestamp write back. 




uint32_t status

Status. 




uint32_t written

Write-back flag. 







struct standard


Public Members


uint64_t addr

Software write address. 







struct writeback


Public Members


uint16_t internetChecksum

Internet Checksum. 




uint16_t parserSummary

Parser Summary. 




uint16_t bufLen

Length of received buffer. 




uint16_t vid

VLAN ID. 




uint16_t dei

VLAN DEI. 




uint16_t pcp

VLAN PCP. 




uint8_t tpid

VLAN TPID. 




uint8_t hr

Host Reason. 




uint8_t flags

Rx information flags. 




uint8_t error

Rx error code. 




uint8_t isReady

Received data ready flag. 




uint8_t isFinal

Final BD flag. 







union __unnamed185__


Public Members


struct _netc_rx_bd




uint32_t rssHashSwt

RSS hash while not used as switch management port. 







struct __unnamed187__


Public Members


uint32_t srcPort

Source port received from switch management port. 




uint32_t rssHash

RSS Hash high field value. 







struct ext


Public Members


uint32_t timestamp

Rx Timestamp. 







Hardware Switch#


enum _netc_swt_port_bitmap

The switch port bitmap. 
Values:


enumerator kNETC_SWTPort0Bit

Switch port0 bitmap 




enumerator kNETC_SWTPort1Bit

Switch port1 bitmap 




enumerator kNETC_SWTPort2Bit

Switch port2 bitmap 




enumerator kNETC_SWTPort3Bit

Switch port3 bitmap 




enumerator kNETC_SWTPort4Bit

Switch port4 (internal port) bitmap 






enum _netc_swt_imr_dest_port

The switch ingress mirror destination port. 
Values:


enumerator kNETC_SWTPort0

Switch port0 




enumerator kNETC_SWTPort1

Switch port1 




enumerator kNETC_SWTPort2

Switch port2 




enumerator kNETC_SWTPort3

Switch port3 




enumerator kNETC_SWTPort4

Switch port4 




enumerator kNETC_SWTMPort

Switch management port 






enum _netc_swt_mac_forward_mode

The switch MAC forwarding options. 
Values:


enumerator kNETC_NoFDBLookUp

No FDB lookup is performed, the frame is flooded. 




enumerator kNETC_FDBLookUpWithFlood

FDB lookup is performed, and if there is no match, the frame is flooded to the port bitmap in VLAN filter entry. 




enumerator kNETC_FDBLookUpWithDiscard

FDB lookup is performed, and if there is no match, the frame is discarded. 






enum _netc_swt_mac_learn_mode

The switch MAC learning options. 
Values:


enumerator kNETC_DisableMACLearn

Disable MAC learning. SMAC FDB lookup is by-passed. 




enumerator kNETC_HardwareMACLearn

Hardware MAC learning is enabled. 




enumerator kNETC_SeSoftwareMACLearn

Software MAC learning secure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is redirected to the switch management port. 




enumerator kNETC_UnseSoftwareMACLearn

Software MAC learning unsecure. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is copied to the switch management port. 




enumerator kNETC_DisableMACLearnWithSMAC

Disable MAC learning with SMAC validation. FDB lookup based on FID and SMAC is performed and if an entry is not found, the frame is discarded. 






enum _netc_swt_port_tx_vlan_act

Switch transmit Bridge Port VLAN Tag Action. 
Values:


enumerator kNETC_NoTxVlanModify

No egress VLAN modification performed 




enumerator kNETC_TxDelOuterVlan

Delete outer VLAN tag 




enumerator kNETC_TxReplOuterVlanVid

Replace outer VLAN tag’s VID with 0; frame to be transmitted as a priority tag frame 






enum _netc_swt_port_stg_mode

Switch port spanning tree group work mode. 
Values:


enumerator kNETC_DiscardFrame

Tx or RX Frames on this port with current spanning tree group ID will be discarded 




enumerator kNETC_LearnWithoutFowrad

RX Frames on this port with current spanning tree group ID will do Learn SMAC, but do not forward, Tx Frame will be discarded 




enumerator kNETC_ForwardFrame

RX Frames on this port with current spanning tree group ID will do both MAC learning and forwarding, , Tx Frame will be forwarded. 






typedef enum _netc_swt_port_bitmap netc_swt_port_bitmap_t

The switch port bitmap. 




typedef enum _netc_swt_imr_dest_port netc_swt_imr_dest_port_t

The switch ingress mirror destination port. 




typedef enum _netc_swt_mac_forward_mode netc_swt_mac_forward_mode_t

The switch MAC forwarding options. 




typedef enum _netc_swt_mac_learn_mode netc_swt_mac_learn_mode_t

The switch MAC learning options. 




typedef enum _netc_swt_port_tx_vlan_act netc_swt_port_tx_vlan_act_t

Switch transmit Bridge Port VLAN Tag Action. 




typedef enum _netc_swt_port_stg_mode netc_swt_port_stg_mode_t

Switch port spanning tree group work mode. 




typedef struct _etc_swt_imr_config netc_swt_imr_config_t

Switch Ingress mirror destination config. 




typedef struct _netc_swt_port_config netc_swt_port_bridge_config_t

Switch port bridge configuration. 




typedef struct _netc_swt_port_fm_config netc_swt_port_fm_config_t

Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP]) 




typedef struct _netc_swt_default_vlan_filter netc_swt_default_vlan_filter_t

Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup. 




typedef struct _netc_swt_bridge_config netc_swt_bridge_config_t

Bridge config. 




typedef struct _netc_swt_psfp_config netc_swt_psfp_config_t

Switch PSFP configuration. 




typedef struct _netc_qos_classify_config netc_swt_qos_classify_config_t

Switch Qos Classification configuration (include two profiles) 




typedef struct _netc_swt_qos_to_vlan_config netc_swt_qos_to_vlan_config_t

Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag. 




typedef struct _netc_switch_inuse_fdb_statistic netc_switch_inuse_fdb_statistic_t

Switch static/dynamic FDB entries in-use statistic. 




typedef struct _netc_swt_port_sr_config netc_swt_port_sr_config_t

Port seamless redundancy configuration. 




struct _etc_swt_imr_config


#include <fsl_netc.h>
Switch Ingress mirror destination config. 

Public Members


bool enMirror

Enable ingress mirroring 




netc_swt_imr_dest_port_t destPort

Port where ingress mirrored frames are sent 




uint8_t dr

Mirrored packet’s DR (drop resilience) 




uint8_t ipv

Mirrored packet’s IPV (internal priority value) 




uint8_t efmLengthChange

Egress Frame Modification Frame Length change in 2s complement notation, Vaild if efmEntryID is noy null 




uint16_t efmEntryID

Egress Frame Modification Entry Id, note 0xFFFF is a Null Frame Modification Entry, Only applicable if destPort != kNETC_SWTMPort 







struct _netc_swt_port_config


#include <fsl_netc.h>
Switch port bridge configuration. 

Public Members


netc_swt_port_tx_vlan_act_t txVlanAction

Only applies for the frame outer VLAN tag’s VID is equal to the port default VID 




bool isRxVlanAware

Receive VLAN Aware Mode 




bool acceptUntag

Accept untagged frame 




bool acceptPriorityTag

Accept priority tagged frame (VID = 0) 




bool acceptSingleTag

Accept single tagged frame 




bool acceptDoubleTag

Accept double tagged frame (ounter and inner) 




bool enSrcPortPrun

Enable/Disable received frame be transmitted to same port it was received 




bool enMacStationMove

Enable/Disable received frame which ingress port not match the FDB entry Destination Port Bitmap 




bool enBcastStormCtrl

Enable/Disable Storm control for broadcast frames 




bool enMcastStormCtrl

Enable/Disable Storm control for multicast frames 




bool enUnMcastStormCtrl

Enable/Disable Storm control for unknown multicast frames 




bool enUnUcastStormCtrl

Enable/Disable Storm control for unknown unicast frames 




uint32_t bcastRpEntryID

Broadcast rate policer entry ID. Valid if enBroadStormCtrl = true 




uint32_t mcastEntryID

Known multicast rate policer entry ID. Valid if enBroadStormCtrl = true 




uint32_t unMcastRpEntryID

Unknown multicast policer entry ID. Valid if enUnMultiStormCtrl = true 




uint32_t unUcastRpEntryID

Unknown unicast rate policer entry ID. Valid if enUnUniStormCtrl = true 




uint16_t maxDynaFDBEntry

The maximium number of dynamic entries in the FDB table, 0 means no limit 







struct _netc_swt_port_fm_config


#include <fsl_netc.h>
Switch Port level Frame Modification configuration (PPCPDEIMR and PQOSMR[QVMP]) 

Public Members


bool ignoreFMMiscfg

Enable/Disable ignore the Frame Modification Misconfiguration Action 




bool enEgressPcpMap

Enable egress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action 




bool enIngressPcpMap

Enable ingress frame modification of outer VLAN tag’s PCP value is mapped to a new value based on egressPcpMap, used for Frame Modification VLAN Outer PCP action 




bool enUpdateVlanDei

Enable update DR value in the outer VLAN based on DEnDEI field, used for egress Frame Modification Outer DEI action 




uint8_t drToDeiMap

Mapping of internal QoS’s DR value n to VLAN DEI, The 4 bits correspond to the DR3 ~ DR0, and 1 means DRn mapping to DEI 1, 0 means DRn mapping to DEI 0 




uint8_t egressPcpMap

Egress PCP to PCP Mapping Profile instance, active when enEgressPcpMap is true 




uint8_t ingressPcpMap

Ingress PCP to PCP Mapping Profile instance, active when enIngressPcpMap is true 




uint8_t qosVlanMap

Transmit QoS to VLAN PCP Mapping Profile index, used for egress Frame Modification VLAN Add/Replace Action 







struct _netc_swt_default_vlan_filter


#include <fsl_netc.h>
Switch VLAN filter hash table default entry configuration, which determines the default entry when not found in VLAN filter lookup. 

Public Members


bool enIPMFlood

Enable IP Multicast Flooding 




bool enIPMFilter

Enable IP Multicast Filtering 




uint8_t stgID

Spanning Tree Group Member ID, range in 0 ~ 15 




uint8_t portMembership

The bit 0 ~ 4 correspond to the 5 ports, When bit set (0b1), means the port is a member of this VLAN. Port membership is used for source/destination pruning 




bool enUseFilterID

Enable use the specified filterID as FID, otherwise will use the frame VID 




uint16_t filterID

Used as a key value to do FDB table and the L2 IPV4 Multicast Filter table lookup. Valid if enUseFilterID is true 




netc_swt_mac_forward_mode_t mfo

MAC forwarding options 




netc_swt_mac_learn_mode_t mlo

MAC learning options 




uint16_t baseETEID

Base Egress Treatment Entry ID 




uint8_t etaPortBitmap

Egress Treatment Applicability Port. Valid if baseETEID is not null. 







struct _netc_swt_bridge_config


#include <fsl_netc.h>
Bridge config. 

Public Members


netc_swt_default_vlan_filter_t dVFCfg

Default VLAN filter entry configuration when not found in VLAN filter lookup 







struct _netc_swt_psfp_config


#include <fsl_netc.h>
Switch PSFP configuration. 

Public Members


netc_isi_kc_rule_t kcRule[4]

Key construction rules 







struct _netc_qos_classify_config


#include <fsl_netc.h>
Switch Qos Classification configuration (include two profiles) 




struct _netc_swt_qos_to_vlan_config


#include <fsl_netc.h>
Switch QoS to PCP mapping and PCP to PCP mapping configuration when egress packet modification the VLAN tag. 


struct fsl_netc


Public Members


uint8_t qos[32]

Index is created from IPV (3 bits) + DR (2 bits) field. Value is the mapped PCP for VLAN tag. 




uint8_t pcp[8]

Index is created from outer PCP (3 bits) field. Value is the mapped PCP for VLAN tag. 









struct _netc_switch_inuse_fdb_statistic


#include <fsl_netc.h>
Switch static/dynamic FDB entries in-use statistic. 

Public Members


uint16_t camEntries

Number of FDB entries in-use in the CAM. 




uint16_t staticEntries

Number of static FDB entries in-use (both hash-based and CAM-based entries). 




uint16_t dynamicEntries

Number of dynamic FDB entries in-use (hash-based and CAM-based entries). 




uint16_t dynamicEntriesHWM

High water mark of dynamic entries in-use in the FDB table. 







struct _netc_swt_port_sr_config


#include <fsl_netc.h>
Port seamless redundancy configuration. 




struct defaultVlan


Public Members


uint32_t vid

Vlan Identifier. 




uint32_t dei

Drop eligible indicator 




uint32_t pcp

Priority code point. 




uint32_t tpid

Tag protocol identifier, 0 = Standard C-VLAN 0x8100, 1 = Standard S-VLAN 0x88A8. 







Hardware Table Access Functions#


enum _netc_tb_index

Table index. 
Values:


enumerator kNETC_TGSTable

Time Gate Scheduling table index 




enumerator kNETC_RPTable

Rate Policer table index 




enumerator kNETC_IPFTable

Ingress Port filter table index 




enumerator kNETC_FDBTable

FDB table index 




enumerator kNETC_L2MCFTable

L2 IPV4 Multicast Filter table index 




enumerator kNETC_VFTable

VLAN Filter table index 




enumerator kNETC_ECQTable

ETM Class Queue table index 




enumerator kNETC_ECSTable

ETM Class Scheduler table index 




enumerator kNETC_ISITable

Ingress Stream Identification table index 




enumerator kNETC_ISTable

Ingress Stream table index 




enumerator kNETC_ISFTable

Ingress Stream Filter table index 




enumerator kNETC_ETTable

Egress Treatment table index 




enumerator kNETC_ISGTable

Ingress Sequence Generation table index 




enumerator kNETC_ESRTable

Egress Sequence Recovery table index 




enumerator kNETC_SGITable

Stream Gate Instance table index 




enumerator kNETC_SGCLTable

Stream Gate Control List table index 




enumerator kNETC_ISCTable

Ingress Stream Count table index 




enumerator kNETC_ECTable

Egress Count table index 




enumerator kNETC_FMTable

Frame Modification table index 




enumerator kNETC_BPTable

Buffer Pool table index 




enumerator kNETC_SBPTable

Shared Buffer Pool table index 




enumerator kNETC_ECGTable

ETM Class Group table index 




enumerator kNETC_FMDTable

Frame Modification Data table index 






enum _netc_tb_cmd

Table management command operations. 
Values:


enumerator kNETC_DeleteEntry

Delete operation 




enumerator kNETC_UpdateEntry

Update operation 




enumerator kNETC_QueryEntry

Query operation 




enumerator kNETC_QueryAndDeleteEntry

Query operation followed by a delete operation 




enumerator kNETC_QueryAndUpdateEntry

Query operation followed by a update operation 




enumerator kNETC_AddEntry

Add operation 




enumerator kNETC_AddOrUpdateEntry

If the entry exists, is update operation, if not exist, is the Add operation 




enumerator kNETC_AddAndQueryEntry

Add operation followed by a query operation 




enumerator kNETC_AddQueryAndUpdateEntry

Add operation followed by a query operation, Then, if the entry existed prior to the Add operation of this command, the Update operation will be performed. 






enum _netc_tb_access_mode

Table Access Method. 
Values:


enumerator kNETC_EntryIDMatch

Entry ID Match 




enumerator kNETC_ExactKeyMatch

Exact Match Key Element Match 




enumerator kNETC_Search

Search with search criteria 




enumerator kNETC_TernaryKeyMatch

Ternary Match Key Element Match 






enum _netc_cbd_version

NTMP version. 
Values:


enumerator kNETC_NtmpV1_0

NTMP Version 1.0 




enumerator kNETC_NtmpV2_0

NTMP Version 2.0 






enum _netc_cmd_error

Table command response error status. 
Values:


enumerator kNETC_FormatError

Format error : 1. Illegal class or command. 2. Invalid SF bit setting. 3. LENGTH is zero for long format. 4. LENGTH is too small for buffer size. 




enumerator kNETC_SizeError

Size error : 1. Invalid table index, out of range. 2. Table overflow, no additional entries available. 




enumerator kNETC_AccessError

Access violation error, the entity is not allowed to perform the task requested 




enumerator kNETC_ClassError

Class specific error 




enumerator kNETC_IntegrityError

Integrity error, the command did not execute due to a data integrity error (ECC on internal memory or AXI read/write error) 




enumerator kNETC_InvTableID

Invalid table ID 




enumerator kNETC_InvAccMethod

Invalid Access method 




enumerator kNETC_TableIdxOutRange

Table index out of range 




enumerator kNETC_DBNotEnough

Request data buffer size or response data buffer size is not sufficient 




enumerator kNETC_InvCmd

Invalid command 




enumerator kNETC_ReqDBError

Request Data buffer error 




enumerator kNETC_MultiBitError

Multi-bit ECC or parity error observed during command processing 




enumerator kNETC_HashEntryLimit

Exceeded hash entry limit 




enumerator kNETC_HashChainLimit

Exceeded maximum hash collision chain limit and the CAM if present is full 




enumerator kNETC_InvHWGenEntryID

Invalid ENTRY_ID for ENTRY_ID generated by hardware 




enumerator kNETC_SrchResDBNotEnough

Search command filled the response data buffer before completing the command 




enumerator kNETC_CmdIdxTableWithITM

Command for index table before OSR[ITM_STATE]=0 




enumerator kNETC_InvQueryAction

Invalid Query action 




enumerator kNETC_InvTableAccPrivilege

Invalid table access privilege 




enumerator kNETC_ReadSysBusErr

System Bus Read Error 




enumerator kNETC_WriteSysBusErr

System Bus Write Error 




enumerator kNETC_ClientErr

Client encountered a fault 




enumerator kNETC_TGSCmdIssue

Command issued when time gating function is disabled for the port. 




enumerator kNETC_TGSUpdateExistList

Update action attempted on an existing admin gate control list. (should delete admin gate control list first before creating a new admin list) 




enumerator kNETC_TGSUpdateOverLength

Update action attempted exceeds TGSTCAPR[MAX_GCL_LEN] 




enumerator kNETC_TGSUpdateOverSize

Update action attempted exceeds TGSTCAPR[NUM_WORDS]. 




enumerator kNETC_TGSEntryNotEnough

Insufficient resources to perform the requested operation (not enough free time gate list entries) 




enumerator kNETC_TGSUpdateNSList

Update action attempted with ADMIN_CYCLE_TIME, ADMIN_TIME_INTERVAL_GE_i or truncated ADMIN_TIME_INTERVAL_GE_n due ADMIN_CYCLE_TIME specified is not sufficient to transmit 64 byte of frame data + header overhead. 




enumerator kNETC_TGSUpdateEarlierStartTime

Update action attempted with ADMIN_BASE_TIME specified s more than one second in the past from tcs advance time. 




enumerator kNETC_TGSUpdateOverflowCycle

Update action attempted with ADMIN_CYCLE_TIME + ADMIN_CYCLE_TIME_EXT is greater than 2^32-1. 




enumerator kNETC_TGSQueryBeforeListActive

Query action issued when config change occurred. Retry query. 




enumerator kNETC_TGSUpdateInvGateValue

Update action attempted with ADMIN_HR_CB_GE_i set to an invalid value 




enumerator kNETC_RPSDUTypeOutRange

SDU_TYPE specified in entry CFGE_DATA is out of range 




enumerator kNETC_IPFInvHR

HR value not valid. Only checked if command issued from the Switch and FLTFA=0x2 or FLTFA=0x3 




enumerator kNETC_IPFEntryNotFit

Entry being added does not fit in table 




enumerator kNETC_IPFWithoutSTSE

CFGE_DATA update without STSE_DATA update 




enumerator kNETC_IPFInvRPP

RPR set to a reserved value. Only checked if FLTA=0x2. 




enumerator kNETC_IPFFLTATGTOutRange

FLTA_TGT is outside valid range and not NULL. Only checked if FLTA>0x0 




enumerator kNETC_IPFInvSwtFLTA

FLTA=0x3 when command issued from the Switch. 




enumerator kNETC_IPFInvEnetcFLTA

FLTFA>0x1 when command issued from an ENETC PF. 




enumerator kNETC_FDBReachPortLimit

Failed to add or update and entry because the Port BPCR[DYN_LIMIT] has been reached 




enumerator kNETC_FDBReachSwtLimit

Failed to add entry because the Switch FDBHTMCR[DYN_LIMIT] has been reached. 




enumerator kNETC_FDBInvEPORT

EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1) 




enumerator kNETC_FDBETEIDOutRange

ET_EID is out of range and not NULL. Only checked if OETEID>0x0 




enumerator kNETC_FDBParityErr

Parity error encountered when adding guaranteed entry 




enumerator kNETC_L2MCFInvEPORT

EPORT value not valid. Only checked if (OETEID=0x1 OR CTD=0x1) 




enumerator kNETC_L2MCFETEIDOutRange

ET_EID is not NULL or within the valid range. Only checked if OETEID>0x0. 




enumerator kNETC_L2MCFInvKEYTYPE

KEY_TYPE value not valid 




enumerator kNETC_VFBASEETEIDOutRange

BASE_ET_EID is out of range or MLO is not valid. 




enumerator kNETC_ECQCQ2CGMAPOutRange

CQ2CG_MAP value out-of-range in update command. 




enumerator kNETC_ISIPortIDOutRange

Port ID specified in KEYE_DATA is out of range. 




enumerator kNETC_ISIInvISEID

IS_EID in invalid. 




enumerator kNETC_ISInvOpt

Option specified in one or more of the following fields is not valid – FA, CTD or ISQA, SDU_TYPE. 




enumerator kNETC_ISInvID

One or more of following : 1. Entry IDs are not in valid range or Entry ID is not Null. 2. Check valid ranges specified for these Entry IDs in Ingress Stream table entry – RP_EID, SGI_EID, ISQ_EID, ET_EID or EPORT. 3. ET_EID is checked if (FA =010b .. 101b) & (OETEID!=0). 4. EPORT is checked if (FA = 010b .. 101b) & (OETEID= 0x1 OR CTD= 0x1). 5. HR is chked if FA = 001b, 100b, or 101b. HR specified cannot be 0x0 




enumerator kNETC_ISInvFMEID

FM_EID format or index is out of range : 1. FM_EID format option type is invalid. 2. FM_EID format is option 1 and the Index is out of range and not Null, or FM_EID format is option 2 and VUDA or SQTA is out of range. 




enumerator kNETC_ISFInvISEID

IS_EID in KEYE_DATA is invalid. 




enumerator kNETC_ISFInvCFGE

Any of the following in CFGE_DATA is invalid : 1. One or more of following Entry IDs are not in valid range or Entry ID specified is not Null. Checks are performed for following Entry IDs CFGE DATA – RP_EID, SGI_EID, ISC_EID. 2. SDU_TYPE is invalid 




enumerator kNETC_ETInvOpt

Command option specified is invalid or not supported. ESQA is not 00 or 10 (others are reserved), or ECA > 1 (reserved). 




enumerator kNETC_ETInvFMEID

FM_EID format or index is out of range. Check performed is as follows : 1. EFM_EID format option type is invalid, or EFM_EID format is option 1 and the Index is out of range and not Null, or EFM_EID format is option 2 and VUDA or SQTA is out of range . 2. the Egress Counter Table index EC_EID is out of range. 3. The Egress Sequence Actions Target Entry ID ESQA_TGT_EID is out of range 




enumerator kNETC_ISGInvQSTAG

SQ_TAG specified is not valid 




enumerator kNETC_SGISGCLEIDOutRange

SGCL_EID specified in out of range for Add or Update operation. 




enumerator kNETC_SGIInvSDUTYPE

SDU_TYPE is specified is invalid for Add or Update operation. 




enumerator kNETC_SGISGCLEIDNotAlloc

Either the SGCL_EID specified as admin gate control list in Add or Update operation has not been allocated or SGCL_EID is not the first entry in gate control list or the reference count in SGCL entry is not 0. 




enumerator kNETC_SGIInvSGCLEID

SGCL_EID specified for Update operation is in invalid. 




enumerator kNETC_SGIInvADMINBASETIME

ADMIN_BASE_TIME specified for Add or Update operation is more than 2^30ns in the past. 




enumerator kNETC_SGIInvCYCLETIME

Cumulated time value of CYCLE_TIME in Stream gate Control list plus CYCLE_TIME_EXT specified in Add or Update operation is >=2^30ns or CYCLE_TIME specified is 0. 




enumerator kNETC_SGCLOverLength

Number words required for the LIST_LENGTH specified for the Add operation exceeds the number of words allocated for SGCL table 




enumerator kNETC_SGCLTimeIntervalZero

TIME_INTERVAL_GE_N specified in Add operation is 0. Note that upper 2 bits of TIME_INTERVAL_GE_N are ignored, TIME_INTERVAL_GE_N[29:0] must not be 0. 




enumerator kNETC_SGCLTimeIntervalOverflow

Cumulated time value of TIME_INTERVAL_GE_N[29:0] for the gate list specified in Add operation is >= 2^30ns. 




enumerator kNETC_FMInvEMEID

FM_EID format is invalid 




enumerator kNETC_FMOptOutRange

Following fields specified are out of range - MAC_HDR_ACT, VLAN_HDR_ACT, SQT_ACT, OUTER_PCP_DEI_ACT, PLD_ACT. 




enumerator kNETC_FMFMDOutRange

FMD_EID,FMD_BYTES specified is out of range. When FMD_EID is not set to Null, valid range is FMD_EID[15:0]*24 + FMD_BYTES <= (FMDITCAPR[NUM_WORDS]*24). 




enumerator kNETC_BPSBPEIDOutRange

SBP_EN is 1 and SBP_EID value is out-of-range in update command 






enum _netc_fm_vlan_ud_act

Frame Modification VLAN Update/Delete Action. 

Note
Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame. 

Values:


enumerator kNETC_NoUDVlanAction

No Update/Delete VLAN action 




enumerator kNETC_ReplVlanPcpAndDei

Replace outer VLAN’s PCP/DEI based on the port’s PPCPDEIMR. The tag’s original VID and TPID are preserved 




enumerator kNETC_DelVlan

Delete outer VLAN Tag 






enum _netc_fm_sqt_act

Frame Modification Sequence Tag Action. 

Note
Must be set to 000b for Ingress frame modification, otherwise misconfiguration error.. 

Values:


enumerator kNETC_NoSqtAction

No SQT action 




enumerator kNETC_ReomveRTag

Remove R-TAG/draft 2.0 R-TAG/HSR tag, If R-TAG/HSR tag not present, misconfiguration error. 






enum _netc_fm_vlan_ar_act

Frame Modification VLAN Add/Replace Action. 

Note
For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value. 

Values:


enumerator kNETC_AddCVlanPcpAndDei

Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x8100 




enumerator kNETC_AddSVlanPcpAndDei

Add outer VLAN with VID and PCP/DEI updated as described above. TPID=0x88A8 




enumerator kNETC_ReplVidOnly

Replace VLAN with VID. The tag’s original PCP, DEI and TPID are preserved 




enumerator kNETC_ReplVidPcpAndDei

Replace VLAN with VID and PCP/DEI updated by port’s PPCPDEIMR. The tag’s original TPID is preserved 






enum _netc_tb_eteid_access_mode

Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode. 

Note
The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached 

Values:


enumerator kNETC_NoETAccess

No Egress Treatment table access 




enumerator kNETC_SinglePortETAccess

Only frame sent to a special port (define in ePort) can access a single Egress Treatment table entry, the applicability bitmap specified by FDB/L2MCF/IS ePort field 




enumerator kNETC_MulitPortPackedETAccess

Only frames sent to a special set of ports (ports set to 1 in ePortBitmap) can access the Egress Treatment table, the applicability bitmap = IS ePortBitmap field or FDB/L2MCF portBitmap field 




enumerator kNETC_MulitPortAbsETAccess

Frames sent to all of ports can access the Egress Treatment table, means the applicability bitmap is set with 1 for all ports 






enum _netc_tb_ipf_update_action

Ingress Port Filter Table Update Actions. 
Values:


enumerator kNETC_IPFCfgEUpdate

Configuration Element Update 




enumerator kNETC_IPFStsEUpdate

Statistics Element Update 






enum _netc_tb_ipf_attr_mask

Ingress Port Filter frame attribute mask. 
Values:


enumerator kNETC_IPFSwtPortMasMask

Switch port masquerading Mask 




enumerator kNETC_IPFEthernetMask

Ethernet type Mask 




enumerator kNETC_IPFOuterVlanMask

Outer VLAN Mask 




enumerator kNETC_IPFInnerVlanMask

Inner VLAN Mask 




enumerator kNETC_IPFSeqTagMask

Sequence Tag Code Mask 




enumerator kNETC_IPFIpHeaderMask

IP Header Mask 




enumerator kNETC_IPFIpVersionMask

IP Version Mask 




enumerator kNETC_IPFIpExtMask

IPv4 option / IPv6 extension Mask 




enumerator kNETC_IPFL4HeaderMask

L4 Code Mask 




enumerator kNETC_IPFWakeOnLanMask

Wake-on-LAN Magic Packet Mask 






enum _netc_tb_ipf_seq_tag

Ingress Port Filter frame attribute Sequence Tag Code. 
Values:


enumerator kNETC_IPFNoRtag

R-TAG/HSR tag is not present 




enumerator kNETC_IPFDraftRtag

802.1CB draft 2.0 R-TAG is present 




enumerator kNETC_IPFRtag

802.1CB R-TAG is present 




enumerator kNETC_IPFHsrTag

HSR Tag is present 






enum _netc_tb_ipf_l4_header

Ingress Port Filter frame attribute L4 Header Code. 
Values:


enumerator kNETC_IPFOtherL4

The L4 Header is considered as other L4 if it is not one of the following L4 Headers 




enumerator kNETC_IPFTcp

TCP header is present 




enumerator kNETC_IPFUdp

UDP header is present 




enumerator kNETC_IPFSctp

SCTP header is present 






enum _netc_tb_ipf_forward_action

Ingress port filter forwarding Action. 
Values:


enumerator kNETC_IPFForwardDiscard

Frame be discard 




enumerator kNETC_IPFForwardPermit

Frame be permit 




enumerator kNETC_IPFRedirectToMgmtPort

Redirect frame to switch management port without any frame modification, Switch only 




enumerator kNETC_IPFCopyToMgmtPort

Copy frame to switch management port without any frame modification, Switch only 






enum _netc_tb_ipf_filter_action

Ingress port filter Filter Action. 
Values:


enumerator kNETC_IPFNoAction

No action 




enumerator kNETC_IPFWithRatePolicer

Rate action with the Rate Policer Entry ID (RP_EID) set to the value configured in the fltaTgt field 




enumerator kNETC_IPFWithIngressStream

Ingress stream identification action where the Ingress Stream Entry ID (IS_EID) is set to the value configured in the fltaTgt field 




enumerator kNETC_IPFWithL2Filtering

Setting a pre L2 filtering SI bitmap (set to the value configured in the fltaTgt) that will be used by the L2 filtering function to determine the final SI bitmap, ENETC only 






enum _netc_tb_isi_key_type

Stream identification table key type. 
Values:


enumerator kNETC_KCRule0

Use key construction rule 0 (ISIDKC0CR0) 




enumerator kNETC_KCRule1

Use key construction rule 1 (ISIDKC1CR0) 




enumerator kNETC_KCRule2

Use key construction rule 2 (ISIDKC2CR0). Only for SWITCH 




enumerator kNETC_KCRule3

Use key construction rule 3 (ISIDKC3CR0). Only for SWITCH 






enum _netc_tb_is_isq_action

Ingress Stream table Ingress Sequence Action. 
Values:


enumerator kNETC_ISNotPerformFRER

Not perform Frame FRER sequence generation function 




enumerator kNETC_ISPerformFRER

Perform Frame FRER sequence generation function 






enum _netc_tb_is_forward_action

Ingress Stream table forwarding Action. 
Values:


enumerator kNETC_ISDiscard

Frame be discard 




enumerator kNETC_ISRedirectToMgmtPort

Frame be Re-direct frame to switch management port, Switch only 




enumerator kNETC_ISAllow

Frame is allow without setting the pre L2 filtering SI bitmap, ENETC only 




enumerator kNETC_ISAllowWithSIMap

Frame is allow with setting the pre L2 filtering SI bitmap to the value configured in the SI_MAP field, ENETC only 




enumerator kNETC_ISStreamForward

Frame is forwarded to the port(s) specified in the EGRESS_PORT_BITMAP field, Switch only 




enumerator kNETC_ISBridgeForward

Frame is do 802.1Q Bridge forwarding (VLAN processing and L2 forwarding), Switch only 




enumerator kNETC_ISCopyToMgmtPortAndStream

Copy frame to switch management port with specified HR and stream forwarding, Switch only 




enumerator kNETC_ISCopyToMgmtPortAndBridge

Copy frame to switch management port with specified HR and Bridge forwarding, Switch only 






enum _netc_tb_is_ctd_mode

Ingress Stream table Cut-Through Disable mode. 
Values:


enumerator kNETC_ISNoCTD

Do not override cut-through state 




enumerator kNETC_ISSinglePortCTD

Disable cut-through for the outgoing port specified in the cfge ePort field 




enumerator kNETC_ISAllPortCTD

Disable cut-through for all ports specified in cfge portBitmap field 






enum _netc_tb_rp_update_action

Rate Policer Table Update Actions. 
Values:


enumerator kNETC_RPCfgEUpdate

Configuration Element Update 




enumerator kNETC_RPFeEUpdate

Functional Enable Element Update 




enumerator kNETC_RPPsEUpdate

Policer State Element Update Element Update 




enumerator kNETC_RPStsEUpdate

Statistics Element Update 






enum _netc_tb_sgi_update_action

Stream Gate Instance table Update Actions. 
Values:


enumerator kNETC_SGIAcfEUpdate

Admin Configuration Element 




enumerator kNETC_SGICfgEUpdate

Configuration Element Update 




enumerator kNETC_SGISgisEUpdate

Stream Gate Instance State Element Update 






enum _netc_tb_sgi_state

Stream Gate Instance State. 
Values:


enumerator kNETC_GSNotOper

Gate instance is not operational or Gate instance and lists are not valid 




enumerator kNETC_GSUseDefaultParam

Gate instance is operational but no stream gate control list specified, use default Gate Instance parameters 




enumerator kNETC_GSUseDefUntilAdminAct

Use default Gate Instance parameters until administrative stream gate control list takes effect 




enumerator kNETC_GSUseOperUntilAdminAct

Use Operational stream gate control list until new administrative stream gate control list takes effect 




enumerator kNETC_GSUseOperList

Operational stream gate control list is in effect 






enum _netc_tb_fm_layer2_act

Frame Modification table Layer 2 Actions. 

Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements. 

Values:


enumerator kNETC_UseL2HeaderAct

L2 actions are specified in L2 header action fields macHdrAct, vlanHdrAct and sqtAct 




enumerator kNETC_UseSpecPlayload

The entire L2 PDU is replaced with fmdBytes of data specified in fmdEID, not applicable for ingress frame modifications 






enum _netc_tb_fm_mac_header_act

Frame Modification table Layer 2 Header MAC Actions. 

Note
Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac. 

Values:


enumerator kNETC_NoMacAction

No Mac header action 




enumerator kNETC_ReplSmac

Replace SMAC with the contents of the port’s PMAR0/1 register, The port is specified by smacPort field 




enumerator kNETC_ReplSmacAndDmacAct1

Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by dmac[6] field 




enumerator kNETC_ReplSmacAndDmacAct2

Replace SMAC and DMAC, The content of SMAC is the same as kNETC_ReplaceSMAC, the DMAC is specified by frame’s SMAC 




enumerator kNETC_ReplDmac

Replace DMAC with specified dmac[6] field value 




enumerator kNETC_SwapDmacAndSmac

Swap DMAC and SMAC 






enum _netc_tb_fm_vlan_header_act

Frame Modification table Layer 2 VLAN Actions. 

Note
For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 

Values:


enumerator kNETC_NoVlanAction

No VLAN header action 




enumerator kNETC_DelOuterVlan

Delete outer VLAN header 




enumerator kNETC_AddOuterVlan

Add outer VLAN header (new VLAN data will be inserted in the outer position), the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field 




enumerator kNETC_ReplOuterVlan

Replace outer VLAN header, the VID, PCP, DEI and TPID values are specified by outerVidAct, outerPcpAct, outerDeiAct and outerTpidAct field 






enum _netc_tb_fm_outer_vid_act

Frame Modification table Layer 2 outer VLAN VID Actions. 

Note
For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 

Values:


enumerator kNETC_UseFrameVid

Use the VID from the valid outer VLAN header of the received frame 




enumerator kNETC_UseSpecVid

Use the VID specified in the outerVlanID field 






enum _netc_tb_fm_outer_tpid_act

Frame Modification table Outer TPID action. 

Note
For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 

Values:


enumerator kNETC_UseFrameTpid

Use TPID from outer VLAN header 




enumerator kNETC_UseStdCVlan

Set TPID to Standard C-VLAN 0x8100 




enumerator kNETC_UseStdSVlan

Set TPID to Standard S-VLAN 0x88A8 




enumerator kNETC_UseCustomCVlan

Set TPID to Custom C-VLAN as defined by CVLANR1[ETYPE] 




enumerator kNETC_UseCustomSVlan

Set TPID to Custom S-VLAN as defined by CVLANR2[ETYPE] 






enum _netc_tb_fm_outer_pcp_act

Frame Modification table Outer PCP action. 

Note
For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 

Values:


enumerator kNETC_UseFramePcp

Use PCP from frame outer VLAN header 




enumerator kNETC_UseSpecPcp

Use the PCP specified in the outerVlanPcp field 




enumerator kNETC_UseFramePcpMap

The PCP is mapping from frame outer VLAN PCP (do mapping according to the PCP to PCP mapping profile which specified in PPCPDEIMR[IPCPMP/EPCPMP]) 




enumerator kNETC_UseQosMap

The PCP is mapping from internal QoS (IPV, DR) (do mapping according to the QOS to PCP mapping profile which specified in QOSVLANMPaR0/1/2/3), not applicable for ingress frame modifications 






enum _netc_tb_fm_outer_dei_act

Frame Modification table Outer DEI action. 

Note
For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 

Values:


enumerator kNETC_UseFrameDei

Use DEI from frame outer VLAN header 




enumerator kNETC_UseSpecDei

Use the DEI specified in the outerVlanDei field 




enumerator kNETC_UseDrMap

The DEI is mapping from internal DR (do mapping according to the DR to DEI mapping profile which specified in PPCPDEIMR[DRnDEI], not applicable for ingress frame modifications 






enum _netc_tb_fm_payload_act

Frame Modification table Payload Actions. 

Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements. 

Values:


enumerator kNETC_NoAction

No Action 




enumerator kNETC_ReplAllEthPld

Remove entire Ethernet payload and insert with fmdBytes of data specified in fmdEID 




enumerator kNETC_ReplPldWithOffset

Replace fmdBytes of raw data in the Ethernet payload starting at pldOffset, data specified in fmdEID 






enum _netc_tb_fdb_update_action

FDB table Update Actions. 
Values:


enumerator kNETC_FDBCfgEUpdate

Configuration Element Update 




enumerator kNETC_FDBActEUpdate

Activity Element Update 






enum _netc_tb_fdb_ctd_mode

FDB table Cut-Through Disable mode. 
Values:


enumerator kNETC_FDBNoCTD

Do not override cut-through state 




enumerator kNETC_FDBSinglePortCTD

Disable cut-through for the outgoing port specified in the cfge ePort field 




enumerator kNETC_FDBAllPortCTD

Disable cut-through for all ports specified in cfge portBitmap field 






enum _netc_tb_fdb_sc_keye_mc

FDB table search criteria Key Element Match Criteria. 
Values:


enumerator kNETC_FDBKeyeMacthAny

Match any Key Element Criteria 




enumerator kNETC_FDBKeyeMacthFID

Match Key Element FID 




enumerator kNETC_FDBKeyeMacthMacMulticast

Match Key Element MAC Multicast bit (MAC_ADDR most significant byte’s least significant bit) 




enumerator kNETC_FDBKeyeMacthBoth

Match both FID field and MAC Multicast bit 






enum _netc_tb_fdb_sc_cfge_mc

FDB table search criteria Configuration Element Match Criteria. 
Values:


enumerator kNETC_FDBCfgeMacthAny

Match any Configuration Element Criteria 




enumerator kNETC_FDBCfgeMacthDynamic

Match Configuration Element dynamic field 




enumerator kNETC_FDBCfgeMacthPortBitmap

Match Configuration Element portBitmap field 




enumerator kNETC_FDBCfgeMacthBoth

Match both dynamic field and portBitmap 






enum _netc_tb_fdb_sc_acte_mc

FDB table search criteria Activity Element Match Criteria. 
Values:


enumerator kNETC_FDBActeMacthAny

Match any Activity Element Criteria 




enumerator kNETC_FDBActeMatchExact

Exact match with Activity Element 






enum _netc_tb_l2mcf_key_type

L2 IPV4 Multicast Filter table key type. 
Values:


enumerator kNETC_IPv4ASMKey

Key consists of a filtering ID (FID) and destination multicast IPv4 address 




enumerator kNETC_IPv4SSMKey

Key consists of a filtering ID (FID), IPv4 source address and multicast IPv4 destination address 






enum _etc_tb_l2mcf_sc_keye_mc

L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria. 
Values:


enumerator kNETC_L2MCFKeyeMacthAny

Match any Key Element Criteria 




enumerator kNETC_L2MCFKeyeMacthFID

Match Key Element FID 






enum _etc_tb_l2mcf_sc_cfge_mc

L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria. 
Values:


enumerator kNETC_L2MCFCfgeMacthAny

Match any Configuration Element Criteria 




enumerator kNETC_L2MCFCfgeMacthDynamic

Match Configuration Element dynamic field 




enumerator kNETC_L2MCFCfgeMacthPortBitmap

Match Configuration Element portBitmap field 




enumerator kNETC_L2MCFCfgeMacthBoth

Match both dynamic field and portBitmap 






enum _etc_tb_l2mcf_sc_acte_mc

FDB table search criteria Activity Element Match Criteria. 
Values:


enumerator kNETC_L2MCFActeMacthAny

Match any Activity Element Criteria 




enumerator kNETC_L2MCFActeMatchExact

Exact match with Activity Element 






enum _netc_tb_iseqg_sqtag

Sequence Tag Type. 
Values:


enumerator kNETC_SqDraftRTag

802.1CB draft 2.0 R-TAG. 




enumerator kNETC_SqRTag

802.1CB R-TAG. 




enumerator kNETC_SqHsrTag

HSR Tag. 






enum _netc_tb_iseqg_update_action

Ingress Sequence Generation Table Update Actions. 
Values:


enumerator kNETC_ISEQGCfgEUpdate

Configuration Element Update 




enumerator kNETC_ISEQGSgsEUpdate

Sequence Generation Element Update 






enum _netc_tb_eseqr_sqtag

Egress Sequence Recovery table Sequence Tag Type. 
Values:


enumerator kNETC_AcceptAnyTag

Accept any incoming tag type (802.1CB draft 2.0 R-TAG, 802.1CB R-TAG or HSR Tag) 




enumerator kNETC_AcceptDraftRTag

802.1CB draft 2.0 R-TAG. 




enumerator kNETC_AcceptRTag

802.1CB R-TAG. 




enumerator kNETC_AcceptHsrTag

HSR Tag. 






enum _netc_tb_tgs_entry_id

Time Gate Scheduling table entry ID for switch and ENETC. 
Values:


enumerator kNETC_TGSSwtPort0

Switch PORT 0 entry ID 




enumerator kNETC_TGSSwtPort1

Switch PORT 1 entry ID 




enumerator kNETC_TGSSwtPort2

Switch PORT 2 entry ID 




enumerator kNETC_TGSSwtPort3

Switch PORT 3 entry ID 




enumerator kNETC_TGSSwtPort4

Switch PORT 4 entry ID 




enumerator kNETC_TGSEnetc0Port

ENETC 0 port entry ID 




enumerator kNETC_TGSEnetc1Port

ENETC 1 port entry ID 






enum _netc_tb_tgs_gate_type

Administrative gate operation type. 
Values:


enumerator kNETC_SetGateStates

HoldRequest is unchanged 




enumerator kNETC_SetAndHoldMac

HoldRequest is set to value hold, only active when enable preemption 




enumerator kNETC_SetAndReleaseMac

HoldRequest is set to value release, only active when enable preemption 






enum _netc_tb_et_efm_mode

Egress Frame Modification entry mode. 
Values:


enumerator kNETC_NormalMode

Egress Frame Modification entry use normal/Default mode 




enumerator kNETC_L2Act1

Egress Frame Modification entry l2Act = kNETC_UseSpecPlayload 




enumerator kNETC_PldAct1

Egress Frame Modification entry pldAct = kNETC_ReplAllEthPld 






enum _netc_tb_et_esq_act

Egress Sequence Actions. 
Values:


enumerator kNETC_NoEsqAction

No Egress Sequence Action required 




enumerator kNETC_HasEsqAction

Has Egress Sequence Recovery action 






enum _netc_tb_et_ec_act

Egress Counter Action. 
Values:


enumerator kNETC_NoEcCounter

Do not increment egress frame counter 




enumerator kNETC_HasEcCounter

Increment egress frame counter 






enum _netc_tb_etmcq_update_action

ETM Class Queue table Update Actions. 
Values:


enumerator kNETC_CQCfgEUpdate

Configuration Element Update 




enumerator kNETC_CQStsEUpdate

Statistics Element Update, all counters (except FRM_CNT) within the Statistics Element are reset 






enum _netc_tb_etmcs_entry_id

ETM Class Scheduler table entry ID. 
Values:


enumerator kNETC_CSSwtPort0

CS Switch PORT 0 entry ID 




enumerator kNETC_CSSwtPort1

CS Switch PORT 1 entry ID 




enumerator kNETC_CSSwtPort2

CS Switch PORT 2 entry ID 




enumerator kNETC_CSSwtPort3

CS Switch PORT 3 entry ID 




enumerator kNETC_CSSwtPort4

CS Switch PORT 4 entry ID 






enum _netc_tb_etmcs_ca_assg

ETM Class Scheduler table Class queue assignment to scheduler inputs mode. 
Values:


enumerator kNETC_CQ7AssignToSchedIn15

CQ 7 assignment to scheduler input 15, means all CQ use strict priority 




enumerator kNETC_CQ7AssignToSchedIn14

CQ 7 assignment to scheduler input 14 




enumerator kNETC_CQ7AssignToSchedIn13

CQ 7 assignment to scheduler input 13 




enumerator kNETC_CQ7AssignToSchedIn12

CQ 7 assignment to scheduler input 12 




enumerator kNETC_CQ7AssignToSchedIn11

CQ 7 assignment to scheduler input 11 




enumerator kNETC_CQ7AssignToSchedIn10

CQ 7 assignment to scheduler input 10 




enumerator kNETC_CQ7AssignToSchedIn9

CQ 7 assignment to scheduler input 9 




enumerator kNETC_CQ7AssignToSchedIn8

CQ 7 assignment to scheduler input 8 




enumerator kNETC_CQ7AssignToSchedIn7

CQ 7 assignment to scheduler input 7, means all CQ use weighted fair 






enum _netc_tb_bp_fc_cfg

Buffer Pool Flow Control (FC) Configuration. 
Values:


enumerator kNETC_FlowCtrlDisable

Flow Control disabled 




enumerator kNETC_FlowCtrlWithBP

Flow Control enabled using only buffer pool FC state. 




enumerator kNETC_FlowCtrlWithSBP

Flow Control enabled using only shared buffer pool FC state. 




enumerator kNETC_FlowCtrlWithBPAndSBP

Flow Control enabled using both buffer pool and shared buffer pool FC state, only both 1 trigger the Flow Control ON 






typedef enum _netc_tb_index netc_tb_index_t

Table index. 




typedef enum _netc_tb_cmd netc_tb_cmd_t

Table management command operations. 




typedef enum _netc_tb_access_mode netc_tb_access_mode_t

Table Access Method. 




typedef enum _netc_cbd_version netc_cbd_version_t

NTMP version. 




typedef enum _netc_cmd_error netc_cmd_error_t

Table command response error status. 




typedef union _netc_cmd_bd netc_cmd_bd_t

The Switch/SI command BD data structure. 




typedef struct _netc_cmd_bdr_config netc_cmd_bdr_config_t

Configuration for the Switch/SI command BD Ring Configuration. 




typedef struct _netc_cmd_bdr netc_cmd_bdr_t

The Switch/SI command BD ring handle data structure. 




typedef struct _netc_tb_common_header netc_tb_common_header_t

Table request data buffer common header. 




typedef enum _netc_fm_vlan_ud_act netc_fm_vlan_ud_act_t

Frame Modification VLAN Update/Delete Action. 

Note
Misconfiguration error if replace or delete action is specified and if VLAN tag is not present in frame. 





typedef enum _netc_fm_sqt_act netc_fm_sqt_act_t

Frame Modification Sequence Tag Action. 

Note
Must be set to 000b for Ingress frame modification, otherwise misconfiguration error.. 





typedef enum _netc_fm_vlan_ar_act netc_fm_vlan_ar_act_t

Frame Modification VLAN Add/Replace Action. 

Note
For ingress frame modificaion with 00b or 01b, use the ingress port to select PCP and DEI from the Bridge port default VLAN register (BPDVR). For egress frame modification with 00b or 01b, use the internal QoS associated with the frame (IPV, DR) to access the QoS to PCP mapping profile (PQOSMR[QVMP] , QOSVLANMPaR0/1/2/3) to set the new PCP value. Use internal DR associated with frame to access the DR to DEI mapping profile (PPCPDEIMR[DRnDEI]) to set the new DEI value. 





typedef enum _netc_tb_eteid_access_mode netc_tb_eteid_access_mode_t

Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode. 

Note
The FDB/L2 IPv4 Multicast filter table has precedence over any assignment made via the Ingress Stream table. For Mulit port mode, the index to access the Egress Treatment table is computed by adding an offset to the base index of the Egress Treatment group. That offset is derived from the applicability bitmap as follows: starting from the lowest significant bit of the bitmap, the first encountered bit set to 1, corresponds to offset 0, and so on. This continues till the destination port location in the bitmap is reached 





typedef enum _netc_tb_ipf_update_action netc_tb_ipf_update_action_t

Ingress Port Filter Table Update Actions. 




typedef enum _netc_tb_ipf_attr_mask netc_tb_ipf_attr_mask_t

Ingress Port Filter frame attribute mask. 




typedef enum _netc_tb_ipf_seq_tag netc_tb_ipf_seq_tag_t

Ingress Port Filter frame attribute Sequence Tag Code. 




typedef enum _netc_tb_ipf_l4_header netc_tb_ipf_l4_header_t

Ingress Port Filter frame attribute L4 Header Code. 




typedef struct _netc_tb_ipf_keye netc_tb_ipf_keye_t

Ingress Port Filter key element. 




typedef enum _netc_tb_ipf_forward_action netc_tb_ipf_forward_action_t

Ingress port filter forwarding Action. 




typedef enum _netc_tb_ipf_filter_action netc_tb_ipf_filter_action_t

Ingress port filter Filter Action. 




typedef struct _netc_tb_ipf_cfge netc_tb_ipf_cfge_t

Ingress port filter config element. 




typedef struct _netc_tb_ipf_stse netc_tb_ipf_stse_t

Ingress port filter statistic element. 




typedef struct _netc_tb_ipf_req_data netc_tb_ipf_req_data_t

Ingress port filter table entry config. 




typedef struct _netc_tb_ipf_rsp_data netc_tb_ipf_rsp_data_t

Ingress port filter table response data. 




typedef struct _netc_tb_ipf_data netc_tb_ipf_data_t

Ingress Port filter table data buffer. 




typedef struct _netc_tb_ipf_config netc_tb_ipf_config_t

Ingress Port filter entry config. 




typedef enum _netc_tb_isi_key_type netc_tb_isi_key_type

Stream identification table key type. 




typedef struct _netc_tb_isi_keye netc_tb_isi_keye_t

Stream identification table key element. 




typedef struct _netc_tb_isi_cfge netc_tb_isi_cfge_t

Stream identification table config element. 




typedef struct _netc_tb_isi_req_data netc_tb_isi_req_data_t

Stream identification table request data buffer. 




typedef struct _netc_tb_isi_rsp_data netc_tb_isi_rsp_data_t

Stream identification table request response data buffer. 




typedef struct _netc_tb_isi_data netc_tb_isi_data_t

Stream identification table data buffer. 




typedef struct _netc_tb_isi_config netc_tb_isi_config_t

Stream identification table entry config. 




typedef enum _netc_tb_is_isq_action netc_tb_is_isq_action_t

Ingress Stream table Ingress Sequence Action. 




typedef enum _netc_tb_is_forward_action netc_tb_is_forward_action_t

Ingress Stream table forwarding Action. 




typedef enum _netc_tb_is_ctd_mode netc_tb_is_ctd_mode_t

Ingress Stream table Cut-Through Disable mode. 




typedef netc_tb_eteid_access_mode_t netc_tb_is_oeteid_mode_t

Ingress Stream table Override ET_EID mode. 




typedef struct _netc_tb_is_cfge netc_tb_is_cfge_t

Ingress Stream table config element. 




typedef struct _netc_tb_is_req_data netc_tb_is_req_data_t

Ingress Stream table request data buffer. 




typedef struct _netc_tb_is_rsp_data netc_tb_is_rsp_data_t

Ingress Stream table request response data buffer. 




typedef struct _netc_tb_is_data netc_tb_is_data_t

Ingress Stream table data buffer. 




typedef struct _netc_tb_is_config netc_tb_is_config_t

Ingress Stream table entry config. 




typedef struct _netc_tb_isf_keye netc_tb_isf_keye_t

Ingress Stream Filter table key element. 




typedef struct _netc_tb_isf_cfge netc_tb_isf_cfge_t

Ingress Stream Filter table config element. 




typedef struct _netc_tb_isf_req_data netc_tb_isf_req_data_t

Ingress Stream Filter table request data buffer. 




typedef struct _netc_tb_isf_rsp_data netc_tb_isf_rsp_data_t

Ingress Stream Filter table request response data buffer. 




typedef struct _netc_tb_isf_data netc_tb_isf_data_t

Ingress Stream Filter table data buffer. 




typedef struct _netc_tb_isf_config netc_tb_isf_config_t

Ingress Stream Filter table entry config. 




typedef enum _netc_tb_rp_update_action netc_tb_rp_update_action_t

Rate Policer Table Update Actions. 




typedef netc_tc_sdu_type_t netc_tb_rp_sdu_type_t

Rate Policer Table Protocol/Service Data Unit Type. 




typedef struct _netc_tb_rp_cfge netc_tb_rp_cfge_t

Rate Policer table config element. 




typedef struct _netc_tb_rp_fee netc_tb_rp_fee_t

Rate Policer table Function Enable element. 




typedef struct _netc_tb_rp_pse netc_tb_rp_pse_t

Rate Policer table Policer State element. 




typedef struct _netc_tb_rp_stse netc_tb_rp_stse_t

Rate Policer table statistic element. 




typedef struct _netc_tb_rp_req_data netc_tb_rp_req_data_t

Rate Policer table request data buffer. 




typedef struct _netc_tb_rp_rsp_data netc_tb_rp_rsp_data_t

Rate Policer table request response data buffer. 




typedef struct _netc_tb_rp_data netc_tb_rp_data_t

Rate Policer table data buffer. 




typedef struct _netc_tb_rp_config netc_tb_rp_config_t

Rate Policer table entry config. 




typedef struct _netc_tb_isc_stse netc_tb_isc_stse_t

Ingress Stream Count table statistic element. 




typedef struct _netc_tb_isc_req_data netc_tb_isc_req_data_t

Ingress Stream Count table request data buffer. 




typedef struct _netc_tb_isc_rsp_data netc_tb_isc_rsp_data_t

Ingress Stream Count table request response data buffer. 




typedef struct _netc_tb_isc_data netc_tb_isc_data_t

Ingress Stream Count table data buffer. 




typedef enum _netc_tb_sgi_update_action netc_tb_sgi_update_action_t

Stream Gate Instance table Update Actions. 




typedef netc_tc_sdu_type_t netc_tb_sgi_sdu_type_t

Stream Gate Instance table Protocol/Service Data Unit Type. 




typedef enum _netc_tb_sgi_state netc_tb_sgi_state_t

Stream Gate Instance State. 




typedef struct _netc_tb_sgi_cfge netc_tb_sgi_cfge_t

Stream Gate Instance table config element. 




typedef struct _netc_tb_sgi_acfge netc_tb_sgi_acfge_t

Stream Gate Instance table Admin Configuration element. 




typedef struct _netc_tb_sgi_icfge netc_tb_sgi_icfge_t

Stream Gate Instance table Initial Configuration element. 




typedef struct _netc_tb_sgi_sgise netc_tb_sgi_sgise_t

Stream Gate Instance table stream gate instance state element. 




typedef struct _netc_tb_sgi_req_data netc_tb_sgi_req_data_t

Stream Gate Instance table request data buffer. 




typedef struct _netc_tb_sgi_rsp_data netc_tb_sgi_rsp_data_t

Stream Gate Instance table request response data buffer. 




typedef struct _netc_tb_sgi_data netc_tb_sgi_data_t

Stream Gate Instance table data buffer. 




typedef struct _netc_tb_sgi_config netc_tb_sgi_config_t

Stream Gate Instance table entry config. 




typedef struct _netc_sgcl_gate_entry netc_sgcl_gate_entry_t

Defines the Stream Gate Control entry structure. 




typedef struct _netc_tb_sgcl_cfge netc_tb_sgcl_cfge_t

Stream Gate Control List table config element. 




typedef struct _netc_tb_sgcl_sgclse netc_tb_sgcl_sgclse_t

Stream Gate Control List table Stream Gate Control List State element. 




typedef struct _netc_tb_sgcl_req_data netc_tb_sgcl_req_data_t

Stream Gate Control List table request data buffer. 




typedef struct _netc_tb_sgcl_rsp_data netc_tb_sgcl_rsp_data_t

Stream Gate Control List table request response data buffer. 




typedef struct _netc_tb_sgcl_data netc_tb_sgcl_data_t

Stream Gate Control List table data buffer. 




typedef struct _netc_tb_sgcl_gcl netc_tb_sgcl_gcl_t

Stream Gate Control List table entry gate control list structure. 




typedef enum _netc_tb_fm_layer2_act netc_tb_fm_layer2_act_t

Frame Modification table Layer 2 Actions. 

Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements. 





typedef enum _netc_tb_fm_mac_header_act netc_tb_fm_mac_header_act_t

Frame Modification table Layer 2 Header MAC Actions. 

Note
Ingress frame modifications only support kNETC_NoAction or kNETC_ReplDmac. 





typedef enum _netc_tb_fm_vlan_header_act netc_tb_fm_vlan_header_act_t

Frame Modification table Layer 2 VLAN Actions. 

Note
For use Delete or Replace action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef enum _netc_tb_fm_outer_vid_act netc_tb_fm_outer_vid_act_t

Frame Modification table Layer 2 outer VLAN VID Actions. 

Note
For use kNETC_UseFrameVID action, if no outer VLAN header is present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef netc_fm_sqt_act_t netc_tb_fm_sqt_act_t

Frame Modification table Sequence Tag Action. 

Note
For use kNETC_ReomveTag action, If R-TAG/draft 2.0 R-TAG/HSR tag not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef enum _netc_tb_fm_outer_tpid_act netc_tb_fm_outer_tpid_act_t

Frame Modification table Outer TPID action. 

Note
For use kNETC_UseFrameTpid action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef enum _netc_tb_fm_outer_pcp_act netc_tb_fm_outer_pcp_act_t

Frame Modification table Outer PCP action. 

Note
For use kNETC_UseFramePcp/kNETC_UseFramePcpMap action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef enum _netc_tb_fm_outer_dei_act netc_tb_fm_outer_dei_act_t

Frame Modification table Outer DEI action. 

Note
For use kNETC_UseFrameDei action, If outer VLAN header not present, then a misconfiguration event will be generated and handled according to the port’s PFMCR register. 





typedef enum _netc_tb_fm_payload_act netc_tb_fm_payload_act_t

Frame Modification table Payload Actions. 

Note
This field must be set to 0 for traffic destined to a pseudo link. This field must be set to 0 for any device with ASIL-B safety requirements. 





typedef struct _netc_tb_fm_cfge netc_tb_fm_cfge_t

Frame Modification table config element. 




typedef struct _netc_tb_fm_req_data netc_tb_fm_req_data_t

Frame Modification table request data buffer. 




typedef struct _netc_tb_fm_rsp_data netc_tb_fm_rsp_data_t

Frame Modification table request response data buffer. 




typedef struct _netc_tb_fm_data netc_tb_fm_data_t

Frame Modification table data buffer. 




typedef struct _netc_tb_fm_config netc_tb_fm_config_t

Frame Modification table entry config. 




typedef struct _netc_tb_fmd_req_data netc_tb_fmd_req_data_t

Frame Modification Data table request data buffer. 




typedef struct _netc_tb_fmd_rsp_data netc_tb_fmd_rsp_data_t

Frame Modification Data table request response data buffer. 




typedef struct _netc_tb_fmd_data netc_tb_fmd_data_t

Frame Modification Data table data buffer. 




typedef struct _netc_tb_fmd_update_config netc_tb_fmd_update_config_t

Frame Modification data table entry update config. 




typedef struct _netc_tb_fmd_query_buffer netc_tb_fmd_query_buffer_t

Frame Modification data table entry query data buffer. 




typedef struct _netc_tb_vf_keye netc_tb_vf_keye_t

Vlan Filter table key element. 




typedef struct _netc_tb_vf_cfge netc_tb_vf_cfge_t

Vlan Filter table config element. 




typedef struct _netc_tb_vf_search_criteria netc_tb_vf_search_criteria_t

Vlan Filter table search criteria format. 




typedef struct _netc_tb_vf_req_data netc_tb_vf_req_data_t

Vlan Filter table request data buffer. 




typedef struct _netc_tb_vf_rsp_data netc_tb_vf_rsp_data_t

Vlan Filter table request response data buffer. 




typedef struct _netc_tb_vf_data netc_tb_vf_data_t

Vlan Filter table data buffer. 




typedef struct _netc_tb_vf_config netc_tb_vf_config_t

Vlan Filter table entry config. 




typedef enum _netc_tb_fdb_update_action netc_tb_fdb_update_action_t

FDB table Update Actions. 




typedef netc_tb_eteid_access_mode_t netc_tb_fdb_oeteid_mode_t

FDB table entry defined the egress packet processing actions (will cover the actions which specified in the Egress Treatment table ) 




typedef enum _netc_tb_fdb_ctd_mode netc_tb_fdb_ctd_mode_t

FDB table Cut-Through Disable mode. 




typedef struct _netc_tb_fdb_keye netc_tb_fdb_keye_t





typedef struct _netc_tb_fdb_cfge netc_tb_fdb_cfge_t

FDB table configuration element. 




typedef struct _netc_tb_fdb_acte netc_tb_fdb_acte_t

FDB table Activity element. 




typedef enum _netc_tb_fdb_sc_keye_mc netc_tb_fdb_sc_keye_mc_t

FDB table search criteria Key Element Match Criteria. 




typedef enum _netc_tb_fdb_sc_cfge_mc netc_tb_fdb_sc_cfge_mc_t

FDB table search criteria Configuration Element Match Criteria. 




typedef enum _netc_tb_fdb_sc_acte_mc netc_tb_fdb_sc_acte_mc_t

FDB table search criteria Activity Element Match Criteria. 




typedef struct _netc_tb_fdb_search_criteria netc_tb_fdb_search_criteria_t

FDB table search criteria format. 




typedef struct _netc_tb_fdb_req_data netc_tb_fdb_req_data_t

FDB table request data buffer. 




typedef struct _netc_tb_fdb_rsp_data netc_tb_fdb_rsp_data_t

FDB table request response data buffer. 




typedef struct _netc_tb_fdb_data netc_tb_fdb_data_t

FDB table data buffer. 




typedef struct _netc_tb_fdb_config netc_tb_fdb_config_t

FDB table entry config. 




typedef enum _netc_tb_l2mcf_key_type netc_tb_l2mcf_key_type_t

L2 IPV4 Multicast Filter table key type. 




typedef struct _netc_tb_l2mcf_keye netc_tb_l2mcf_keye_t

L2 IPV4 Multicast Filter table key element. 




typedef enum _etc_tb_l2mcf_sc_keye_mc etc_tb_l2mcf_sc_keye_mc_t

L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria. 




typedef enum _etc_tb_l2mcf_sc_cfge_mc etc_tb_l2mcf_sc_cfge_mc_t

L2 IPV4 Multicast Filter table search criteria Configuration Element Match Criteria. 




typedef enum _etc_tb_l2mcf_sc_acte_mc etc_tb_l2mcf_sc_acte_mc_t

FDB table search criteria Activity Element Match Criteria. 




typedef netc_tb_fdb_cfge_t netc_tb_l2mcf_cfge_t

L2 IPV4 Multicast Filter table config element. 




typedef netc_tb_fdb_acte_t netc_tb_l2mcf_acte_t

L2 IPV4 Multicast Filter table activity lement. 




typedef struct _etc_tb_l2mcf_search_criteria netc_tb_l2mcf_search_criteria_t

L2 IPV4 Multicast Filter table search criteria format. 




typedef struct _netc_tb_l2mcf_req_data netc_tb_l2mcf_req_data_t

L2 IPV4 Multicast Filter table request data buffer. 




typedef struct _netc_tb_l2mcf_rsp_data netc_tb_l2mcf_rsp_data_t

L2 IPV4 Multicast Filter table request response data buffer. 




typedef struct _netc_tb_l2mcf_data netc_tb_l2mcf_data_t

L2 IPV4 Multicast Filter table data buffer. 




typedef struct _netc_tb_l2mcf_config netc_tb_l2mcf_config_t

L2 IPV4 Multicast Filter table entry config. 




typedef enum _netc_tb_iseqg_sqtag netc_tb_iseqg_sqtag_t

Sequence Tag Type. 




typedef struct _netc_tb_iseqg_cfge netc_tb_iseqg_cfge_t

Ingress Sequence Generation table config element. 




typedef struct _netc_tb_iseqg_sgse netc_tb_iseqg_sgse_t

Ingress Sequence Generation table Sequence generation state element. 




typedef struct _netc_tb_iseqg_req_data netc_tb_iseqg_req_data_t

Ingress Sequence Generation table request data buffer. 




typedef struct _netc_tb_iseqg_rsp_data netc_tb_iseqg_rsp_data_t

Ingress Sequence Generation table request response data buffer. 




typedef struct _netc_tb_iseqg_data netc_tb_iseqg_data_t

Ingress Sequence Generation table data buffer. 




typedef struct _netc_tb_iseqg_config netc_tb_iseqg_config_t

Ingress Sequence Generation table entry config. 




typedef enum _netc_tb_iseqg_update_action netc_tb_iseqg_update_action_t

Ingress Sequence Generation Table Update Actions. 




typedef enum _netc_tb_eseqr_sqtag netc_tb_eseqr_sqtag_t

Egress Sequence Recovery table Sequence Tag Type. 




typedef struct _netc_tb_eseqr_cfge netc_tb_eseqr_cfge_t

Egress Sequence Recovery table config element. 




typedef struct _netc_tb_eseqr_stse netc_tb_eseqr_stse_t

Egress Sequence Recovery table statistic element. 




typedef struct _netc_tb_eseqr_srse netc_tb_eseqr_srse_t

Egress Sequence Recovery table sequence recovery state element. 




typedef struct _netc_tb_eseqr_req_data netc_tb_eseqr_req_data_t

Egress Sequence Recovery table request data buffer. 




typedef struct _netc_tb_eseqr_rsp_data netc_tb_eseqr_rsp_data_t

Egress Sequence Recovery table request response data buffer. 




typedef struct _netc_tb_eseqr_data netc_tb_eseqr_data_t

Egress Sequence Recovery table data buffer. 




typedef struct _netc_tb_eseqr_config netc_tb_eseqr_config_t

Egress Sequence Recovery table entry config. 




typedef enum _netc_tb_tgs_entry_id netc_tb_tgs_entry_id_t

Time Gate Scheduling table entry ID for switch and ENETC. 




typedef enum _netc_tb_tgs_gate_type netc_tb_tgs_gate_type_t

Administrative gate operation type. 




typedef struct _netc_tgs_gate_entry netc_tgs_gate_entry_t

Defines the Time Gate Scheduling gate control entry structure. 




typedef struct _netc_tb_tgs_cfge netc_tb_tgs_cfge_t

Time Gate Scheduling table config element. 




typedef struct _netc_tb_tgs_olse netc_tb_tgs_olse_t

Time Gate Scheduling table statistic element. 




typedef struct _netc_tb_tgs_req_data netc_tb_tgs_req_data_t

Time Gate Scheduling table request data buffer. 




typedef struct _netc_tb_tgs_rsp_data netc_tb_tgs_rsp_data_t

Time Gate Scheduling table request response data buffer. 




typedef struct _netc_tb_tgs_data netc_tb_tgs_data_t

Time Gate Scheduling table data buffer, set with max size. 




typedef struct _netc_tb_tgs_gcl netc_tb_tgs_gcl_t

Time Gate Scheduling table entry gate control list structure. 




typedef enum _netc_tb_et_efm_mode netc_tb_et_efm_mode_t

Egress Frame Modification entry mode. 




typedef enum _netc_tb_et_esq_act netc_tb_et_esq_act_t

Egress Sequence Actions. 




typedef enum _netc_tb_et_ec_act netc_tb_et_ec_act_t

Egress Counter Action. 




typedef struct _netc_tb_et_cfge netc_tb_et_cfge_t

Egress Treatment table config element. 




typedef struct _netc_tb_et_req_data netc_tb_et_req_data_t

Egress Treatment table request data buffer. 




typedef struct _netc_tb_et_rsp_data netc_tb_et_rsp_data_t

Egress Treatment table request response data buffer. 




typedef struct _netc_tb_et_data netc_tb_et_data_t

Egress Treatment table data buffer. 




typedef struct _netc_tb_et_config netc_tb_et_config_t

Egress Treatment table entry config. 




typedef enum _netc_tb_etmcq_update_action netc_tb_etmcq_update_action_t

ETM Class Queue table Update Actions. 




typedef struct _netc_tb_etmcq_cfge netc_tb_etmcq_cfge_t

ETM Class Queue table config element. 




typedef struct _netc_tb_etmcq_stse netc_tb_etmcq_stse_t

ETM Class Queue table statistic element. 




typedef struct _netc_tb_etmcq_req_data netc_tb_etmcq_req_data_t

ETM Class Queue table request data buffer. 




typedef struct _netc_tb_etmcq_rsp_data netc_tb_etmcq_rsp_data_t

ETM Class Queue table request response data buffer. 




typedef struct _netc_tb_etmcq_data netc_tb_etmcq_data_t

ETM Class Queue table data buffer. 




typedef struct _netc_tb_etmcq_config netc_tb_etmcq_config_t

ETM Class Queue table entry config. 




typedef enum _netc_tb_etmcs_entry_id netc_tb_etmcs_entry_id_t

ETM Class Scheduler table entry ID. 




typedef enum _netc_tb_etmcs_ca_assg netc_tb_etmcs_ca_assg_t

ETM Class Scheduler table Class queue assignment to scheduler inputs mode. 




typedef struct _netc_tb_etmcs_cfge netc_tb_etmcs_cfge_t

ETM Class Scheduler table config element. 




typedef struct _netc_tb_etmcs_req_data netc_tb_etmcs_req_data_t

ETM Class Scheduler table request data buffer. 




typedef struct _netc_tb_etmcs_rsp_data netc_tb_etmcs_rsp_data_t

ETM Class Scheduler table request response data buffer. 




typedef struct _netc_tb_etmcs_data netc_tb_etmcs_data_t

ETM Class Scheduler table data buffer. 




typedef struct _netc_tb_etmcs_config netc_tb_etmcs_config_t

ETM Class Scheduler table entry config. 




typedef struct _netc_tb_etmcg_cfge netc_tb_etmcg_cfge_t

ETM Congestion Group table config element. 




typedef struct _netc_tb_etmcg_stse netc_tb_etmcg_stse_t

ETM Congestion Group table statistic element. 




typedef struct _netc_tb_etmcg_req_data netc_tb_etmcg_req_data_t

ETM Congestion Group table request data buffer. 




typedef struct _netc_tb_etmcg_rsp_data netc_tb_etmcg_rsp_data_t

ETM Congestion Group table request response data buffer. 




typedef struct _netc_tb_etmcg_data netc_tb_etmcg_data_t

ETM Congestion Group table data buffer. 




typedef struct _netc_tb_etmcg_config netc_tb_etmcg_config_t

ETM Congestion Group table entry config. 




typedef struct _netc_tb_ec_stse netc_tb_ec_stse_t

Egress Count table statistic element. 




typedef struct _netc_tb_ec_req_data netc_tb_ec_req_data_t

Egress Count table request data buffer. 




typedef struct _netc_tb_ec_rsp_data netc_tb_ec_rsp_data_t

Egress Count table request response data buffer. 




typedef struct _netc_tb_ec_data netc_tb_ec_data_t

Egress Count table data buffer. 




typedef enum _netc_tb_bp_fc_cfg netc_tb_bp_fc_cfg_t

Buffer Pool Flow Control (FC) Configuration. 




typedef struct _netc_tb_bp_cfge netc_tb_bp_cfge_t

Buffer Pool table config element. 




typedef struct _netc_tb_bp_bpse netc_tb_bp_bpse_t

Buffer Pool table State Element Data. 




typedef struct _netc_tb_bp_req_data netc_tb_bp_req_data_t

Buffer Pool table request data buffer. 




typedef struct _netc_tb_bp_rsp_data netc_tb_bp_rsp_data_t

Buffer Pool table request response data buffer. 




typedef struct _netc_tb_bp_data netc_tb_bp_data_t

Buffer Pool table data buffer. 




typedef struct _netc_tb_bp_config netc_tb_bp_config_t

Buffer Pool table entry config. 




typedef struct _netc_tb_sbp_cfge netc_tb_sbp_cfge_t

Shared Buffer Pool table config element. 




typedef struct _netc_tb_sbp_sbpse netc_tb_sbp_sbpse_t

Shared Buffer Pool table State Element Data. 




typedef struct _netc_tb_sbp_req_data netc_tb_sbp_req_data_t

Shared Buffer Pool table request data buffer. 




typedef struct _netc_tb_sbp_rsp_data netc_tb_sbp_rsp_data_t

Shared Buffer Pool table request response data buffer. 




typedef struct _netc_tb_sbp_data netc_tb_sbp_data_t

Shared Buffer Pool table data buffer. 




typedef struct _netc_tb_sbp_config netc_tb_sbp_config_t

Shared Buffer Pool table entry config. 




typedef union _netc_tb_data_buffer netc_tb_data_buffer_t

Table common data buffer. 




typedef struct _netc_cbdr_hw netc_cbdr_hw_t

Register group for SI/Switch command bd ring. 




typedef struct _netc_cbdr_handle netc_cbdr_handle_t

Handle for common part of EP/Switch NTMP. 




status_t NETC_CmdBDRInit(netc_cbdr_hw_t *base, const netc_cmd_bdr_config_t *config)

Initialize the command BD ring. 

Parameters:

base – 
config – 


Returns:
kStatus_Success 

Returns:
kStatus_Fail 






status_t NETC_CmdBDRDeinit(netc_cbdr_hw_t *base)

Deinitialize the command BD ring. 

Parameters:

base – 


Returns:
kStatus_Success 






status_t NETC_CmdBDSendCommand(netc_cbdr_hw_t *base, netc_cmd_bdr_t *cbdr, netc_cmd_bd_t *cbd, netc_cbd_version_t version)

Send the Command Buffer Descriptor to operate on a NTMP table. 

Parameters:

base – 
cbdr – 
cbd – 
version – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddIPFTableEntry(netc_cbdr_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)

Add entry into the ingress Port Filter Table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_UpdateIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)

Update entry in the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ipf_config_t *config)

Query entry in the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_ResetIPFMatchCounter(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset the counter of an ingress port filter Table entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetIPFMatchedCount(netc_cbdr_handle_t *handle, uint32_t entryID, uint64_t *count)

Get the matched count of an ingress port filter Table entry. 

Parameters:

handle – 
entryID – 
count – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddISITableEntry(netc_cbdr_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)

Add entry into Ingress Stream Identification table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream identification table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isi_config_t *config)

Query Ingress Stream Identification table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp)

Query Ingress Stream Identification table with key. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddOrUpdateISTableEntry(netc_cbdr_handle_t *handle, netc_tb_is_config_t *config, bool isAdd)

Add or update entry in Ingress Stream table. 

Parameters:

handle – 
config – 
isAdd – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_is_config_t *config)

Query Ingress Stream table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)

Add entry into ingress stream filter table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_UpdateISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)

Update entry into ingress stream filter table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelISFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete an entry in Ingress stream filter table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryISFTableEntry(netc_cbdr_handle_t *handle, netc_tb_isf_keye_t *keye, netc_tb_isf_rsp_data_t *rsp)

Query entry from the Ingress stream filter table. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddISCTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Add entry in ingress stream count table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 






status_t NETC_GetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)

Get ingress stream count statistic. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_ResetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset the count of the ingress stream count. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddOrUpdateSGITableEntry(netc_cbdr_handle_t *handle, netc_tb_sgi_config_t *config, bool isAdd)

Add or update entry in stream gate instance table. 

Parameters:

handle – 
config – 
isAdd – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_ResetIRXOEXSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset IRX and OEX flags in stream gate instance entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry in the stream gate instance table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *statis)

Get statistic of specified stream gate instance table entry. 

Parameters:

handle – 
entryID – 
statis – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config)

Query entry from the stream gate instance table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddSGCLTableEntry(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *config)

Add entry into Stream Gate Control List Table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelSGCLTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry of Stream Gate Control List Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetSGCLGateList(netc_cbdr_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)

Get Stream Gate Control List Table entry gate control list. 

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetSGCLState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)

Get state (ref count) for Stream Gate Control List table entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_QueryRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp)

Query entry from the Rate Policer table. 

Parameters:

handle – 
entryID – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_AddOrUpdateRPTableEntry(netc_cbdr_handle_t *handle, netc_tb_rp_config_t *config, netc_tb_cmd_t cmd)

Add or update entry in Rate Policer table. 

Parameters:

handle – 
config – 
cmd – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_DelRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Delete entry in the Rate Policer table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetRPStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)

Get statistic of specified Rate Policer table entry. 

Parameters:

handle – 
entryID – 
statis – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_ResetMRRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID)

Reset mark red parameter of specified Rate Policer table entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_ConfigTGSAdminList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *config)

Config the QBV (Time Gate Scheduling) 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t NETC_GetTGSOperationList(netc_cbdr_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)

Get time gate table operation list. 

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






NETC_FD_EID_ENCODE_OPTION_0(entryId)

Frame Modification Entry ID encode options. 

Note
sqta should be netc_fm_sqt_act_t type, vuda should be netc_fm_vlan_ud_act_t type and vara should be netc_fm_vlan_ar_act_t type. 





NETC_FD_EID_ENCODE_OPTION_1(sqta, vuda)





NETC_FD_EID_ENCODE_OPTION_2(vara, vid)





NETC_ISI_VLAN_FRAME_KEY(valid, pcp, vid)

2 Bytes VLAN field which may added to the frame Key 




NETC_TB_SGCL_MAX_ENTRY

Stream Gate Control List Table maximum gate control list length. 




NETC_TB_FMD_UPDATE_CONFIG_LENGTH(x)

TFrame Modification Data table update config Data Buffer length, x is the number of update data bytes. 




NETC_TB_TGS_MAX_ENTRY

Time Gate Scheduling Table maximum gate control list length (TGSTCAPR[MAX_GCL_LEN]) 




NETC_TB_ETM_CQ_ENTRY_ID(portID, cqID)

ETM Class Queue table entry ID macro, cqID is represents the Class Queue ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4. 




NETC_TB_ETM_CG_ENTRY_ID(portID, cgID)

ETM Congestion Group table entry ID macro, cgID is represents the Congestion Group ID ,rang in 0 ~ 7, portID is Switch ID, rang in 0 ~ 4. 




NETC_TB_BP_THRESH(mant, exp)

Buffer pool and shared buffer pool threshold macro, the threshold = MANT*2^EXP, uint is internal memory words (avergae of 20 bytes each) 




union _netc_cmd_bd


#include <fsl_netc.h>
The Switch/SI command BD data structure. 

Public Members


struct _netc_cmd_bd req





struct _netc_cmd_bd resp





struct _netc_cmd_bd generic








struct _netc_cmd_bdr_config


#include <fsl_netc.h>
Configuration for the Switch/SI command BD Ring Configuration. 

Public Members


netc_cmd_bd_t *bdBase

BDR base address which shall be 128 bytes aligned 




uint16_t bdLength

Size of BD ring which shall be multiple of 8 BD 




bool enCompInt

Enable/Disable command BD completion interrupt 







struct _netc_cmd_bdr


#include <fsl_netc.h>
The Switch/SI command BD ring handle data structure. 

Public Members


netc_cmd_bd_t *bdBase

BDR base address which shall be 128 bytes aligned 




uint16_t bdLength

Size of BD ring 




uint16_t producerIndex

Current index for execution. 




uint16_t cleanIndex

Current index for cleaning. 




bool bdrEnable

Current command BD ring is enable or not. 







struct _netc_tb_common_header


#include <fsl_netc.h>
Table request data buffer common header. 

Public Members


uint32_t updateActions

Update Actions 




uint32_t queryActions

Query Actions 







struct _netc_tb_ipf_keye


#include <fsl_netc.h>
Ingress Port Filter key element. 

Public Members


uint16_t precedence

Precedence value of an entry 




struct _netc_tb_ipf_keye frameAttr

Frame Attribute flags 




uint16_t frameAttrMask

Frame attribute mask, set with OR of netc_tb_ipf_attr_mask_t




uint16_t dscp

Differentiated Services Code Point 




uint16_t dscpMask

Differentiated Services Code Point Mask 




uint16_t srcPort

Source Port ID 




uint16_t srcPortMask

Source Port ID Mask 




uint16_t outerVlanTCI

Outer VLAN Tag Control Information 




uint16_t outerVlanTCIMask

Outer VLAN Tag Control Information Mask 




uint8_t dmac[6]

Destination MAC Address 




uint8_t dmacMask[6]

Destination MAC Address Mask 




uint8_t smac[6]

Source MAC Address 




uint8_t smacMask[6]

Source MAC Address Mask 




uint16_t innerVlanTCI

Inner VLAN Tag Control Information 




uint16_t innerVlanTCIMask

Inner VLAN Tag Control Information Mask 




uint16_t etherType

2-byte EtherType 




uint16_t etherTypeMask

EtherType Mask 




uint8_t IPProtocol

IP Protocol 




uint8_t IPProtocolMask

IP Protocol Mask 




uint8_t srcIPAddr[16]

IP Source Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address 




uint8_t srcIPAddrMask[16]

IP Source Address Mask 




uint16_t l4SrcPort

L4 Source Port 




uint16_t l4SrcPortMask

L4 Source Port Mask 




uint8_t destIPAddr[16]

IP Destination Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address 




uint8_t destIPAddrMask[16]

IP Destination Address Mask 




uint16_t l4DestPort

L4 Destination Port 




uint16_t l4DestPortMask

L4 Destination Port Mask 







struct _netc_tb_ipf_cfge


#include <fsl_netc.h>
Ingress port filter config element. 

Public Members


uint32_t ipv

Internal Priority Value 




uint32_t oipv

Overwrite IPV 




uint32_t dr

Drop Resilience 




uint32_t odr

Overwrite DR 




netc_tb_ipf_forward_action_t fltfa

Filter Forwarding action. 




uint32_t imire

Ingress Mirroring Enable 




uint32_t wolte

Wake-onLAN trigger enable 




netc_tb_ipf_filter_action_t flta

FIlter Action. 




uint32_t rpr

Relative Precedent Resolution 




uint32_t ctd

Cut through disable. 




netc_host_reason_t hr

Host Reason metadata when frame is redirected/copied to the switch management port 




uint32_t timecape

Timestam capture enable 




uint32_t rrt

Report Receive Timestamp 




uint32_t fltaTgt

Target for selected switch forwarding action or filter action 







struct _netc_tb_ipf_stse


#include <fsl_netc.h>
Ingress port filter statistic element. 

Public Members


uint32_t matchCount[2]

A count of how many times this entry has been matched. 







struct _netc_tb_ipf_req_data


#include <fsl_netc.h>
Ingress port filter table entry config. 




struct _netc_tb_ipf_rsp_data


#include <fsl_netc.h>
Ingress port filter table response data. 

Public Members


uint32_t entryID

Present only for commands which perform a query 




netc_tb_ipf_keye_t keye

Present only for commands which perform a query 




netc_tb_ipf_stse_t stse

Present only for commands which perform a query 




netc_tb_ipf_cfge_t cfge

Present only for commands which perform a query 







struct _netc_tb_ipf_data


#include <fsl_netc.h>
Ingress Port filter table data buffer. 




struct _netc_tb_ipf_config


#include <fsl_netc.h>
Ingress Port filter entry config. 




struct _netc_tb_isi_keye


#include <fsl_netc.h>
Stream identification table key element. 

Public Members


netc_tb_isi_key_type keyType

Define the key type used for the current isi entry 




uint8_t srcPortID

Source Port ID, used when kc portp filed is 1. Only for SWITCH 




uint8_t spm

Source Port Masquerading, used when kc spm filed is 1. Only for SWITCH 




uint8_t framekey[16]

Frame portion of the key. 







struct _netc_tb_isi_cfge


#include <fsl_netc.h>
Stream identification table config element. 

Public Members


uint32_t iSEID

Ingress stream entry ID, 0xFFFFFFFF means NULL 







struct _netc_tb_isi_req_data


#include <fsl_netc.h>
Stream identification table request data buffer. 




struct _netc_tb_isi_rsp_data


#include <fsl_netc.h>
Stream identification table request response data buffer. 

Public Members


uint32_t entryID

Only present for query command 




netc_tb_isi_keye_t keye

Only present for query command 




netc_tb_isi_cfge_t cfge

Only present for query command 







struct _netc_tb_isi_data


#include <fsl_netc.h>
Stream identification table data buffer. 




struct _netc_tb_isi_config


#include <fsl_netc.h>
Stream identification table entry config. 




struct _netc_tb_is_cfge


#include <fsl_netc.h>
Ingress Stream table config element. 

Public Members


uint32_t sfe

Stream Filtering Enable 




uint32_t ipv

Internal Priority Value, active when opiv is set to 1 




uint32_t oipv

Override internal priority value 




uint32_t dr

Drop Resilience, active when odr is set to 1 




uint32_t odr

Overwrite DR 




uint32_t imire

Ingress Mirroring Enable, not applicable to ENETC 




uint32_t timecape

Timestamp Capture Enable, not applicable to ENETC 




uint32_t sppd

Source Port Pruning Disable, not applicable to ENETC 




netc_tb_is_isq_action_t isqa

Ingress Sequence Action, not applicable to ENETC 




uint32_t orp

Override Rate Policer ID 




uint32_t osgi

Override stream gate instance entry id (default is NULL) 




netc_host_reason_t hr

Host Reason when frame is redirected (fa = 01b) to the switch management port or copied to the switch management port (fa = 100b or 101b), value specified has to be a software defined Host Reason (8-15). 




netc_tb_is_forward_action_t fa

Forwad Option 




netc_tc_sdu_type_t sduType

Service Data Unit Type to user for MSDU 




uint32_t msdu

Maximum Service Data Unit 




uint32_t ifmeLenChange

Ingress Frame Modification Entry Frame Length Change, specified in unit of bytes using a 2’s complement notation 




uint32_t eport

Egress Port which need do egress packet processing, active when oeteid is set to 1, not applicable to ENETC 




netc_tb_is_oeteid_mode_t oETEID

Override ET_EID (Egress Treatment table entry, which specified egress packet processing actions) 




netc_tb_is_ctd_mode_t ctd

Cut-Through Disable mode, valid if fa = 010b ~ 101b 




uint32_t isqEID

Ingress Sequence Generation Entry ID, Valid when isqa is set to 1. 0xFFFF_FFFF is NULL. Not applicable to ENETC 




uint32_t rpEID

Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL 




uint32_t sgiEID

Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL 




uint32_t ifmEID

Ingress Frame Modification Entry ID. 0xFFFF_FFFF is NULL 




uint32_t etEID

Base Egress Treatment Entry ID for primary Egress Treatment group, Valid alid if fa = 010b ~ 101b. 0xFFFF_FFFF is NULL. Not applicable to ENETC 




uint32_t iscEID

Ingress Stream counter Index. 0xFFFF_FFFF is NULL. 




uint32_t ePortBitmap

Egress Port bitmap, identifies the ports to which the frame is to be forwarding or ET applicability port bitmap when oETEID = 10b. Not applicable to ENETC 




uint32_t siMap

Station Interface Map, only valid for ENETC function when fa field is set to 10b 







struct _netc_tb_is_req_data


#include <fsl_netc.h>
Ingress Stream table request data buffer. 

Public Members


netc_tb_is_cfge_t cfge

Only perform for update or add command 







struct _netc_tb_is_rsp_data


#include <fsl_netc.h>
Ingress Stream table request response data buffer. 

Public Members


uint32_t entryID

Only perform for query command 




netc_tb_is_cfge_t cfge

Only perform for query command 







struct _netc_tb_is_data


#include <fsl_netc.h>
Ingress Stream table data buffer. 




struct _netc_tb_is_config


#include <fsl_netc.h>
Ingress Stream table entry config. 




struct _netc_tb_isf_keye


#include <fsl_netc.h>
Ingress Stream Filter table key element. 

Public Members


uint32_t isEID

Ingress Stream Entry ID 




uint8_t pcp

Priority Code Point, Outer VLAN TAG PCP of the received frame 







struct _netc_tb_isf_cfge


#include <fsl_netc.h>
Ingress Stream Filter table config element. 

Public Members


uint32_t ipv

Internal Priority Value, active when opiv is set to 1 




uint32_t oipv

Override internal priority value 




uint32_t dr

Drop Resilience, active when odr is set to 1 




uint32_t odr

Overwrite DR 




uint32_t imire

Ingress Mirroring Enable, not applicable to ENETC 




uint32_t timecape

Timestamp Capture Enable, not applicable to ENETC 




uint32_t osgi

Override stream gate instance entry id 




uint32_t ctd

Cut-Through Disable, will disable cut-through for all destined ports when set 1, not applicable to ENETC 




uint32_t orp

Override Rate Policer (instance) ID 




netc_tc_sdu_type_t sduType

Service Data Unit Type to user for MSDU 




uint32_t msdu

Maximum Service Data Unit 




uint32_t rpEID

Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL 




uint32_t sgiEID

Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL 




uint32_t iscEID

Ingress Stream counter Index. 0xFFFF_FFFF is NULL. 







struct _netc_tb_isf_req_data


#include <fsl_netc.h>
Ingress Stream Filter table request data buffer. 

Public Members


netc_tb_isf_cfge_t cfge

Only perform for update or add command 







struct _netc_tb_isf_rsp_data


#include <fsl_netc.h>
Ingress Stream Filter table request response data buffer. 

Public Members


uint32_t entryID

Only perform for query command 




netc_tb_isf_keye_t keye

Only perform for query command 




netc_tb_isf_cfge_t cfge

Only perform for query command 







struct _netc_tb_isf_data


#include <fsl_netc.h>
Ingress Stream Filter table data buffer. 




struct _netc_tb_isf_config


#include <fsl_netc.h>
Ingress Stream Filter table entry config. 




struct _netc_tb_rp_cfge


#include <fsl_netc.h>
Rate Policer table config element. 

Public Members


uint32_t cir

Committed information Rate 




uint32_t cbs

Commited Burst Size 




uint32_t eir

Excess information Rate 




uint32_t ebs

Excess Burst Size 




uint32_t mren

Mark All Frames Red Enable, Not valid when ndor=1 




uint32_t doy

Drop on Yellow enable 




uint32_t cm

Color mode, 0b = Color blind, 1b = Color aware 




uint32_t cf

Coupling flag, enables coupling the Committed (C) bucket and Excess (E) bucket 




uint32_t ndor

No drop on red 




netc_tb_rp_sdu_type_t sduType

Service Data Unit Type 




uint32_t __pad0__

Reserved 







struct _netc_tb_rp_fee


#include <fsl_netc.h>
Rate Policer table Function Enable element. 

Public Members


uint8_t fen

Function Enable 




uint8_t __pad0__

Reserved 







struct _netc_tb_rp_pse


#include <fsl_netc.h>
Rate Policer table Policer State element. 

Public Members


uint8_t mr

Mark Red Flag 




uint8_t res0

Reserved 







struct _netc_tb_rp_stse


#include <fsl_netc.h>
Rate Policer table statistic element. 

Public Members


uint32_t byteCount[2]

Number of bytes received by the rate policer instance 




uint32_t dropFrames[2]

Number of frames dropped by the rate policer instance 




uint32_t dr0GrnFrames[2]

Number of frames marked green with DR=0 by the rate policer instance 




uint32_t dr1GrnFrames[2]

Number of frames marked green with DR=1 by the rate policer instance 




uint32_t dr2GrnFrames[2]

Number of frames marked yellow with DR=2 by the rate policer instance 




uint32_t remarkYlwFrames[2]

Number of frames re-marked from green to yellow by the rate policer instance 




uint32_t dr3RedFrames[2]

Number of frames marked red with DR=3 by the rate policer instance 




uint32_t remarkRedFrames[2]

Number of frames re-marked from green or yellow to red by the rate policer instance 




uint32_t lts

Last timestamp 




uint32_t bci

Committed token bucket contents, integer portion (31 bits) 




uint32_t bcs

Committed token bucket sign bit (1 bit) 




uint32_t bcf

Committed token bucket contents, fractional portion (31 bits) 




uint32_t bei

Excess token bucket contents, integer portion (32 bits) 




uint32_t bef

Excess token bucket contents, fractional portion (31 bits) 




uint32_t bes

Committed token bucket sign bit 







struct _netc_tb_rp_req_data


#include <fsl_netc.h>
Rate Policer table request data buffer. 




struct _netc_tb_rp_rsp_data


#include <fsl_netc.h>
Rate Policer table request response data buffer. 

Public Members


uint32_t entryID

Present only for commands which perform a query 




netc_tb_rp_stse_t stse

Present only for commands which perform a query 







struct _netc_tb_rp_data


#include <fsl_netc.h>
Rate Policer table data buffer. 




struct _netc_tb_rp_config


#include <fsl_netc.h>
Rate Policer table entry config. 




struct _netc_tb_isc_stse


#include <fsl_netc.h>
Ingress Stream Count table statistic element. 

Public Members


uint32_t rxCount

Receive Count 




uint32_t msduDropCount

MSDU Drop Count 




uint32_t policerDropCount

Policer Drop Count 




uint32_t sgDropCount

Stream Gating Drop Count 







struct _netc_tb_isc_req_data


#include <fsl_netc.h>
Ingress Stream Count table request data buffer. 




struct _netc_tb_isc_rsp_data


#include <fsl_netc.h>
Ingress Stream Count table request response data buffer. 




struct _netc_tb_isc_data


#include <fsl_netc.h>
Ingress Stream Count table data buffer. 




struct _netc_tb_sgi_cfge


#include <fsl_netc.h>
Stream Gate Instance table config element. 

Public Members


uint8_t oexen

Octets Exceeded (Gate Closed Due To Octets Exceeded function) Enable 




uint8_t irxen

Invalid Receive (Gate Closed Due To Invalid Rx) Enable 




netc_tb_sgi_sdu_type_t sduType

The type of PDU/SDU for Interval Octets Maximum check for Gate Entry 







struct _netc_tb_sgi_acfge


#include <fsl_netc.h>
Stream Gate Instance table Admin Configuration element. 

Public Members


uint32_t adminSgclEID

Administrative Stream Gate Control List Entry ID, 0xFFFFFFFF is NULL 




uint32_t adminBaseTime[2]

Admin Base Time 




uint32_t adminCycleTimeExt

Admin Cycle Time Extension 







struct _netc_tb_sgi_icfge


#include <fsl_netc.h>
Stream Gate Instance table Initial Configuration element. 

Public Members


uint8_t ipv

Internal Priority Value (IPV), Valid if oipv is 1 




uint8_t oipv

Override frame IPV, otherwise the IPV value is determined by the stream gate control list entry 




uint8_t gst

Specifies Gate State before the administrative stream gate control list takes affect, 0b = Closed; 1b = Open 




uint8_t ctd

Specifies Cut Through disable status before the administrative stream gate control list takes affect , Not applicable to ENETC function 







struct _netc_tb_sgi_sgise


#include <fsl_netc.h>
Stream Gate Instance table stream gate instance state element. 

Public Members


uint32_t operSgclEID

Operational Stream Gate Control List Entry ID 




uint32_t configChangeTime[2]

Configuration Change Time 




uint32_t operBaseTime[2]

Operational Base Time 




uint32_t operCycleTimeExt

Oper Cycle Time Extension 




uint32_t oex

Octets Exceeded Flag 




uint32_t irx

Invalid Receive Flag 




netc_tb_sgi_state_t state

Current Gate Instance State 







struct _netc_tb_sgi_req_data


#include <fsl_netc.h>
Stream Gate Instance table request data buffer. 




struct _netc_tb_sgi_rsp_data


#include <fsl_netc.h>
Stream Gate Instance table request response data buffer. 




struct _netc_tb_sgi_data


#include <fsl_netc.h>
Stream Gate Instance table data buffer. 




struct _netc_tb_sgi_config


#include <fsl_netc.h>
Stream Gate Instance table entry config. 




struct _netc_sgcl_gate_entry


#include <fsl_netc.h>
Defines the Stream Gate Control entry structure. 

Public Members


uint32_t timeInterval

Time Interval for Gate Entry 




uint32_t iom

Interval Octets Maximum for Gate Entry, specifies the maximum bytes (octets) allowed to pass (open), valid if iomen = 1 




uint32_t ipv

Internal Priority Value for Gate Entry 




uint32_t oipv

Override Internal Priority Value for Gate Entry 




uint32_t ctd

Cut Through Disable for Gate Entry 




uint32_t iomen

Interval Octet Maximum Enabled for Gate Entry, 0b = Don’track count, 1b = Track count 




uint32_t gtst

Gate State for Gate Entry, 0b = Closed; 1b = Open 







struct _netc_tb_sgcl_cfge


#include <fsl_netc.h>
Stream Gate Control List table config element. 

Public Members


uint32_t cycleTime

Cycle Time 




uint8_t listLength

List Length 




uint16_t extOipv

Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value 




uint16_t extIpv

List Extension Internal Priority Value, valid if extOipv = 1 




uint16_t extCtd

Extension Cut Through Disabled, 0b = No action, 1b = Disabled 




uint16_t extGtst

Extension Gate State, 0b = closed, 1b = Open 







struct _netc_tb_sgcl_sgclse


#include <fsl_netc.h>
Stream Gate Control List table Stream Gate Control List State element. 

Public Members


uint8_t refCount

Reference Count, 1 indicates that the gate control list is an administrative or an operational gate control list in a stream gate instance 







struct _netc_tb_sgcl_req_data


#include <fsl_netc.h>
Stream Gate Control List table request data buffer. 




struct _netc_tb_sgcl_rsp_data


#include <fsl_netc.h>
Stream Gate Control List table request response data buffer. 




struct _netc_tb_sgcl_data


#include <fsl_netc.h>
Stream Gate Control List table data buffer. 




struct _netc_tb_sgcl_gcl


#include <fsl_netc.h>
Stream Gate Control List table entry gate control list structure. 

Public Members


uint16_t extOipv

Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value 




uint16_t extIpv

List Extension Internal Priority Value, valid if extOipv = 1 




uint16_t extCtd

Extension Cut Through Disabled, 0b = No action, 1b = Disabled 




uint16_t extGtst

Extension Gate State, 0b = closed, 1b = Open 




uint32_t cycleTime

Cycle Time 




uint32_t numEntries

Control List entry numbers 




netc_sgcl_gate_entry_t *gcList

Pointer to stream gate control list array 







struct _netc_tb_fm_cfge


#include <fsl_netc.h>
Frame Modification table config element. 

Public Members


netc_tb_fm_layer2_act_t l2Act

Layer 2 Actions 




netc_tb_fm_mac_header_act_t macHdrAct

Layer 2 Header MAC Actions 




netc_tb_fm_vlan_header_act_t vlanHdrAct

Layer 2 VLAN Actions 




netc_tb_fm_outer_vid_act_t outerVidAct

Outer VID Actions 




netc_tb_fm_sqt_act_t sqtAct

Sequence Tag Action, Not applicable for ingress frame modifications 




uint16_t smacPort

Source MAC Address Register Port, valid if macHdrAct=010b,011b,100b 




uint8_t dmac[6]

Destination MAC Address, valid if macHdrAct = 011b,101b 




uint32_t outerVlanID

Outer VLAN VID, valid if outerVidAct = 01b 




uint32_t outerVlanPcp

Outer VLAN PCP, valid if outerPcpAct = 01b 




uint32_t outerVlanDei

Outer VLAN DEI, valid if outerDeiAct = 01b 




netc_tb_fm_outer_tpid_act_t outerTpidAct

Outer TPID action 




netc_tb_fm_outer_pcp_act_t outerPcpAct

Outer PCP action 




netc_tb_fm_outer_dei_act_t outerDeiAct

Outer DEI action 




netc_tb_fm_payload_act_t pldAct

Payload Actions, Not applicable for ingress frame modifications 




uint8_t pldOffset

Payload Offset, valid if outerPldAct = 010b 




uint16_t fmdBytes

Frame Modification Bytes, valid if outerPldAct = 001b,010b or l2Act = 1b 




uint32_t fmdEID

Frame Modification Data Entry ID, valid if outerPldAct = 001b,010b or l2Act = 1b. 0xFFFF is null pointer 







struct _netc_tb_fm_req_data


#include <fsl_netc.h>
Frame Modification table request data buffer. 




struct _netc_tb_fm_rsp_data


#include <fsl_netc.h>
Frame Modification table request response data buffer. 




struct _netc_tb_fm_data


#include <fsl_netc.h>
Frame Modification table data buffer. 




struct _netc_tb_fm_config


#include <fsl_netc.h>
Frame Modification table entry config. 




struct _netc_tb_fmd_req_data


#include <fsl_netc.h>
Frame Modification Data table request data buffer. 

Public Members


uint8_t cfge[]

Configuration Element Data size is variable 







struct _netc_tb_fmd_rsp_data


#include <fsl_netc.h>
Frame Modification Data table request response data buffer. 

Public Members


uint8_t cfge[]

Configuration Element Data size is variable 







struct _netc_tb_fmd_data


#include <fsl_netc.h>
Frame Modification Data table data buffer. 




struct _netc_tb_fmd_update_config


#include <fsl_netc.h>
Frame Modification data table entry update config. 

Public Members


uint32_t res

Hold for request->commonHeader 




uint8_t cfge[]

Configuration Element Data size is variable 







struct _netc_tb_fmd_query_buffer


#include <fsl_netc.h>
Frame Modification data table entry query data buffer. 

Public Members


uint32_t entryID

EntryID of the queried entry 




uint8_t cfge[]

Configuration Element Data size is variable 







struct _netc_tb_vf_keye


#include <fsl_netc.h>
Vlan Filter table key element. 




struct _netc_tb_vf_cfge


#include <fsl_netc.h>
Vlan Filter table config element. 

Public Members


uint32_t portMembership

Port Membership Bitmap 




uint32_t stgID

Spanning Tree Group Member ID 




uint32_t fid

Filtering ID 




uint32_t mlo

MAC Learning Options 




uint32_t mfo

MAC Forwarding Options 




uint32_t ipmfe

IP Multicast Filtering Enable 




uint32_t ipmfle

IP Multicast Flooding Enable 




uint32_t etaPortBitmap

Egress Treatment Applicability Port Bitmap for the secondary Egress Treatment group 




uint32_t baseETEID

Base Egress Treatment Entry ID for the secondary Egress Treatment group 







struct _netc_tb_vf_search_criteria


#include <fsl_netc.h>
Vlan Filter table search criteria format. 

Public Members


uint32_t resumeEntryId

Resume Entry ID, when starting a search, pass the NULL Entry ID. 







struct _netc_tb_vf_req_data


#include <fsl_netc.h>
Vlan Filter table request data buffer. 

Public Members


netc_tb_vf_cfge_t cfge

Present only for update or add commands 







struct _netc_tb_vf_rsp_data


#include <fsl_netc.h>
Vlan Filter table request response data buffer. 

Public Members


uint32_t status

Present only for query command with search access method 




uint32_t entryID

Present only for query command 




netc_tb_vf_keye_t keye

Present only for query command 




netc_tb_vf_cfge_t cfge

Present only for query command 







struct _netc_tb_vf_data


#include <fsl_netc.h>
Vlan Filter table data buffer. 




struct _netc_tb_vf_config


#include <fsl_netc.h>
Vlan Filter table entry config. 




struct _netc_tb_fdb_keye


Public Members


uint8_t macAddr[6]

Destination MAC address of the frame for MAC forwarding lookups and the source MAC address of the frame for MAC learning lookups 




uint32_t fid

Filtering ID, is obtained from an ingress lookup into the VLAN Filter table 







struct _netc_tb_fdb_cfge


#include <fsl_netc.h>
FDB table configuration element. 

Public Members


uint32_t portBitmap

Forwarding destination Port Bitmap and ET applicability port bitmap when oETEID = 10b 




netc_tb_fdb_oeteid_mode_t oETEID

Override ET_EID option 




uint32_t ePort

Egress Ports, active when oETEid = 01b or ctd = 01b 




uint32_t iMirE

Ingress Mirroring Enable 




netc_tb_fdb_ctd_mode_t ctd

Cut-Through Disable 




uint32_t dynamic

Static or Dynamic Entry, 0b = Static entry, 1b = Dynamic entry 




uint32_t timeCapE

Timestamp Capture Enable when set 




uint32_t etEID

Base egress treatment table entry id for primary Egress Treatment group, is valid if the oETEID field is set to value other than kNETC_FDBNoEPP. 0xFFFFFFFF is NULL. 







struct _netc_tb_fdb_acte


#include <fsl_netc.h>
FDB table Activity element. 

Public Members


uint8_t actCnt

Activity Counter 




uint8_t actFlag

Activity Flag 







struct _netc_tb_fdb_search_criteria


#include <fsl_netc.h>
FDB table search criteria format. 

Public Members


uint32_t resumeEntryId

Resume Entry ID, pass the NULL Entry ID when starting a search 




netc_tb_fdb_keye_t keye

Key Element data which used to match against the table entries 




netc_tb_fdb_cfge_t cfge

Configuration Element data which used to match against the table entries 







struct _netc_tb_fdb_req_data


#include <fsl_netc.h>
FDB table request data buffer. 

Public Members


netc_tb_common_header_t commonHeader

Define update actions (use netc_tb_fdb_update_action_t) and query actions 




netc_tb_fdb_cfge_t cfge

Present only for commands which perform an update or add 







struct _netc_tb_fdb_rsp_data


#include <fsl_netc.h>
FDB table request response data buffer. 

Public Members


uint32_t status

RESUME_ENTRY_ID, valid only in responses for commands which use the Search Access Method 




uint32_t entryID

Present only for query command 




netc_tb_fdb_keye_t keye

Present only for query command 




netc_tb_fdb_cfge_t cfge

Present only for query command 




netc_tb_fdb_acte_t acte

Present only for query command 







struct _netc_tb_fdb_data


#include <fsl_netc.h>
FDB table data buffer. 




struct _netc_tb_fdb_config


#include <fsl_netc.h>
FDB table entry config. 




struct _netc_tb_l2mcf_keye


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table key element. 

Public Members


netc_tb_l2mcf_key_type_t keyType

Key Type 




uint32_t fid

Filtering ID 




uint32_t ipv4DestAddr

IPv4 Destination Address 




uint32_t ipv4SrcAddr

IPv4 Source Address 







struct _etc_tb_l2mcf_search_criteria


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table search criteria format. 

Public Members


uint32_t resumeEntryId

Resume Entry ID, pass the NULL Entry ID when starting a search 




netc_tb_l2mcf_keye_t keye

Key Element data which used to match against the table entries 




netc_tb_l2mcf_cfge_t cfge

Configuration Element data which used to match against the table entries 







struct _netc_tb_l2mcf_req_data


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table request data buffer. 




struct _netc_tb_l2mcf_rsp_data


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table request response data buffer. 




struct _netc_tb_l2mcf_data


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table data buffer. 




struct _netc_tb_l2mcf_config


#include <fsl_netc.h>
L2 IPV4 Multicast Filter table entry config. 




struct _netc_tb_iseqg_cfge


#include <fsl_netc.h>
Ingress Sequence Generation table config element. 

Public Members


netc_tb_iseqg_sqtag_t sqTag

Sequence Tag Type. 




uint8_t __pad0__

Reserved. 







struct _netc_tb_iseqg_sgse


#include <fsl_netc.h>
Ingress Sequence Generation table Sequence generation state element. 

Public Members


uint16_t sqgNum

Sequence Generation Number 







struct _netc_tb_iseqg_req_data


#include <fsl_netc.h>
Ingress Sequence Generation table request data buffer. 




struct _netc_tb_iseqg_rsp_data


#include <fsl_netc.h>
Ingress Sequence Generation table request response data buffer. 




struct _netc_tb_iseqg_data


#include <fsl_netc.h>
Ingress Sequence Generation table data buffer. 




struct _netc_tb_iseqg_config


#include <fsl_netc.h>
Ingress Sequence Generation table entry config. 




struct _netc_tb_eseqr_cfge


#include <fsl_netc.h>
Egress Sequence Recovery table config element. 

Public Members


netc_tb_eseqr_sqtag_t sqTag

Sequence Tag, specify the expected sequence tag type in the frame 




uint32_t sqrTnsq

Sequence Recovery Take No Sequence 




uint32_t sqrAlg

Sequence Recovery Algorithm, 0b = Vector algorithm, 1b = Match algorithm 




uint32_t sqrType

Sequence Recovery Function type, 0b = Sequence recovery function, 1b = Individual recovery function 




uint32_t sqrHl

Sequence Recovery History Length, valid if sqrAlg = 0b 




uint32_t sqrFwl

Sequence Recovery Future Window Length, valid if sqrAlg = 0b 




uint32_t sqrTp

Sequence Timeout Period, the unit is 1.048576 milliseconds 







struct _netc_tb_eseqr_stse


#include <fsl_netc.h>
Egress Sequence Recovery table statistic element. 

Public Members


uint32_t inOrderPackets[2]

In Order Packets 




uint32_t outOfOrderPackets[2]

Out of Order Packets 




uint32_t roguePackets[2]

Rogue Packets 




uint32_t duplicatePackets[2]

Duplicate Packets 




uint32_t lostPackets[2]

Lost Packets 




uint32_t taglessPackets[2]

Tag-Less Packets 




uint32_t esqrResetCounts

Sequence Recovery Resets 







struct _netc_tb_eseqr_srse


#include <fsl_netc.h>
Egress Sequence Recovery table sequence recovery state element. 

Public Members


uint32_t sqrNum

Sequence Recovery Number 




uint32_t takeAny

Take Any 




uint32_t lce

Lost Count Enable 




uint32_t sqrTs

Sequence Recovery Timestamp 




uint32_t sqrHistory[4]

Recovery History bit vector, each bit corresponding to sequence numbers, bit 1 means a packet with that sequence number has been previously received 







struct _netc_tb_eseqr_req_data


#include <fsl_netc.h>
Egress Sequence Recovery table request data buffer. 




struct _netc_tb_eseqr_rsp_data


#include <fsl_netc.h>
Egress Sequence Recovery table request response data buffer. 




struct _netc_tb_eseqr_data


#include <fsl_netc.h>
Egress Sequence Recovery table data buffer. 




struct _netc_tb_eseqr_config


#include <fsl_netc.h>
Egress Sequence Recovery table entry config. 




struct _netc_tgs_gate_entry


#include <fsl_netc.h>
Defines the Time Gate Scheduling gate control entry structure. 

Public Members


uint32_t interval

Entry Time Interval 







struct _netc_tb_tgs_cfge


#include <fsl_netc.h>
Time Gate Scheduling table config element. 

Public Members


uint64_t adminBaseTime

Administrative Base Time 




uint32_t adminCycleTime

Administrative Cycle Time 




uint32_t adminCycleTimeExt

Administrative Cycle Time Extension 




uint32_t adminControlListLength

Administrative Control List Length 




netc_tgs_gate_entry_t adminGcl[]

Administrative Gate control list 







struct _netc_tb_tgs_olse


#include <fsl_netc.h>
Time Gate Scheduling table statistic element. 

Public Members


uint64_t configChangeTime

The time at which this operational gate control list became active 




uint64_t configChangeError

Count of error configuration changes 




uint64_t operBaseTime

Operational Base Time 




uint32_t operCycleTime

Operational Cycle Time 




uint32_t operCycleTimeExt

Operational Cycle Time Extension 




uint32_t operControlListLength

Operational Control List Length 




netc_tgs_gate_entry_t operGcl[]

Operational Gate control list 







struct _netc_tb_tgs_req_data


#include <fsl_netc.h>
Time Gate Scheduling table request data buffer. 

Public Members


netc_tb_tgs_cfge_t cfge

Present only for commands which perform a update 







struct _netc_tb_tgs_rsp_data


#include <fsl_netc.h>
Time Gate Scheduling table request response data buffer. 

Public Members


uint32_t entryID

Present only for commands which perform a query 




netc_tb_tgs_cfge_t cfge

Present only for commands which perform a query 




netc_tb_tgs_olse_t olse

Present only for commands which perform a query 







struct _netc_tb_tgs_data


#include <fsl_netc.h>
Time Gate Scheduling table data buffer, set with max size. 




struct _netc_tb_tgs_gcl


#include <fsl_netc.h>
Time Gate Scheduling table entry gate control list structure. 

Public Members


uint64_t baseTime

Base Time 




uint32_t cycleTime

Cycle Time 




uint32_t extTime

Cycle Time Extension 




uint32_t numEntries

Control List entry numbers 




netc_tgs_gate_entry_t *gcList

Pointer to time gate control list array 







struct _netc_tb_et_cfge


#include <fsl_netc.h>
Egress Treatment table config element. 

Public Members


netc_tb_et_efm_mode_t efmMode

Egress Frame Modification mode 




netc_tb_et_esq_act_t esqa

Egress Sequence Actions 




netc_tb_et_ec_act_t eca

Egress Counter Action 




uint8_t __pad1__

Reserve for data align 




uint8_t efmLenChange

Egress Frame Modification Length Change, specified in units of bytes using a 2’s complement notation 




uint16_t efmDataLen

Egress Frame Modification Data Length 




uint32_t efmEID

Egress Frame Modification Entry Id 




uint32_t ecEID

Egress Count Table Entry ID 




uint32_t esqaTgtEID

Egress Sequence Actions Target Entry ID, active when esqa = 10b 







struct _netc_tb_et_req_data


#include <fsl_netc.h>
Egress Treatment table request data buffer. 




struct _netc_tb_et_rsp_data


#include <fsl_netc.h>
Egress Treatment table request response data buffer. 




struct _netc_tb_et_data


#include <fsl_netc.h>
Egress Treatment table data buffer. 




struct _netc_tb_et_config


#include <fsl_netc.h>
Egress Treatment table entry config. 




struct _netc_tb_etmcq_cfge


#include <fsl_netc.h>
ETM Class Queue table config element. 

Public Members


netc_hw_etm_class_queue_idx_t cq2cgMap

Class Queue to Congestion Group Mapping 







struct _netc_tb_etmcq_stse


#include <fsl_netc.h>
ETM Class Queue table statistic element. 

Public Members


uint32_t rejByteCnt[2]

Reject Byte Count 




uint32_t rejFrameCnt[2]

Reject Frame Count 




uint32_t deqByteCnt[2]

Dequeue Byte Count 




uint32_t deqFrameCnt[2]

Dequeue Frame Count 




uint32_t dropByteCnt[2]

Dropped Frames, Memory Lost 




uint32_t dropFrameCnt[2]

Dropped Frames, Memory Recovered 




uint32_t frmCnt

Frame Count 







struct _netc_tb_etmcq_req_data


#include <fsl_netc.h>
ETM Class Queue table request data buffer. 




struct _netc_tb_etmcq_rsp_data


#include <fsl_netc.h>
ETM Class Queue table request response data buffer. 




struct _netc_tb_etmcq_data


#include <fsl_netc.h>
ETM Class Queue table data buffer. 




struct _netc_tb_etmcq_config


#include <fsl_netc.h>
ETM Class Queue table entry config. 

Public Members


uint32_t entryID

Need use NETC_TB_ETM_CQ_ENTRY_ID macro to create entry ID 







struct _netc_tb_etmcs_cfge


#include <fsl_netc.h>
ETM Class Scheduler table config element. 

Public Members


netc_tb_etmcs_ca_assg_t cqAssg

Class Queue Assignment, input 0 to 7 are weighted fair whereby input 8 to 15 are strict priority 




uint32_t oal

Overead accounting length 




struct _netc_tb_etmcs_cfge wbfsWeight[8]

Weight for scheduler input 0 ~ 7, effective weight is: (2^x)/(1-(y/64)) 







struct _netc_tb_etmcs_req_data


#include <fsl_netc.h>
ETM Class Scheduler table request data buffer. 

Public Members


netc_tb_etmcs_entry_id_t entryID

One class scheduler entry per port 







struct _netc_tb_etmcs_rsp_data


#include <fsl_netc.h>
ETM Class Scheduler table request response data buffer. 




struct _netc_tb_etmcs_data


#include <fsl_netc.h>
ETM Class Scheduler table data buffer. 




struct _netc_tb_etmcs_config


#include <fsl_netc.h>
ETM Class Scheduler table entry config. 

Public Members


netc_tb_etmcs_entry_id_t entryID

One class scheduler entry per port 







struct _netc_tb_etmcg_cfge


#include <fsl_netc.h>
ETM Congestion Group table config element. 

Public Members


uint16_t tdDr0En

Tail drop enable for DR0 Frame 




uint16_t tdDr1En

Tail drop enable for DR1 Frame 




uint16_t tdDr2En

Tail drop enable for DR2 Frame 




uint16_t tdDr3En

Tail drop enable for DR3 Frame 




uint16_t oal

Overhead accounting length, 2’s complement value (range -2048 to +2047) 




struct _netc_tb_etmcg_cfge tdDRThresh[4]

Tail Drop Threshold (TA * 2^Tn) for DR0 ~ DR3 Frames, valid if tdDrnEn = 1b 







struct _netc_tb_etmcg_stse


#include <fsl_netc.h>
ETM Congestion Group table statistic element. 

Public Members


uint32_t byteCount[2]

Number of bytes currently in use in all class queues that are members of this group. 







struct _netc_tb_etmcg_req_data


#include <fsl_netc.h>
ETM Congestion Group table request data buffer. 




struct _netc_tb_etmcg_rsp_data


#include <fsl_netc.h>
ETM Congestion Group table request response data buffer. 




struct _netc_tb_etmcg_data


#include <fsl_netc.h>
ETM Congestion Group table data buffer. 




struct _netc_tb_etmcg_config


#include <fsl_netc.h>
ETM Congestion Group table entry config. 

Public Members


uint32_t entryID

Need use NETC_TB_ETM_CG_ENTRY_ID macro to create entry ID 







struct _netc_tb_ec_stse


#include <fsl_netc.h>
Egress Count table statistic element. 

Public Members


uint32_t enqFrmCnt[2]

Enqueued Frame Count 




uint32_t rejFrmCnt[2]

Rejected Frame Count 







struct _netc_tb_ec_req_data


#include <fsl_netc.h>
Egress Count table request data buffer. 




struct _netc_tb_ec_rsp_data


#include <fsl_netc.h>
Egress Count table request response data buffer. 




struct _netc_tb_ec_data


#include <fsl_netc.h>
Egress Count table data buffer. 




struct _netc_tb_bp_cfge


#include <fsl_netc.h>
Buffer Pool table config element. 

Public Members


bool sbpEn

Shared Buffer Pool Enable, set true measn a shared buffer pool is associated with this buffer pool 




netc_tb_bp_fc_cfg_t gcCfg

Flow Control (FC) Configuration 




uint8_t pfcVector

Priority Flow Control (PFC) Vector, not support in NETC 3.0 and 3.1 version 




uint16_t maxThresh

Maximum Threshold, value 0 means disable maximum threshold checking, use NETC_TB_BP_THRESH macro to set this value 




uint16_t fcOnThresh

Flow Control On Threshold, If the buffer pool usage crosses this threshold, and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool is set to 1, use NETC_TB_BP_THRESH macro to set this value. 




uint16_t fcOffThresh

Flow Control Off Threshold, If buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, , use NETC_TB_BP_THRESH macro to set this value 




uint32_t sbpThresh

Shared Buffer Pool Threshold, use NETC_TB_BP_THRESH macro to set this value 




uint32_t sbpEid

Shared Buffer Pool Entry ID, valid if sbpEn is true 




uint32_t fcPorts

Flow Control Port bitmap, indicates which ports are to be flow controlled for this buffer pool 







struct _netc_tb_bp_bpse


#include <fsl_netc.h>
Buffer Pool table State Element Data. 

Public Members


uint32_t amountUsed

Amount Used, number of internal memory words (average of 20 bytes each) currently in use in this buffer pool. 




uint32_t amountUsedHWM

Amount Used High Watermark, value sticks at the highest AMOUNT_USED seen since the last watermark reset 




uint32_t fcState

Flow Control (FC) State, ON (1) or OFF (0) 




uint32_t bpd

Buffer Pool Disabled, 1 means the buffer pool has been disabled due to an uncorrectable ECC error 







struct _netc_tb_bp_req_data


#include <fsl_netc.h>
Buffer Pool table request data buffer. 




struct _netc_tb_bp_rsp_data


#include <fsl_netc.h>
Buffer Pool table request response data buffer. 




struct _netc_tb_bp_data


#include <fsl_netc.h>
Buffer Pool table data buffer. 




struct _netc_tb_bp_config


#include <fsl_netc.h>
Buffer Pool table entry config. 

Public Members


uint32_t entryID

Buffer pool ID, range in 0 ~ (SWT_GetBPTableEntryNum() - 1) 




netc_tb_bp_cfge_t cfge

Buffer Pool table config element 







struct _netc_tb_sbp_cfge


#include <fsl_netc.h>
Shared Buffer Pool table config element. 

Public Members


uint32_t maxThresh

Maximum Threshold, If shared buffer pool usage is greater than or equal to this threshold, use NETC_TB_BP_THRESH macro to set this value 




uint16_t fcOnThresh

Flow Control On Threshold, If the shared buffer pool usage crosses this threshold, and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool is set to 1, use NETC_TB_BP_THRESH macro to set this value. 




uint16_t fcOffThresh

Flow Control Off Threshold, If shared buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, use NETC_TB_BP_THRESH macro to set this value 







struct _netc_tb_sbp_sbpse


#include <fsl_netc.h>
Shared Buffer Pool table State Element Data. 

Public Members


uint32_t amountUsed

Amount Used, number of internal memory words (average of 20 bytes each) currently in use in this buffer pool. 




uint32_t amountUsedHWM

Amount Used High Watermark, value sticks at the highest AMOUNT_USED seen since the last watermark reset 




uint32_t fcState

Flow Control (FC) State, ON (1) or OFF (0) 







struct _netc_tb_sbp_req_data


#include <fsl_netc.h>
Shared Buffer Pool table request data buffer. 




struct _netc_tb_sbp_rsp_data


#include <fsl_netc.h>
Shared Buffer Pool table request response data buffer. 




struct _netc_tb_sbp_data


#include <fsl_netc.h>
Shared Buffer Pool table data buffer. 




struct _netc_tb_sbp_config


#include <fsl_netc.h>
Shared Buffer Pool table entry config. 

Public Members


uint32_t entryID

Shared Buffer pool ID, range in 0 ~ (SWT_GetSBPTableEntryNum() - 1) 




netc_tb_sbp_cfge_t cfge

Shared Buffer Pool table config element 







union _netc_tb_data_buffer


#include <fsl_netc.h>
Table common data buffer. 

Public Members


netc_tb_tgs_data_t tgs

Time Gate Scheduling table data buffer 




netc_tb_rp_data_t rp

Rate Policer table data buffer 




netc_tb_ipf_data_t ipf

Ingress Port filter table data buffer 




netc_tb_fdb_data_t fdb

FDB table data buffer 




netc_tb_l2mcf_data_t l2mcf

L2 IPV4 Multicast Filter table data buffer 




netc_tb_vf_data_t vf

VLAN Filter table data buffer 




netc_tb_isi_data_t isi

Ingress Stream Identification table data buffer 




netc_tb_is_data_t is

Ingress Stream table data buffer 




netc_tb_isf_data_t isf

Ingress Stream Filter table data buffer 




netc_tb_isc_data_t isc

Ingress Stream Count table data buffer 




netc_tb_sgi_data_t sgi

Stream Gate Instance table data buffer 




netc_tb_sgcl_data_t sgcl

Stream Gate Control List table data buffer 




netc_tb_fm_data_t fm

Frame Modification table data buffer 




netc_tb_fmd_data_t fmd

Frame Modification Data table data buffer 




netc_tb_et_data_t et

Egress Treatment table data buffer 




netc_tb_ec_data_t ec

Egress Count table data buffer 




netc_tb_etmcq_data_t cq

ETM Class Queue table data buffer 




netc_tb_etmcs_data_t cs

ETM Class Scheduler table data buffer 




netc_tb_etmcg_data_t cg

ETM Class Group table data buffer 




netc_tb_iseqg_data_t iseqg

Ingress Sequence Generation table data buffer 




netc_tb_eseqr_data_t eseqr

Egress Sequence Recovery table data buffer 




netc_tb_bp_data_t bp

Buffer Pool table data buffer 




netc_tb_sbp_data_t sbp

Shared Buffer Pool table data buffer 







struct _netc_cbdr_hw


#include <fsl_netc_hw.h>
Register group for SI/Switch command bd ring. 

Public Members


__IO uint32_t CBDRMR
Command BDR mode register. 




__I uint32_t CBDRSR
Command BDR status register. 




__IO uint32_t CBDRBAR0
Command BDR base address register 0 




__IO uint32_t CBDRBAR1
Command BDR base address register 1 




__IO uint32_t CBDRPIR
Command BDR producer index register 




__IO uint32_t CBDRCIR
Command BDR consumer index register 




__IO uint32_t CBDRLENR
Command BDR length register 







struct _netc_cbdr_handle


#include <fsl_netc_hw.h>
Handle for common part of EP/Switch NTMP. 

Public Members


netc_cbdr_hw_t *base

Point to hardware command bd ring register group. 




netc_cmd_bdr_t *cmdr

Point to command BD ring handle. 




netc_tb_data_buffer_t *buffer

Point to table common data buffer. 







struct req


Public Members


uint64_t addr

The request and response data buffers address 







struct __unnamed83__


Public Members


uint32_t resLength

The length of the Response Data Buffer 




uint32_t reqLength

The length of the Request Data Buffer 







struct __unnamed85__


Public Members


netc_tb_cmd_t cmd

Access table entry command, see netc_tb_cmd_t . 




netc_tb_access_mode_t accessType

Access table entry method, see netc_tb_access_mode_t. 




uint32_t __pad1__

RSS Hash high field value. 




uint32_t version

Protocol Version. 




uint32_t enCompInt

Command Completion Interrupt. 




uint32_t resReady

Response Ready. 







struct __unnamed87__


Public Members


uint32_t npf

NTMP Protocol Format. 







struct resp





struct __unnamed89__


Public Members


uint32_t numMatched

Number of Entries Matched. 




uint32_t error

Error status. 




uint32_t resReady

Response Ready. 







struct generic


Public Members


uint64_t addr

Data. 




uint32_t en

Enable entry. 




uint32_t siBitMap

Station interfaces 15-0 for which this filter applies. 




uint32_t index

The index refers to an entry location within a table. 




uint32_t length

NA 




uint32_t cmd

Command. 




uint32_t __pad2__

< Class of command. 




uint32_t status

Status. 




uint32_t ci

Completion interrupt. 




uint32_t sf

Short format. 







struct frameAttr


Public Members


uint16_t swtPortMas

Switch port masquerading, applicable only if the incoming port is designated as a switch management port 




uint16_t ethernet

Ethernet type Present 




uint16_t outerVlan

Outer VLAN Present 




uint16_t innerVlan

Inner VLAN Present 




netc_tb_ipf_seq_tag_t seqTag

Sequence Tag Code 




uint16_t ipHeader

IP Header Present 




uint16_t ipVersion

0b = IPv4, 1b = IPv6 




uint16_t ipExt

IPv4 option / IPv6 extension present 




netc_tb_ipf_l4_header_t l4Header

L4 Header code 




uint16_t wakeOnLan

Wake-on-LAN Magic Packet Present 







struct payload


Public Members


uint8_t data

Payload Byte n 




uint8_t mask

Payload Byte n Mask 







union __unnamed93__


Public Members


netc_tb_ipf_keye_t keye





uint32_t entryID





uint32_t sCriteria








union __unnamed95__


Public Members


netc_tb_ipf_req_data_t request





netc_tb_ipf_rsp_data_t response








union __unnamed97__


Public Members


uint32_t entryID





uint32_t sCriteria





netc_tb_isi_keye_t keye








union __unnamed99__


Public Members


netc_tb_isi_req_data_t request





netc_tb_isi_rsp_data_t response








union __unnamed101__


Public Members


netc_tb_is_req_data_t request





netc_tb_is_rsp_data_t response








union __unnamed103__


Public Members


uint32_t entryID





uint32_t sCriteria





netc_tb_isf_keye_t keye








union __unnamed105__


Public Members


netc_tb_isf_req_data_t request





netc_tb_isf_rsp_data_t response








union __unnamed107__


Public Members


netc_tb_rp_cfge_t cfge

Present only for commands which perform an update or add 




struct _netc_tb_rp_req_data







struct __unnamed109__


Public Members


netc_tb_rp_fee_t fee

Present only for commands which perform an update or add 







union __unnamed111__


Public Members


netc_tb_rp_cfge_t cfge

Present only for commands which perform a query 




struct _netc_tb_rp_rsp_data




struct _netc_tb_rp_rsp_data







struct __unnamed113__


Public Members


netc_tb_rp_fee_t fee

Present only for commands which perform a query 







struct __unnamed115__


Public Members


netc_tb_rp_pse_t pse

Present only for commands which perform a query 







union __unnamed117__


Public Members


netc_tb_rp_req_data_t request





netc_tb_rp_rsp_data_t response








union __unnamed119__


Public Members


netc_tb_isc_req_data_t request





netc_tb_isc_rsp_data_t response








union __unnamed121__


Public Members


netc_tb_sgi_sgise_t sgise





struct _netc_tb_sgi_rsp_data







struct __unnamed123__





union __unnamed125__


Public Members


netc_tb_sgi_req_data_t request





netc_tb_sgi_rsp_data_t response








union __unnamed127__


Public Members


netc_tb_sgcl_req_data_t request





netc_tb_sgcl_rsp_data_t response





struct _netc_tb_sgcl_data







struct __unnamed129__





union __unnamed131__


Public Members


netc_tb_fm_req_data_t request





netc_tb_fm_rsp_data_t response








union __unnamed133__


Public Members


netc_tb_fmd_req_data_t request





netc_tb_fmd_rsp_data_t response








union __unnamed135__


Public Members


uint32_t entryID





netc_tb_vf_search_criteria_t sCriteria

Active when access method is kNETC_Search 




netc_tb_vf_keye_t keye








union __unnamed137__


Public Members


netc_tb_vf_req_data_t request





netc_tb_vf_rsp_data_t response








struct __unnamed139__


Public Members


netc_tb_fdb_acte_t acte

Activity Element data which used to match against the table entries 




netc_tb_fdb_sc_keye_mc_t keyeMc

Key Element data match criteria 




netc_tb_fdb_sc_cfge_mc_t cfgeMc

Configuration Element data match criteria 




netc_tb_fdb_sc_acte_mc_t acteMc

Activity Element data match criteria 







union __unnamed141__


Public Members


uint32_t entryID

Active when access method is kNETC_EntryIDMatch 




netc_tb_fdb_keye_t keye

Active when access method is kNETC_ExactKeyMatch 




netc_tb_fdb_search_criteria_t sCriteria

Active when access method is kNETC_Search 







union __unnamed143__


Public Members


netc_tb_fdb_req_data_t request





netc_tb_fdb_rsp_data_t response








struct __unnamed145__


Public Members


netc_tb_l2mcf_acte_t acte

Activity Element data which used to match against the table entries 




etc_tb_l2mcf_sc_keye_mc_t keyeMc

Key Element data match criteria 




etc_tb_l2mcf_sc_cfge_mc_t cfgeMc

Configuration Element data match criteria 




etc_tb_l2mcf_sc_acte_mc_t acteMc

Activity Element data match criteria 







union __unnamed147__


Public Members


uint32_t entryID





netc_tb_l2mcf_search_criteria_t sCriteria





netc_tb_l2mcf_keye_t keye








union __unnamed149__


Public Members


netc_tb_l2mcf_req_data_t request





netc_tb_l2mcf_rsp_data_t response








union __unnamed151__


Public Members


netc_tb_iseqg_req_data_t request





netc_tb_iseqg_rsp_data_t response








union __unnamed153__


Public Members


netc_tb_eseqr_req_data_t request





netc_tb_eseqr_rsp_data_t response








union __unnamed155__


Public Members


struct _netc_tgs_gate_entry




uint32_t gate

Entry Gate Mask 







struct __unnamed157__


Public Members


uint32_t tcGateState

Traffic Class Gate States for Gate Entry, 8 bits for 8 Traffic Class , 0b means Gate closed, 1b means Gate open 




netc_tb_tgs_gate_type_t operType

Gate operation type ( IEEE 802.1Q-2018) field for gate control list entry i 







union __unnamed159__


Public Members


netc_tb_tgs_req_data_t request





netc_tb_tgs_rsp_data_t response





struct _netc_tb_tgs_data







struct __unnamed161__





union __unnamed163__


Public Members


netc_tb_et_req_data_t request





netc_tb_et_rsp_data_t response








union __unnamed165__


Public Members


netc_tb_etmcq_req_data_t request





netc_tb_etmcq_rsp_data_t response








struct wbfsWeight


Public Members


uint8_t xCode

Weight code x value 




uint8_t yCode

Weight code y value 







union __unnamed168__


Public Members


netc_tb_etmcs_req_data_t request





netc_tb_etmcs_rsp_data_t response








struct tdDRThresh


Public Members


uint16_t tn

TA 




uint16_t ta

Tn 







union __unnamed171__


Public Members


netc_tb_etmcg_req_data_t request





netc_tb_etmcg_rsp_data_t response








union __unnamed173__


Public Members


netc_tb_ec_req_data_t request





netc_tb_ec_rsp_data_t response








union __unnamed175__


Public Members


netc_tb_bp_req_data_t request





netc_tb_bp_rsp_data_t response








union __unnamed177__


Public Members


netc_tb_sbp_req_data_t request





netc_tb_sbp_rsp_data_t response








NETC MDIO Driver#


MDIO initialization module#


enum _netc_mdio_type

Enumeration for the MAC port MDIO type. 
Values:


enumerator kNETC_EMdio

Bound handle to EMDIO access, submodule of NETC. 




enumerator kNETC_InternalMdio

Bound handle to MAC port internal MDIO access, submodule of EP/Switch. 




enumerator kNETC_ExternalMdio

Bound handle to MAC port external MDIO access, submodule of EP/Switch. 






typedef enum _netc_mdio_type netc_mdio_type_t

Enumeration for the MAC port MDIO type. 




typedef struct _netc_mdio netc_mdio_t

Structure to choose MDIO entity(Internal/external MDIO for specified EP/Switch port) 




typedef struct _netc_mdio_handle netc_mdio_handle_t

MDIO handle. 




typedef struct _netc_mdio_config netc_mdio_config_t

MDIO configuration structure. 




status_t NETC_MDIOInit(netc_mdio_handle_t *handle, netc_mdio_config_t *config)

Initialize the MDIO. 

Note
The EMDIO can be used independently. The port internal/external MDIO is a part of EP/Switch, should be initialized and used after EP/Switch is enabled.


Parameters:

handle – MDIO handle. 
config – MDIO configuration. 


Returns:
status_t 






struct _netc_mdio


#include <fsl_netc_mdio.h>
Structure to choose MDIO entity(Internal/external MDIO for specified EP/Switch port) 

Public Members


netc_mdio_type_t type

Internal or external MAC port MDIO. 




netc_hw_eth_port_idx_t port

MDIO port index, only meaningful when port MDIO type is used. 







struct _netc_mdio_handle


#include <fsl_netc_mdio.h>
MDIO handle. 

Public Members


netc_mdio_t mdio

MDIO identificator. 







struct _netc_mdio_config


#include <fsl_netc_mdio.h>
MDIO configuration structure. 

Public Members


netc_mdio_t mdio

MDIO identificator. 




uint32_t srcClockHz

MDIO reference clock for MDC frequency calculation. 




bool isNegativeDriven

MDIO driven at positive(false)/negative(true) of MDC edge. 




bool isPreambleDisable

Enable/Disable generation of MDIO preamble. 







MDIO PHY status module#


typedef struct _netc_mdio_phy_status netc_mdio_phy_status_t

PHY auto status check configuration structure. 




status_t NETC_MDIOSetPhyStatusCheck(netc_mdio_handle_t *handle, netc_mdio_phy_status_t *config)

Setup the mechanism to check PHY status automatically This is a hardware mechanism to read specified PHY register in a configured time interval instead of polling the PHY in software. 

Parameters:

handle – MDIO handle. 
config – The configuration of the PHY status automatical check. 


Returns:
status_t 






void NETC_MDIOPhyStatusGetFlags(netc_mdio_handle_t *handle, uint16_t *low2HighMask, uint16_t *high2LowMask)

Get the PHY register bit status transition interrupt flag(s). 

Parameters:

handle – MDIO handle. 
low2HighMask – The interrupt flag of a 0->1 transition on a corresponding bit of PHY register. 
high2LowMask – The interrupt flag of a 1->0 transition on a corresponding bit of PHY register. 







void NETC_MDIOPhyStatusClearFlags(netc_mdio_handle_t *handle, uint16_t low2HighMask, uint16_t high2LowMask)

Clear the PHY register bit status transition interrupt flag(s). 

Parameters:

handle – MDIO handle. 
low2HighMask – Clear the interrupt flag of a 0->1 transition on a corresponding bit of PHY register. 
high2LowMask – Clear the interrupt flag of a 1->0 transition on a corresponding bit of PHY register. 







struct _netc_mdio_phy_status


#include <fsl_netc_mdio.h>
PHY auto status check configuration structure. 

Public Members


uint16_t interval

PHY status read interval in units of 1-2 ms. A value of 0 indicates disable. 




bool isC45Used

PHY status read with Clause 22/45 MDIO access. 




uint8_t phyOrPortAddr

MDIO PHY address(Clause 22) / port address(Clause 45). 




uint8_t regiOrDevAddr

MDIO register address(Clause 22) / device address(Clause 45). 




uint16_t c45RegiAddr

MDIO register address(Clause 45). 




uint16_t enableIntrHigh2Low

Bit high-to-low event interrupt enable. 




uint16_t enableIntrLow2High

Bit low-to-high event interrupt enable. 







MDIO write/read module#


status_t NETC_MDIOWrite(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

IEEE802.3 Clause 22 MDIO write data. 

Parameters:

handle – MDIO handle. 
phyAddr – The PHY address. 
regAddr – The PHY register address. 
data – The data written to PHY. 


Returns:
status_t 






status_t NETC_MDIORead(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)

IEEE802.3 Clause 22 MDIO read data. 

Parameters:

handle – MDIO handle. 
phyAddr – The PHY address. 
regAddr – The PHY register address. 
pData – The received data from PHY. 


Returns:
status_t 






status_t NETC_MDIOC45Write(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

IEEE802.3 Clause 45 MDIO write data. 

Parameters:

handle – MDIO handle. 
portAddr – The MDIO port address(PHY address). 
devAddr – The device address. 
regAddr – The PHY register address. 
data – The data written to PHY. 


Returns:
status_t 






status_t NETC_MDIOC45Read(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)

IEEE802.3 Clause 45 MDIO read data. 

Parameters:

handle – MDIO handle. 
portAddr – The MDIO port address(PHY address). 
devAddr – The device address. 
regAddr – The PHY register address. 
pData – The received data from PHY. 


Returns:
status_t 






NETC SWITCH (SWT) Driver#


Switch (SWT) data path#


Switch (SWT) Generic Configuration#


typedef struct _swt_handle swt_handle_t





typedef struct _swt_transfer_config swt_transfer_config_t





typedef status_t (*swt_reclaim_cb_t)(swt_handle_t *handle, netc_tx_frame_info_t *frameInfo, void *userData)

Callback for reclaimed tx frames. 




typedef void *(*swt_rx_alloc_cb_t)(swt_handle_t *handle, uint32_t length, void *userData)

Defines the Switch Rx memory buffer alloc function pointer. 




typedef void (*swt_rx_free_cb_t)(swt_handle_t *handle, void *address, void *userData)

Defines the Switch Rx memory buffer free function pointer. 




typedef struct _swt_config swt_config_t

Configuration structure for Switch. 




typedef struct _swt_config_const swt_config_const_t

Configuration constant structure for Switch in handle. 




status_t SWT_Init(swt_handle_t *handle, const swt_config_t *config)

Init SWITCH. 

Parameters:

handle – 
config – The user configuration 


Returns:
status_t 






status_t SWT_Deinit(swt_handle_t *handle)

Deinit switch. 

Parameters:

handle – 


Returns:
status_t 






status_t SWT_GetDefaultConfig(swt_config_t *config)

Get deafult configuration for switch. 

Parameters:

config – 


Returns:
status_t 






status_t SWT_SetEthPortMII(swt_handle_t *handle, uint8_t ethPort, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex)

Set MII speed and duplex for switch ethernet port. 

Parameters:

handle – 
ethPort – 
speed – 
duplex – 


Returns:
status_t 






static inline void SWT_SetPortSpeed(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t pSpeed)

Set switch port speed. 

Parameters:

handle – 
portIdx – 
pSpeed – 







status_t SWT_PortStop(swt_handle_t *handle, netc_hw_port_idx_t portIdx)

Stop Switch Port receive/transmit (disable both ETH and port) 

Parameters:

handle – 
portIdx – 


Returns:
status_t 






status_t SWT_SetPortMaxFrameSize(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t size)

Set switch port maximum supported received frame size. 

Parameters:

handle – 
portIdx – 
size – 


Returns:
status_t 






struct _swt_config


#include <fsl_netc_switch.h>
Configuration structure for Switch. 

Public Members


netc_hw_switch_idx_t switchIdx

Switch index 




struct _swt_config ports[5]

The common configuration required for all ports 




uint16_t dynFDBLimit

Maximum number of entries which can be dynamically learned by FDB table, a value of 0 implies no limit. 




netc_swt_psfp_config_t psfpCfg

The switch PSFP configuration, cover the ISI key construction profiles configuration 




netc_ipf_config_t ipfCfg

The switch ingress port filter configuration 




netc_vlan_classify_config_t vlanCfg

The switch ingress vlan classify configuration 




netc_swt_qos_classify_config_t rxqosCfg

The switch ingress VLAN to QoS mapping configuration 




netc_swt_qos_to_vlan_config_t txqosCfg

The switch egress QoS to VLAN mapping configuration 




netc_swt_imr_config_t imrCfg

The switch Ingress mirror configuration 




netc_swt_bridge_config_t bridgeCfg

The switch bridge configuration 




uint8_t cmdRingUse

Number of command BD rings to be used 




netc_cmd_bdr_config_t cmdBdrCfg[2]

The switch command BD rings configuration 




netc_msix_entry_t *msixEntry

MSIX table entry array. 




uint8_t entryNum

MSIX entry number. 




uint8_t cmdBdrEntryIdx[2]

MSIX entry index of command BD ring interrupt. 




uint8_t timeCaptureEntryIdx

MSIX entry index of time capture interrupt. 







struct _swt_config_const


#include <fsl_netc_switch.h>
Configuration constant structure for Switch in handle. 

Public Members


uint8_t cmdRingUse

Number of command BD rings to be used 




uint8_t entryNum

MSIX entry number. 




bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver. 




bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver. 




bool enUseMgmtRxBdRing

Enable/Disable use Switch management Rx BD ring. 




bool rxZeroCopy

Enable zero-copy receive mode. 




swt_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx. 




swt_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx. 




swt_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx Switch management frames. 




void *userData

User data, return in callback. 







struct _swt_handle


#include <fsl_netc_switch.h>
Handle for SWITCH. 

Public Members


netc_switch_hw_t hw

Hardware register map resource. 




swt_config_const_t cfg

Switch configuration constant. 




netc_cmd_bdr_t cmdBdRing[2]

Command BD ring handle for switch. 




ep_handle_t *epHandle

The EP handle to send/receive management frame. 




netc_rx_bdr_t mgmtRxBdRing

Management Receive BD ring for frames with Host Reason filed not zero. 




netc_tx_bdr_t mgmtTxBdRing

Management Transmit BD ring for Direct Switch Enqueue frames. 







struct ports


Public Members


netc_port_ethmac_t ethMac

Ethernet MAC configuration, vaild only on port 0 ~ 3 




netc_port_common_t commonCfg

Port common configuration 




netc_swt_port_bridge_config_t bridgeCfg

Port bridge configuration 




netc_swt_port_fm_config_t fmCfg

Port Frame Modification configuration 




netc_port_tx_tc_config_t txTcCfg[8]

Port Tx traffic class related configuration, vaild only on port 0 ~ 3 




uint8_t ipvToTC[8]

Port IPV to Tx traffic class queue index mapping, value means TC index, range in 0 ~ 7 




uint8_t ipvToBP[8]

Port IPV to buffer pool ID mapping, value means BP ID, range in 0 ~ (SWT_GetBPTableEntryNum() - 1) 




netc_port_psfp_isi_config isiCfg

Port Ingress stream identification 




bool enMirror

Enable/Disable Ingress Mirroring on this port 




uint8_t lanID

The HSR’s LANID this port belong to 




bool inCutThrough

Enable/Disable Ingress Cut Through on this port, vaild only on port 0 ~ 3 




bool outCutThrough

Enable/Disable Egress Cut Through on this port, vaild only on port 0 ~ 3 




bool enableTg

Enable port time gate scheduling. 




bool enTxRx

Enable port transmit/receive path, if disabled, the tx/rx of the mac corresponding to the port will also be closed. 







Switch (SWT) Interrupt Module#


status_t SWT_MsixSetGlobalMask(swt_handle_t *handle, bool mask)

Set the global MSIX mask status. 
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.

Parameters:

handle – The EP handle 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t SWT_MsixSetEntryMask(swt_handle_t *handle, uint8_t entryIdx, bool mask)

Set the MSIX entry mask status for specified entry. 
This function masks/unmasks MSIX message for specified entry.

Parameters:

handle – SWT handle. 
entryIdx – The entry index in the table. 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t SWT_MsixGetPendingStatus(swt_handle_t *handle, uint8_t pbaIdx, uint64_t *status)

Get the MSIX pending status in MSIX PBA table. 
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.

Parameters:

handle – SWT handle. 
pbaIdx – The index of PBA array with 64-bit unit. 
status – Pending status bit mask, bit n for entry n. 


Returns:
status_t 






Switch (SWT) management#


status_t SWT_BridgeInit(swt_handle_t *handle, const netc_swt_bridge_config_t *config)

Config the Bridge. 
Cover configuration below

Vlan filter table default VFHTDRCR0-2


Not Cover

Port specific Vlan config
Port Storm Control BPSCR0/R1
FDB entry
Vlan Filter Table entry
Multicast filter entry



Parameters:

handle – 
config – 


Returns:
status_t 






status_t SWT_BridgeConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_swt_port_bridge_config_t *config)

Config bridge port vlan Tx/Rx. 
Cover configuration below

Port specific Vlan config
Port Storm Control BPSCR0/R1



Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t vid)

Config bridge port default VID. 

Parameters:

handle – 
portIdx – 
vid – 


Returns:
status_t 






static inline uint32_t SWT_BridgeGetVFTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of bridge vlan filter table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, FDB, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_BridgeAddVFTableEntry(swt_handle_t *handle, netc_tb_vf_config_t *config, uint32_t *entryID)

Add entry into bridge vlan filter table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeUpdateVFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_vf_cfge_t *cfg)

Update entry in bridge vlan filter table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, netc_tb_vf_keye_t *keye, netc_tb_vf_rsp_data_t *rsp)

Query an entry in bridge VF Table. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeDelVFTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry in bridge vlan filter table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, netc_tb_vf_search_criteria_t *sCriteria, netc_tb_vf_rsp_data_t *rsp)

Search entry in bridge vlan filter table. 

Note
Only support search and return one entry at a time.


Parameters:

handle – 
sCriteria – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_BridgeGetFDBTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of bridge FDB table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, VLAN Filter, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_BridgeAddFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_config_t *config, uint32_t *entryID)

Add entry into bridge FDB table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeUpdateFDBTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_fdb_cfge_t *cfg)

Update entry in bridge FDB table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeQueryFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_keye_t *keye, netc_tb_fdb_rsp_data_t *rsp)

Query an entry in bridge FDB Table. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeSearchFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_search_criteria_t *sCriteria, netc_tb_fdb_rsp_data_t *rsp)

Search entry in bridge FDB table. 

Note
Only support search and return one entry at a time.


Parameters:

handle – 
sCriteria – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeDelFDBTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete an entry in bridge FDB Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeGetFDBActivityState(swt_handle_t *handle, uint32_t entryID, netc_tb_fdb_acte_t *state)

Get the activity data for FDB table entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_BridgeGetL2MCFTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of bridge L2 IPV4 multicast filter table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, Ingress Stream Filter, VLAN Filter, FDB table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_BridgeAddL2MCFTableEntry(swt_handle_t *handle, netc_tb_l2mcf_config_t *config, uint32_t *entryID)

Add entry into Bridge L2 IPV4 multicast filter table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeUpdateL2MCFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_l2mcf_cfge_t *cfg)

Update entry in bridge L2 IPV4 multicast filter table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeSearchL2MCFTableEntry(swt_handle_t *handle, netc_tb_l2mcf_search_criteria_t *sCriteria, netc_tb_l2mcf_rsp_data_t *rsp)

Search entry in bridge L2 IPV4 multicast filter table. 

Note
Only support search and return one entry at a time.


Parameters:

handle – 
sCriteria – 
rsp – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeGetL2MCFActivityState(swt_handle_t *handle, uint32_t entryID, netc_tb_l2mcf_acte_t *state)

Get the activity data for bridge L2 IPV4 multicast filter table entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_BridgeDelL2MCFTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry in bridge L2 IPV4 multicast filter table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline status_t SWT_FMConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_swt_port_fm_config_t *config)

Config Port level Frame Modification. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline uint32_t SWT_FMGetTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of Frame Modification table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






static inline uint32_t SWT_FMGetTableMaxEntryNum(swt_handle_t *handle)

Get maximum entry number of Frame Modification table. 

Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_FMAddTableEntry(swt_handle_t *handle, netc_tb_fm_config_t *config)

Add entry into the Frame Modification table. 
Add entry of the frame modification table. Frame modification can be encoded into the table id directly or provided as index of the table entry. refer to the frame modification entry definition.

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FMUpdateTableEntry(swt_handle_t *handle, netc_tb_fm_config_t *config)

Update entry in the Frame Modification table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FMDelTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete table entry in Frame Modification Table. 
The provided ID must be table index. Error return if the id is action encoded id.

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FMQueryTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_fm_config_t *config)

Query table entry in Frame Modification Table. 
The provided ID must be table index. Error return if the id is action encoded id.

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_FMDGetTableWordsNum(swt_handle_t *handle)

Get word number (word size is 24 bytes) of Frame Modification data table. 

Note
This is a static bounded index table, when update or query table, should satisifed: numBytes + ENTRY_ID <= 24 * wordNumber .


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_FMDUpdateTableEntry(swt_handle_t *handle, netc_tb_fmd_update_config_t *config, uint32_t length)

Update Frame Modification data table contents. 

Parameters:

handle – 
config – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FMDQueryTableEntry(swt_handle_t *handle, netc_tb_fmd_query_buffer_t *query, uint32_t length)

Query Frame Modification data table contents. 

Parameters:

handle – 
query – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_FRERGetISEQGTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of ingress Sequence Generation table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_FRERAddISEQGTableEntry(swt_handle_t *handle, netc_tb_iseqg_config_t *config)

Add entry into FRER sequence number generation table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERUpdateISEQGTableEntry(swt_handle_t *handle, netc_tb_iseqg_config_t *config)

Update entry in FRER sequence number generation table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERResetSEQGTableEntry(swt_handle_t *handle, uint32_t entryID)

Reset sequence number generation in FRER sequence generation entry. 

Parameters:

handle – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERDelISEQGTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry in FRER sequence number generation table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERGetISEQGState(swt_handle_t *handle, uint32_t entryID, netc_tb_iseqg_sgse_t *state)

Get the Sequence generation number form sequence generation table for specified entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_FRERGetESEQRTableEntryNum(swt_handle_t *handle)

Get the number of entries assigned to FRER sequence number recovery table. 

Note
This is a static bounded index table, so all entries in the table are available for SWT_FRERConfigESEQRTableEntry() API


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_FRERConfigESEQRTableEntry(swt_handle_t *handle, netc_tb_eseqr_config_t *config)

Config FRER sequence number recovery table entry. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERQueryESEQRTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_eseqr_stse_t *statistic, netc_tb_eseqr_cfge_t *config, netc_tb_eseqr_srse_t *state)

Query FRER sequence recovery table entry. 

Parameters:

handle – 
entryID – 
statistic – 
config – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_FRERGetESEQRStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_eseqr_stse_t *statistic, netc_tb_eseqr_srse_t *state)

Get FRER sequence recorvery table state and statistic. 

Parameters:

handle – 
entryID – 
statistic – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_GetBPTableEntryNum(swt_handle_t *handle)

Get Buffer Pool table entry number. 

Note
This is a static bounded index table, so all entries in the table are available for SWT_UpdateBPTableEntry() API


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_UpdateBPTableEntry(swt_handle_t *handle, netc_tb_bp_config_t *config)

Update Buffer Pool table entry. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_GetBPEntryState(swt_handle_t *handle, uint32_t entryID, netc_tb_bp_bpse_t *state)

Get Buffer Pool table entry State. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_GetSBPTableEntryNum(swt_handle_t *handle)

Get Shared Buffer Pool table entry number. 

Note
This is a static bounded index table, so all entries in the table are available for SWT_UpdateSBPTableEntry() API


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_UpdateSBPTableEntry(swt_handle_t *handle, netc_tb_sbp_config_t *config)

Update Shared Buffer Pool table entry. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_GetSBPEntryState(swt_handle_t *handle, uint32_t entryID, netc_tb_sbp_sbpse_t *state)

Get Shared Buffer Pool table entry State. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






Switch (SWT) Table Management Module#


status_t SWT_CmdBDRInit(swt_handle_t *handle, netc_hw_swt_cbdr_idx_t ring, const netc_cmd_bdr_config_t *config)

Init SWITCH command BD ring. 

Parameters:

handle – 
ring – Command BD ring index 
config – The user configuration 


Returns:
status_t 






status_t SWT_CmdBDRDeinit(swt_handle_t *handle, netc_hw_swt_cbdr_idx_t ring)

Deinit switch command BD ring. 

Parameters:

handle – 
ring – Command BD ring index 


Returns:
status_t 






Switch (SWT) Ingress data path configuration#


status_t SWT_RxMirrorConfig(swt_handle_t *handle, const netc_swt_imr_config_t *config)

Configure switch ingress mirror. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t SWT_RxParserConfig(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_parser_config_t *config)

Configure Parser in Receive Data Path. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline status_t SWT_RxVlanCInit(swt_handle_t *handle, const netc_vlan_classify_config_t *config)

Configure the customer vlan type. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t SWT_RxVlanCConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_vlan_classify_config_t *config)

Configure the Accepted Vlan for PORT. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline status_t SWT_RxQosCInit(swt_handle_t *handle, const netc_swt_qos_classify_config_t *config)

Init the ingress QoS classification for Switch. 

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t SWT_RxQosCConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_qos_classify_config_t *config)

Configure the QoS Classification for Switch Port. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline status_t SWT_RxIPFInit(swt_handle_t *handle, const netc_ipf_config_t *config)

Enable/Disable Ingress Port Filtering. 
Applied for both Switch and ENETC

Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t SWT_RxIPFConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_ipf_config_t *config)

Config the IPF for specified Port. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline uint32_t SWT_RxIPFGetTableRemainWordNum(swt_handle_t *handle)

Get remaining available word number (words size is 6 bytes) of the ingress Port Filter Table. 

Note
This is a ternary match table, and the entries can vary in size, from 2 to 14 words.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxIPFAddTableEntry(swt_handle_t *handle, netc_tb_ipf_config_t *config, uint32_t *entryID)

Add an entry for the ingress Port Filter Table. 
This function do an add & query with return hardware id which can be used as future query / delete / update.

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxIPFUpdateTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_ipf_cfge_t *cfg)

Update entry in the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxIPFQueryTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_ipf_config_t *config)

Query an entry for the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxIPFDelTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete an entry for the ingress Port Filter Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxIPFResetMatchCounter(swt_handle_t *handle, uint32_t entryID)

Reset the counter of an ingress port filter entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxIPFGetMatchedCount(swt_handle_t *handle, uint32_t entryID, uint64_t *count)

Get the matched count for entry in IPF. 

Parameters:

handle – 
entryID – 
count – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline status_t SWT_RxPSFPInit(swt_handle_t *handle, const netc_swt_psfp_config_t *config)

Init the Switch PSFP Cover configuration below. 

ISI key construction profiles (ISIDKC0CR0 - ISIDKC3CR0)


Not Cover

Port specific isi config



Parameters:

handle – 
config – 


Returns:
status_t 






static inline status_t SWT_RxPSFPConfigPortISI(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_psfp_isi_config *config)

Configure Ingress stream identification for specified port. 

Parameters:

handle – 
portIdx – 
config – 


Returns:
status_t 






static inline uint32_t SWT_RxPSFPGetISITableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of stream identification table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Filter, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddISITableEntry(swt_handle_t *handle, netc_tb_isi_config_t *config, uint32_t *entryID)

Add an entry into the stream identification table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPQueryISITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_isi_config_t *config)

Query an entry in ingress stream identification table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 






status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp)

Query an entry in ingress stream identification table using key match. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 






status_t SWT_RxPSFPDelISITableEntry(swt_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetISTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of ingress stream table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddISTableEntry(swt_handle_t *handle, netc_tb_is_config_t *config)

Add an entry into the ingress stream table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPUpdateISTableEntry(swt_handle_t *handle, netc_tb_is_config_t *config)

Updtae an entry in the ingress stream table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPQueryISTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_is_config_t *config)

Query an entry in ingress stream table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPDelISTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete an entry in the stream identification table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetISFTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number (entry size is 24 bytes) of ingress stream filter table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






static inline uint32_t SWT_RxPSFPGetISFTableMaxEntryNum(swt_handle_t *handle)

Get maximum available entry number (entry size is 24 bytes) of ingress stream filter table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddISFTableEntry(swt_handle_t *handle, netc_tb_isf_config_t *config, uint32_t *entryID)

Add an entry into the ingress stream filter table. 

Parameters:

handle – 
config – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPUpdateISFTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_isf_cfge_t *cfg)

Update an entry in the ingress stream filter table. 

Parameters:

handle – 
entryID – 
cfg – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPDelISFTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete an entry in the ingress stream filter table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetRPTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of Rate Policer table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






static inline uint32_t SWT_RxPSFPGetRPTableMaxEntryNum(swt_handle_t *handle)

Get maximum available entry number (entry size is 24 bytes) of Rate Policer table. 

Note
This is a Exact Match hash table, and it shares the remaining available entries with Ingress Stream Identification, VLAN Filter, FDB, L2 IPV4 Multicast Filter table.


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)

Add entry to Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPUpdateRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)

Update entry in Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPAddOrUpdateRPTableEntry(swt_handle_t *handle, netc_tb_rp_config_t *config)

Add or update entry in Rate Policer table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPDelRPTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry in the Rate Policer table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPQueryRPTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp)

Query entry in the stream Rate Policer table. 

Parameters:

handle – 
entryID – 
rsp – 


Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPGetRPStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_rp_stse_t *statis)

Get statistic of specified Rate Policer entry. 

Parameters:

handle – 
entryID – 
statis – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPResetMRRPTableEntry(swt_handle_t *handle, uint32_t entryID)

Reset mark red parameter of specified Rate Policer entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetISCTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of ingress stream count table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPQueryISFTableEntry(swt_handle_t *handle, netc_tb_isf_keye_t *keye, netc_tb_isf_rsp_data_t *rsp)

Query entry from the Ingress Stream Filter table. 

Parameters:

handle – 
keye – 
rsp – 


Returns:
status_t 






status_t SWT_RxPSFPAddISCTableEntry(swt_handle_t *handle, uint32_t entryID)

Add entry in ingress stream count table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPGetISCStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_isc_stse_t *statistic)

Get ingress stream count statistic. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPResetISCStatistic(swt_handle_t *handle, uint32_t entryID)

Reset the count of the ingress stream count. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetSGITableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of stream gate instance table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






static inline uint32_t SWT_RxPSFPGetSGITableMaxEntryNum(swt_handle_t *handle)

Get maximum entry number of stream gate instance table. 

Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_t *config)

Add entry in stream gate instance table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPResetIRXOEXSGITableEntry(swt_handle_t *handle, uint32_t entryID)

Reset IRX and OEX flag in stream gate instance entry. 

Parameters:

handle – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPUpdateSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_t *config)

Update entry in stream gate instance table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPDelSGITableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry in stream gate instance table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPGetSGIState(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state)

Get state of the stream gate instance for specified entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config)

Query entry in the stream gate instance table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
See netc_cmd_error_t






static inline uint32_t SWT_RxPSFPGetSGCLTableRemainWordNum(swt_handle_t *handle)

Get remaining available words number of Stream Gate Control List table. 

Note
This is a dynamic bounded index table, and number of words required for a stream gate control list is 1+N/2 where N is number of gate time slots in the stream gate control list. The remaining word should be greater than the want added entry size


Parameters:

handle – 


Returns:
uint32_t 






static inline uint32_t SWT_RxPSFPGetSGCLTableMaxWordNum(swt_handle_t *handle)

Get maximum words number of Stream Gate Control List table. 

Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_RxPSFPAddSGCLTableEntry(swt_handle_t *handle, netc_tb_sgcl_gcl_t *config)

Add entry into Stream Gate Control List Table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPDelSGCLTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry of Stream Gate Control List Table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPGetSGCLGateList(swt_handle_t *handle, netc_tb_sgcl_gcl_t *gcl, uint32_t length)

Get Stream Gate Control List Table entry gate control list. 

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_RxPSFPGetSGCLState(swt_handle_t *handle, uint32_t entryID, netc_tb_sgcl_sgclse_t *state)

Get state (ref count) for Stream Gate Control List table entry. 

Parameters:

handle – 
entryID – 
state – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






Switch (SWT) Statistic Module#


static inline status_t SWT_GetCutThroughForwardStatistic(swt_handle_t *handle, uint32_t *statistic)

Get Switch cut through forwarding count. 
Get the Cut-through frames counter of frames forwarded to at least one egress port.

Parameters:

handle – 
statistic – pointer to the statistic count data 


Returns:
kStatus_Success 






status_t SWT_GetETMCongestionGroupStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_etmcg_stse_t *statistic)

Get statistic of the congestion group. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_GetETMClassQueueStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_etmcq_stse_t *statistic)

Get the statistic for the class queue in specified switch port. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline uint32_t SWT_GetECEntryNum(swt_handle_t *handle)

Get egress count table entry number. 

Note
This is a static bounded index table, so all entries in the table are available for SWT_GetECStatistic()/SWT_ResetECStatistic() API


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_GetECStatistic(swt_handle_t *handle, uint32_t entryID, netc_tb_ec_stse_t *statistic)

Get statistic for specified egress count table entry. 

Parameters:

handle – 
entryID – 
statistic – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_ResetECStatistic(swt_handle_t *handle, uint32_t entryID)

Reset statistic for specified egress count table entry. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline status_t SWT_GetPortDiscardStatistic(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_discard_tpye_t discardType, netc_port_discard_statistic_t *statistic)

Get the port discard statistic and reason. 
Get the discarded count of frames and its reasons.

Parameters:

handle – 
portIdx – port index 
discardType – Port discard type. 
statistic – pointer to the statistic data 


Returns:
kStatus_Success 






static inline status_t SWT_ClearPortDiscardReason(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_discard_tpye_t discardType, uint32_t reason0, uint32_t reason1)

Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons. 

Parameters:

handle – 
portIdx – port index 
discardType – Port discard type. 
reason0 – 
reason1 – 


Returns:
kStatus_Success 






static inline status_t SWT_GetFDBInUseEntriesNumber(swt_handle_t *handle, netc_switch_inuse_fdb_statistic_t *statistic)

Clean the Port Rx discard reason. Set the related bits to 1 to clear the specific reasons. 

Parameters:

handle – 
statistic – 


Returns:
kStatus_Success 






static inline uint32_t SWT_GetPortTGSListStatus(swt_handle_t *handle, netc_hw_port_idx_t portIdx)

Get Switch port time gate scheduling gate list status. 

Parameters:

handle – 
portIdx – port index 


Returns:
Port status flags which are ORed by the enumerators in the netc_port_tgsl_status_t






static inline status_t SWT_SetPortIPV2QMR(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const uint8_t *ipvToTC)

Set IPV to queue mapping on Switch port. 

Parameters:

handle – 
portIdx – port index 
ipvToTC[] – queue number of each ipv value 


Returns:
kStatus_Success 






static inline status_t SWT_EnablePortMacStationMove(swt_handle_t *handle, netc_hw_port_idx_t portIdx, bool enable)

Enable MAC station move on Switch port. 

Parameters:

handle – 
portIdx – port index 
enable – Allow MAC station move 


Returns:
kStatus_Success 






static inline status_t SWT_SetPortSR(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_swt_port_sr_config_t *sr)

Set the port seamless redundancy configuration. 
Set the port seamless redundancy configuration.

Parameters:

handle – 
portIdx – port index 
sr – netc_swt_port_sr_config_t 


Returns:
kStatus_Success 






static inline status_t SWT_SetPortGroup(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint8_t pgid)

Set the port group configuration. 
Set the port group configuration.

Parameters:

handle – 
portIdx – port index 
pgid – Port Group ID 


Returns:
kStatus_Success 






Switch (SWT) Egress data path configuration#


static inline status_t SWT_TxSDUConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tc_sdu_config_t *config)

Configure the transmit maximum SDU for port Traffic Class. 

Parameters:

handle – 
portIdx – 
tcIdx – 
config – 


Returns:
status_t 






static inline status_t SWT_TxCBSConfigPort(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tc_cbs_config_t *config)

Configure the Credit Based Shaper for port Traffic Class. 

Parameters:

handle – 
portIdx – 
tcIdx – 
config – 


Returns:
status_t 






status_t SWT_TxTGSConfigAdminGcl(swt_handle_t *handle, netc_tb_tgs_gcl_t *config)

Config the Time Gate Scheduling entry admin gate control list. 
This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxtTGSGetOperGcl(swt_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32_t length)

Get Time Gate Scheduling entry operation gate control list. 
This function is used to read the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

handle – 
gcl – 
length – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxTrafficClassConfig(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config)

Config the TC (traffic class) property. 

Parameters:

handle – 
portIdx – 
tcIdx – 
config – 


Returns:
status_t 






status_t SWT_TxPortTGSEnable(swt_handle_t *handle, netc_hw_port_idx_t portIdx, bool enable, uint8_t gateState)

Enable the switch port time gate scheduling. 

Parameters:

handle – 
portIdx – 
enable – 
gateState – 


Returns:
status_t 






static inline uint32_t SWT_TxEPPGetETTableRemainEntryNum(swt_handle_t *handle)

Get remaining available entry number of egress treatment table. 

Note
This is a dynamic bounded index table, the remaining entry can’t be zero before add entry into it


Parameters:

handle – 


Returns:
uint32_t 






status_t SWT_TxEPPAddETTableEntry(swt_handle_t *handle, netc_tb_et_config_t *config)

Add entry in the egress treatment table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxEPPUpdateETTableEntry(swt_handle_t *handle, netc_tb_et_config_t *config)

Update entry in the egress treatment table. 

Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxEPPQueryETTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_et_config_t *config)

Query an entry in the egress treatment table. 

Parameters:

handle – 
entryID – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxEPPDelETTableEntry(swt_handle_t *handle, uint32_t entryID)

Delete entry for the egress treatment table. 

Parameters:

handle – 
entryID – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxEPPQosToVlanConfig(swt_handle_t *handle, const netc_swt_qos_to_vlan_config_t *config)

Configure switch egress QOS to VLAN map classification. 

Parameters:

handle – 
config – 


Returns:
status_t 






status_t SWT_TxETMConfigClassScheduler(swt_handle_t *handle, netc_tb_etmcs_config_t *config)

Configure the WBFS and Strict priority for each PORT by using ETM Class Scheduler table. 

Note
There is one class queue scheduler per switch port, and there is limitation between TSD and class queue scheduler configuration


Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxETMConfigClassQueue(swt_handle_t *handle, netc_tb_etmcq_config_t *config)

Configure the class queue to congestion group map by using ETM class queue table. 

Note
The number of class queue table entry is equal to the number of class queues in the switch


Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






status_t SWT_TxETMConfigCongestionGroup(swt_handle_t *handle, netc_tb_etmcg_config_t *config)

Config congestion group map by using ETM congestion group table. 

Note
The number of congestion groups table entry is equal to the number of class queues in the switch


Parameters:

handle – 
config – 


Returns:
status_t 

Returns:
See netc_cmd_error_t






static inline void SWT_TxTcConfigPreemption(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, const bool enable)

Config Preemption for each port TC (traffic class) 

Parameters:

handle – 
portIdx – 
tcIdx – 
enable – 







static inline void SWT_TxGetTcPreemption(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_hw_tc_idx_t tcIdx, bool *enabled)

Get Preemption configuration for each port TC (traffic class) 

Parameters:

handle – 
portIdx – 
tcIdx – 
enabled – 







static inline void SWT_TxPortEthMacConfigPreemption(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const netc_port_preemption_config *config)

Configure Preemption control configuration for an ethernet MAC. 

Parameters:

handle – 
portIdx – 
config – 







static inline void SWT_TxPortGetEthMacPreemption(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_port_preemption_config *config, netc_port_phy_mac_preemption_status_t *status)

Get Preemption control configuration from ethernet MAC port. 

Parameters:

handle – 
portIdx – 
config – 







Switch (SWT) Transmit/Receive#


enum _swt_mgmt_tx_opt_flags

Switch management Tx Option flags. 
Values:


enumerator kSWT_TX_OPT_VLAN_INSERT

Enable VLAN insert, only active when use Switch Port masquerading Tx option. 




enumerator kSWT_TX_OPT_OFFLOAD

Tx offload. 






typedef union _swt_mgmt_tx_arg_t swt_mgmt_tx_arg_t

Switch management Tx parameter. 




typedef enum _swt_mgmt_tx_opt_flags swt_mgmt_tx_opt_flags

Switch management Tx Option flags. 




typedef struct _swt_tx_opt swt_tx_opt





status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, const swt_transfer_config_t *txRxConfig)

Set the EP handle used by switch frame management. 

Parameters:

handle – 
epHandle – The EP handle 
txRxConfig – Switch transfer config 


Return values:
status_t – 






status_t SWT_SendFrame(swt_handle_t *handle, netc_frame_struct_t *frame, void *context, swt_tx_opt *opt)

Transmits a frame on management port. 

Parameters:

handle – The SWT handle 
frame – The frame descriptor pointer 
context – Private context provided back on reclaim 
opt – Tx options. 


Return values:
status_t – 






static inline void SWT_WaitUnitilTxComplete(swt_handle_t *handle, bool enMasquerade, uint8_t ring)

Wait until the EP Tx ring has completed the transfer. 

Note
Only call after EP_SendFrame() to do a no-interrupt transfer


Parameters:

handle – 
ring – Tx ring. 







void SWT_ReclaimTxDescriptor(swt_handle_t *handle, uint8_t ring)

Reclaim tx descriptors. This function is used to update the tx descriptor status. For each reclaimed transmit frame the ep_reclaim_cb_t is called. 
This is called after being notified of a transmit completion from ISR. It runs until there are no more frames to be reclaimed in the BD ring.

Parameters:

handle – 
ring – Tx ring. 







status_t SWT_ReceiveFrame(swt_handle_t *handle, netc_frame_struct_t *frame, netc_frame_attr_t *attr)

Receives management frames (host reason not zero) with zero copy. 

Parameters:

handle – 
frame – The frame descriptor pointer 
attr – Frame attribute pointer 


Returns:
kStatus_Success Successfully receive a management (host reason not zero) frame frame 

Returns:
kStatus_NETC_RxHRZeroFrame Frame in Rx BD ring is regular frame, need call EP_ReceiveFrame()

Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response 

Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty 

Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped 

Returns:
kStatus_InvalidArgument No Rx BD ring is available 

Returns:
kStatus_NETC_LackOfResource Appliction provided buffer is not enough 






status_t SWT_ReceiveFrameCopy(swt_handle_t *handle, void *buffer, uint32_t length, netc_frame_attr_t *attr)

Receives management frame (host reason not zero) which will be copied in the provided buffer. 

Note
The buffer size MUST be queried using SWT_GetRxFrameSize() beforehand.


Parameters:

handle – 
buffer – Buffer address 
length – Buffer length 
attr – Frame attribute pointer 


Returns:
kStatus_Success Successfully receive a management (host reason not zero) frame frame 

Returns:
kStatus_InvalidArgument No Rx BD ring is available 






status_t SWT_GetRxFrameSize(swt_handle_t *handle, uint32_t *length)

brief Gets the size of the pending frame in the specified receive ring buffer.

Note
Frame size without FCS, and the size will be zero when Rx BD is Timestamp Reference Response message.


Parameters:

handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init. 
length – The length of the valid frame received. 


Returns:
kStatus_Success Successfully get the length of a management (host reason not zero) frame 

Returns:
kStatus_NETC_RxHRZeroFrame Frame in Rx BD ring is regular frame, need call EP_GetRxFrameSize() to get frame size 

Returns:
kStatus_NETC_RxTsrResp Frame in Rx BD ring is Transmit Timestamp Reference Response messages, need call SWT_GetTimestampRefResp() to get Transmit Timestamp Reference Response 

Returns:
kStatus_NETC_RxFrameEmpty Rx BD ring is empty 

Returns:
kStatus_NETC_RxFrameError Frame in Rx BD ring has error, need be dropped 

Returns:
kStatus_InvalidArgument No Rx BD ring is available 






union _swt_mgmt_tx_arg_t


#include <fsl_netc_switch.h>
Switch management Tx parameter. 

Public Members


uint8_t ring

Tx ring index, use for Switch Port masquerading Tx option 




struct _swt_mgmt_tx_arg_t







struct _swt_tx_opt


Public Members


uint8_t ring

Tx ring index. 




uint32_t flags

A bitmask of @swt_mgmt_tx_opt_flags. 




netc_enetc_vlan_tag_t vlan

VLAN tag which will be inserted, used if enVlanInsert is set. 




netc_tx_offload_t offload

Offload parameters. 







struct _swt_transfer_config


#include <fsl_netc_switch.h>
Transfer configuration structure for Switch. 

Note
When need use Switch/EP receive APIs, recommended enable mgmtRxBdrConfig to use special MgmtRxBdRing rings to receive these host reason not-zero frames 


Public Members


bool rxCacheMaintain

Enable/Disable Rx buffer cache maintain in driver. 




bool txCacheMaintain

Enable/Disable Tx buffer cache maintain in driver. 




bool rxZeroCopy

Enable zero-copy receive mode. 




swt_rx_alloc_cb_t rxBuffAlloc

Callback function to alloc memory, must be provided for zero-copy Rx. 




swt_rx_free_cb_t rxBuffFree

Callback function to free memory, must be provided for zero-copy Rx. 




bool enUseMgmtRxBdRing

Enable/Disable use Switch management Rx BD ring, if disabled, the Switch/EP receive APIs (SWT_GetRxFrameSize()/SWT_ReceiveFrameCopy()/SWT_GetTimestampRefResp()/SWT_ReceiveFrame()) will use EP Rx BD ring 0 to receive frames. 




netc_rx_bdr_config_t mgmtRxBdrConfig

Switch management Rx BD ring configuration. 




bool enUseMgmtTxBdRing

Enable/Disable use Switch management Tx BD ring, if disabled, can’t use Switch transfer API (SWT_SendFrame()) to send frames. 




netc_tx_bdr_config_t mgmtTxBdrConfig

Switch management Rx BD ring configuration. 




swt_reclaim_cb_t reclaimCallback

Callback for reclaimed Tx Switch management frames. 




void *userData

User data, return in callback. 







struct __unnamed196__


Public Members


uint8_t ipv

Internal Priority Value, use for Direct Switch Enqueue Tx option 




uint8_t dr

Discard Resiliance, use for Direct Switch Enqueue Tx option 







NETC Timer Driver#


Timer adjustment module#


void NETC_TimerGetTime(ENETC_PF_TMR_Type *base, uint64_t *nanosecond)

Get the timer’s current or default time. 

Parameters:

base – NETC timer base address. 
nanosecond – Time in nanosecond. 







void NETC_TimerGetCurrentTime(netc_timer_handle_t *handle, uint64_t *nanosecond)

Get the timer’s current time. 

Parameters:

handle – NETC timer handle. 
nanosecond – Time in nanosecond. 







void NETC_TimerGetFreeRunningTime(netc_timer_handle_t *handle, uint64_t *nanosecond)

Get the timer’s freerunning time. 

Parameters:

handle – NETC timer handle. 
nanosecond – Time in nanosecond. 







void NETC_TimerAddOffset(netc_timer_handle_t *handle, int64_t nanosecond)

Correct the current timer. 

Note
Need stop all mechanims based on 1588 timers during call this API. To take time gate scheduling as example, if the port is enabled with TGS and it contains an operational list, user need to call SWT_TxPortTGSEnable()/SWT_TxPortTGSEnable() to disable the port time gate before call this API, and re-enable and configure the port TGS after the execution of this API.


Parameters:

handle – NETC timer handle. 
nanosecond – Time in nanosecond. 







void NETC_TimerAdjustFreq(netc_timer_handle_t *handle, int32_t ppb)

Adjust the timer frequency. 

Parameters:

handle – NETC timer handle. 
ppb – Parts per billion. 







void NETC_TimerGetFrtSrtTime(netc_timer_handle_t *handle, uint64_t *frt, uint64_t *srt)

Get the free running and synchronized current time with an atomic read. 

Parameters:

handle – NETC timer handle. 
frt – The free-running time in nanosecond. 
srt – The synchronized current time in nanosecond. 







Timer initialization module#


enum _netc_timer_irq_flags

Timer interrupt flags. 
Values:


enumerator kNETC_TimerFiper1IrqFlag

Periodic pulse 1 interrupt. 




enumerator kNETC_TimerFiper2IrqFlag

Periodic pulse 2 interrupt. 




enumerator kNETC_TimerFiper3IrqFlag

Periodic pulse 3 interrupt. 




enumerator kNETC_TimerAlarm1IrqFlag

Alarm 1 interrupt. 




enumerator kNETC_TimerAlarm2IrqFlag

Alarm 2 interrupt. 




enumerator kNETC_TimerExtTrig1ThresholdIrqFlag

External trigger 1 timestamp FIFO threshold hit interrupt. 




enumerator kNETC_TimerExtTrig2ThresholdIrqFlag

External trigger 2 timestamp FIFO threshold hit interrupt. 




enumerator kNETC_TimerExtTrig1TsAvailIrqFlag

External trigger 1 new timestamp available interrupt. 




enumerator kNETC_TimerExtTrig2TsAvailIrqFlag

External trigger 2 new timestamp available interrupt. 




enumerator kNETC_TimerExtTrig1OverflowIrqFlag

External trigger 1 timestamp FIFO overflow interrupt. 




enumerator kNETC_TimerExtTrig2OverflowIrqFlag

External trigger 2 timestamp FIFO overflow interrupt. 






typedef enum _netc_timer_irq_flags netc_timer_irq_flags_t

Timer interrupt flags. 




typedef struct _netc_timer_handle netc_timer_handle_t





typedef struct _netc_timer_config netc_timer_config_t

Structure to configure timer. 




status_t NETC_TimerInit(netc_timer_handle_t *handle, const netc_timer_config_t *config)

Initialize the NETC PTP1588 timer. 

Parameters:

handle – NETC timer handle. 
config – The configuration of the timer. 


Returns:
status_t 






void NETC_TimerDeinit(netc_timer_handle_t *handle)

Deinitialize the NETC PTP1588 timer. 

Parameters:

handle – NETC timer handle. 







void NETC_TimerInitHandle(netc_timer_handle_t *handle)

Initialize a NETC PTP1588 timer handle. 

Parameters:

handle – NETC timer handle. 







void NETC_TimerEnable(netc_timer_handle_t *handle, bool enable)

Enable/Disable the NETC PTP1588 timer. 

Parameters:

handle – NETC timer handle. 
enable – Whether enable the PTP1588 timer. 







struct _netc_timer_handle


#include <fsl_netc_timer.h>
Timer handler structure. 

Public Members


netc_timer_hw_t hw

Hardware register map resource. 




uint32_t timerFreq

Timer clock frequency(Hz). 




uint8_t entryNum

MSIX entry number. 







struct _netc_timer_config


#include <fsl_netc_timer.h>
Structure to configure timer. 

Public Members


bool clkOutputPhase

True: Inverted divided clock is output, False: Non-inverted divided clock is output. 




bool clkInputPhase

True: Inverted frequency tuned timer input clock, False: Non-inverted frequency tuned timer input clock. 




bool enableTimer

True: Enable 1588 timer, False: Disable 1588 timer, use default counter. 




netc_timer_ref_clk_t clockSelect

Timer reference clock. 




uint32_t refClkHz

Timer reference clock frequency in Hz. 




int32_t defaultPpb

Default ppb. 




netc_msix_entry_t *msixEntry

MSIX table entry array. 




uint8_t entryNum

MSIX entry number. 







Local time synchronization module#


enum _netc_timer_alarm_index

Enumeration for NETC timer alarm index. 
Values:


enumerator kNETC_TimerAlarm1





enumerator kNETC_TimerAlarm2







enum _netc_timer_fiper_index

Enumeration for NETC timer FIPER index. 
Values:


enumerator kNETC_TimerFiper1





enumerator kNETC_TimerFiper2





enumerator kNETC_TimerFiper3







typedef enum _netc_timer_alarm_index netc_timer_alarm_index_t

Enumeration for NETC timer alarm index. 




typedef struct _netc_timer_alarm_t netc_timer_alarm_t

Structure to configure timer alarm. 




typedef enum _netc_timer_fiper_index netc_timer_fiper_index_t

Enumeration for NETC timer FIPER index. 




typedef struct _netc_timer_fiper_config netc_timer_fiper_config_t

Structure to configure timer FIPER. 




typedef struct _netc_timer_fiper netc_timer_fiper_t

Structure to set and start timer FIPER. 




typedef struct _netc_timer_ext_pulse_trig netc_timer_ext_trig_t

Structure to configure external pulse trigger timestamp. 




void NETC_TimerConfigureAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId, const netc_timer_alarm_t *alarm)

Configure the timer alarm feature. 

Parameters:

handle – NETC timer handle. 
alarmId – The alarm index. 
alarm – The timer alarm configuration structure. 







void NETC_TimerStartAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId, uint64_t nanosecond)

Start the alarm with specified time after alarm feature is configured This function can generate a pulse on a GPIO and/or an interrupt at specified future time. It also can trigger FIPER at specified time. 

Parameters:

handle – NETC timer handle. 
alarmId – The alarm index. 
nanosecond – The time in nanosecond to generate alarm pulse. 







void NETC_TimerStopAlarm(netc_timer_handle_t *handle, netc_timer_alarm_index_t alarmId)

Stop the alarm before/after it’s fired This function can deactivate alarm. 

Parameters:

handle – NETC timer handle. 
alarmId – The alarm index. 







void NETC_TimerConfigureFIPER(netc_timer_handle_t *handle, const netc_timer_fiper_config_t *config)

Configure the timer FIPER feature. 

Parameters:

handle – NETC timer handle. 
config – The timer FIPER configuration structure. 







void NETC_TimerStartFIPER(netc_timer_handle_t *handle, netc_timer_fiper_index_t fiperId, const netc_timer_fiper_t *fiper)

Start the timer FIPER to generate pulse This function can generate a periodic(Fixed Period-FIPER) pulse on a GPIO pin and/or an interrupt to the host. 

Parameters:

handle – NETC timer handle. 
fiperId – The timer FIPER index. 
fiper – The timer FIPER configuration structure. 







void NETC_TimerStopFIPER(netc_timer_handle_t *handle, netc_timer_fiper_index_t fiperId)

Stop the timer FIPER to generate pulse. 

Parameters:

handle – NETC timer handle. 
fiperId – The timer FIPER index. 







void NETC_TimerConfigureExtPulseTrig(netc_timer_handle_t *handle, netc_timer_exttrig_index_t extTrigId, const netc_timer_ext_trig_t *extTrig)

Configure the external pulse trigger timestamp capture. 

Parameters:

handle – NETC timer handle. 
extTrigId – The timer FIPER index. 
extTrig – The external pulse trigger configuration structure. 







status_t NETC_TimerSetTsFifoThreshold(netc_timer_handle_t *handle, uint8_t threshold)

Set timestamp FIFO threshold of the external pulse trigger timestamp capture. 

Parameters:

handle – NETC timer handle. 
threshold – Timestamp FIFO threshold. 


Returns:
status_t 






status_t NETC_TimerReadExtPulseCaptureTime(netc_timer_handle_t *handle, netc_timer_exttrig_index_t extTrigId, uint64_t *nanosecond)

Read the timestamp captured by external pulse trigger in FIFO. 

Parameters:

handle – NETC timer handle. 
extTrigId – The timer FIPER index. 
nanosecond – Timestamp in nanosecond. 


Returns:
status_t 






static inline void NETC_TimerClearInterruptStatus(netc_timer_handle_t *handle, uint32_t flags)

Clear timer interrupt flags. 

Parameters:

handle – NETC timer handle. 
flags – Timer interrupt flags. This is a logical OR of enumeration :: netc_timer_irq_flags_t. 







status_t NETC_TimerMsixSetGlobalMask(netc_timer_handle_t *handle, bool mask)

Set the global MSIX mask status. 
This function masks/unmasks global MSIX message. Mask - All of the vectors are masked, regardless of their per-entry mask bit states. Unmask - Each entry’s mask status determines whether the vector is masked or not.

Parameters:

handle – The timer handle 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t NETC_TimerMsixSetEntryMask(netc_timer_handle_t *handle, uint8_t entryIdx, bool mask)

Set the MSIX entry mask status for specified entry. 
This function masks/unmasks MSIX message for specified entry.

Parameters:

handle – NETC timer handle. 
entryIdx – The entry index in the table. 
mask – The mask state. True: Mask, False: Unmask. 


Returns:
status_t 






status_t NETC_TimerMsixGetPendingStatus(netc_timer_handle_t *handle, uint8_t pbaIdx, uint64_t *status)

Get the MSIX pending status in MSIX PBA table. 
This function is to get the entry pending status from MSIX PBA table. If interrupt occurs but masked by vector control of entry, pending bit in PBA will be set.

Parameters:

handle – NETC timer handle. 
pbaIdx – The index of PBA array with 64-bit unit. 
status – Pending status bit mask, bit n for entry n. 


Returns:
status_t 






struct _netc_timer_alarm_t


#include <fsl_netc_timer.h>
Structure to configure timer alarm. 

Public Members


bool enableInterrupt

Enable/Disable ALARM interrupt enable. 




bool polarity

True: Active low output, False: Active high output. 




bool pulseGenSync

True: ALARM output asserted synchronous to timer generated clock, False: ALARM output asserted immediately. 




uint8_t pulseWidth

Pulse width in number of timer generated clocks the alarm will be active for. 







struct _netc_timer_fiper_config


#include <fsl_netc_timer.h>
Structure to configure timer FIPER. 

Public Members


bool startCondition

True: FIPER is enabled through timer enable and alarm getting set, False: FIPER is enabled through timer enable. 




bool fiper1Loopback

True: FIPER1 pulse is looped back into Trigger1 input, False: Trigger1 input is based upon normal external trigger input. 




bool fiper2Loopback

True: FIPER2 pulse is looped back into Trigger2 input, False: Trigger2 input is based upon normal external trigger input. 




uint16_t prescale

Output FIPER pulse clock is generated by dividing the timer input clock by this number. Must be an even value. 







struct _netc_timer_fiper


#include <fsl_netc_timer.h>
Structure to set and start timer FIPER. 

Public Members


bool enableInterrupt

Enable/Disable FIPER interrupt interrupt. 




bool pulseGenSync

True: FIPER output asserted synchronous to timer generated clock, False: FIPER output asserted immediately. 




uint8_t pulseWidth

FIPER pulse width. 




uint32_t pulsePeriod

Interval of FIPER pulses. 







struct _netc_timer_ext_pulse_trig


#include <fsl_netc_timer.h>
Structure to configure external pulse trigger timestamp. 

Public Members


bool polarity

Time stamp on the falling(true)/rising(false) edge of the external trigger. 




bool enableFifoOverflowInterrupt

Enable/Disable FIFO Overflow interrupt. 




bool enableFifoThresholdHitInterrupt

Enable/Disable FIFO Threshold Hit interrupt. 




bool enableTsAvailInterrupt

Enable/Disable timestamp capture interrupt. 







PDM: Microphone Interface#


PDM Driver#


void PDM_Init(PDM_Type *base, const pdm_config_t *config)

Initializes the PDM peripheral. 
Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. The configuration structure can be custom filled or set with default values by PDM_GetDefaultConfig().

Note
This API should be called at the beginning of the application to use the PDM driver. Otherwise, accessing the PDM module can cause a hard fault because the clock is not enabled.


Parameters:

base – PDM base pointer 
config – PDM configuration structure. 







void PDM_Deinit(PDM_Type *base)

De-initializes the PDM peripheral. 
This API gates the PDM clock. The PDM module can’t operate unless PDM_Init is called to enable the clock.

Parameters:

base – PDM base pointer 







static inline void PDM_Reset(PDM_Type *base)

Resets the PDM module. 

Parameters:

base – PDM base pointer 







static inline void PDM_Enable(PDM_Type *base, bool enable)

Enables/disables PDM interface. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is enabled, false means PDM interface is disabled. 







static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable)

Enables/disables debug mode for PDM. The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface enter debug mode, false means PDM interface in normal mode. 







static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable)

Enables/disables PDM interface in debug mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is enabled debug mode, false means PDM interface is disabled after after completing the current frame in debug mode. 







static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable)

Enables/disables PDM interface disable/Low Leakage mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is in disable/low leakage mode, False means PDM interface is in normal mode. 







static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable)

Enables/disables the PDM channel. 

Parameters:

base – PDM base pointer 
channel – PDM channel number need to enable or disable. 
enable – True means enable PDM channel, false means disable. 







void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config)

PDM one channel configurations. 

Parameters:

base – PDM base pointer 
config – PDM channel configurations. 
channel – channel number. after completing the current frame in debug mode. 







status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ)

PDM set sample rate. 

Note
This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is 
PDM_Init(base, pdmConfig)
PDM_SetChannelConfig(base, channel, &channelConfig)
PDM_SetSampleRateConfig(base, source, sampleRate)





Parameters:

base – PDM base pointer 
sourceClock_HZ – PDM source clock frequency. 
sampleRate_HZ – PDM sample rate. 







status_t PDM_SetSampleRate(PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv)

PDM set sample rate. 


Deprecated:
Do not use this function. It has been superceded by PDM_SetSampleRateConfig




Parameters:

base – PDM base pointer 
enableChannelMask – PDM channel enable mask. 
qualityMode – quality mode. 
osr – cic oversample rate 
clkDiv – clock divider 







uint32_t PDM_GetInstance(PDM_Type *base)

Get the instance number for PDM. 

Parameters:

base – PDM base pointer. 







static inline uint32_t PDM_GetStatus(PDM_Type *base)

Gets the PDM internal status flag. Use the Status Mask in _pdm_internal_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
PDM status flag value. 






static inline uint32_t PDM_GetFifoStatus(PDM_Type *base)

Gets the PDM FIFO status flag. Use the Status Mask in _pdm_fifo_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
FIFO status. 






static inline uint32_t PDM_GetRangeStatus(PDM_Type *base)

Gets the PDM Range status flag. Use the Status Mask in _pdm_range_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
output status. 






static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status. 

Parameters:

base – PDM base pointer 
mask – State mask. It can be a combination of the status between kPDM_StatusFrequencyLow and kPDM_StatusCh7FifoDataAvaliable. 







static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status. 

Parameters:

base – PDM base pointer 
mask – State mask.It can be a combination of the status in _pdm_fifo_status. 







static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask)

Clears the PDM range status. 

Parameters:

base – PDM base pointer 
mask – State mask. It can be a combination of the status in _pdm_range_status. 







void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask)

Enables the PDM interrupt requests. 

Parameters:

base – PDM base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kPDM_ErrorInterruptEnable 
kPDM_FIFOInterruptEnable 









static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask)

Disables the PDM interrupt requests. 

Parameters:

base – PDM base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kPDM_ErrorInterruptEnable 
kPDM_FIFOInterruptEnable 









static inline void PDM_EnableDMA(PDM_Type *base, bool enable)

Enables/disables the PDM DMA requests. 

Parameters:

base – PDM base pointer 
enable – True means enable DMA, false means disable DMA. 







static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel)

Gets the PDM data register address. 
This API is used to provide a transfer address for the PDM DMA transfer configuration.

Parameters:

base – PDM base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






void PDM_ReadFifo(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth)

PDM read fifo. 

Note
: This function support 16 bit only for IP version that only supports 16bit.


Parameters:

base – PDM base pointer. 
startChannel – start channel number. 
channelNums – total enabled channelnums. 
buffer – received buffer address. 
size – number of samples to read. 
dataWidth – sample width. 







void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain)

Set the PDM channel gain. 
Please note for different quality mode, the valid gain value is different, reference RM for detail. 

Parameters:

base – PDM base pointer. 
channel – PDM channel index. 
gain – channel gain, the register gain value range is 0 - 15. 







void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData)

Initializes the PDM handle. 
This function initializes the handle for the PDM transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – PDM base pointer. 
handle – PDM handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function. 







status_t PDM_TransferSetChannelConfig(PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format)

PDM set channel transfer config. 

Parameters:

base – PDM base pointer. 
handle – PDM handle pointer. 
channel – PDM channel. 
config – channel config. 
format – data format, support data width configurations,_pdm_data_width. 


Return values:
kStatus_PDM_ChannelConfig_Failed – or kStatus_Success. 






status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on PDM. 

Note
This API returns immediately after the transfer initiates. Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer is finished.


Parameters:

base – PDM base pointer 
handle – Pointer to the pdm_handle_t structure which stores the transfer state. 
xfer – Pointer to the pdm_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_PDM_Busy – Previous receive still not finished. 







void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle)

Aborts the current IRQ receive. 

Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – PDM base pointer 
handle – Pointer to the pdm_handle_t structure which stores the transfer state. 







void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – PDM base pointer. 
handle – Pointer to the pdm_handle_t structure. 







FSL_PDM_DRIVER_VERSION

Version 2.9.6 





PDM return status. 
Values:


enumerator kStatus_PDM_Busy

PDM is busy. 




enumerator kStatus_PDM_CLK_LOW

PDM clock frequency low 




enumerator kStatus_PDM_FIFO_ERROR

PDM FIFO underrun or overflow 




enumerator kStatus_PDM_QueueFull

PDM FIFO underrun or overflow 




enumerator kStatus_PDM_Idle

PDM is idle 




enumerator kStatus_PDM_Output_ERROR

PDM is output error 




enumerator kStatus_PDM_ChannelConfig_Failed

PDM channel config failed 






enum _pdm_interrupt_enable

The PDM interrupt enable flag. 
Values:


enumerator kPDM_ErrorInterruptEnable

PDM channel error interrupt enable. 




enumerator kPDM_FIFOInterruptEnable

PDM channel FIFO interrupt 






enum _pdm_internal_status

The PDM status. 
Values:


enumerator kPDM_StatusDfBusyFlag

Decimation filter is busy processing data 




enumerator kPDM_StatusFrequencyLow

Mic app clock frequency not high enough 




enumerator kPDM_StatusCh0FifoDataAvaliable

channel 0 fifo data reached watermark level 




enumerator kPDM_StatusCh1FifoDataAvaliable

channel 1 fifo data reached watermark level 




enumerator kPDM_StatusCh2FifoDataAvaliable

channel 2 fifo data reached watermark level 




enumerator kPDM_StatusCh3FifoDataAvaliable

channel 3 fifo data reached watermark level 






enum _pdm_channel_enable_mask

PDM channel enable mask. 
Values:


enumerator kPDM_EnableChannel0

channgel 0 enable mask 




enumerator kPDM_EnableChannel1

channgel 1 enable mask 




enumerator kPDM_EnableChannel2

channgel 2 enable mask 




enumerator kPDM_EnableChannel3

channgel 3 enable mask 




enumerator kPDM_EnableChannelAll







enum _pdm_fifo_status

The PDM fifo status. 
Values:


enumerator kPDM_FifoStatusUnderflowCh0

channel0 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh1

channel1 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh2

channel2 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh3

channel3 fifo status underflow 




enumerator kPDM_FifoStatusOverflowCh0

channel0 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh1

channel1 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh2

channel2 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh3

channel3 fifo status overflow 






enum _pdm_range_status

The PDM output status. 
Values:


enumerator kPDM_RangeStatusUnderFlowCh0

channel0 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh1

channel1 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh2

channel2 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh3

channel3 range status underflow 




enumerator kPDM_RangeStatusOverFlowCh0

channel0 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh1

channel1 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh2

channel2 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh3

channel3 range status overflow 






enum _pdm_dc_remover

PDM DC remover configurations. 
Values:


enumerator kPDM_DcRemoverCutOff20Hz

DC remover cut off 20HZ 




enumerator kPDM_DcRemoverCutOff13Hz

DC remover cut off 13.3HZ 




enumerator kPDM_DcRemoverCutOff40Hz

DC remover cut off 40HZ 




enumerator kPDM_DcRemoverBypass

DC remover bypass 






enum _pdm_df_quality_mode

PDM decimation filter quality mode. 
Values:


enumerator kPDM_QualityModeMedium

quality mode memdium 




enumerator kPDM_QualityModeHigh

quality mode high 




enumerator kPDM_QualityModeLow

quality mode low 




enumerator kPDM_QualityModeVeryLow0

quality mode very low0 




enumerator kPDM_QualityModeVeryLow1

quality mode very low1 




enumerator kPDM_QualityModeVeryLow2

quality mode very low2 






enum _pdm_qulaity_mode_k_factor

PDM quality mode K factor. 
Values:


enumerator kPDM_QualityModeHighKFactor

high quality mode K factor = 1 / 2 




enumerator kPDM_QualityModeMediumKFactor

medium/very low0 quality mode K factor = 2 / 2 




enumerator kPDM_QualityModeLowKFactor

low/very low1 quality mode K factor = 4 / 2 




enumerator kPDM_QualityModeVeryLow2KFactor

very low2 quality mode K factor = 8 / 2 






enum _pdm_df_output_gain

PDM decimation filter output gain. 
Values:


enumerator kPDM_DfOutputGain0

Decimation filter output gain 0 




enumerator kPDM_DfOutputGain1

Decimation filter output gain 1 




enumerator kPDM_DfOutputGain2

Decimation filter output gain 2 




enumerator kPDM_DfOutputGain3

Decimation filter output gain 3 




enumerator kPDM_DfOutputGain4

Decimation filter output gain 4 




enumerator kPDM_DfOutputGain5

Decimation filter output gain 5 




enumerator kPDM_DfOutputGain6

Decimation filter output gain 6 




enumerator kPDM_DfOutputGain7

Decimation filter output gain 7 




enumerator kPDM_DfOutputGain8

Decimation filter output gain 8 




enumerator kPDM_DfOutputGain9

Decimation filter output gain 9 




enumerator kPDM_DfOutputGain10

Decimation filter output gain 10 




enumerator kPDM_DfOutputGain11

Decimation filter output gain 11 




enumerator kPDM_DfOutputGain12

Decimation filter output gain 12 




enumerator kPDM_DfOutputGain13

Decimation filter output gain 13 




enumerator kPDM_DfOutputGain14

Decimation filter output gain 14 




enumerator kPDM_DfOutputGain15

Decimation filter output gain 15 






enum _pdm_data_width

PDM data width. 
Values:


enumerator kPDM_DataWwidth24

PDM data width 24bit 




enumerator kPDM_DataWwidth32

PDM data width 32bit 






typedef enum _pdm_dc_remover pdm_dc_remover_t

PDM DC remover configurations. 




typedef enum _pdm_df_quality_mode pdm_df_quality_mode_t

PDM decimation filter quality mode. 




typedef enum _pdm_df_output_gain pdm_df_output_gain_t

PDM decimation filter output gain. 




typedef struct _pdm_channel_config pdm_channel_config_t

PDM channel configurations. 




typedef struct _pdm_config pdm_config_t

PDM user configuration structure. 




typedef struct _pdm_transfer pdm_transfer_t

PDM SDMA transfer structure. 




typedef struct _pdm_handle pdm_handle_t

PDM handle. 




typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData)

PDM transfer callback prototype. 




PDM_XFER_QUEUE_SIZE

PDM XFER QUEUE SIZE. 




struct _pdm_channel_config


#include <fsl_pdm.h>
PDM channel configurations. 

Public Members


pdm_dc_remover_t outputCutOffFreq

PDM output DC remover cut off frequency 




pdm_df_output_gain_t gain

Decimation Filter Output Gain 







struct _pdm_config


#include <fsl_pdm.h>
PDM user configuration structure. 

Public Members


bool enableDoze

This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted 




bool enableFilterBypass

Switchable bypass path for the decimation filter 




uint8_t fifoWatermark

Watermark value for FIFO 




pdm_df_quality_mode_t qualityMode

Quality mode 




uint8_t cicOverSampleRate

CIC filter over sampling rate 







struct _pdm_transfer


#include <fsl_pdm.h>
PDM SDMA transfer structure. 

Public Members


volatile uint8_t *data

Data start address to transfer. 




volatile size_t dataSize

Total Transfer bytes size. 







struct _pdm_handle


#include <fsl_pdm.h>
PDM handle structure. 

Public Members


uint32_t state

Transfer status 




pdm_transfer_callback_t callback

Callback function called at transfer event 




void *userData

Callback parameter passed to callback function 




pdm_transfer_t pdmQueue[(4U)]

Transfer queue storing queued transfer 




size_t transferSize[(4U)]

Data bytes need to transfer 




volatile uint8_t queueUser

Index for user to queue transfer 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 




uint32_t format

data format 




uint8_t watermark

Watermark value 




uint8_t startChannel

end channel 




uint8_t channelNums

Enabled channel number 







PDM EDMA Driver#


void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum)

Install EDMA descriptor memory. 

Parameters:

handle – Pointer to EDMA channel transfer handle. 
tcdAddr – EDMA head descriptor address. 
tcdNum – EDMA link descriptor address. 







void PDM_TransferCreateHandleEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the PDM Rx eDMA handle. 
This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. Usually, for a specified PDM instance, call this API once to get the initialized handle.

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
dmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, pdm_edma_multi_channel_interleave_t multiChannelInterleaveType)

Initializes the multi PDM channel interleave type. 
This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is kPDM_EDMAMultiChannelInterleavePerChannelSample always

Parameters:

handle – PDM eDMA handle pointer. 
multiChannelInterleaveType – Multi channel interleave type. 







void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, pdm_edma_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config)

Configures the PDM channel. 

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 
channel – channel index. 
config – pdm channel configurations. 







status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer)

Performs a non-blocking PDM receive using eDMA. 

Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally.

Scatter gather case: This functio support dynamic scatter gather and staic scatter gather, a. for the dynamic scatter gather case: Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit before the previous one finish. b. for the static scatter gather case: Application should use the link transfer feature and make sure a loop link transfer is provided, such as: 
pdm_edma_transfer_t pdmXfer[2] =
 {
     {
     .data  = s_buffer,
     .dataSize = BUFFER_SIZE,
     .linkTransfer = &pdmXfer[1],
     },

     {
     .data  = &s_buffer[BUFFER_SIZE],
     .dataSize = BUFFER_SIZE,
     .linkTransfer = &pdmXfer[0]
     },
 };



Multi channel case: This function support receive multi pdm channel data, for example, if two channel is requested, 
PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig);
PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig);
PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer);


 The output data will be formatted as below if handle->interleaveType = 



Note
This interface returns immediately after the transfer initiates. Call the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished.





void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Terminate all PDM receive. 
This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the current transfer slot, please call PDM_TransferAbortReceiveEDMA.

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 







void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Aborts a PDM receive using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA.

Parameters:

base – PDM base pointer 
handle – PDM eDMA handle pointer. 







status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count)

Gets byte count received by PDM. 

Parameters:

base – PDM base pointer 
handle – PDM eDMA handle pointer. 
count – Bytes count received by PDM. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







FSL_PDM_EDMA_DRIVER_VERSION

Version 2.6.5 




enum _pdm_edma_multi_channel_interleave

pdm multi channel interleave type 
Values:


enumerator kPDM_EDMAMultiChannelInterleavePerChannelSample





enumerator kPDM_EDMAMultiChannelInterleavePerChannelBlock







typedef struct _pdm_edma_handle pdm_edma_handle_t

PDM edma handler. 




typedef enum _pdm_edma_multi_channel_interleave pdm_edma_multi_channel_interleave_t

pdm multi channel interleave type 




typedef struct _pdm_edma_transfer pdm_edma_transfer_t

PDM edma transfer. 




typedef void (*pdm_edma_callback_t)(PDM_Type *base, pdm_edma_handle_t *handle, status_t status, void *userData)

PDM eDMA transfer callback function for finish and error. 




MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL

the PDM enable position When calling PDM_TransferReceiveEDMA 




struct _pdm_edma_transfer


#include <fsl_pdm_edma.h>
PDM edma transfer. 

Public Members


volatile uint8_t *data

Data start address to transfer. 




volatile size_t dataSize

Total Transfer bytes size. 




struct _pdm_edma_transfer *linkTransfer

linked transfer configurations 







struct _pdm_edma_handle


#include <fsl_pdm_edma.h>
PDM DMA transfer handle, users should not touch the content of the handle. 

Public Members


edma_handle_t *dmaHandle

DMA handler for PDM send 




uint8_t count

The transfer data count in a DMA request 




uint32_t receivedBytes

total transfer count 




uint32_t state

Internal state for PDM eDMA transfer 




pdm_edma_callback_t callback

Callback for users while transfer finish or error occurs 




bool isLoopTransfer

loop transfer 




void *userData

User callback parameter 




edma_tcd_t *tcd

TCD pool for eDMA transfer. 




uint32_t tcdNum

TCD number 




uint32_t tcdUser

Index for user to queue transfer. 




uint32_t tcdDriver

Index for driver to get the transfer data and size 




volatile uint32_t tcdUsedNum

Index for user to queue transfer. 




pdm_edma_multi_channel_interleave_t interleaveType

multi channel transfer interleave type 




uint8_t endChannel

The last enabled channel 




uint8_t channelNums

total channel numbers 







PWM: Pulse Width Modulator#


status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)

Ungates the PWM submodule clock and configures the peripheral for basic operation. 
This API should be called at the beginning of the application using the PWM driver. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. When output PWMX in center aligned mode, VAL1 register controls both PWM period and PWMX duty cycle, PWMA and PWMB output will be corrupted. But edge aligned PWMX output do not have such limit. In master reload counter initialization mode, PWM period is depended by period of set LDOK in submodule 0 because this operation will reload register. Submodule 0 counter initialization cannot be master sync or master reload.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
config – Pointer to user’s PWM config structure.


Returns:
kStatus_Success means success; else failed. 






void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)

Gate the PWM submodule clock. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to deinitialize 







void PWM_GetDefaultConfig(pwm_config_t *config)

Fill in the PWM config struct with the default settings. 
The default values are: 
config->enableDebugMode = false;
config->enableWait = false;
config->reloadSelect = kPWM_LocalReload;
config->clockSource = kPWM_BusClock;
config->prescale = kPWM_Prescale_Divide_1;
config->initializationControl = kPWM_Initialize_LocalSync;
config->forceTrigger = kPWM_Force_Local;
config->reloadFrequency = kPWM_LoadEveryOportunity;
config->reloadLogic = kPWM_ReloadImmediate;
config->pairOperation = kPWM_Independent;


 

Parameters:

config – Pointer to user’s PWM config structure. 







status_t PWM_SetupPwm(PWM_Type *base, pwm_submodule_t subModule, const pwm_signal_param_t *chnlParams, uint8_t numOfChnls, pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)

Sets up the PWM signals for a PWM submodule. 
The function initializes the submodule according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. Due to edge aligned PWMX is negative true signal, need to configure PWMX active low true level to get correct duty cycle. The half cycle point will not be exactly in the middle of the PWM cycle when PWMX enabled.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
chnlParams – Array of PWM channel parameters to configure the channel(s). 
numOfChnls – Number of channels to configure, this should be the size of the array passed in. Array size should not be more than 3 as each submodule has 3 pins to output PWM. 
mode – PWM operation mode, options available in enumeration pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz 
srcClock_Hz – PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 prescaler value instead of submodule0 source clock.


Returns:
Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise 






status_t PWM_SetupPwmPhaseShift(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, uint8_t shiftvalue, bool doSync)

Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
pwmFreq_Hz – PWM signal frequency in Hz 
srcClock_Hz – PWM main counter clock in Hz. 
shiftvalue – Phase shift value, range in 0 ~ 50 
doSync – true: Set LDOK bit for the submodule list; false: LDOK bit don’t set, need to call PWM_SetPwmLdok to sync update.


Returns:
Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise 






void PWM_UpdatePwmDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint8_t dutyCyclePercent)

Updates the PWM signal’s dutycycle. 
The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmSignal – Signal (PWM A, PWM B, PWM X) to update 
currPwmMode – The current PWM mode set during PWM setup 
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle) 







void PWM_UpdatePwmDutycycleHighAccuracy(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle)

Updates the PWM signal’s dutycycle with 16-bit accuracy. 
The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmSignal – Signal (PWM A, PWM B, PWM X) to update 
currPwmMode – The current PWM mode set during PWM setup 
dutyCycle – New PWM pulse width, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle) 







void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t pulseCnt, uint16_t dutyCycle)

Update the PWM signal’s period and dutycycle for a PWM submodule. 
The function updates PWM signal period generated by a specific submodule according to the parameters passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle or update new dutycycle. Call this function in local sync control mode because PWM period is depended by
INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. PWM signal will not be generated if its period is less than dead time duration.


Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmSignal – Signal (PWM A or PWM B) to update 
currPwmMode – The current PWM mode set during PWM setup, options available in enumeration pwm_mode_t
pulseCnt – New PWM period, value should be between 0 to 65535 0=minimum PWM period… 65535=maximum PWM period 
dutyCycle – New PWM pulse width of channel, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle) You can keep original duty cycle or update new duty cycle 







static inline void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Enables the selected PWM interrupts. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t







static inline void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Disables the selected PWM interrupts. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t







static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)

Gets the enabled PWM interrupts. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t






static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, pwm_submodule_t subModule, pwm_watermark_control_t pwm_watermark_control)

Capture DMA Enable Source Select. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwm_watermark_control – PWM FIFO watermark and control 







static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, pwm_submodule_t subModule, pwm_dma_source_select_t pwm_dma_source_select)

Capture DMA Enable Source Select. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwm_dma_source_select – PWM capture DMA enable source select 







static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate)

Enables or disables the selected PWM DMA Capture read request. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
mask – The DMA to enable or disable. This is a logical OR of members of the enumeration pwm_dma_enable_t
activate – true: Enable DMA read request; false: Disable DMA read request 







static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate)

Enables or disables the PWM DMA write request. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
activate – true: Enable DMA write request; false: Disable DMA write request 







static inline uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)

Gets the PWM status flags. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure


Returns:
The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t






static inline void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)

Clears the PWM status flags. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
mask – The status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t







static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart)

Starts the PWM counter for a single or multiple submodules. 
Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple submodules at the same time.

Parameters:

base – PWM peripheral base address 
subModulesToStart – PWM submodules to start. This is a logical OR of members of the enumeration pwm_module_control_t







static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop)

Stops the PWM counter for a single or multiple submodules. 
Clears the Run bit which resets the submodule’s counter. This function can stop multiple submodules at the same time.

Parameters:

base – PWM peripheral base address 
subModulesToStop – PWM submodules to stop. This is a logical OR of members of the enumeration pwm_module_control_t







FSL_PWM_DRIVER_VERSION

Version 2.10.1 




enum _pwm_submodule

List of PWM submodules. 
Values:


enumerator kPWM_Module_0

Submodule 0 




enumerator kPWM_Module_1

Submodule 1 




enumerator kPWM_Module_2

Submodule 2 






enum _pwm_channels

List of PWM channels in each module. 
Values:


enumerator kPWM_PwmB





enumerator kPWM_PwmA





enumerator kPWM_PwmX







enum _pwm_value_register

List of PWM value registers. 
Values:


enumerator kPWM_ValueRegister_0

PWM Value0 register 




enumerator kPWM_ValueRegister_1

PWM Value1 register 




enumerator kPWM_ValueRegister_2

PWM Value2 register 




enumerator kPWM_ValueRegister_3

PWM Value3 register 




enumerator kPWM_ValueRegister_4

PWM Value4 register 




enumerator kPWM_ValueRegister_5

PWM Value5 register 






enum _pwm_value_register_mask

List of PWM value registers mask. 
Values:


enumerator kPWM_ValueRegisterMask_0

PWM Value0 register mask 




enumerator kPWM_ValueRegisterMask_1

PWM Value1 register mask 




enumerator kPWM_ValueRegisterMask_2

PWM Value2 register mask 




enumerator kPWM_ValueRegisterMask_3

PWM Value3 register mask 




enumerator kPWM_ValueRegisterMask_4

PWM Value4 register mask 




enumerator kPWM_ValueRegisterMask_5

PWM Value5 register mask 






enum _pwm_clock_source

PWM clock source selection. 
Values:


enumerator kPWM_BusClock

Device specific IPBus clock, refer reference manual for frequency 




enumerator kPWM_ExternalClock

EXT_CLK is used as the clock 




enumerator kPWM_Submodule0Clock

Clock of the submodule 0 (AUX_CLK) is used as the source clock 






enum _pwm_clock_prescale

PWM prescaler factor selection for clock source. 
Values:


enumerator kPWM_Prescale_Divide_1

PWM clock frequency = fclk/1 




enumerator kPWM_Prescale_Divide_2

PWM clock frequency = fclk/2 




enumerator kPWM_Prescale_Divide_4

PWM clock frequency = fclk/4 




enumerator kPWM_Prescale_Divide_8

PWM clock frequency = fclk/8 




enumerator kPWM_Prescale_Divide_16

PWM clock frequency = fclk/16 




enumerator kPWM_Prescale_Divide_32

PWM clock frequency = fclk/32 




enumerator kPWM_Prescale_Divide_64

PWM clock frequency = fclk/64 




enumerator kPWM_Prescale_Divide_128

PWM clock frequency = fclk/128 






enum _pwm_force_output_trigger

Options that can trigger a PWM FORCE_OUT. 
Values:


enumerator kPWM_Force_Local

The local force signal, CTRL2[FORCE], from the submodule is used to force updates 




enumerator kPWM_Force_Master

The master force signal from submodule 0 is used to force updates 




enumerator kPWM_Force_LocalReload

The local reload signal from this submodule is used to force updates without regard to the state of LDOK 




enumerator kPWM_Force_MasterReload

The master reload signal from submodule 0 is used to force updates if LDOK is set 




enumerator kPWM_Force_LocalSync

The local sync signal from this submodule is used to force updates 




enumerator kPWM_Force_MasterSync

The master sync signal from submodule0 is used to force updates 




enumerator kPWM_Force_External

The external force signal, EXT_FORCE, from outside the PWM module causes updates 




enumerator kPWM_Force_ExternalSync

The external sync signal, EXT_SYNC, from outside the PWM module causes updates 






enum _pwm_output_state

PWM channel output status. 
Values:


enumerator kPWM_HighState

The output state of PWM channel is high 




enumerator kPWM_LowState

The output state of PWM channel is low 




enumerator kPWM_NormalState

The output state of PWM channel is normal 




enumerator kPWM_InvertState

The output state of PWM channel is invert 




enumerator kPWM_MaskState

The output state of PWM channel is mask 






enum _pwm_init_source

PWM counter initialization options. 
Values:


enumerator kPWM_Initialize_LocalSync

Local sync causes initialization 




enumerator kPWM_Initialize_MasterReload

Master reload from submodule 0 causes initialization 




enumerator kPWM_Initialize_MasterSync

Master sync from submodule 0 causes initialization 




enumerator kPWM_Initialize_ExtSync

EXT_SYNC causes initialization 






enum _pwm_load_frequency

PWM load frequency selection. 
Values:


enumerator kPWM_LoadEveryOportunity

Every PWM opportunity 




enumerator kPWM_LoadEvery2Oportunity

Every 2 PWM opportunities 




enumerator kPWM_LoadEvery3Oportunity

Every 3 PWM opportunities 




enumerator kPWM_LoadEvery4Oportunity

Every 4 PWM opportunities 




enumerator kPWM_LoadEvery5Oportunity

Every 5 PWM opportunities 




enumerator kPWM_LoadEvery6Oportunity

Every 6 PWM opportunities 




enumerator kPWM_LoadEvery7Oportunity

Every 7 PWM opportunities 




enumerator kPWM_LoadEvery8Oportunity

Every 8 PWM opportunities 




enumerator kPWM_LoadEvery9Oportunity

Every 9 PWM opportunities 




enumerator kPWM_LoadEvery10Oportunity

Every 10 PWM opportunities 




enumerator kPWM_LoadEvery11Oportunity

Every 11 PWM opportunities 




enumerator kPWM_LoadEvery12Oportunity

Every 12 PWM opportunities 




enumerator kPWM_LoadEvery13Oportunity

Every 13 PWM opportunities 




enumerator kPWM_LoadEvery14Oportunity

Every 14 PWM opportunities 




enumerator kPWM_LoadEvery15Oportunity

Every 15 PWM opportunities 




enumerator kPWM_LoadEvery16Oportunity

Every 16 PWM opportunities 






enum _pwm_fault_input

List of PWM fault selections. 
Values:


enumerator kPWM_Fault_0

Fault 0 input pin 




enumerator kPWM_Fault_1

Fault 1 input pin 




enumerator kPWM_Fault_2

Fault 2 input pin 




enumerator kPWM_Fault_3

Fault 3 input pin 






enum _pwm_fault_disable

List of PWM fault disable mapping selections. 
Values:


enumerator kPWM_FaultDisable_0

Fault 0 disable mapping 




enumerator kPWM_FaultDisable_1

Fault 1 disable mapping 




enumerator kPWM_FaultDisable_2

Fault 2 disable mapping 




enumerator kPWM_FaultDisable_3

Fault 3 disable mapping 






enum _pwm_fault_channels

List of PWM fault channels. 
Values:


enumerator kPWM_faultchannel_0







enum _pwm_input_capture_edge

PWM capture edge select. 
Values:


enumerator kPWM_Disable

Disabled 




enumerator kPWM_FallingEdge

Capture on falling edge only 




enumerator kPWM_RisingEdge

Capture on rising edge only 




enumerator kPWM_RiseAndFallEdge

Capture on rising or falling edge 






enum _pwm_force_signal

PWM output options when a FORCE_OUT signal is asserted. 
Values:


enumerator kPWM_UsePwm

Generated PWM signal is used by the deadtime logic. 




enumerator kPWM_InvertedPwm

Inverted PWM signal is used by the deadtime logic. 




enumerator kPWM_SoftwareControl

Software controlled value is used by the deadtime logic. 




enumerator kPWM_UseExternal

PWM_EXTA signal is used by the deadtime logic. 






enum _pwm_chnl_pair_operation

Options available for the PWM A & B pair operation. 
Values:


enumerator kPWM_Independent

PWM A & PWM B operate as 2 independent channels 




enumerator kPWM_ComplementaryPwmA

PWM A & PWM B are complementary channels, PWM A generates the signal 




enumerator kPWM_ComplementaryPwmB

PWM A & PWM B are complementary channels, PWM B generates the signal 






enum _pwm_register_reload

Options available on how to load the buffered-registers with new values. 
Values:


enumerator kPWM_ReloadImmediate

Buffered-registers get loaded with new values as soon as LDOK bit is set 




enumerator kPWM_ReloadPwmHalfCycle

Registers loaded on a PWM half cycle 




enumerator kPWM_ReloadPwmFullCycle

Registers loaded on a PWM full cycle 




enumerator kPWM_ReloadPwmHalfAndFullCycle

Registers loaded on a PWM half & full cycle 






enum _pwm_fault_recovery_mode

Options available on how to re-enable the PWM output when recovering from a fault. 
Values:


enumerator kPWM_NoRecovery

PWM output will stay inactive 




enumerator kPWM_RecoverHalfCycle

PWM output re-enabled at the first half cycle 




enumerator kPWM_RecoverFullCycle

PWM output re-enabled at the first full cycle 




enumerator kPWM_RecoverHalfAndFullCycle

PWM output re-enabled at the first half or full cycle 






enum _pwm_interrupt_enable

List of PWM interrupt options. 
Values:


enumerator kPWM_CompareVal0InterruptEnable

PWM VAL0 compare interrupt 




enumerator kPWM_CompareVal1InterruptEnable

PWM VAL1 compare interrupt 




enumerator kPWM_CompareVal2InterruptEnable

PWM VAL2 compare interrupt 




enumerator kPWM_CompareVal3InterruptEnable

PWM VAL3 compare interrupt 




enumerator kPWM_CompareVal4InterruptEnable

PWM VAL4 compare interrupt 




enumerator kPWM_CompareVal5InterruptEnable

PWM VAL5 compare interrupt 




enumerator kPWM_CaptureX0InterruptEnable

PWM capture X0 interrupt 




enumerator kPWM_CaptureX1InterruptEnable

PWM capture X1 interrupt 




enumerator kPWM_CaptureB0InterruptEnable

PWM capture B0 interrupt 




enumerator kPWM_CaptureB1InterruptEnable

PWM capture B1 interrupt 




enumerator kPWM_CaptureA0InterruptEnable

PWM capture A0 interrupt 




enumerator kPWM_CaptureA1InterruptEnable

PWM capture A1 interrupt 




enumerator kPWM_ReloadInterruptEnable

PWM reload interrupt 




enumerator kPWM_ReloadErrorInterruptEnable

PWM reload error interrupt 




enumerator kPWM_Fault0InterruptEnable

PWM fault 0 interrupt 




enumerator kPWM_Fault1InterruptEnable

PWM fault 1 interrupt 




enumerator kPWM_Fault2InterruptEnable

PWM fault 2 interrupt 




enumerator kPWM_Fault3InterruptEnable

PWM fault 3 interrupt 






enum _pwm_status_flags

List of PWM status flags. 
Values:


enumerator kPWM_CompareVal0Flag

PWM VAL0 compare flag 




enumerator kPWM_CompareVal1Flag

PWM VAL1 compare flag 




enumerator kPWM_CompareVal2Flag

PWM VAL2 compare flag 




enumerator kPWM_CompareVal3Flag

PWM VAL3 compare flag 




enumerator kPWM_CompareVal4Flag

PWM VAL4 compare flag 




enumerator kPWM_CompareVal5Flag

PWM VAL5 compare flag 




enumerator kPWM_CaptureX0Flag

PWM capture X0 flag 




enumerator kPWM_CaptureX1Flag

PWM capture X1 flag 




enumerator kPWM_CaptureB0Flag

PWM capture B0 flag 




enumerator kPWM_CaptureB1Flag

PWM capture B1 flag 




enumerator kPWM_CaptureA0Flag

PWM capture A0 flag 




enumerator kPWM_CaptureA1Flag

PWM capture A1 flag 




enumerator kPWM_ReloadFlag

PWM reload flag 




enumerator kPWM_ReloadErrorFlag

PWM reload error flag 




enumerator kPWM_RegUpdatedFlag

PWM registers updated flag 




enumerator kPWM_Fault0Flag

PWM fault 0 flag 




enumerator kPWM_Fault1Flag

PWM fault 1 flag 




enumerator kPWM_Fault2Flag

PWM fault 2 flag 




enumerator kPWM_Fault3Flag

PWM fault 3 flag 






enum _pwm_dma_enable

List of PWM DMA options. 
Values:


enumerator kPWM_CaptureX0DMAEnable

PWM capture X0 DMA 




enumerator kPWM_CaptureX1DMAEnable

PWM capture X1 DMA 




enumerator kPWM_CaptureB0DMAEnable

PWM capture B0 DMA 




enumerator kPWM_CaptureB1DMAEnable

PWM capture B1 DMA 




enumerator kPWM_CaptureA0DMAEnable

PWM capture A0 DMA 




enumerator kPWM_CaptureA1DMAEnable

PWM capture A1 DMA 






enum _pwm_dma_source_select

List of PWM capture DMA enable source select. 
Values:


enumerator kPWM_DMARequestDisable

Read DMA requests disabled 




enumerator kPWM_DMAWatermarksEnable

Exceeding a FIFO watermark sets the DMA read request 




enumerator kPWM_DMALocalSync

A local sync (VAL1 matches counter) sets the read DMA request 




enumerator kPWM_DMALocalReload

A local reload (STS[RF] being set) sets the read DMA request 






enum _pwm_watermark_control

PWM FIFO Watermark AND Control. 
Values:


enumerator kPWM_FIFOWatermarksOR

Selected FIFO watermarks are OR’ed together 




enumerator kPWM_FIFOWatermarksAND

Selected FIFO watermarks are AND’ed together 






enum _pwm_mode

PWM operation mode. 
Values:


enumerator kPWM_SignedCenterAligned

Signed center-aligned 




enumerator kPWM_CenterAligned

Unsigned cente-aligned 




enumerator kPWM_SignedEdgeAligned

Signed edge-aligned 




enumerator kPWM_EdgeAligned

Unsigned edge-aligned 






enum _pwm_level_select

PWM output pulse mode, high-true or low-true. 
Values:


enumerator kPWM_HighTrue

High level represents “on” or “active” state 




enumerator kPWM_LowTrue

Low level represents “on” or “active” state 






enum _pwm_fault_state

PWM output fault status. 
Values:


enumerator kPWM_PwmFaultState0

Output is forced to logic 0 state prior to consideration of output polarity control. 




enumerator kPWM_PwmFaultState1

Output is forced to logic 1 state prior to consideration of output polarity control. 




enumerator kPWM_PwmFaultState2

Output is tristated. 




enumerator kPWM_PwmFaultState3

Output is tristated. 






enum _pwm_reload_source_select

PWM reload source select. 
Values:


enumerator kPWM_LocalReload

The local reload signal is used to reload registers 




enumerator kPWM_MasterReload

The master reload signal (from submodule 0) is used to reload 






enum _pwm_fault_clear

PWM fault clearing options. 
Values:


enumerator kPWM_Automatic

Automatic fault clearing 




enumerator kPWM_ManualNormal

Manual fault clearing with no fault safety mode 




enumerator kPWM_ManualSafety

Manual fault clearing with fault safety mode 






enum _pwm_module_control

Options for submodule master control operation. 
Values:


enumerator kPWM_Control_Module_0

Control submodule 0’s start/stop,buffer reload operation 




enumerator kPWM_Control_Module_1

Control submodule 1’s start/stop,buffer reload operation 




enumerator kPWM_Control_Module_2

Control submodule 2’s start/stop,buffer reload operation 




enumerator kPWM_Control_Module_3

Control submodule 3’s start/stop,buffer reload operation 






typedef enum _pwm_submodule pwm_submodule_t

List of PWM submodules. 




typedef enum _pwm_channels pwm_channels_t

List of PWM channels in each module. 




typedef enum _pwm_value_register pwm_value_register_t

List of PWM value registers. 




typedef enum _pwm_clock_source pwm_clock_source_t

PWM clock source selection. 




typedef enum _pwm_clock_prescale pwm_clock_prescale_t

PWM prescaler factor selection for clock source. 




typedef enum _pwm_force_output_trigger pwm_force_output_trigger_t

Options that can trigger a PWM FORCE_OUT. 




typedef enum _pwm_output_state pwm_output_state_t

PWM channel output status. 




typedef enum _pwm_init_source pwm_init_source_t

PWM counter initialization options. 




typedef enum _pwm_load_frequency pwm_load_frequency_t

PWM load frequency selection. 




typedef enum _pwm_fault_input pwm_fault_input_t

List of PWM fault selections. 




typedef enum _pwm_fault_disable pwm_fault_disable_t

List of PWM fault disable mapping selections. 




typedef enum _pwm_fault_channels pwm_fault_channels_t

List of PWM fault channels. 




typedef enum _pwm_input_capture_edge pwm_input_capture_edge_t

PWM capture edge select. 




typedef enum _pwm_force_signal pwm_force_signal_t

PWM output options when a FORCE_OUT signal is asserted. 




typedef enum _pwm_chnl_pair_operation pwm_chnl_pair_operation_t

Options available for the PWM A & B pair operation. 




typedef enum _pwm_register_reload pwm_register_reload_t

Options available on how to load the buffered-registers with new values. 




typedef enum _pwm_fault_recovery_mode pwm_fault_recovery_mode_t

Options available on how to re-enable the PWM output when recovering from a fault. 




typedef enum _pwm_interrupt_enable pwm_interrupt_enable_t

List of PWM interrupt options. 




typedef enum _pwm_status_flags pwm_status_flags_t

List of PWM status flags. 




typedef enum _pwm_dma_enable pwm_dma_enable_t

List of PWM DMA options. 




typedef enum _pwm_dma_source_select pwm_dma_source_select_t

List of PWM capture DMA enable source select. 




typedef enum _pwm_watermark_control pwm_watermark_control_t

PWM FIFO Watermark AND Control. 




typedef enum _pwm_mode pwm_mode_t

PWM operation mode. 




typedef enum _pwm_level_select pwm_level_select_t

PWM output pulse mode, high-true or low-true. 




typedef enum _pwm_fault_state pwm_fault_state_t

PWM output fault status. 




typedef enum _pwm_reload_source_select pwm_reload_source_select_t

PWM reload source select. 




typedef enum _pwm_fault_clear pwm_fault_clear_t

PWM fault clearing options. 




typedef enum _pwm_module_control pwm_module_control_t

Options for submodule master control operation. 




typedef struct _pwm_signal_param pwm_signal_param_t

Structure for the user to define the PWM signal characteristics. 




typedef struct _pwm_config pwm_config_t

PWM config structure. 
This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 




typedef struct _pwm_fault_input_filter_param pwm_fault_input_filter_param_t

Structure for the user to configure the fault input filter. 




typedef struct _pwm_fault_param pwm_fault_param_t

Structure is used to hold the parameters to configure a PWM fault. 




typedef struct _pwm_input_capture_param pwm_input_capture_param_t

Structure is used to hold parameters to configure the capture capability of a signal pin. 




void PWM_SetupInputCapture(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, const pwm_input_capture_param_t *inputCaptureParams)

Sets up the PWM input capture. 
Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function sets up the capture parameters for each pin and enables the pin for input capture operation.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – Channel in the submodule to setup 
inputCaptureParams – Parameters passed in to set up the input pin 







status_t PWM_GetInputCaptureValue(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint8_t captureIndex, uint16_t *captureValue)

Read the capture value. 
This function reads the capture value stored in channel’s capture value register. It should be called when a valid edge is detected on the input capture pin(related capture flag is set). The capture circuit has two input capture registers per channel for first edge and second edge capture.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to read from (PWM A, PWM B, or PWM X) 
captureIndex – Capture register to read (0 for first edge capture, 1 for second edge capture)


Returns:
Returns kStatus_InvalidArgument if pwmChannel does not support capture feature; kStatus_Success otherwise 






void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams)

Sets up the PWM fault channel 0 input filter. 

Parameters:

base – PWM peripheral base address 
faultInputFilterParams – Parameters passed in to set up the fault input filter. 







void PWM_SetupFaultInputFilterExt(PWM_Type *base, pwm_fault_channels_t faultChannel, const pwm_fault_input_filter_param_t *faultInputFilterParams)

Sets up the PWM fault input filter. 

Parameters:

base – PWM peripheral base address 
faultChannel – PWM fault channel to configure. 
faultInputFilterParams – Parameters passed in to set up the fault input filter. 







void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)

Sets up the PWM fault channel 0 protection. 

Parameters:

base – PWM peripheral base address 
faultNum – PWM fault to configure. 
faultParams – Pointer to the PWM fault config structure 







void PWM_SetupFaultsExt(PWM_Type *base, pwm_fault_channels_t faultChannel, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)

Sets up the PWM fault protection. 

Parameters:

base – PWM peripheral base address 
faultChannel – PWM fault channel to configure. 
faultNum – PWM fault to configure. 
faultParams – Pointer to the PWM fault config structure 







void PWM_FaultDefaultConfig(pwm_fault_param_t *config)

Fill in the PWM fault config struct with the default settings. 
The default values are: 
config->faultClearingMode = kPWM_Automatic;
config->faultLevel = false;
config->enableCombinationalPath = true;
config->recoverMode = kPWM_NoRecovery;


 

Parameters:

config – Pointer to user’s PWM fault config structure. 







void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)

Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. 
The user specifies which channel to configure by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – Channel to configure 
mode – Signal to output when a FORCE_OUT is triggered 







static inline void PWM_EnableLocalForce(PWM_Type *base, pwm_submodule_t subModule)

Enables local software force initialization on a PWM submodule. 
This function performs a software-controlled initialization, causes a FORCE_OUT event which latches all double-buffered fields (DTSRCSEL, MCTRL[IPOL], SWCOUT) into their active registers and, if MCTRL[LDOK] is set, also triggers a register reload.
Call this function after updating the desired buffered registers (e.g. after PWM_SetupForceSignal()) to apply the new values synchronously.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to enable local force on 







void PWM_UpdateCurrentPolarity(PWM_Type *base, pwm_submodule_t subModule, pwm_chnl_pair_operation_t polarity)

Updates the current polarity (MCTRL[IPOL]) for a PWM submodule. 
MCTRL[IPOL] is a double-buffered field. This function only writes the shadow register; the value does NOT take effect until a FORCE_OUT event occurs. Call PWM_EnableLocalForce() after this function to apply all pending changes atomically in one FORCE_OUT event.
Only meaningful when the submodule operates in complementary mode (CTRL2[INDEP] = 0).

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
polarity – kPWM_ComplementaryPwmA: PWM23 (VAL2/VAL3) drives the complementary pair kPWM_ComplementaryPwmB: PWM45 (VAL4/VAL5) drives the complementary pair 







static inline void PWM_SetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, uint16_t value)

Set the PWM VALx registers. 
This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is reached.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
valueRegister – VALx register that will be writen new value 
value – Value that will been write into VALx register 







static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister)

Get the PWM VALx registers. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
valueRegister – VALx register that will be read value 


Returns:
The VALx register value 






static inline void PWM_OutputTriggerEnable(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, bool activate)

Enables or disables the PWM output trigger. 
This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated when the counter matches VAL 1, VAL 3, or VAL 5 register.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
valueRegister – Value register that will activate the trigger 
activate – true: Enable the trigger; false: Disable the trigger 







static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)

Enables the PWM output trigger. 
This function allows the user to enable one or more (VAL0-5) PWM trigger.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
valueRegisterMask – Value register mask that will activate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask







static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)

Disables the PWM output trigger. 
This function allows the user to disables one or more (VAL0-5) PWM trigger.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
valueRegisterMask – Value register mask that will Deactivate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask







static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value)

Sets the software control output for a pin to high or low. 
The user specifies which channel to modify by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – Channel to configure 
value – true: Supply a logic 1, false: Supply a logic 0. 







static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value)

Sets or clears the PWM LDOK bit on a single or multiple submodules. 
Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the values are loaded at the next PWM reload point. This function can issue the load command to multiple submodules at the same time.

Parameters:

base – PWM peripheral base address 
subModulesToUpdate – PWM submodules to update with buffered values. This is a logical OR of members of the enumeration pwm_module_control_t
value – true: Set LDOK bit for the submodule list; false: Clear LDOK bit 







static inline void PWM_SetPwmFaultState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_state_t faultState)

Set PWM output fault status. 
These bits determine the fault state for the PWM_A output in fault conditions and STOP mode. It may also define the output state in WAIT and DEBUG modes depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. This function can update PWM output fault status.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – Channel to configure 
faultState – PWM output fault status 







static inline void PWM_SetupFaultDisableMap(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_channels_t pwm_fault_channels, uint16_t value)

Set PWM fault disable mapping. 
Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned off if there is a logic 1 on an FAULTx input and a 1 in the corresponding bit of this field. A reset sets all bits in this field.

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
pwm_fault_channels – PWM fault channel to configure 
value – Fault disable mapping mask value enumeration pwm_fault_disable_t







static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)

Set PWM output enable. 
This feature allows the user to enable the PWM Output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

base – PWM peripheral base address 
pwmChannel – PWM channel to configure 
subModule – PWM submodule to configure 







static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)

Set PWM output disable. 
This feature allows the user to disable the PWM output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

base – PWM peripheral base address 
pwmChannel – PWM channel to configure 
subModule – PWM submodule to configure 







uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel)

Get the dutycycle value. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure


Returns:
Current channel dutycycle value. 






status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus)

Set PWM output in idle status (high or low). 

Note
This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported.


Parameters:

base – PWM peripheral base address 
pwmChannel – PWM channel to configure 
subModule – PWM submodule to configure 
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.


Returns:
kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success 






void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler)

Set the pwm submodule prescaler. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
prescaler – Set prescaler value 







void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero)

This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0. 

Parameters:

base – PWM peripheral base address 
pwmChannel – PWM channel to configure 
subModule – PWM submodule to configure 
forcetozero – True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal function. 







void PWM_SetChannelOutput(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_output_state_t outputstate)

This function set the output state of the PWM pin as requested for the current cycle. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
outputstate – Set pwm output state, see pwm_output_state_t. 







status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles)

This function set the phase delay from the master sync signal of submodule 0. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
delayCycles – Number of cycles delayed from submodule 0.


Returns:
kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; kStatus_Success if set phase delay success 






static inline void PWM_SetFilterSampleCount(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSampleCount)

This function set the number of consecutive samples that must agree prior to the input filter. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
filterSampleCount – Number of consecutive samples. 







static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSamplePeriod)

This function set the sampling period of the fault pin input filter. 

Parameters:

base – PWM peripheral base address 
subModule – PWM submodule to configure 
pwmChannel – PWM channel to configure 
filterSamplePeriod – Sampling period of input filter. 







PWM_SUBMODULE_SWCONTROL_WIDTH

Number of bits per submodule for software output control 




PWM_SUBMODULE_CHANNEL

Submodule channels include PWMA, PWMB, PWMX. 




struct _pwm_signal_param


#include <fsl_pwm.h>
Structure for the user to define the PWM signal characteristics. 

Public Members


pwm_channels_t pwmChannel

PWM channel being configured; PWM A or PWM B 




uint8_t dutyCyclePercent

PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle) 




pwm_level_select_t level

PWM output active level select 




uint16_t deadtimeValue

The deadtime value; only used if channel pair is operating in complementary mode 




pwm_fault_state_t faultState

PWM output fault status 




bool pwmchannelenable

Enable PWM output 







struct _pwm_config


#include <fsl_pwm.h>
PWM config structure. 
This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 

Public Members


bool enableDebugMode

true: PWM continues to run in debug mode; false: PWM is paused in debug mode 




pwm_init_source_t initializationControl

Option to initialize the counter 




pwm_clock_source_t clockSource

Clock source for the counter 




pwm_clock_prescale_t prescale

Pre-scaler to divide down the clock 




pwm_chnl_pair_operation_t pairOperation

Channel pair in indepedent or complementary mode 




pwm_register_reload_t reloadLogic

PWM Reload logic setup 




pwm_reload_source_select_t reloadSelect

Reload source select 




pwm_load_frequency_t reloadFrequency

Specifies when to reload, used when user’s choice is not immediate reload 




pwm_force_output_trigger_t forceTrigger

Specify which signal will trigger a FORCE_OUT 







struct _pwm_fault_input_filter_param


#include <fsl_pwm.h>
Structure for the user to configure the fault input filter. 

Public Members


uint8_t faultFilterCount

Fault filter count 




uint8_t faultFilterPeriod

Fault filter period;value of 0 will bypass the filter 




bool faultGlitchStretch

Fault Glitch Stretch Enable: A logic 1 means that input fault signals will be stretched to at least 2 IPBus clock cycles 







struct _pwm_fault_param


#include <fsl_pwm.h>
Structure is used to hold the parameters to configure a PWM fault. 

Public Members


pwm_fault_clear_t faultClearingMode

Fault clearing mode to use 




bool faultLevel

true: Logic 1 indicates fault; false: Logic 0 indicates fault 




bool enableCombinationalPath

true: Combinational Path from fault input is enabled; false: No combination path is available 




pwm_fault_recovery_mode_t recoverMode

Specify when to re-enable the PWM output 







struct _pwm_input_capture_param


#include <fsl_pwm.h>
Structure is used to hold parameters to configure the capture capability of a signal pin. 

Public Members


bool captureInputSel

true: Use the edge counter signal as source false: Use the raw input signal from the pin as source 




uint8_t edgeCompareValue

Compare value, used only if edge counter is used as source 




pwm_input_capture_edge_t edge0

Specify which edge causes a capture for input circuitry 0 




pwm_input_capture_edge_t edge1

Specify which edge causes a capture for input circuitry 1 




bool enableOneShotCapture

true: Use one-shot capture mode; false: Use free-running capture mode 




uint8_t fifoWatermark

Watermark level for capture FIFO. The capture flags in the status register will set if the word count in the FIFO is greater than this watermark level 







PWR_driver#


typedef struct _pwr_s pwr_s_t





int32_t POWER_SetState(pwr_s_t *pwr_st)





uint32_t POWER_GetState(pwr_s_t *pwr_st)





POWER_NUM_MIX_SLICE





POWER_MIX_SLICE_IDX_ANA





POWER_MIX_SLICE_IDX_AON





POWER_MIX_SLICE_IDX_BBSM





POWER_MIX_SLICE_IDX_M7_1





POWER_MIX_SLICE_IDX_CCMSRCGPC





POWER_MIX_SLICE_IDX_A55C0





POWER_MIX_SLICE_IDX_A55C1





POWER_MIX_SLICE_IDX_A55C2





POWER_MIX_SLICE_IDX_A55C3





POWER_MIX_SLICE_IDX_A55P





POWER_MIX_SLICE_IDX_DDR





POWER_MIX_SLICE_IDX_DISPLAY





POWER_MIX_SLICE_IDX_M7_0





POWER_MIX_SLICE_IDX_HSIO_TOP





POWER_MIX_SLICE_IDX_HSIO_WAON





POWER_MIX_SLICE_IDX_NETC





POWER_MIX_SLICE_IDX_NOC





POWER_MIX_SLICE_IDX_NPU





POWER_MIX_SLICE_IDX_WAKEUP





POWER_MEM_SLICE_IDX_AON





POWER_MEM_SLICE_IDX_M7_1





POWER_MEM_SLICE_IDX_A55C0





POWER_MEM_SLICE_IDX_A55C1





POWER_MEM_SLICE_IDX_A55C2





POWER_MEM_SLICE_IDX_A55C3





POWER_MEM_SLICE_IDX_A55P





POWER_MEM_SLICE_IDX_A55L3





POWER_MEM_SLICE_IDX_DDR





POWER_MEM_SLICE_IDX_DISPLAY





POWER_MEM_SLICE_IDX_M7_0





POWER_MEM_SLICE_IDX_HSIO





POWER_MEM_SLICE_IDX_NETC





POWER_MEM_SLICE_IDX_NOC1





POWER_MEM_SLICE_IDX_NOC2





POWER_MEM_SLICE_IDX_NPU





POWER_MEM_SLICE_IDX_WAKEUP





POWER_MIX_SLICE_IDX_A55C_LAST





struct _pwr_s





PXP: Pixel Pipeline#


void PXP_Init(PXP_Type *base)

Initialize the PXP. 
This function enables the PXP peripheral clock, and resets the PXP registers to default status.

Parameters:

base – PXP peripheral base address. 







void PXP_Deinit(PXP_Type *base)

De-initialize the PXP. 
This function disables the PXP peripheral clock.

Parameters:

base – PXP peripheral base address. 







void PXP_Reset(PXP_Type *base)

Reset the PXP. 
This function resets the PXP peripheral registers to default status.

Parameters:

base – PXP peripheral base address. 







void PXP_ResetControl(PXP_Type *base)

Reset the PXP and the control register to initialized state. 

Parameters:

base – PXP peripheral base address. 







static inline void PXP_Start(PXP_Type *base)

Start process. 
Start PXP process using current configuration.

Parameters:

base – PXP peripheral base address. 







static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)

Enable or disable LCD hand shake. 

Parameters:

base – PXP peripheral base address. 
enable – True to enable, false to disable. 







static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)

Enable or disable continous run. 
If continous run not enabled, PXP_Start starts the PXP process. When completed, PXP enters idle mode and flag kPXP_CompleteFlag asserts.
If continous run enabled, the PXP will repeat based on the current configuration register settings.

Parameters:

base – PXP peripheral base address. 
enable – True to enable, false to disable. 







static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)

Set the PXP processing block size. 
This function chooses the pixel block size that PXP using during process. Larger block size means better performace, but be careful that when PXP is rotating, the output must be divisible by the block size selected.

Parameters:

base – PXP peripheral base address. 
size – The pixel block size. 







static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable)

Enables or disables PXP engines in the process flow. 

Parameters:

base – PXP peripheral base address. 
mask – The engines to enable. Logical OR of pxp_process_engine_name_t. 
enable – true to enable, false to disable. 







static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)

Gets PXP status flags. 
This function gets all PXP status flags. The flags are returned as the logical OR value of the enumerators _pxp_flags. To check a specific status, compare the return value with enumerators in _pxp_flags. For example, to check whether the PXP has completed process, use like this: 
if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP))
{
    ...
}




Parameters:

base – PXP peripheral base address. 


Returns:
PXP status flags which are OR’ed by the enumerators in the _pxp_flags. 






static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)

Clears status flags with the provided mask. 
This function clears PXP status flags with a provided mask.

Parameters:

base – PXP peripheral base address. 
statusMask – The status flags to be cleared; it is logical OR value of _pxp_flags. 







static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)

Gets the AXI ID of the failing bus operation. 

Parameters:

base – PXP peripheral base address. 
axiIndex – Whitch AXI to get

0: AXI0
1: AXI1 




Returns:
The AXI ID of the failing bus operation. 






static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)

Enables PXP interrupts according to the provided mask. 
This function enables the PXP interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _pxp_interrupt_enable. For example, to enable PXP process complete interrupt and command loaded interrupt, do the following. 
PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable);




Parameters:

base – PXP peripheral base address. 
mask – The interrupts to enable. Logical OR of _pxp_interrupt_enable. 







static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)

Disables PXP interrupts according to the provided mask. 
This function disables the PXP interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _pxp_interrupt_enable.

Parameters:

base – PXP peripheral base address. 
mask – The interrupts to disable. Logical OR of _pxp_interrupt_enable. 







void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config)

Set the alpha surface input buffer configuration. 

Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration. 







void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config)

Set the alpha surface blending configuration. 

Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration structure. 







void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config)

Set the alpha surface blending configuration for the secondary engine. 

Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration structure. 







void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)

Set the alpha surface overlay color key. 
If a pixel in the current overlay image with a color that falls in the range from the colorKeyLow to colorKeyHigh range, it will use the process surface pixel value for that location. If no PS image is present or if the PS image also matches its colorkey range, the PS background color is used.

Note
Colorkey operations are higher priority than alpha or ROP operations 


Parameters:

base – PXP peripheral base address. 
num – instance number. 0 for alpha engine A, 1 for alpha engine B. 
colorKeyLow – Color key low range. 
colorKeyHigh – Color key high range.







static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable)

Enable or disable the alpha surface color key. 

Parameters:

base – PXP peripheral base address. 
num – instance number. 0 for alpha engine A, 1 for alpha engine B. 
enable – True to enable, false to disable. 







void PXP_SetAlphaSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)

Set the alpha surface position in output buffer. 

Parameters:

base – PXP peripheral base address. 
upperLeftX – X of the upper left corner. 
upperLeftY – Y of the upper left corner. 
lowerRightX – X of the lower right corner. 
lowerRightY – Y of the lower right corner. 







static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor)

Set the back ground color of PS. 

Parameters:

base – PXP peripheral base address. 
num – instance number. 0 for alpha engine A, 1 for alpha engine B. 
backGroundColor – Pixel value of the background color. 







void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config)

Set the process surface input buffer configuration. 

Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration. 







void PXP_SetProcessSurfaceScaler(PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight)

Set the process surface scaler configuration. 
The valid down scale fact is 1/(2^12) ~ 16.

Parameters:

base – PXP peripheral base address. 
inputWidth – Input image width. 
inputHeight – Input image height. 
outputWidth – Output image width. 
outputHeight – Output image height. 







void PXP_SetProcessSurfacePosition(PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)

Set the process surface position in output buffer. 

Parameters:

base – PXP peripheral base address. 
upperLeftX – X of the upper left corner. 
upperLeftY – Y of the upper left corner. 
lowerRightX – X of the lower right corner. 
lowerRightY – Y of the lower right corner. 







void PXP_SetProcessSurfaceBufferSize(PXP_Type *base, uint16_t lowerRightX, uint16_t lowerRightY)

Set the size of the process surface frame buffer in pixels. 

Parameters:

base – PXP peripheral base address. 
lowerRightX – X of the number of horizontal PIXELS in the processed surface. 
lowerRightY – Y of the number of vertical PIXELS in the processed surface. 







void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)

Set the process surface color key. 
If the PS image matches colorkey range, the PS background color is output. Set colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying.

Parameters:

base – PXP peripheral base address. 
num – instance number. 0 for alpha engine A, 1 for alpha engine B. 
colorKeyLow – Color key low range. 
colorKeyHigh – Color key high range. 







static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)

Set the process surface input pixel format YUV or YCbCr. 
If process surface input pixel format is YUV and CSC1 is not enabled, in other words, the process surface output pixel format is also YUV, then this function should be called to set whether input pixel format is YUV or YCbCr.

Parameters:

base – PXP peripheral base address. 
format – The YUV format. 







void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config)

Set the PXP outpt buffer configuration. 

Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration. 







static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)

Set the global overwritten alpha value. 
If global overwritten alpha is enabled, the alpha component in output buffer pixels will be overwritten, otherwise the computed alpha value is used.

Parameters:

base – PXP peripheral base address. 
alpha – The alpha value. 







static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)

Enable or disable the global overwritten alpha value. 
If global overwritten alpha is enabled, the alpha component in output buffer pixels will be overwritten, otherwise the computed alpha value is used.

Parameters:

base – PXP peripheral base address. 
enable – True to enable, false to disable. 







static inline void PXP_SetRotateConfig(PXP_Type *base, pxp_rotate_position_t position, pxp_rotate_degree_t degree, pxp_flip_mode_t flipMode)

Set the rotation configuration. 
The PXP could rotate the process surface or the output buffer. There are two PXP versions:

Version 1: Only has one rotate sub module, the output buffer and process surface share the same rotate sub module, which means the process surface and output buffer could not be rotate at the same time. When pass in kPXP_RotateOutputBuffer, the process surface could not use the rotate, Also when pass in kPXP_RotateProcessSurface, output buffer could not use the rotate.
Version 2: Has two seperate rotate sub modules, the output buffer and process surface could configure the rotation independently.


Upper layer could use the macro PXP_SHARE_ROTATE to check which version is. PXP_SHARE_ROTATE=1 means version 1.

Note
This function is different depends on the macro PXP_SHARE_ROTATE. 


Parameters:

base – PXP peripheral base address. 
position – Rotate process surface or output buffer. 
degree – Rotate degree. 
flipMode – Flip mode.







void PXP_BuildRect(PXP_Type *base, pxp_output_pixel_format_t outFormat, uint32_t value, uint16_t width, uint16_t height, uint16_t pitch, uint32_t outAddr)

Build a solid rectangle of given pixel value. 

Parameters:

base – PXP peripheral base address. 
outFormat – output pixel format. 
value – The value of the pixel to be filled in the rectangle in ARGB8888 format. 
width – width of the rectangle. 
height – height of the rectangle. 
pitch – output pitch in byte. 
outAddr – address of the memory to store the rectangle. 







void PXP_SetNextCommand(PXP_Type *base, void *commandAddr)

Set the next command. 
The PXP supports a primitive ability to queue up one operation while the current operation is running. Workflow:

Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory in the order they appear in the register map.
Call this function sets the new operation to PXP.
There are two methods to check whether the PXP has loaded the new operation. The first method is using PXP_IsNextCommandPending. If there is new operation not loaded by the PXP, this function returns true. The second method is checking the flag kPXP_CommandLoadFlag, if command loaded, this flag asserts. User could enable interrupt kPXP_CommandLoadInterruptEnable to get the loaded signal in interrupt way.
When command loaded by PXP, a new command could be set using this function.


uint32_t pxp_command1[48];
uint32_t pxp_command2[48];

pxp_command1[0] = ...;
pxp_command1[1] = ...;
...
pxp_command2[0] = ...;
pxp_command2[1] = ...;
...

while (PXP_IsNextCommandPending(PXP))
{
}

PXP_SetNextCommand(PXP, pxp_command1);

while (PXP_IsNextCommandPending(PXP))
{
}

PXP_SetNextCommand(PXP, pxp_command2);



Parameters:

base – PXP peripheral base address. 
commandAddr – Address of the new command. 







static inline bool PXP_IsNextCommandPending(PXP_Type *base)

Check whether the next command is pending. 

Parameters:

base – UART peripheral base address. 


Returns:
True is pending, false is not. 






static inline void PXP_CancelNextCommand(PXP_Type *base)

Cancel command set by PXP_SetNextCommand. 

Parameters:

base – UART peripheral base address. 







void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)

Set the CSC1 mode. 
The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and converts the pixels to the RGB888 color space. It could only be used by process surface.

Parameters:

base – PXP peripheral base address. 
mode – The conversion mode. 







static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)

Enable or disable the CSC1. 

Parameters:

base – PXP peripheral base address. 
enable – True to enable, false to disable. 







void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint16_t bytesNum, uint8_t *data, uint16_t memStartAddr)

Write data to the PXP internal memory. 

Parameters:

base – PXP peripheral base address. 
ram – Which internal memory to write. 
bytesNum – How many bytes to write. 
data – Pointer to the data to write. 
memStartAddr – The start address in the internal memory to write the data. 







void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data)

Set the dither final LUT data. 
The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] of the output pixel and looks up and 8 bit value from the 16 value LUT to generate the final output pixel to the next process module.

Parameters:

base – PXP peripheral base address. 
data – Pointer to the LUT data to set. 







static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)

Set the configuration for the dither block. 
If the pre-dither LUT, post-dither LUT or ordered dither is used, please call PXP_SetInternalRamData to set the LUT data to internal memory.
If the final LUT is used, please call PXP_SetDitherFinalLutData to set the LUT data.

Note
When using ordered dithering, please set the PXP process block size same with the ordered dithering matrix size using function PXP_SetProcessBlockSize. 


Parameters:

base – PXP peripheral base address. 
config – Pointer to the configuration.







void PXP_EnableDither(PXP_Type *base, bool enable)

Enable or disable dither engine in the PXP process path. 
After the initialize function PXP_Init, the dither engine is disabled and not use in the PXP processing path. This function enables the dither engine and routes the dither engine output to the output buffer. When the dither engine is enabled using this function, PXP_SetDitherConfig must be called to configure dither engine correctly, otherwise there is not output to the output buffer.

Parameters:

base – PXP peripheral base address. 
enable – Pass in true to enable, false to disable. 







void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config)

Set the Porter Duff configuration for one of the alpha process engine. 

Parameters:

base – PXP peripheral base address. 
num – instance number. 
config – Pointer to the configuration. 







status_t PXP_GetPorterDuffConfigExt(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config, uint8_t dstGlobalAlphaMode, uint8_t dstAlphaMode, uint8_t dstColorMode, uint8_t srcGlobalAlphaMode, uint8_t srcAlphaMode, uint8_t srcColorMode, uint8_t dstGlobalAlpha, uint8_t srcGlobalAlpha)

Get the Porter Duff configuration. 
The FactorMode are selected based on blend mode, the other values are set based on input parameters. These values could be modified after calling this function. This function is extened PXP_GetPorterDuffConfig.

Parameters:

mode – The blend mode. 
config – Pointer to the configuration. 
dstGlobalAlphaMode – Destination layer (or PS, s0) global alpha mode, see pxp_porter_duff_global_alpha_mode
dstAlphaMode – Destination layer (or PS, s0) alpha mode, see pxp_porter_duff_alpha_mode. 
dstColorMode – Destination layer (or PS, s0) color mode, see pxp_porter_duff_color_mode. 
srcGlobalAlphaMode – Source layer (or AS, s1) global alpha mode, see pxp_porter_duff_global_alpha_mode
srcAlphaMode – Source layer (or AS, s1) alpha mode, see pxp_porter_duff_alpha_mode. 
srcColorMode – Source layer (or AS, s1) color mode, see pxp_porter_duff_color_mode. 
dstGlobalAlpha – Destination layer (or PS, s0) global alpha value, 0~255 
srcGlobalAlpha – Source layer (or AS, s1) global alpha value, 0~255 


Return values:

kStatus_Success – Successfully get the configuratoin. 
kStatus_InvalidArgument – The blend mode not supported. 







static inline status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config)

Get the Porter Duff configuration by blend mode. 
The FactorMode are selected based on blend mode, the AlphaMode are set to kPXP_PorterDuffAlphaStraight, the ColorMode are set to kPXP_PorterDuffColorWithAlpha, the GlobalAlphaMode are set to kPXP_PorterDuffLocalAlpha. These values could be modified after calling this function.

Parameters:

mode – The blend mode. 
config – Pointer to the configuration. 


Return values:

kStatus_Success – Successfully get the configuratoin. 
kStatus_InvalidArgument – The blend mode not supported. 







FSL_PXP_DRIVER_VERSION





enum _pxp_interrupt_enable

PXP interrupts to enable. 
Values:


enumerator kPXP_CompleteInterruptEnable

PXP process completed. bit 1 




enumerator kPXP_CommandLoadInterruptEnable

Interrupt to show that the command set by PXP_SetNextCommand has been loaded. bit 2 




enumerator kPXP_CompressDoneInterruptEnable

Compress done interrupt enable. bit 15 




enumerator kPXP_InputFetchCh0InterruptEnable

Input fetch channel 0 completed. bit 16 




enumerator kPXP_InputFetchCh1InterruptEnable

Input fetch channel 1 completed. bit 17 




enumerator kPXP_InputStoreCh0InterruptEnable

Input store channel 0 completed. bit 18 




enumerator kPXP_InputStoreCh1InterruptEnable

Input store channel 1 completed. bit 19 




enumerator kPXP_DitherFetchCh0InterruptEnable

Dither fetch channel 0 completed. bit 20 




enumerator kPXP_DitherFetchCh1InterruptEnable

Dither fetch channel 1 completed. bit 21 




enumerator kPXP_DitherStoreCh0InterruptEnable

Dither store channle 0 completed. bit 22 




enumerator kPXP_DitherStoreCh1InterruptEnable

Dither store channle 1 completed. bit 23 




enumerator kPXP_WfeaStoreCh0InterruptEnable

WFE-A store channel 0 completed. bit 24 




enumerator kPXP_WfeaStoreCh1InterruptEnable

WFE-A store channel 1 completed. bit 25 




enumerator kPXP_WfebStoreCh0InterruptEnable

WFE-B store channel 0 completed. bit 26 




enumerator kPXP_WfebStoreCh1InterruptEnable

WFE-B store channel 1 completed. bit 27 




enumerator kPXP_InputStoreInterruptEnable

Input store completed. bit 28 




enumerator kPXP_DitherStoreInterruptEnable

Dither store completed. bit 29 




enumerator kPXP_WfeaStoreInterruptEnable

WFE-A store completed. bit 30 




enumerator kPXP_WfebStoreInterruptEnable

WFE-B store completed. bit 31 






enum _pxp_flags

PXP status flags. 

Note
These enumerations are meant to be OR’d together to form a bit mask. 

Values:


enumerator kPXP_CompleteFlag

PXP process completed. bit 0 




enumerator kPXP_Axi0WriteErrorFlag

PXP encountered an AXI write error and processing has been terminated. bit 1 




enumerator kPXP_Axi0ReadErrorFlag

PXP encountered an AXI read error and processing has been terminated. bit 2 




enumerator kPXP_CommandLoadFlag

The command set by PXP_SetNextCommand has been loaded, could set new command. bit 3 




enumerator kPXP_CompressDoneFlag

Compress done. bit 15 




enumerator kPXP_InputFetchCh0CompleteFlag

Input fetch channel 0 completed. bit 16 




enumerator kPXP_InputFetchCh1CompleteFlag

Input fetch channel 1 completed. bit 17 




enumerator kPXP_InputStoreCh0CompleteFlag

Input store channel 0 completed. bit 18 




enumerator kPXP_InputStoreCh1CompleteFlag

Input store channel 1 completed. bit 19 




enumerator kPXP_DitherFetchCh0CompleteFlag

Dither fetch channel 0 completed. bit 20 




enumerator kPXP_DitherFetchCh1CompleteFlag

Dither fetch channel 1 completed. bit 21 




enumerator kPXP_DitherStoreCh0CompleteFlag

Dither store channel 0 completed. bit 22 




enumerator kPXP_DitherStoreCh1CompleteFlag

Dither store channel 1 completed. bit 23 




enumerator kPXP_WfeaStoreCh0CompleteFlag

WFE-A store channel 0 completed. bit 24 




enumerator kPXP_WfeaStoreCh1CompleteFlag

WFE-A store channel 1 completed. bit 25 




enumerator kPXP_WfebStoreCh0CompleteFlag

WFE-B store channel 0 completed. bit 26 




enumerator kPXP_WfebStoreCh1CompleteFlag

WFE-B store channel 1 completed. bit 27 




enumerator kPXP_InputStoreCompleteFlag

Input store completed. bit 28 




enumerator kPXP_DitherStoreCompleteFlag

Dither store completed. bit 29 




enumerator kPXP_WfeaStoreCompleteFlag

WFE-A store completed. bit 30 




enumerator kPXP_WfebStoreCompleteFlag

WFE-B store completed. bit 31 






enum _pxp_flip_mode

PXP output flip mode. 
Values:


enumerator kPXP_FlipDisable

Flip disable. 




enumerator kPXP_FlipHorizontal

Horizontal flip. 




enumerator kPXP_FlipVertical

Vertical flip. 




enumerator kPXP_FlipBoth

Flip both directions. 






enum _pxp_rotate_position

PXP rotate mode. 
Values:


enumerator kPXP_RotateOutputBuffer

Rotate the output buffer. 




enumerator kPXP_RotateProcessSurface

Rotate the process surface. Cannot be used together with flip, scale, or decimation function. 






enum _pxp_rotate_degree

PXP rotate degree. 
Values:


enumerator kPXP_Rotate0

Clock wise rotate 0 deg. 




enumerator kPXP_Rotate90

Clock wise rotate 90 deg. 




enumerator kPXP_Rotate180

Clock wise rotate 180 deg. 




enumerator kPXP_Rotate270

Clock wise rotate 270 deg. 






enum _pxp_interlaced_output_mode

PXP interlaced output mode. 
Values:


enumerator kPXP_OutputProgressive

All data written in progressive format to output buffer 0. 




enumerator kPXP_OutputField0

Only write field 0 data to output buffer 0. 




enumerator kPXP_OutputField1

Only write field 1 data to output buffer 0. 




enumerator kPXP_OutputInterlaced

Field 0 write to buffer 0, field 1 write to buffer 1. 






enum _pxp_output_pixel_format

PXP output buffer format. 
Values:


enumerator kPXP_OutputPixelFormatARGB8888

32-bit pixels with alpha. 




enumerator kPXP_OutputPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format) 




enumerator kPXP_OutputPixelFormatRGB888P

24-bit pixels without alpha (packed 24-bit format) 




enumerator kPXP_OutputPixelFormatARGB1555

16-bit pixels with alpha. 




enumerator kPXP_OutputPixelFormatARGB4444

16-bit pixels with alpha. 




enumerator kPXP_OutputPixelFormatRGB555

16-bit pixels without alpha. 




enumerator kPXP_OutputPixelFormatRGB444

16-bit pixels without alpha. 




enumerator kPXP_OutputPixelFormatRGB565

16-bit pixels without alpha. 




enumerator kPXP_OutputPixelFormatYUV1P444

32-bit pixels (1-plane XYUV unpacked). 




enumerator kPXP_OutputPixelFormatUYVY1P422

16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 




enumerator kPXP_OutputPixelFormatVYUY1P422

16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 




enumerator kPXP_OutputPixelFormatY8

8-bit monochrome pixels (1-plane Y luma output) 




enumerator kPXP_OutputPixelFormatY4

4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 




enumerator kPXP_OutputPixelFormatYUV2P422

16-bit pixels (2-plane UV interleaved bytes) 




enumerator kPXP_OutputPixelFormatYUV2P420

16-bit pixels (2-plane UV) 




enumerator kPXP_OutputPixelFormatYVU2P422

16-bit pixels (2-plane VU interleaved bytes) 




enumerator kPXP_OutputPixelFormatYVU2P420

16-bit pixels (2-plane VU) 






enum _pxp_ps_pixel_format

PXP process surface buffer pixel format. 
Values:


enumerator kPXP_PsPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format) 




enumerator kPXP_PsPixelFormatRGB555

16-bit pixels without alpha. 




enumerator kPXP_PsPixelFormatRGB444

16-bit pixels without alpha. 




enumerator kPXP_PsPixelFormatRGB565

16-bit pixels without alpha. 




enumerator kPXP_PsPixelFormatYUV1P444

32-bit pixels (1-plane XYUV unpacked). 




enumerator kPXP_PsPixelFormatUYVY1P422

16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 




enumerator kPXP_PsPixelFormatVYUY1P422

16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 




enumerator kPXP_PsPixelFormatY8

8-bit monochrome pixels (1-plane Y luma output) 




enumerator kPXP_PsPixelFormatY4

4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 




enumerator kPXP_PsPixelFormatYUV2P422

16-bit pixels (2-plane UV interleaved bytes) 




enumerator kPXP_PsPixelFormatYUV2P420

16-bit pixels (2-plane UV) 




enumerator kPXP_PsPixelFormatYVU2P422

16-bit pixels (2-plane VU interleaved bytes) 




enumerator kPXP_PsPixelFormatYVU2P420

16-bit pixels (2-plane VU) 




enumerator kPXP_PsPixelFormatYVU422

16-bit pixels (3-plane) 




enumerator kPXP_PsPixelFormatYVU420

16-bit pixels (3-plane) 






enum _pxp_ps_yuv_format

PXP process surface buffer YUV format. 
Values:


enumerator kPXP_PsYUVFormatYUV

YUV format. 




enumerator kPXP_PsYUVFormatYCbCr

YCbCr format. 






enum _pxp_as_pixel_format

PXP alpha surface buffer pixel format. 
Values:


enumerator kPXP_AsPixelFormatARGB8888

32-bit pixels with alpha. 




enumerator kPXP_AsPixelFormatRGB888

32-bit pixels without alpha (unpacked 24-bit format) 




enumerator kPXP_AsPixelFormatARGB1555

16-bit pixels with alpha. 




enumerator kPXP_AsPixelFormatARGB4444

16-bit pixels with alpha. 




enumerator kPXP_AsPixelFormatRGB555

16-bit pixels without alpha. 




enumerator kPXP_AsPixelFormatRGB444

16-bit pixels without alpha. 




enumerator kPXP_AsPixelFormatRGB565

16-bit pixels without alpha. 






enum _pxp_alpha_mode

PXP alpha mode during blending. 
Values:


enumerator kPXP_AlphaEmbedded

The alpha surface pixel alpha value will be used for blend. 




enumerator kPXP_AlphaOverride

The user defined alpha value will be used for blend directly. 




enumerator kPXP_AlphaMultiply

The alpha surface pixel alpha value scaled the user defined alpha value will be used for blend, for example, pixel alpha set set to 200, user defined alpha set to 100, then the reault alpha is 200 * 100 / 255. 




enumerator kPXP_AlphaRop

Raster operation. 






enum _pxp_rop_mode

PXP ROP mode during blending. 
Explanation:

AS: Alpha surface
PS: Process surface
nAS: Alpha surface NOT value
nPS: Process surface NOT value 


Values:


enumerator kPXP_RopMaskAs

AS AND PS. 




enumerator kPXP_RopMaskNotAs

nAS AND PS. 




enumerator kPXP_RopMaskAsNot

AS AND nPS. 




enumerator kPXP_RopMergeAs

AS OR PS. 




enumerator kPXP_RopMergeNotAs

nAS OR PS. 




enumerator kPXP_RopMergeAsNot

AS OR nPS. 




enumerator kPXP_RopNotCopyAs

nAS. 




enumerator kPXP_RopNot

nPS. 




enumerator kPXP_RopNotMaskAs

AS NAND PS. 




enumerator kPXP_RopNotMergeAs

AS NOR PS. 




enumerator kPXP_RopXorAs

AS XOR PS. 




enumerator kPXP_RopNotXorAs

AS XNOR PS. 






enum _pxp_block_size

PXP process block size. 
Values:


enumerator kPXP_BlockSize8

Process 8x8 pixel blocks. 




enumerator kPXP_BlockSize16

Process 16x16 pixel blocks. 






enum _pxp_csc1_mode

PXP CSC1 mode. 
Values:


enumerator kPXP_Csc1YUV2RGB

YUV to RGB. 




enumerator kPXP_Csc1YCbCr2RGB

YCbCr to RGB. 






enum _pxp_csc2_mode

PXP CSC2 mode. 
Values:


enumerator kPXP_Csc2YUV2RGB

YUV to RGB. 




enumerator kPXP_Csc2YCbCr2RGB

YCbCr to RGB. 




enumerator kPXP_Csc2RGB2YUV

RGB to YUV. 




enumerator kPXP_Csc2RGB2YCbCr

RGB to YCbCr. 






enum _pxp_ram

PXP internal memory. 
Values:


enumerator kPXP_RamDither0Lut

Dither 0 LUT memory. 




enumerator kPXP_RamDither1Lut

Dither 1 LUT memory. 




enumerator kPXP_RamDither2Lut

Dither 2 LUT memory. 




enumerator kPXP_RamDither0Err0

Dither 0 ERR0 memory. 




enumerator kPXP_RamDither0Err1

Dither 0 ERR1 memory. 




enumerator kPXP_RamAluA

ALU A instr memory. 




enumerator kPXP_RamAluB

ALU B instr memory. 




enumerator kPXP_WfeAFetch

WFE-A fetch memory. 




enumerator kPXP_WfeBFetch

WFE-B fetch memory. 






enum _pxp_dither_mode

PXP dither mode. 
Values:


enumerator kPXP_DitherPassThrough

Pass through, no dither. 




enumerator kPXP_DitherFloydSteinberg

Floyd-Steinberg. For dither engine 0 only. 




enumerator kPXP_DitherAtkinson

Atkinson. For dither engine 0 only. 




enumerator kPXP_DitherOrdered

Ordered dither. 




enumerator kPXP_DitherQuantOnly

No dithering, only quantization. 




enumerator kPXP_DitherSierra

Sierra. For dither engine 0 only. 






enum _pxp_dither_lut_mode

PXP dither LUT mode. 
Values:


enumerator kPXP_DitherLutOff

The LUT memory is not used for LUT, could be used as ordered dither index matrix. 




enumerator kPXP_DitherLutPreDither

Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode or Atkinson mode, which are not supported by current PXP module. 




enumerator kPXP_DitherLutPostDither

Use LUT at the post-dither stage. 






enum _pxp_dither_matrix_size

PXP dither matrix size. 
Values:


enumerator kPXP_DitherMatrix4

The dither index matrix is 4x4. 




enumerator kPXP_DitherMatrix8

The dither index matrix is 8x8. 




enumerator kPXP_DitherMatrix16

The dither index matrix is 16x16. 







Porter Duff factor mode. . 
Values:


enumerator kPXP_PorterDuffFactorOne

Use 1. 




enumerator kPXP_PorterDuffFactorZero

Use 0. 




enumerator kPXP_PorterDuffFactorStraight

Use straight alpha. 




enumerator kPXP_PorterDuffFactorInversed

Use inversed alpha. 







Porter Duff global alpha mode. . 
Values:


enumerator kPXP_PorterDuffGlobalAlpha

Use global alpha. 




enumerator kPXP_PorterDuffLocalAlpha

Use local alpha in each pixel. 




enumerator kPXP_PorterDuffScaledAlpha

Use global alpha * local alpha. 







Porter Duff alpha mode. . 
Values:


enumerator kPXP_PorterDuffAlphaStraight

Use straight alpha, s0_alpha’ = s0_alpha. 




enumerator kPXP_PorterDuffAlphaInversed

Use inversed alpha, s0_alpha’ = 0xFF - s0_alpha. 







Porter Duff color mode. . 
Values:


enumerator kPXP_PorterDuffColorStraight



Deprecated:
Use kPXP_PorterDuffColorNoAlpha. 







enumerator kPXP_PorterDuffColorInversed



Deprecated:
Use kPXP_PorterDuffColorWithAlpha. 







enumerator kPXP_PorterDuffColorNoAlpha

s0_pixel’ = s0_pixel. 




enumerator kPXP_PorterDuffColorWithAlpha

s0_pixel’ = s0_pixel * s0_alpha”. 






enum _pxp_porter_duff_blend_mode

PXP Porter Duff blend mode. Note: don’t change the enum item value. 
Values:


enumerator kPXP_PorterDuffSrc

Source Only 




enumerator kPXP_PorterDuffAtop

Source Atop 




enumerator kPXP_PorterDuffOver

Source Over 




enumerator kPXP_PorterDuffIn

Source In. 




enumerator kPXP_PorterDuffOut

Source Out. 




enumerator kPXP_PorterDuffDst

Destination Only. 




enumerator kPXP_PorterDuffDstAtop

Destination Atop. 




enumerator kPXP_PorterDuffDstOver

Destination Over. 




enumerator kPXP_PorterDuffDstIn

Destination In. 




enumerator kPXP_PorterDuffDstOut

Destination Out. 




enumerator kPXP_PorterDuffXor

XOR. 




enumerator kPXP_PorterDuffClear

Clear. 




enumerator kPXP_PorterDuffMax







enum _pxp_process_engine_name

PXP process engine enumeration. 
Values:


enumerator kPXP_PsAsOutEngine





enumerator kPXP_DitherEngine





enumerator kPXP_WfeaEngine





enumerator kPXP_WfebEngine





enumerator kPXP_InputFetchStoreEngine





enumerator kPXP_Alpha1Engine





enumerator kPXP_Csc2Engine





enumerator kPXP_LutEngine





enumerator kPXP_Rotate0Engine





enumerator kPXP_Rotate1Engine







enum _pxp_fetch_engine_name

PXP fetch engine enumeration. 
There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, whose registers are reserved from developer. 
Values:


enumerator kPXP_FetchInput





enumerator kPXP_FetchDither







enum _pxp_fetch_interface_mode

PXP fetch engine interface mode with the upstream store engine. 
Values:


enumerator kPXP_FetchModeNormal





enumerator kPXP_FetchModeHandshake





enumerator kPXP_FetchModeBypass







enum _pxp_scanline_burst

PXP fetch/store engine burst length for scanline mode. 
Values:


enumerator kPXP_Scanline8bytes





enumerator kPXP_Scanline16bytes





enumerator kPXP_Scanline32bytes





enumerator kPXP_Scanline64bytes







enum _pxp_activeBits

PXP fetch/store engine input/output active bits configuration. 
Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input mode. And expand configuration will have no effect. 
Values:


enumerator kPXP_Active8Bits





enumerator kPXP_Active16Bits





enumerator kPXP_Active32Bits





enumerator kPXP_Active64Bits







enum _pxp_fetch_output_word_order

PXP fetch engine output word order when using 2 channels for 64-bit mode. 
Values:


enumerator kPXP_FetchOutputChannel1channel0

In 64bit mode, channel 1 output high byte. 




enumerator kPXP_FetchOutputChannel0channel1

In 64bit mode, channel 0 output high byte. 






enum _pxp_fetch_pixel_format

PXP fetch engine input pixel format. 
Values:


enumerator kPXP_FetchFormatRGB565





enumerator kPXP_FetchFormatRGB555





enumerator kPXP_FetchFormatARGB1555





enumerator kPXP_FetchFormatRGB444





enumerator kPXP_FetchFormatARGB4444





enumerator kPXP_FetchFormatYUYVorYVYU





enumerator kPXP_FetchFormatUYVYorVYUY





enumerator kPXP_FetchFormatYUV422_2P







enum _pxp_store_engine_name

PXP store engine enumeration. 
There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, whose registers are reserved from developer. 
Values:


enumerator kPXP_StoreInput





enumerator kPXP_StoreDither







enum _pxp_store_interface_mode

PXP store engine interface mode with the downstream fetch engine. 
Values:


enumerator kPXP_StoreModeBypass

Store engine output the input data, after the shift function directly to the downstream Fetch Engine. 




enumerator kPXP_StoreModeNormal

Store engine stores the input data to memory. 




enumerator kPXP_StoreModeHandshake

Downstream fetch engine fetch data per scanline from memory using buffer sharing with store engine. 




enumerator kPXP_StoreModeDual

Store engine outputs data directly to downstream fetch engine(Bypass) but also storing it to memory at the same time. 






enum _pxp_store_yuv_mode

PXP store engine YUV output mode. 
Values:


enumerator kPXP_StoreYUVDisable

Do not output YUV pixel format. 




enumerator kPXP_StoreYUVPlane1

Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}. 




enumerator kPXP_StoreYUVPlane2

Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}. 






enum _pxp_cfa_input_format

PXP pre-dither CFA engine input pixel format. 
Values:


enumerator kPXP_CfaRGB888





enumerator kPXP_CfaRGB444







enum _pxp_histogram_mask_condition

PXP histogram mask condition. 
Values:


enumerator kPXP_HistogramMaskEqual

Value that equal to value0 will pass the mask operation. 




enumerator kPXP_HistogramMaskNotequal

Value that not equal to value0 will pass the mask operation. 




enumerator kPXP_HistogramMaskIn

Value that within the range of value0-value1 will pass the mask operation. 




enumerator kPXP_HistogramMaskOut

Value that without the range of value0-value1 will pass the mask operation. 






enum _pxp_histgram_flags

PXP Histogram operation result flags. 
Values:


enumerator kPXP_Histogram2levelMatch





enumerator kPXP_Histogram4levelMatch





enumerator kPXP_Histogram8levelMatch





enumerator kPXP_Histogram16levelMatch





enumerator kPXP_Histogram32levelMatch







typedef enum _pxp_flip_mode pxp_flip_mode_t

PXP output flip mode. 




typedef enum _pxp_rotate_position pxp_rotate_position_t

PXP rotate mode. 




typedef enum _pxp_rotate_degree pxp_rotate_degree_t

PXP rotate degree. 




typedef enum _pxp_interlaced_output_mode pxp_interlaced_output_mode_t

PXP interlaced output mode. 




typedef enum _pxp_output_pixel_format pxp_output_pixel_format_t

PXP output buffer format. 




typedef struct _pxp_output_buffer_config pxp_output_buffer_config_t

PXP output buffer configuration. 




typedef enum _pxp_ps_pixel_format pxp_ps_pixel_format_t

PXP process surface buffer pixel format. 




typedef enum _pxp_ps_yuv_format pxp_ps_yuv_format_t

PXP process surface buffer YUV format. 




typedef struct _pxp_ps_buffer_config pxp_ps_buffer_config_t

PXP process surface buffer configuration. 




typedef enum _pxp_as_pixel_format pxp_as_pixel_format_t

PXP alpha surface buffer pixel format. 




typedef struct _pxp_as_buffer_config pxp_as_buffer_config_t

PXP alphs surface buffer configuration. 




typedef enum _pxp_alpha_mode pxp_alpha_mode_t

PXP alpha mode during blending. 




typedef enum _pxp_rop_mode pxp_rop_mode_t

PXP ROP mode during blending. 
Explanation:

AS: Alpha surface
PS: Process surface
nAS: Alpha surface NOT value
nPS: Process surface NOT value 






typedef struct _pxp_as_blend_config pxp_as_blend_config_t

PXP alpha surface blending configuration. 




typedef struct _pxp_as_blend_secondary_config pxp_as_blend_secondary_config_t

PXP secondary alpha surface blending engine configuration. 




typedef enum _pxp_block_size pxp_block_size_t

PXP process block size. 




typedef enum _pxp_csc1_mode pxp_csc1_mode_t

PXP CSC1 mode. 




typedef enum _pxp_csc2_mode pxp_csc2_mode_t

PXP CSC2 mode. 




typedef struct _pxp_csc2_config pxp_csc2_config_t

PXP CSC2 configuration. 
Converting from YUV/YCbCr color spaces to the RGB color space uses the following equation structure:
R = A1(Y+D1) + A2(U+D2) + A3(V+D3) G = B1(Y+D1) + B2(U+D2) + B3(V+D3) B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
Converting from the RGB color space to YUV/YCbCr color spaces uses the following equation structure:
Y = A1*R + A2*G + A3*B + D1 U = B1*R + B2*G + B3*B + D2 V = C1*R + C2*G + C3*B + D3 




typedef enum _pxp_ram pxp_ram_t

PXP internal memory. 




typedef struct _pxp_dither_final_lut_data pxp_dither_final_lut_data_t

PXP dither final LUT data. 




typedef struct _pxp_dither_config pxp_dither_config_t

PXP dither configuration. 




typedef enum _pxp_porter_duff_blend_mode pxp_porter_duff_blend_mode_t

PXP Porter Duff blend mode. Note: don’t change the enum item value. 




typedef struct _pxp_pic_copy_config pxp_pic_copy_config_t

PXP Porter Duff blend mode. Note: don’t change the enum item value. 




typedef enum _pxp_process_engine_name pxp_process_engine_name_t

PXP process engine enumeration. 




typedef enum _pxp_fetch_engine_name pxp_fetch_engine_name_t

PXP fetch engine enumeration. 
There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, whose registers are reserved from developer. 




typedef enum _pxp_fetch_interface_mode pxp_fetch_interface_mode_t

PXP fetch engine interface mode with the upstream store engine. 




typedef enum _pxp_scanline_burst pxp_scanline_burst_t

PXP fetch/store engine burst length for scanline mode. 




typedef struct _pxp_block_format_config pxp_block_config_t

PXP fetch engine block configuration. 




typedef enum _pxp_activeBits pxp_active_bits_t

PXP fetch/store engine input/output active bits configuration. 
Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input mode. And expand configuration will have no effect. 




typedef enum _pxp_fetch_output_word_order pxp_fetch_output_word_order_t

PXP fetch engine output word order when using 2 channels for 64-bit mode. 




typedef struct _pxp_fetch_shift_component pxp_fetch_shift_component_t

PXP fetch engine shift component configuration. 
Fetch engine can divded each word into 4 components and shift them. 




typedef struct _pxp_fetch_shift_config pxp_fetch_shift_config_t

PXP fetch engine shift configuration. 
Fetch engine can divded each word into 4 components and shift them. For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, OFFSET3=24, WIDTH0/1/2/3=8 




typedef enum _pxp_fetch_pixel_format pxp_fetch_pixel_format_t

PXP fetch engine input pixel format. 




typedef struct _pxp_fetch_engine_config pxp_fetch_engine_config_t

PXP fetch engine configuration for one of the channel. 




typedef enum _pxp_store_engine_name pxp_store_engine_name_t

PXP store engine enumeration. 
There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, whose registers are reserved from developer. 




typedef enum _pxp_store_interface_mode pxp_store_interface_mode_t

PXP store engine interface mode with the downstream fetch engine. 




typedef enum _pxp_store_yuv_mode pxp_store_yuv_mode_t

PXP store engine YUV output mode. 




typedef struct _pxp_store_shift_config pxp_store_shift_config_t

Shift configuration for PXP store engine. 




typedef struct _pxp_store_engine_config pxp_store_engine_config_t

PXP store engine configuration for one of the channel. 




typedef enum _pxp_cfa_input_format pxp_cfa_input_format_t

PXP pre-dither CFA engine input pixel format. 




typedef struct _pxp_cfa_config pxp_cfa_config_t

PXP pre-dither CFA engine configuration. 




typedef enum _pxp_histogram_mask_condition pxp_histogram_mask_condition_t

PXP histogram mask condition. 




typedef struct _pxp_histogram_config pxp_histogram_config_t

PXP Histogram configuration. 




typedef struct _pxp_histogram_mask_result pxp_histogram_mask_result_t

PXP Histogram mask result. 




typedef struct _pxp_wfea_engine_config pxp_wfea_engine_config_t

PXP WFE-A engine configuration. 




PXP_LUT_TABLE_BYTE





PXP_INTERNAL_RAM_LUT_BYTE





PXP_SHARE_ROTATE





PXP_USE_PATH





PXP_COMBINE_BYTE_TO_WORD(dataAddr)





struct _pxp_output_buffer_config


#include <fsl_pxp.h>
PXP output buffer configuration. 

Public Members


pxp_output_pixel_format_t pixelFormat

Output buffer pixel format. 




pxp_interlaced_output_mode_t interlacedMode

Interlaced output mode. 




uint32_t buffer0Addr

Output buffer 0 address. 




uint32_t buffer1Addr

Output buffer 1 address, used for UV data in YUV 2-plane mode, or field 1 in output interlaced mode. 




uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels. 




uint16_t width

Pixels per line. 




uint16_t height

How many lines in output buffer. 







struct _pxp_ps_buffer_config


#include <fsl_pxp.h>
PXP process surface buffer configuration. 

Public Members


pxp_ps_pixel_format_t pixelFormat

PS buffer pixel format. 




bool swapByte

For each 16 bit word, set true to swap the two bytes. 




uint32_t bufferAddr

Input buffer address for the first panel. 




uint32_t bufferAddrU

Input buffer address for the second panel. 




uint32_t bufferAddrV

Input buffer address for the third panel. 




uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels. 







struct _pxp_as_buffer_config


#include <fsl_pxp.h>
PXP alphs surface buffer configuration. 

Public Members


pxp_as_pixel_format_t pixelFormat

AS buffer pixel format. 




uint32_t bufferAddr

Input buffer address. 




uint16_t pitchBytes

Number of bytes between two vertically adjacent pixels. 







struct _pxp_as_blend_config


#include <fsl_pxp.h>
PXP alpha surface blending configuration. 

Public Members


uint8_t alpha

User defined alpha value, only used when alphaMode is kPXP_AlphaOverride or kPXP_AlphaRop. 




bool invertAlpha

Set true to invert the alpha. 




pxp_alpha_mode_t alphaMode

Alpha mode. 




pxp_rop_mode_t ropMode

ROP mode, only valid when alphaMode is kPXP_AlphaRop. 







struct _pxp_as_blend_secondary_config


#include <fsl_pxp.h>
PXP secondary alpha surface blending engine configuration. 

Public Members


bool invertAlpha

Set true to invert the alpha. 




bool ropEnable

Enable rop mode. 




pxp_rop_mode_t ropMode

ROP mode, only valid when ropEnable is true. 







struct _pxp_csc2_config


#include <fsl_pxp.h>
PXP CSC2 configuration. 
Converting from YUV/YCbCr color spaces to the RGB color space uses the following equation structure:
R = A1(Y+D1) + A2(U+D2) + A3(V+D3) G = B1(Y+D1) + B2(U+D2) + B3(V+D3) B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
Converting from the RGB color space to YUV/YCbCr color spaces uses the following equation structure:
Y = A1*R + A2*G + A3*B + D1 U = B1*R + B2*G + B3*B + D2 V = C1*R + C2*G + C3*B + D3 

Public Members


pxp_csc2_mode_t mode

Convertion mode. 




float A1

A1. 




float A2

A2. 




float A3

A3. 




float B1

B1. 




float B2

B2. 




float B3

B3. 




float C1

C1. 




float C2

C2. 




float C3

C3. 




int16_t D1

D1. 




int16_t D2

D2. 




int16_t D3

D3. 







struct _pxp_dither_final_lut_data


#include <fsl_pxp.h>
PXP dither final LUT data. 

Public Members


uint32_t data_3_0

Data 3 to data 0. Data 0 is the least significant byte. 




uint32_t data_7_4

Data 7 to data 4. Data 4 is the least significant byte. 




uint32_t data_11_8

Data 11 to data 8. Data 8 is the least significant byte. 




uint32_t data_15_12

Data 15 to data 12. Data 12 is the least significant byte. 







struct _pxp_dither_config


#include <fsl_pxp.h>
PXP dither configuration. 

Public Members


uint32_t enableDither0

Enable dither engine 0 or not, set 1 to enable, 0 to disable. 




uint32_t enableDither1

Enable dither engine 1 or not, set 1 to enable, 0 to disable. 




uint32_t enableDither2

Enable dither engine 2 or not, set 1 to enable, 0 to disable. 




uint32_t ditherMode0

Dither mode for dither engine 0. See _pxp_dither_mode. 




uint32_t ditherMode1

Dither mode for dither engine 1. See _pxp_dither_mode. 




uint32_t ditherMode2

Dither mode for dither engine 2. See _pxp_dither_mode. 




uint32_t quantBitNum

Number of bits quantize down to, the valid value is 1~7. 




uint32_t lutMode

How to use the memory LUT, see _pxp_dither_lut_mode. This must be set to kPXP_DitherLutOff if any dither engine uses kPXP_DitherOrdered mode. 




uint32_t idxMatrixSize0

Size of index matrix used for dither for dither engine 0, see _pxp_dither_matrix_size. 




uint32_t idxMatrixSize1

Size of index matrix used for dither for dither engine 1, see _pxp_dither_matrix_size. 




uint32_t idxMatrixSize2

Size of index matrix used for dither for dither engine 2, see _pxp_dither_matrix_size. 




uint32_t enableFinalLut

Enable the final LUT, set 1 to enable, 0 to disable. 







struct pxp_porter_duff_config_t


#include <fsl_pxp.h>
PXP Porter Duff configuration. 

Public Members


uint32_t enable

Enable or disable Porter Duff. 




uint32_t srcFactorMode

Source layer (or AS, s1) factor mode, see pxp_porter_duff_factor_mode. 




uint32_t dstGlobalAlphaMode

Destination layer (or PS, s0) global alpha mode, see pxp_porter_duff_global_alpha_mode. 




uint32_t dstAlphaMode

Destination layer (or PS, s0) alpha mode, see pxp_porter_duff_alpha_mode. 




uint32_t dstColorMode

Destination layer (or PS, s0) color mode, see pxp_porter_duff_color_mode. 




uint32_t dstFactorMode

Destination layer (or PS, s0) factor mode, see pxp_porter_duff_factor_mode. 




uint32_t srcGlobalAlphaMode

Source layer (or AS, s1) global alpha mode, see pxp_porter_duff_global_alpha_mode. 




uint32_t srcAlphaMode

Source layer (or AS, s1) alpha mode, see pxp_porter_duff_alpha_mode. 




uint32_t srcColorMode

Source layer (or AS, s1) color mode, see pxp_porter_duff_color_mode. 




uint32_t dstGlobalAlpha

Destination layer (or PS, s0) global alpha value, 0~255. 




uint32_t srcGlobalAlpha

Source layer (or AS, s1) global alpha value, 0~255. 







struct _pxp_pic_copy_config


#include <fsl_pxp.h>
PXP Porter Duff blend mode. Note: don’t change the enum item value. 

Public Members


uint32_t srcPicBaseAddr

Source picture base address. 




uint16_t srcPitchBytes

Pitch of the source buffer. 




uint16_t srcOffsetX

Copy position in source picture. 




uint16_t srcOffsetY

Copy position in source picture. 




uint32_t destPicBaseAddr

Destination picture base address. 




uint16_t destPitchBytes

Pitch of the destination buffer. 




uint16_t destOffsetX

Copy position in destination picture. 




uint16_t destOffsetY

Copy position in destination picture. 




uint16_t width

Pixel number each line to copy. 




uint16_t height

Lines to copy. 




pxp_as_pixel_format_t pixelFormat

Buffer pixel format. 







struct _pxp_block_format_config


#include <fsl_pxp.h>
PXP fetch engine block configuration. 

Public Members


bool enableblock

Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If LUT processing is in the path between the fetch and store engind, block mode must be enabled. 




bool blockSize16

Enable to use 16*16 block, otherwise it will be 8*8 block. 




pxp_scanline_burst_t burstLength

When using scanline mode, configure this for burst length. 







struct _pxp_fetch_shift_component


#include <fsl_pxp.h>
PXP fetch engine shift component configuration. 
Fetch engine can divded each word into 4 components and shift them. 




struct _pxp_fetch_shift_config


#include <fsl_pxp.h>
PXP fetch engine shift configuration. 
Fetch engine can divded each word into 4 components and shift them. For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, OFFSET3=24, WIDTH0/1/2/3=8 




struct _pxp_fetch_engine_config


#include <fsl_pxp.h>
PXP fetch engine configuration for one of the channel. 

Public Members


bool channelEnable

Enable channel. 




uint32_t inputBaseAddr0

The input base address. Used for Y plane input when pixel format is YUV422_2p. 




uint32_t inputBaseAddr1

Must configure this for UV plane when input pixel format is YUV422_2p. 




uint16_t totalHeight

Total height for the actual fetch size. 




uint16_t totalWidth

Total width for the actual fetch size. 




uint16_t pitchBytes

Channel input pitch 




uint16_t ulcX

X coordinate of upper left coordinate in pixels of the active area of the total input memory 




uint16_t ulcY

Y coordinate of upper left coordinate in pixels of the active area of the total input memory 




uint16_t lrcX

X coordinate of Lower right coordinate in pixels of the active area of the total input memory 




uint16_t lrcY

Y coordinate of Lower right coordinate in pixels of the active area of the total input memory 




uint32_t backGroundColor

Pixel value of the background color for the space outside the active area. 




pxp_fetch_interface_mode_t interface

Interface mode, normal/bypass/handshake 




pxp_active_bits_t activeBits

Input active bits. 




pxp_fetch_pixel_format_t pixelFormat

Input pixel fetch format 




bool expandEnable

If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at the output. 




pxp_flip_mode_t flipMode

Flip the fetched input. 




pxp_rotate_degree_t rotateDegree

Rotate the fetched input. 




pxp_block_config_t fetchFormat

Block mode configuration. Make sure to enable block if rotate or flip mode is enabled. 




pxp_fetch_shift_config_t shiftConfig

Shift operation configuration. 




pxp_fetch_output_word_order_t wordOrder

Output word order when using 2 channels for 64-bit mode. 







struct _pxp_store_shift_config


#include <fsl_pxp.h>
Shift configuration for PXP store engine. 

Public Members


bool shiftBypass

Bypass the data shift 




uint64_t *pDataShiftMask

Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then shifted according to width. 




uint8_t *pDataShiftWidth

Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for shift width. 




uint8_t *pFlagShiftMask

Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then shifted according to width. 




uint8_t *pFlagShiftWidth

Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for shift width. 







struct _pxp_store_engine_config


#include <fsl_pxp.h>
PXP store engine configuration for one of the channel. 

Public Members


bool channelEnable

Enable channel. 




uint32_t outputBaseAddr0

The channel 0 output address if using 2 channels. If using 1 channel(must be channel
0) and YUV422_2p output format, is for Y plane address.





uint32_t outputBaseAddr1

The channel 1 output address if using 2 channels. If using 1 channel(must be channel
0) and YUV422_2p output format, is for UV plane address.





uint16_t totalHeight

Total height for the actual store size. 




uint16_t totalWidth

Total width for the actual store size. 




uint16_t pitchBytes

Channel input pitch 




pxp_store_interface_mode_t interface

Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use the same mode if both enabled. 




pxp_active_bits_t activeBits

Output active bits. 




pxp_store_yuv_mode_t yuvMode

Whether to output YUV pixel format. 




bool useFixedData

Whether to use fixed value for the output data. Can be used to write fixed value to specific memory location for memory initialization. 




uint32_t fixedData

The value of the fixed data. 




bool packInSelect

When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select high 32 bit, otherwise all 64-bit of data will be selected. 




pxp_block_config_t storeFormat

The format to store data, block or otherwise. 




pxp_store_shift_config_t shiftConfig

Shift operation configuration. 







struct _pxp_cfa_config


#include <fsl_pxp.h>
PXP pre-dither CFA engine configuration. 

Public Members


bool bypass

Bypass the CFA process 




pxp_cfa_input_format_t pixelInFormat

The pixel input format for CFA. 




uint8_t arrayWidth

CFA array vertical size in pixels, min 3 max 15. 




uint8_t arrayHeight

CFA array horizontal size in pixels, min 3 max 15. 




uint16_t totalHeight

Total height for the buffer size, make sure it is aligned with the dither fetch engine and dither engine. 




uint16_t totalWidth

Total width for the buffer size, make sure it is aligned with the dither fetch engine and dither engine. 




uint32_t *cfaValue

Pointer to the value for the CFA array. 2-bit per component: 00-R,01-G,10-B,11-W. For a 4x4 array, 32 bits are need. 







struct _pxp_histogram_config


#include <fsl_pxp.h>
PXP Histogram configuration. 

Public Members


bool enable

Enable histogram process. 




uint8_t *pParamValue

Pointer to the 62(2+4+8+16+32) byte of param value for 2-level, 4-level…..32-level parameters. Only low 5-bit of each byte is valid. 




uint8_t lutValueOffset

The starting bit position of the LUT value. 




uint8_t lutValueWidth

The bit width of the LUT value, should be no more than 6 bits since only 63 LUTs are supported. 




bool enableMask

Enable mask operation. 




uint8_t maskValue0

Value 0 for the condition judgement. 




uint8_t maskValue1

Value 1 for the condition judgement. 




uint8_t maskOffset

The starting bit position of the field to be checked against mask condition. 




uint8_t maskWidth

The width of the field to be checked against mask condition. 




pxp_histogram_mask_condition_t condition

The mask condition. 




uint16_t totalHeight

Total height for the buffer size, make sure it is aligned with the output of legacy flow or the WFE-A/B engine. 




uint16_t totalWidth

Total width for the buffer size, make sure it is aligned with the output of legacy flow or the WFE-A/B engine. 







struct _pxp_histogram_mask_result


#include <fsl_pxp.h>
PXP Histogram mask result. 

Public Members


uint32_t pixelCount

The total count of the pixels that pass the mask(collided pixels). 




uint32_t minX

The x offset of the ULC of the minimal histogram that covers all passed pixels. 




uint32_t minY

The y offset of the ULC of the minimal histogram that covers all passed pixels. 




uint32_t maxX

The x offset of the LRC of the minimal histogram that covers all passed pixels. 




uint32_t maxY

The y offset of the LRC of the minimal histogram that covers all passed pixels. 




uint64_t lutlist

The 64-bit LUT list of collided pixels, if pixel of LUT17 is collided, bit17 in the list is set. 







struct _pxp_wfea_engine_config


#include <fsl_pxp.h>
PXP WFE-A engine configuration. 

Public Members


uint32_t y4Addr

Address for Y4 buffer. 




uint32_t y4cAddr

Address for Y4C buffer, {Y4[3:0],3’b000,collision}, 8bpp. 




uint32_t wbAddr

Address for EPDC working buffer. 




uint16_t updateWidth

Width of the update area. 




uint16_t updateHeight

Height of the update area. 




uint16_t updatePitch

Pitch of the update area. 




uint16_t ulcX

X coordinate of upper left coordinate of the total input memory 




uint16_t ulcY

Y coordinate of upper left coordinate of the total input memory 




uint16_t resX

Horizontal resolution in pixels. 




uint8_t lutNum

The EPDC LUT number for the update. 




bool fullUpdateEnable

Enable full update. 




bool alphaEnable

Enable alpha field, upd is {Y4[3:0],3’b000,alpha} format, otherwise its {Y4[3:0],4’b0000}. 




bool detectionOnly

Detection only, do not write working buffer. 







QTMR: Quad Timer Driver#


void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)

Ungates the Quad Timer clock and configures the peripheral for basic operation. 

Note
This API should be called at the beginning of the application using the Quad Timer driver.


Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
config – Pointer to user’s Quad Timer config structure 







void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the counter and gates the Quad Timer clock. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 







void QTMR_GetDefaultConfig(qtmr_config_t *config)

Fill in the Quad Timer config struct with the default settings. 
The default values are: 
config->debugMode = kQTMR_RunNormalInDebug;
config->enableExternalForce = false;
config->enableMasterMode = false;
config->faultFilterCount = 0;
config->faultFilterPeriod = 0;
config->primarySource = kQTMR_ClockDivide_2;
config->secondarySource = kQTMR_Counter0InputPin;


 

Parameters:

config – Pointer to user’s Quad Timer config structure. 







void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Enables the selected Quad Timer interrupts. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t







void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Disables the selected Quad Timer interrupts. 

Parameters:

base – Quad Timer peripheral base addres 
channel – Quad Timer channel number 
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t







uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the enabled Quad Timer interrupts. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration qtmr_interrupt_enable_t






uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the Quad Timer status flags. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number


Returns:
The status flags. This is the logical OR of members of the enumeration qtmr_status_flags_t






void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Clears the Quad Timer status flags. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
mask – The status flags to clear. This is a logical OR of members of the enumeration qtmr_status_flags_t







void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)

Sets the timer period in ticks. 
Timers counts from initial value till it equals the count value set here. The counter will then reinitialize to the value specified in the Load register.

Note

This function will write the time period in ticks to COMP1 or COMP2 register depending on the count direction
User can call the utility macros provided in fsl_common.h to convert to ticks
This function supports cases, providing only primary source clock without secondary source clock.




Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
ticks – Timer period in units of ticks 







void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)

Set compare value. 
This function sets the value used for comparison with the counter value.

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
ticks – Timer period in units of ticks. 







static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t value)

Set load value. 
This function sets the value used to initialize the counter after a counter comparison.

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
value – Load register initialization value. 







static inline uint32_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)

Reads the current timer counting value. 
This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note
User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec


Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number


Returns:
Current counter value in ticks 






static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)

Starts the Quad Timer counter. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
clockSource – Quad Timer clock source 







static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the Quad Timer counter. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 







void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Enable the Quad Timer DMA. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t







void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Disable the Quad Timer DMA. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t







FSL_QTMR_DRIVER_VERSION

Version 




enum _qtmr_primary_count_source

Quad Timer primary clock source selection. 
Values:


enumerator kQTMR_ClockCounter0InputPin

Use counter 0 input pin 




enumerator kQTMR_ClockCounter1InputPin

Use counter 1 input pin 




enumerator kQTMR_ClockCounter2InputPin

Use counter 2 input pin 




enumerator kQTMR_ClockCounter3InputPin

Use counter 3 input pin 




enumerator kQTMR_ClockCounter0Output

Use counter 0 output 




enumerator kQTMR_ClockCounter1Output

Use counter 1 output 




enumerator kQTMR_ClockCounter2Output

Use counter 2 output 




enumerator kQTMR_ClockCounter3Output

Use counter 3 output 




enumerator kQTMR_ClockDivide_1

IP bus clock divide by 1 prescaler 




enumerator kQTMR_ClockDivide_2

IP bus clock divide by 2 prescaler 




enumerator kQTMR_ClockDivide_4

IP bus clock divide by 4 prescaler 




enumerator kQTMR_ClockDivide_8

IP bus clock divide by 8 prescaler 




enumerator kQTMR_ClockDivide_16

IP bus clock divide by 16 prescaler 




enumerator kQTMR_ClockDivide_32

IP bus clock divide by 32 prescaler 




enumerator kQTMR_ClockDivide_64

IP bus clock divide by 64 prescaler 




enumerator kQTMR_ClockDivide_128

IP bus clock divide by 128 prescaler 






enum _qtmr_input_source

Quad Timer input sources selection. 
Values:


enumerator kQTMR_Counter0InputPin

Use counter 0 input pin 




enumerator kQTMR_Counter1InputPin

Use counter 1 input pin 




enumerator kQTMR_Counter2InputPin

Use counter 2 input pin 




enumerator kQTMR_Counter3InputPin

Use counter 3 input pin 






enum _qtmr_counting_mode

Quad Timer counting mode selection. 
Values:


enumerator kQTMR_NoOperation

No operation 




enumerator kQTMR_PriSrcRiseEdge

Count rising edges of primary source 




enumerator kQTMR_PriSrcRiseAndFallEdge

Count rising and falling edges of primary source 




enumerator kQTMR_PriSrcRiseEdgeSecInpHigh

Count rise edges of pri SRC while sec inp high active 




enumerator kQTMR_QuadCountMode

Quadrature count mode, uses pri and sec sources 




enumerator kQTMR_PriSrcRiseEdgeSecDir

Count rising edges of pri SRC; sec SRC specifies dir 




enumerator kQTMR_SecSrcTrigPriCnt

Edge of sec SRC trigger primary count until compare 




enumerator kQTMR_CascadeCount

Cascaded count mode (up/down) 






enum _qtmr_pwm_out_state

Quad Timer PWM output state. 
Values:


enumerator kQTMR_PwmLow

The output state of PWM channel is low 




enumerator kQTMR_PwmHigh

The output state of PWM channel is low 






enum _qtmr_output_mode

Quad Timer output mode selection. 
Values:


enumerator kQTMR_AssertWhenCountActive

Assert OFLAG while counter is active 




enumerator kQTMR_ClearOnCompare

Clear OFLAG on successful compare 




enumerator kQTMR_SetOnCompare

Set OFLAG on successful compare 




enumerator kQTMR_ToggleOnCompare

Toggle OFLAG on successful compare 




enumerator kQTMR_ToggleOnAltCompareReg

Toggle OFLAG using alternating compare registers 




enumerator kQTMR_SetOnCompareClearOnSecSrcInp

Set OFLAG on compare, clear on sec SRC input edge 




enumerator kQTMR_SetOnCompareClearOnCountRoll

Set OFLAG on compare, clear on counter rollover 




enumerator kQTMR_EnableGateClock

Enable gated clock output while count is active 






enum _qtmr_input_capture_edge

Quad Timer input capture edge mode, rising edge, or falling edge. 
Values:


enumerator kQTMR_NoCapture

Capture is disabled 




enumerator kQTMR_RisingEdge

Capture on rising edge (IPS=0) or falling edge (IPS=1) 




enumerator kQTMR_FallingEdge

Capture on falling edge (IPS=0) or rising edge (IPS=1) 




enumerator kQTMR_RisingAndFallingEdge

Capture on both edges 






enum _qtmr_preload_control

Quad Timer input capture edge mode, rising edge, or falling edge. 
Values:


enumerator kQTMR_NoPreload

Never preload 




enumerator kQTMR_LoadOnComp1

Load upon successful compare with value in COMP1 




enumerator kQTMR_LoadOnComp2

Load upon successful compare with value in COMP2 






enum _qtmr_debug_action

List of Quad Timer run options when in Debug mode. 
Values:


enumerator kQTMR_RunNormalInDebug

Continue with normal operation 




enumerator kQTMR_HaltCounter

Halt counter 




enumerator kQTMR_ForceOutToZero

Force output to logic 0 




enumerator kQTMR_HaltCountForceOutZero

Halt counter and force output to logic 0 






enum _qtmr_interrupt_enable

List of Quad Timer interrupts. 
Values:


enumerator kQTMR_CompareInterruptEnable

Compare interrupt. 




enumerator kQTMR_Compare1InterruptEnable

Compare 1 interrupt. 




enumerator kQTMR_Compare2InterruptEnable

Compare 2 interrupt. 




enumerator kQTMR_OverflowInterruptEnable

Timer overflow interrupt. 




enumerator kQTMR_EdgeInterruptEnable

Input edge interrupt. 






enum _qtmr_status_flags

List of Quad Timer flags. 
Values:


enumerator kQTMR_CompareFlag

Compare flag 




enumerator kQTMR_Compare1Flag

Compare 1 flag 




enumerator kQTMR_Compare2Flag

Compare 2 flag 




enumerator kQTMR_OverflowFlag

Timer overflow flag 




enumerator kQTMR_EdgeFlag

Input edge flag 






enum _qtmr_channel_selection

List of channel selection. 
Values:


enumerator kQTMR_Channel_0

TMR Channel 0 




enumerator kQTMR_Channel_1

TMR Channel 1 




enumerator kQTMR_Channel_2

TMR Channel 2 




enumerator kQTMR_Channel_3

TMR Channel 3 






enum _qtmr_dma_enable

List of Quad Timer DMA enable. 
Values:


enumerator kQTMR_InputEdgeFlagDmaEnable

Input Edge Flag DMA Enable. 




enumerator kQTMR_ComparatorPreload1DmaEnable

Comparator Preload Register 1 DMA Enable. 




enumerator kQTMR_ComparatorPreload2DmaEnable

Comparator Preload Register 2 DMA Enable. 






typedef uint32_t qtmrRegType





typedef enum _qtmr_primary_count_source qtmr_primary_count_source_t

Quad Timer primary clock source selection. 




typedef enum _qtmr_input_source qtmr_input_source_t

Quad Timer input sources selection. 




typedef enum _qtmr_counting_mode qtmr_counting_mode_t

Quad Timer counting mode selection. 




typedef enum _qtmr_pwm_out_state qtmr_pwm_out_state_t

Quad Timer PWM output state. 




typedef enum _qtmr_output_mode qtmr_output_mode_t

Quad Timer output mode selection. 




typedef enum _qtmr_input_capture_edge qtmr_input_capture_edge_t

Quad Timer input capture edge mode, rising edge, or falling edge. 




typedef enum _qtmr_preload_control qtmr_preload_control_t

Quad Timer input capture edge mode, rising edge, or falling edge. 




typedef enum _qtmr_debug_action qtmr_debug_action_t

List of Quad Timer run options when in Debug mode. 




typedef enum _qtmr_interrupt_enable qtmr_interrupt_enable_t

List of Quad Timer interrupts. 




typedef enum _qtmr_status_flags qtmr_status_flags_t

List of Quad Timer flags. 




typedef enum _qtmr_channel_selection qtmr_channel_selection_t

List of channel selection. 




typedef enum _qtmr_dma_enable qtmr_dma_enable_t

List of Quad Timer DMA enable. 




typedef struct _qtmr_config qtmr_config_t

Quad Timer config structure. 
This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 




status_t QTMR_SetupPwm(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)

Sets up Quad timer module for PWM signal output. 
The function initializes the timer module according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements.

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
pwmFreqHz – PWM signal frequency in Hz 
dutyCyclePercent – PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle) 
outputPolarity – true: invert polarity of the output signal, false: no inversion 
srcClock_Hz – Main counter clock in Hz.


Returns:
Returns an error if there was error setting up the signal. 






void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, bool inputPolarity, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode)

Allows the user to count the source clock cycles until a capture event arrives. 
The count is stored in the capture register.

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
capturePin – Pin through which we receive the input signal to trigger the capture 
inputPolarity – true: invert polarity of the input signal, false: no inversion 
reloadOnCapture – true: reload the counter when an input capture occurs, false: no reload 
captureMode – Specifies which edge of the input signal triggers a capture 







void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus)

Set PWM output in idle status (high or low). 

Note
When the PWM is set again, the counting needs to be restarted.


Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status. 







static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the channel output status. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number


Returns:
Current channel output status. 






uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the PWM channel dutycycle value. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number


Returns:
Current channel dutycycle value. 






void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler)

This function set the value of the prescaler on QTimer channels. 

Parameters:

base – Quad Timer peripheral base address 
channel – Quad Timer channel number 
prescaler – Set prescaler value 







TMR_CSCTRL_OFLAG_MASK





TMR_CSCTRL_OFLAG_SHIFT





struct _qtmr_config


#include <fsl_qtmr.h>
Quad Timer config structure. 
This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 

Public Members


qtmr_primary_count_source_t primarySource

Specify the primary count source 




qtmr_input_source_t secondarySource

Specify the secondary count source 




bool enableMasterMode

true: Broadcast compare function output to other counters; false no broadcast 




bool enableExternalForce

true: Compare from another counter force state of OFLAG signal false: OFLAG controlled by local counter 




uint8_t faultFilterCount

Fault filter count 




uint8_t faultFilterPeriod

Fault filter period;value of 0 will bypass the filter 




qtmr_debug_action_t debugMode

Operation in Debug mode 







RGPIO: Rapid General-Purpose Input/Output Driver#


FSL_RGPIO_DRIVER_VERSION

RGPIO driver version 2.2.0. 




enum _rgpio_pin_direction

RGPIO direction definition. 
Values:


enumerator kRGPIO_DigitalInput

Set current pin as digital input 




enumerator kRGPIO_DigitalOutput

Set current pin as digital output 






enum _rgpio_checker_attribute

RGPIO checker attribute. 
Values:


enumerator kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW

User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW

User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW

User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW

User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW

User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW

User nonsecure:None; User Secure:None; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR

User nonsecure:None; User Secure:None; Privileged Secure:Read 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN

User nonsecure:None; User Secure:None; Privileged Secure:None 




enumerator kRGPIO_IgnoreAttributeCheck

Ignores the attribute check 






enum _rgpio_interrupt_sel

Configures the interrupt generation condition. 
Values:


enumerator kRGPIO_InterruptOutput0

Interrupt/DMA request/trigger output 0. 




enumerator kRGPIO_InterruptOutput1

Interrupt/DMA request/trigger output 1. 




enumerator kRGPIO_InterruptOutput2

Interrupt/DMA request/trigger output 2. 




enumerator kRGPIO_InterruptOutput3

Interrupt/DMA request/trigger output 3. 






enum _rgpio_interrupt_config

Configures the interrupt generation condition. 
Values:


enumerator kRGPIO_InterruptOrDMADisabled

Interrupt/DMA request is disabled. 




enumerator kRGPIO_DMARisingEdge

DMA request on rising edge. 




enumerator kRGPIO_DMAFallingEdge

DMA request on falling edge. 




enumerator kRGPIO_DMAEitherEdge

DMA request on either edge. 




enumerator kRGPIO_FlagRisingEdge

Flag sets on rising edge. 




enumerator kRGPIO_FlagFallingEdge

Flag sets on falling edge. 




enumerator kRGPIO_FlagEitherEdge

Flag sets on either edge. 




enumerator kRGPIO_InterruptLogicZero

Interrupt when logic zero. 




enumerator kRGPIO_InterruptRisingEdge

Interrupt on rising edge. 




enumerator kRGPIO_InterruptFallingEdge

Interrupt on falling edge. 




enumerator kRGPIO_InterruptEitherEdge

Interrupt on either edge. 




enumerator kRGPIO_InterruptLogicOne

Interrupt when logic one. 




enumerator kRGPIO_ActiveHighTriggerOutputEnable

Enable active high-trigger output. 




enumerator kRGPIO_ActiveLowTriggerOutputEnable

Enable active low-trigger output. 






typedef enum _rgpio_pin_direction rgpio_pin_direction_t

RGPIO direction definition. 




typedef enum _rgpio_checker_attribute rgpio_checker_attribute_t

RGPIO checker attribute. 




typedef enum _rgpio_interrupt_sel rgpio_interrupt_sel_t

Configures the interrupt generation condition. 




typedef enum _rgpio_interrupt_config rgpio_interrupt_config_t

Configures the interrupt generation condition. 




typedef struct _rgpio_pin_config rgpio_pin_config_t

The RGPIO pin configuration structure. 
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig(). 




struct _rgpio_pin_config


#include <fsl_rgpio.h>
The RGPIO pin configuration structure. 
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig(). 

Public Members


rgpio_pin_direction_t pinDirection

RGPIO direction, input or output 




uint8_t outputLogic

Set a default output logic, which has no use in input 







RGPIO Driver#


void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config)

Initializes a RGPIO pin used by the board. 
To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. Then, call the RGPIO_PinInit() function.
This is an example to define an input pin or an output pin configuration. 
 Define a digital input pin configuration,
rgpio_pin_config_t config =
{
  kRGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
rgpio_pin_config_t config =
{
  kRGPIO_DigitalOutput,
  0,
}




Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO port pin number 
config – RGPIO pin configuration pointer 







uint32_t RGPIO_GetInstance(RGPIO_Type *base)

Gets the RGPIO instance according to the RGPIO base. 

Parameters:

base – RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) 


Return values:
RGPIO – instance 






static inline rgpio_pin_direction_t RGPIO_GetPinDirection(RGPIO_Type *base, uint32_t pin)

Gets the current direction of a RGPIO pin. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO port pin number 


Return values:
RGPIO – pin direction

kRGPIO_DigitalInput: pin is configured as digital input.
kRGPIO_DigitalOutput: pin is configured as digital output. 








static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple RGPIO pins to the logic 1 or 0. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO pin number 
output – RGPIO pin output logic level.

0: corresponding pin output low-logic level.
1: corresponding pin output high-logic level. 









static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple RGPIO pins to the logic 1 or 0. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PinWrite. 







static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 1. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 1. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortSet. 







static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 0. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 0. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortClear.




Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple RGPIO pins. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple RGPIO pins. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortToggle. 







static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin)

Reads the current input value of the RGPIO port. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO pin number 


Return values:
RGPIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level. 








static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin)

Reads the current input value of the RGPIO port. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PinRead. 







static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable)


Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number mask 
enable – RGPIO digital input enable/disable flag. 







void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute)

The RGPIO module supports a device-specific number of data ports, organized as 32-bit words. Each 32-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base, uint32_t pin, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)

Configures the gpio pin interrupt/DMA request. 

Parameters:

base – RGPIO peripheral base pointer. 
pin – RGPIO pin number. 
sel – RGPIO pin interrupt selection(0-3). 
config – RGPIO pin interrupt configuration. 







static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base, uint32_t mask, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)

Sets the gpio interrupt configuration in ICR register for multiple pins. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro. 
sel – RGPIO pin interrupt selection(0-3). 
config – RGPIO pin interrupt configuration. 







static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel)

Reads the whole gpio status flag. 
If a pin is configured to generate the DMA request, the corresponding flag is cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted, the flag is set again immediately.

Parameters:

base – RGPIO peripheral base pointer. 
sel – RGPIO pin interrupt selection(0-3). 


Returns:
Current gpio interrupt status flags, for example, 0x00010001 means the pin 0 and 16 have the interrupt. 






static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask)

Clears the multiple pin interrupt status flag. 

Parameters:

base – RGPIO peripheral base pointer. 
sel – RGPIO pin interrupt selection(0-3). 
mask – RGPIO pin number macro. 







S3MU: Sentinel#


FSL_S3MU_DRIVER_VERSION

Defines S3MU driver version 2.0.2. 
Change log:

Version 2.0.2

Fix macro BIT redefined warning when compiling with Zephyr.


Version 2.0.1

Update kStatusGroup_SNT to kStatusGroup_ELEMU


Version 2.0.0

initial version 









Values:


enumerator kStatus_S3MU_AgumentOutOfRange

S3MU status for out of range access. 




enumerator kStatus_S3MU_InvalidArgument

S3MU status for invalid argument check. 




enumerator kStatus_S3MU_RequestTimeout

S3MU status for timeout. 




enumerator kStatus_S3MU_Busy

S3MU status for reservation by other core. 






status_t S3MU_SendMessage(S3MU_Type *mu, void *buf, size_t wordCount)

Send message to MU. 
This function writes messgae into MU regsters and send message to EdgeLock Enclave.

Parameters:

base – MU peripheral base address 
buf – buffer to store read data 
wordCount – size of data in words


Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange 






status_t S3MU_GetResponse(S3MU_Type *mu, void *buf)

Get response from MU. 
This function reads response data from EdgeLock Enclave if available.

Note: number of read response word is obtained by header, so user need to prepare buffer with enough space for expected response

Parameters:

base – MU peripheral base address 
buf – buffer to store read data


Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange 






status_t S3MU_WaitForData(S3MU_Type *mu, uint32_t *buf, size_t wordCount, uint32_t wait)

Wait and Read data from MU. 
This function waits limited time (ticks) and tests if data are ready to be read. When data are ready, reads them into buffer, timeout otherwise.

Parameters:

base – MU peripheral base address 
buf – buffer to store read data 
wordCount – size of data in words 
wait – number of iterations to wait


Returns:
Status kStatus_Success if success, kStatus_S3MU_RequestTimeout if timeout Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange 






status_t S3MU_ReadMessage(S3MU_Type *mu, uint32_t *buf, size_t *size, uint8_t read_header)

Read message from MU. 
This function reads message date from EdgeLock Enclave if available.

Parameters:

base – MU peripheral base address 
buf – buffer to store read data 
size – lenght of data in words. If read_header equal MU_READ_HEADER, size is read from response header. 
read_header – specifies if size is obtained by response header or provided in parameter.


Returns:
Status kStatus_Success if success, kStatus_Fail if fail Possible errors: kStatus_S3MU_InvalidArgument, kStatus_S3MU_AgumentOutOfRange 






void S3MU_Init(S3MU_Type *mu)

Init MU. 
This function does nothing. MU is initialized after leaving ROM.

Parameters:

base – MU peripheral base address 







uint32_t S3MU_ComputeMsgCrc(uint32_t *msg, uint32_t msg_len)

Computes CRC. 
This function computes CRC of input message.

Parameters:

msg – pointer to message 
msg_len – size of message in words


Returns:
CRC32 checksum value 






MU_MSG_HEADER_SIZE





MESSAGING_TAG_COMMAND





MESSAGING_TAG_REPLY





struct mu_hdr_t





union __unnamed204__


Public Members


uint32_t value





struct mu_hdr_t hdr_byte








struct hdr_byte





SAI: Serial Audio Interface#


SAI Driver#


void SAI_Init(I2S_Type *base)

Initializes the SAI peripheral. 
This API gates the SAI clock. The SAI module can’t operate unless SAI_Init is called to enable the clock.

Parameters:

base – SAI base pointer. 







void SAI_Deinit(I2S_Type *base)

De-initializes the SAI peripheral. 
This API gates the SAI clock. The SAI module can’t operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.

Parameters:

base – SAI base pointer. 







void SAI_TxReset(I2S_Type *base)

Resets the SAI Tx. 
This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer 







void SAI_RxReset(I2S_Type *base)

Resets the SAI Rx. 
This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer 







void SAI_TxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Tx. 

Parameters:

base – SAI base pointer. 
enable – True means enable SAI Tx, false means disable. 







void SAI_RxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Rx. 

Parameters:

base – SAI base pointer. 
enable – True means enable SAI Rx, false means disable. 







static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction. 
Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction. 
Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx frame sync direction. 
Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Tx frame sync direction. 
Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







void SAI_TxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Transmitter bit clock rate configurations. 

Parameters:

base – SAI base pointer. 
sourceClockHz – Bit clock source frequency. 
sampleRate – Audio data sample rate. 
bitWidth – Audio data bitWidth. 
channelNumbers – Audio channel numbers. 







void SAI_RxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Receiver bit clock rate configurations. 

Parameters:

base – SAI base pointer. 
sourceClockHz – Bit clock source frequency. 
sampleRate – Audio data sample rate. 
bitWidth – Audio data bitWidth. 
channelNumbers – Audio channel numbers. 







void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Transmitter Bit clock configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – bit clock other configurations, can be NULL in slave mode. 







void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Receiver Bit clock configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – bit clock other configurations, can be NULL in slave mode. 







void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)

Master clock configurations. 

Parameters:

base – SAI base pointer. 
config – master clock configurations. 







void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI transmitter fifo configurations. 

Parameters:

base – SAI base pointer. 
config – fifo configurations. 







void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI receiver fifo configurations. 

Parameters:

base – SAI base pointer. 
config – fifo configurations. 







void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI transmitter Frame sync configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – frame sync configurations, can be NULL in slave mode. 







void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI receiver Frame sync configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – frame sync configurations, can be NULL in slave mode. 







void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI transmitter Serial data configurations. 

Parameters:

base – SAI base pointer. 
config – serial data configurations. 







void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI receiver Serial data configurations. 

Parameters:

base – SAI base pointer. 
config – serial data configurations. 







void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI transmitter configurations. 

Parameters:

base – SAI base pointer. 
config – transmitter configurations. 







void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI receiver configurations. 

Parameters:

base – SAI base pointer. 
config – receiver configurations. 







void SAI_GetClassicI2SConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get classic I2S mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get left justified mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get right justified mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetTDMConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)

Get TDM mode configurations. 

Parameters:

config – transceiver configurations. 
frameSyncWidth – length of frame sync. 
bitWidth – audio data word width. 
dataWordNum – word number in one frame. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetDSPConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get DSP mode configurations. 

DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: 
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
SAI_TxSetConfig(base, config)




Note
DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: 
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
config->frameSync.frameSyncEarly    = true;
SAI_TxSetConfig(base, config)





Parameters:

config – transceiver configurations. 
frameSyncWidth – length of frame sync. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to enable. 







static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 


Returns:
SAI Tx status flag value. Use the Status Mask to get the status value needed. 






static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 
mask – State mask. It can be a combination of the following source if defined: 

kSAI_WordStartFlag 
kSAI_SyncErrorFlag 
kSAI_FIFOErrorFlag 









static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 


Returns:
SAI Rx status flag value. Use the Status Mask to get the status value needed. 






static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Rx status flag state. 

Parameters:

base – SAI base pointer 
mask – State mask. It can be a combination of the following sources if defined. 

kSAI_WordStartFlag 
kSAI_SyncErrorFlag 
kSAI_FIFOErrorFlag 









void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset . 
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer 
resetType – Reset type, FIFO reset or software reset 







void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset . 
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer 
resetType – Reset type, FIFO reset or software reset 







void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Tx channel FIFO enable mask. 

Parameters:

base – SAI base pointer 
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled. 







void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Rx channel FIFO enable mask. 

Parameters:

base – SAI base pointer 
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled. 







void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
order – Data order MSB or LSB 







void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
order – Data order MSB or LSB 







void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Tx FIFO packing feature. 

Parameters:

base – SAI base pointer. 
pack – FIFO pack type. It is element of sai_fifo_packing_t. 







void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Rx FIFO packing feature. 

Parameters:

base – SAI base pointer. 
pack – FIFO pack type. It is element of sai_fifo_packing_t. 







static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Tx FIFO error continue. 
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.

Parameters:

base – SAI base pointer. 
isEnabled – Is FIFO error continue enabled, true means enable, false means disable. 







static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Rx FIFO error continue. 
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.

Parameters:

base – SAI base pointer. 
isEnabled – Is FIFO error continue enabled, true means enable, false means disable. 







static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Tx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Rx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Tx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Rx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Tx DMA requests. 

Parameters:

base – SAI base pointer 
mask – DMA source The parameter can be combination of the following sources if defined. 

kSAI_FIFOWarningDMAEnable 
kSAI_FIFORequestDMAEnable 


enable – True means enable DMA, false means disable DMA. 







static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Rx DMA requests. 

Parameters:

base – SAI base pointer 
mask – DMA source The parameter can be a combination of the following sources if defined. 

kSAI_FIFOWarningDMAEnable 
kSAI_FIFORequestDMAEnable 


enable – True means enable DMA, false means disable DMA. 







static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Tx data register address. 
This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Rx data register address. 
This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be written. 
size – Bytes to be written. 







void SAI_WriteMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data to multi channel using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
channelMask – channel mask. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be written. 
size – Bytes to be written. 







static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)

Writes data into SAI FIFO. 

Parameters:

base – SAI base pointer. 
channel – Data channel used. 
data – Data needs to be written. 







void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be read. 
size – Bytes to be read. 







void SAI_ReadMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives multi channel data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
channelMask – channel mask. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be read. 
size – Bytes to be read. 







static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)

Reads data from the SAI FIFO. 

Parameters:

base – SAI base pointer. 
channel – Data channel used. 


Returns:
Data in SAI FIFO. 






void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Tx handle. 
This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer 
handle – SAI handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function 







void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Rx handle. 
This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function. 







void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI transmitter transfer configurations. 
This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
config – tranmitter configurations. 







void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI receiver transfer configurations. 
This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
config – receiver configurations. 







status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on SAI. 

Note
This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.


Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
xfer – Pointer to the sai_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_SAI_TxBusy – Previous receive still not finished. 
kStatus_InvalidArgument – The input parameter is invalid. 







status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on SAI. 

Note
This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.


Parameters:

base – SAI base pointer 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
xfer – Pointer to the sai_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_SAI_RxBusy – Previous receive still not finished. 
kStatus_InvalidArgument – The input parameter is invalid. 







status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a set byte count. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
count – Bytes count sent. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a received byte count. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
count – Bytes count received. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)

Aborts the current send. 

Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 







void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)

Aborts the current IRQ receive. 

Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – SAI base pointer 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 







void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI send. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI receive. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure. 







void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure. 







void SAI_DriverIRQHandler(uint32_t instance)

SAI driver IRQ handler common entry. 
This function provides the common IRQ request entry for SAI.

Parameters:

instance – SAI instance. 







FSL_SAI_DRIVER_VERSION

Version 2.4.11 





_sai_status_t, SAI return status. 
Values:


enumerator kStatus_SAI_TxBusy

SAI Tx is busy. 




enumerator kStatus_SAI_RxBusy

SAI Rx is busy. 




enumerator kStatus_SAI_TxError

SAI Tx FIFO error. 




enumerator kStatus_SAI_RxError

SAI Rx FIFO error. 




enumerator kStatus_SAI_QueueFull

SAI transfer queue is full. 




enumerator kStatus_SAI_TxIdle

SAI Tx is idle 




enumerator kStatus_SAI_RxIdle

SAI Rx is idle 







_sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific 
Values:


enumerator kSAI_Channel0Mask

channel 0 mask value 




enumerator kSAI_Channel1Mask

channel 1 mask value 




enumerator kSAI_Channel2Mask

channel 2 mask value 




enumerator kSAI_Channel3Mask

channel 3 mask value 




enumerator kSAI_Channel4Mask

channel 4 mask value 




enumerator kSAI_Channel5Mask

channel 5 mask value 




enumerator kSAI_Channel6Mask

channel 6 mask value 




enumerator kSAI_Channel7Mask

channel 7 mask value 






enum _sai_protocol

Define the SAI bus type. 
Values:


enumerator kSAI_BusLeftJustified

Uses left justified format. 




enumerator kSAI_BusRightJustified

Uses right justified format. 




enumerator kSAI_BusI2S

Uses I2S format. 




enumerator kSAI_BusPCMA

Uses I2S PCM A format. 




enumerator kSAI_BusPCMB

Uses I2S PCM B format. 






enum _sai_master_slave

Master or slave mode. 
Values:


enumerator kSAI_Master

Master mode include bclk and frame sync 




enumerator kSAI_Slave

Slave mode include bclk and frame sync 




enumerator kSAI_Bclk_Master_FrameSync_Slave

bclk in master mode, frame sync in slave mode 




enumerator kSAI_Bclk_Slave_FrameSync_Master

bclk in slave mode, frame sync in master mode 






enum _sai_mono_stereo

Mono or stereo audio format. 
Values:


enumerator kSAI_Stereo

Stereo sound. 




enumerator kSAI_MonoRight

Only Right channel have sound. 




enumerator kSAI_MonoLeft

Only left channel have sound. 






enum _sai_data_order

SAI data order, MSB or LSB. 
Values:


enumerator kSAI_DataLSB

LSB bit transferred first 




enumerator kSAI_DataMSB

MSB bit transferred first 






enum _sai_clock_polarity

SAI clock polarity, active high or low. 
Values:


enumerator kSAI_PolarityActiveHigh

Drive outputs on rising edge 




enumerator kSAI_PolarityActiveLow

Drive outputs on falling edge 




enumerator kSAI_SampleOnFallingEdge

Sample inputs on falling edge 




enumerator kSAI_SampleOnRisingEdge

Sample inputs on rising edge 






enum _sai_sync_mode

Synchronous or asynchronous mode. 
Values:


enumerator kSAI_ModeAsync

Asynchronous mode 




enumerator kSAI_ModeSync

Synchronous mode (with receiver or transmit) 




enumerator kSAI_ModeSyncWithOtherTx

Synchronous with another SAI transmit 




enumerator kSAI_ModeSyncWithOtherRx

Synchronous with another SAI receiver 






enum _sai_bclk_source

Bit clock source. 
Values:


enumerator kSAI_BclkSourceBusclk

Bit clock using bus clock 




enumerator kSAI_BclkSourceMclkOption1

Bit clock MCLK option 1 




enumerator kSAI_BclkSourceMclkOption2

Bit clock MCLK option2 




enumerator kSAI_BclkSourceMclkOption3

Bit clock MCLK option3 




enumerator kSAI_BclkSourceMclkDiv

Bit clock using master clock divider 




enumerator kSAI_BclkSourceOtherSai0

Bit clock from other SAI device 




enumerator kSAI_BclkSourceOtherSai1

Bit clock from other SAI device 







_sai_interrupt_enable_t, The SAI interrupt enable flag 
Values:


enumerator kSAI_WordStartInterruptEnable

Word start flag, means the first word in a frame detected 




enumerator kSAI_SyncErrorInterruptEnable

Sync error flag, means the sync error is detected 




enumerator kSAI_FIFOWarningInterruptEnable

FIFO warning flag, means the FIFO is empty 




enumerator kSAI_FIFOErrorInterruptEnable

FIFO error flag 




enumerator kSAI_FIFORequestInterruptEnable

FIFO request, means reached watermark 







_sai_dma_enable_t, The DMA request sources 
Values:


enumerator kSAI_FIFOWarningDMAEnable

FIFO warning caused by the DMA request 




enumerator kSAI_FIFORequestDMAEnable

FIFO request caused by the DMA request 







_sai_flags, The SAI status flag 
Values:


enumerator kSAI_WordStartFlag

Word start flag, means the first word in a frame detected 




enumerator kSAI_SyncErrorFlag

Sync error flag, means the sync error is detected 




enumerator kSAI_FIFOErrorFlag

FIFO error flag 




enumerator kSAI_FIFORequestFlag

FIFO request flag. 




enumerator kSAI_FIFOWarningFlag

FIFO warning flag 






enum _sai_reset_type

The reset type. 
Values:


enumerator kSAI_ResetTypeSoftware

Software reset, reset the logic state 




enumerator kSAI_ResetTypeFIFO

FIFO reset, reset the FIFO read and write pointer 




enumerator kSAI_ResetAll

All reset. 






enum _sai_fifo_packing

The SAI packing mode The mode includes 8 bit and 16 bit packing. 
Values:


enumerator kSAI_FifoPackingDisabled

Packing disabled 




enumerator kSAI_FifoPacking8bit

8 bit packing enabled 




enumerator kSAI_FifoPacking16bit

16bit packing enabled 






enum _sai_sample_rate

Audio sample rate. 
Values:


enumerator kSAI_SampleRate8KHz

Sample rate 8000 Hz 




enumerator kSAI_SampleRate11025Hz

Sample rate 11025 Hz 




enumerator kSAI_SampleRate12KHz

Sample rate 12000 Hz 




enumerator kSAI_SampleRate16KHz

Sample rate 16000 Hz 




enumerator kSAI_SampleRate22050Hz

Sample rate 22050 Hz 




enumerator kSAI_SampleRate24KHz

Sample rate 24000 Hz 




enumerator kSAI_SampleRate32KHz

Sample rate 32000 Hz 




enumerator kSAI_SampleRate44100Hz

Sample rate 44100 Hz 




enumerator kSAI_SampleRate48KHz

Sample rate 48000 Hz 




enumerator kSAI_SampleRate96KHz

Sample rate 96000 Hz 




enumerator kSAI_SampleRate192KHz

Sample rate 192000 Hz 




enumerator kSAI_SampleRate384KHz

Sample rate 384000 Hz 






enum _sai_word_width

Audio word width. 
Values:


enumerator kSAI_WordWidth8bits

Audio data width 8 bits 




enumerator kSAI_WordWidth16bits

Audio data width 16 bits 




enumerator kSAI_WordWidth24bits

Audio data width 24 bits 




enumerator kSAI_WordWidth32bits

Audio data width 32 bits 






enum _sai_data_pin_state

sai data pin state definition 
Values:


enumerator kSAI_DataPinStateTriState

transmit data pins are tri-stated when slots are masked or channels are disabled 




enumerator kSAI_DataPinStateOutputZero

transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled 






enum _sai_fifo_combine

sai fifo combine mode definition 
Values:


enumerator kSAI_FifoCombineDisabled

sai TX/RX fifo combine mode disabled 




enumerator kSAI_FifoCombineModeEnabledOnRead

sai TX fifo combine mode enabled on FIFO reads 




enumerator kSAI_FifoCombineModeEnabledOnWrite

sai TX fifo combine mode enabled on FIFO write 




enumerator kSAI_RxFifoCombineModeEnabledOnWrite

sai RX fifo combine mode enabled on FIFO write 




enumerator kSAI_RXFifoCombineModeEnabledOnRead

sai RX fifo combine mode enabled on FIFO reads 




enumerator kSAI_FifoCombineModeEnabledOnReadWrite

sai TX/RX fifo combined mode enabled on FIFO read/writes 






enum _sai_transceiver_type

sai transceiver type 
Values:


enumerator kSAI_Transmitter

sai transmitter 




enumerator kSAI_Receiver

sai receiver 






enum _sai_frame_sync_len

sai frame sync len 
Values:


enumerator kSAI_FrameSyncLenOneBitClk

1 bit clock frame sync len for DSP mode 




enumerator kSAI_FrameSyncLenPerWordWidth

Frame sync length decided by word width 






typedef enum _sai_protocol sai_protocol_t

Define the SAI bus type. 




typedef enum _sai_master_slave sai_master_slave_t

Master or slave mode. 




typedef enum _sai_mono_stereo sai_mono_stereo_t

Mono or stereo audio format. 




typedef enum _sai_data_order sai_data_order_t

SAI data order, MSB or LSB. 




typedef enum _sai_clock_polarity sai_clock_polarity_t

SAI clock polarity, active high or low. 




typedef enum _sai_sync_mode sai_sync_mode_t

Synchronous or asynchronous mode. 




typedef enum _sai_bclk_source sai_bclk_source_t

Bit clock source. 




typedef enum _sai_reset_type sai_reset_type_t

The reset type. 




typedef enum _sai_fifo_packing sai_fifo_packing_t

The SAI packing mode The mode includes 8 bit and 16 bit packing. 




typedef struct _sai_config sai_config_t

SAI user configuration structure. 




typedef enum _sai_sample_rate sai_sample_rate_t

Audio sample rate. 




typedef enum _sai_word_width sai_word_width_t

Audio word width. 




typedef enum _sai_data_pin_state sai_data_pin_state_t

sai data pin state definition 




typedef enum _sai_fifo_combine sai_fifo_combine_t

sai fifo combine mode definition 




typedef enum _sai_transceiver_type sai_transceiver_type_t

sai transceiver type 




typedef enum _sai_frame_sync_len sai_frame_sync_len_t

sai frame sync len 




typedef struct _sai_transfer_format sai_transfer_format_t

sai transfer format 




typedef struct _sai_master_clock sai_master_clock_t

master clock configurations 




typedef struct _sai_fifo sai_fifo_t

sai fifo configurations 




typedef struct _sai_bit_clock sai_bit_clock_t

sai bit clock configurations 




typedef struct _sai_frame_sync sai_frame_sync_t

sai frame sync configurations 




typedef struct _sai_serial_data sai_serial_data_t

sai serial data configurations 




typedef struct _sai_transceiver sai_transceiver_t

sai transceiver configurations 




typedef struct _sai_transfer sai_transfer_t

SAI transfer structure. 




typedef struct _sai_handle sai_handle_t





typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData)

SAI transfer callback prototype. 




MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK

Used to control whether SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() allows a NULL FIFO watermark. 
If this macro is set to 0 then SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() will set the watermark to half of the FIFO’s depth if passed a NULL watermark. 




MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG

Disable implicit channel data configuration within SAI_TxSetConfig()/SAI_RxSetConfig(). 
Use this macro to control whether SAI_RxSetConfig()/SAI_TxSetConfig() will attempt to implicitly configure the channel data. By channel data we mean the startChannel, channelMask, endChannel, and channelNums fields from the sai_transciever_t structure. By default, SAI_TxSetConfig()/SAI_RxSetConfig() will attempt to compute these fields, which may not be desired in cases where the user wants to set them before the call to said functions. 




SAI_XFER_QUEUE_SIZE

SAI transfer queue size, user can refine it according to use case. 




FSL_SAI_HAS_FIFO_EXTEND_FEATURE

sai fifo feature 




struct _sai_config


#include <fsl_sai.h>
SAI user configuration structure. 

Public Members


sai_protocol_t protocol

Audio bus protocol in SAI 




sai_sync_mode_t syncMode

SAI sync mode, control Tx/Rx clock sync 




bool mclkOutputEnable

Master clock output enable, true means master clock divider enabled 




sai_bclk_source_t bclkSource

Bit Clock source 




sai_master_slave_t masterSlave

Master or slave 







struct _sai_transfer_format


#include <fsl_sai.h>
sai transfer format 

Public Members


uint32_t sampleRate_Hz

Sample rate of audio data 




uint32_t bitWidth

Data length of audio data, usually 8/16/24/32 bits 




sai_mono_stereo_t stereo

Mono or stereo 




uint32_t masterClockHz

Master clock frequency in Hz 




uint8_t watermark

Watermark value 




uint8_t channel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 




sai_protocol_t protocol

Which audio protocol used 




bool isFrameSyncCompact

True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock. 







struct _sai_master_clock


#include <fsl_sai.h>
master clock configurations 

Public Members


bool mclkOutputEnable

master clock output enable 




uint32_t mclkHz

target mclk frequency 




uint32_t mclkSourceClkHz

mclk source frequency 







struct _sai_fifo


#include <fsl_sai.h>
sai fifo configurations 

Public Members


bool fifoContinueOneError

fifo continues when error occur 




sai_fifo_combine_t fifoCombine

fifo combine mode 




sai_fifo_packing_t fifoPacking

fifo packing mode 




uint8_t fifoWatermark

fifo watermark 







struct _sai_bit_clock


#include <fsl_sai.h>
sai bit clock configurations 

Public Members


bool bclkSrcSwap

bit clock source swap 




bool bclkInputDelay

bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time . 




sai_clock_polarity_t bclkPolarity

bit clock polarity 




sai_bclk_source_t bclkSource

bit Clock source 







struct _sai_frame_sync


#include <fsl_sai.h>
sai frame sync configurations 

Public Members


uint8_t frameSyncWidth

frame sync width in number of bit clocks 




bool frameSyncEarly

TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame 




bool frameSyncGenerateOnDemand

internal frame sync is generated when FIFO waring flag is clear 




sai_clock_polarity_t frameSyncPolarity

frame sync polarity 







struct _sai_serial_data


#include <fsl_sai.h>
sai serial data configurations 

Public Members


sai_data_pin_state_t dataMode

sai data pin state when slots masked or channel disabled 




sai_data_order_t dataOrder

configure whether the LSB or MSB is transmitted first 




uint8_t dataWord0Length

configure the number of bits in the first word in each frame 




uint8_t dataWordNLength

configure the number of bits in the each word in each frame, except the first word 




uint8_t dataWordLength

used to record the data length for dma transfer 




uint8_t dataFirstBitShifted

Configure the bit index for the first bit transmitted for each word in the frame 




uint8_t dataWordNum

configure the number of words in each frame 




uint32_t dataMaskedWord

configure whether the transmit word is masked 







struct _sai_transceiver


#include <fsl_sai.h>
sai transceiver configurations 

Public Members


sai_serial_data_t serialData

serial data configurations 




sai_frame_sync_t frameSync

ws configurations 




sai_bit_clock_t bitClock

bit clock configurations 




sai_fifo_t fifo

fifo configurations 




sai_master_slave_t masterSlave

transceiver is master or slave 




sai_sync_mode_t syncMode

transceiver sync mode 




uint8_t startChannel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 







struct _sai_transfer


#include <fsl_sai.h>
SAI transfer structure. 

Public Members


uint8_t *data

Data start address to transfer. 




size_t dataSize

Transfer size. 







struct _sai_handle


#include <fsl_sai.h>
SAI handle structure. 

Public Members


I2S_Type *base

base address 




uint32_t state

Transfer status 




sai_transfer_callback_t callback

Callback function called at transfer event 




void *userData

Callback parameter passed to callback function 




uint8_t bitWidth

Bit width for transfer, 8/16/24/32 bits 




uint8_t channel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, refernece _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 




sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer 




size_t transferSize[(4U)]

Data bytes need to transfer 




volatile uint8_t queueUser

Index for user to queue transfer 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 




uint8_t watermark

Watermark value 







SAI EDMA Driver#


void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle)

Initializes the SAI eDMA handle. 
This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
txDmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle)

Initializes the SAI Rx eDMA handle. 
This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
rxDmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType)

Initializes the SAI interleave type. 
This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is kSAI_EDMAInterleavePerChannelSample always

Parameters:

handle – SAI eDMA handle pointer. 
interleaveType – Multi channel interleave type. 







void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Tx. 

Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step. 
sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite;
SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config);





Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
saiConfig – sai configurations. 







void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Rx. 

Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step. 
sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead;
SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config);





Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
saiConfig – sai configurations. 







status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI transfer using DMA. 

This function support multi channel transfer,

for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.



Note
This interface returns immediately after the transfer initiates. Call SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure. 


Return values:

kStatus_Success – Start a SAI eDMA send successfully. 
kStatus_InvalidArgument – The input argument is invalid. 
kStatus_TxBusy – SAI is busy sending data. 







status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI receive using eDMA. 

This function support multi channel transfer,

for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.



Note
This interface returns immediately after the transfer initiates. Call the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.


Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 
xfer – Pointer to DMA transfer structure. 


Return values:

kStatus_Success – Start a SAI eDMA receive successfully. 
kStatus_InvalidArgument – The input argument is invalid. 
kStatus_RxBusy – SAI is busy receiving data. 







status_t SAI_TransferSendLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA. 

Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer.

Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). 
loopTransferCount – the counts of xfer array. 


Return values:

kStatus_Success – Start a SAI eDMA send successfully. 
kStatus_InvalidArgument – The input argument is invalid. 







status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA. 

Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer.

Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). 
loopTransferCount – the counts of xfer array. 


Return values:

kStatus_Success – Start a SAI eDMA receive successfully. 
kStatus_InvalidArgument – The input argument is invalid. 







void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI send. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSendEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI receive. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceiveEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI transfer using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI receive using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 







status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count sent by SAI. 

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
count – Bytes count sent by SAI. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count received by SAI. 

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 
count – Bytes count received by SAI. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Gets valid transfer slot. 
This function can be used to query the valid transfer request slot that the application can submit. It should be called in the critical section, that means the application could call it in the corresponding callback function or disable IRQ before calling it in the application, otherwise, the returned value may not correct.

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 


Return values:
valid – slot count that application submit. 






FSL_SAI_EDMA_DRIVER_VERSION

Version 2.7.4 




enum _sai_edma_interleave

sai interleave type 
Values:


enumerator kSAI_EDMAInterleavePerChannelSample





enumerator kSAI_EDMAInterleavePerChannelBlock







typedef struct sai_edma_handle sai_edma_handle_t





typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)

SAI eDMA transfer callback function for finish and error. 




typedef enum _sai_edma_interleave sai_edma_interleave_t

sai interleave type 




MCUX_SDK_SAI_EDMA_RX_ENABLE_INTERNAL

the SAI enable position When calling SAI_TransferReceiveEDMA 




MCUX_SDK_SAI_EDMA_TX_ENABLE_INTERNAL

the SAI enable position When calling SAI_TransferSendEDMA 




struct sai_edma_handle


#include <fsl_sai_edma.h>
SAI DMA transfer handle, users should not touch the content of the handle. 

Public Members


edma_handle_t *dmaHandle

DMA handler for SAI send 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




uint8_t bytesPerFrame

Bytes in a frame 




uint8_t channelMask

Enabled channel mask value, reference _sai_channel_mask 




uint8_t channelNums

total enabled channel nums 




uint8_t channel

Which data channel 




uint8_t count

The transfer data count in a DMA request 




uint32_t state

Internal state for SAI eDMA transfer 




sai_edma_callback_t callback

Callback for users while transfer finish or error occurs 




void *userData

User callback parameter 




uint8_t tcd[((4U) + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA transfer. 




sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer. 




size_t transferSize[(4U)]

Data bytes need to transfer 




sai_edma_interleave_t interleaveType

Transfer interleave type 




volatile uint8_t queueUser

Index for user to queue transfer. 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 







SAR_ADC: SAR_ADC Module#


void ADC_GetDefaultConfig(adc_config_t *config)

This function is used to get available predefined configurations for the ADC initialization. 

Parameters:

config – Pointer to the ADC configuration structure, please refer to adc_config_t for details. 







void ADC_Init(ADC_Type *base, const adc_config_t *config)

This function is used to initialize the ADC. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the ADC configuration structure, please refer to adc_config_t for details. 







void ADC_Deinit(ADC_Type *base)

This function is used to de-initialize the ADC. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_SetPowerDownMode(ADC_Type *base, bool enable)

This function is used to enter or exit power-down mode. 
After the release of the reset, the ADC analog module will be kept in power-down mode by default. The power-down mode can be set anytime. However, ADC can enter the power-down mode successfully only after completion of an ongoing conversion (if there is one). In scan mode, the ongoing operation should be aborted manually before or after switching mode. If the power-down mode is entered by setting MCR[PWDN], the process running in the previous mode must be restarted manually (by setting the appropriate START bit in the MCR register) after exiting power-down mode.

Note
After setting the ADC mode, it is recommended to use the function ADC_GetAdcState to query whether the ADC has correctly entered the mode.


Parameters:

base – ADC peripheral base address. 
enable – Indicates whether to enter or exit power-down mode.

true Request to enter power-down mode.
false When ADC status is in power-down mode (MSR[ADCSTATUS] = 001b), start ADC transition to IDLE mode. 









static inline void ADC_SetOperatingClock(ADC_Type *base, adc_clock_frequency_t clockSelect)

This function is used to select the ADC operating clock. 

Note
Needs to enter power-down mode before changing the ADC internal operating clock.


Parameters:

base – ADC peripheral base address. 
clockSelect – ADC clock frequency selection, please refer to adc_clock_frequency_t for details. 







static inline adc_state_t ADC_GetAdcState(ADC_Type *base)

This function is used to get the ADC state. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC state, for possible states, please refer to adc_state_t for details. 






static inline bool ADC_CheckAutoClockOffEnabled(ADC_Type *base)

This function is used to check whether the ADC auto clock-off feature has been enabled or not. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC auto clock-off feature status.

true Auto clock-off feature has been enabled.
false Auto clock-off feature has not been enabled. 








static inline uint8_t ADC_GetCurrentConvertedChannelId(ADC_Type *base)

This function is used to get the ID of the channel that is currently being converted. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC channel ID that is currently being converted. 






static inline bool ADC_CheckSelfTestConvInProcess(ADC_Type *base)

This function is used to check whether the self-test conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Self-test conversion status.

true Self-test conversion is in process.
false Self-test conversion is not in process. 








static inline bool ADC_CheckInjectConvInProcess(ADC_Type *base)

This function is used to check whether the inject conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Inject conversion status.

true Inject conversion is in process.
false Inject conversion is not in process. 








static inline bool ADC_CheckInjectConvAborted(ADC_Type *base)

This function is used to check whether the inject conversion has been aborted or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Inject conversion abort status.

true Injected conversion has been aborted.
false Injected conversion has not been aborted. 








static inline bool ADC_CheckNormalConvInProcess(ADC_Type *base)

This function is used to check whether the normal conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Normal conversion status.

true Normal conversion is in process.
false Normal conversion is not in process. 








static inline bool ADC_CheckCalibrationBusy(ADC_Type *base)

This function is used to check whether the ADC is executing calibration or ready for use. 

Parameters:

base – ADC peripheral base address.


Returns:
Calibration process status.

true ADC is busy in a calibration process.
false ADC is ready for use. 








static inline bool ADC_CheckCalibrationFailed(ADC_Type *base)

This function is used to check whether the calibration has failed or passed. 

Note
When the user clears the calibration failed status and then reads the status, it will display the calibration passed. At this time, the calibration may not be successful. The user must read the MSR[CALBUSY] bit by function ADC_CheckCalibrationBusy to perform a double check.


Returns:
Normal conversion status.

true Calibration failed.
false Calibration passed (must be checked with CALBUSY = 0b). 








static inline void ADC_ClearCalibrationFailedFlag(ADC_Type *base)

This function is used to clear the flag of calibration. 

Parameters:

base – ADC peripheral base address. 







static inline bool ADC_CheckCalibrationSuccessful(ADC_Type *base)

This function is used to check whether the calibration is successful or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Normal conversion status.

true Calibrated or calibration successful.
false Uncalibrated or calibration unsuccessful. 








void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config)

This function is used to configure the chain. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the chain configuration structure, please refer to adc_chain_config_t for details. 







static inline void ADC_EnableSpecificChannelNormalConv(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel to execute normal conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the normal conversion. 







static inline void ADC_DisableSpecificChannelNormalConv(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel to execute the normal conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the normal conversion. 







static inline void ADC_EnableSpecificChannelInjectConv(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel to execute the inject conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the inject conversion. 







static inline void ADC_DisableSpecificChannelInjectConv(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel to execute the inject conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the inject conversion. 







static inline void ADC_SetConvMode(ADC_Type *base, adc_conv_mode_t convMode)

This function is used to set the ADC conversion mode. 

Note
Before setting the conversion mode, users need to check whether the ADC is in the idle status through the function ADC_GetAdcState.


Parameters:

base – ADC peripheral base address. 
convMode – ADC conversion mode, please refer to adc_conv_mode_t for details. 







static inline void ADC_StartConvChain(ADC_Type *base, adc_conv_mode_t convMode)

This function is used to start the ADC conversion chain to execute the conversion. 

Note
Normal conversion supports two conversion modes, one is one-shot conversion mode, and the other is scan conversion mode. Normal conversion should usually be used to convert analog samples most of the time in an application, unless there is a special need. Inject conversion has a higher priority than normal conversion and it runs in one-shot mode only, it can be started in IDLE condition or when normal conversion is in process.


Parameters:

base – ADC peripheral base address. 
convMode – Pointer to the ADC conversion chain, please refer to adc_conv_mode_t for details. 







static inline void ADC_StopConvChain(ADC_Type *base)

This function is used to stop scan in normal conversion scan operation mode. 

Note
In scan operation mode, the MCR[NSTART] field remains high after setting. Clearing this field in scan operation mode causes the current chain conversion to finish, then stop the scan.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_AbortCurrentConvChain(ADC_Type *base)

This function is used to abort the conversion chain. 
Abort the current chain of conversions by setting MCR[ABORTCHAIN]. In that case, the behavior of the ADC depends on MCR[MODE] (one-shot/scan conversion modes). In one-shot mode, MSR[NSTART] is automatically reset together with MCR[ABORTCHAIN], an end-of-chain interrupt is not generated in the case of an abort chain. In scan mode, a new chain is started. The end-of-conversion interrupt of the current aborted conversion is not generated but an end-of-chain interrupt is generated.

Note
Setting this field in an IDLE state (for example, no normal/inject conversion is in process) has no effect. In this case, the MCR[ABORTCHAIN] field is reset immediately.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_AbortCurrentConv(ADC_Type *base)

This function is used to abort the conversion channel. 
Abort the current conversion and immediately start the conversion of the next channel of the chain. In the case of an abort operation, MSR[NSTART/JSTART] remains set if not in the last channel of the chain, and MCR[ABORT] is reset as soon as the channel is aborted. The end-of-conversion interrupt corresponds to the aborted channel is not generated. This behavior is true for normal or inject conversion modes. If the last channel of a chain is aborted, and the end-of-chain is reported, then an end-of-chain interrupt will be generated.

Note
This conversion can not abort while the self-test channel conversion is in process.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableConvInt(ADC_Type *base, uint32_t mask)

This function is used to enable the ADC end-of-conversion and end-of-chain interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the ADC end-of-conversion and end-of-chain interrupts, please refer to _adc_conv_int_enable for details. 







static inline void ADC_DisableConvInt(ADC_Type *base, uint32_t mask)

This function is used to disable the ADC end-of-conversion and end-of-chain interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the ADC end-of-conversion and end-of-chain interrupts, please refer to _adc_conv_int_enable for details. 







static inline uint32_t ADC_GetConvIntStatus(ADC_Type *base)

This function is used to get the ADC end-of-conversion and end-of-chain interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC end-of-conversion and end-of-chain interrupts status mask. 






static inline void ADC_ClearConvIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the ADC end-of-conversion and end-of-chain interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_conv_int_flag for details. 







static inline void ADC_EnableSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel end-of-conversion interrupt. 

Note
This function can only turn on the interrupt of a specific channel, if the interrupt occurs, the user also needs to turn on the global end-of-conversion interrupt by using function ADC_EnableConvInt


Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the end-of-conversion interrupt. 







static inline void ADC_DisableSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel end-of-conversion interrupt. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the end-of-conversion interrupt. 







static inline bool ADC_CheckSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to check whether the specific conversion channel’s end-of-conversion interrupt has been occured. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to check the end-of-conversion interrupt status.


Returns:
Channel end-of-conversion interrupt status flag of the specific channel.

true Channel end-of-conversion interrupt has been occured.
false Channel end-of-conversion interrupt has not been occured. 








static inline void ADC_ClearSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to clear specific channel end-of-conversion interrupt flag. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to clear the end-of-conversion interrupt flag. 







static inline void ADC_EnableDmaTransfer(ADC_Type *base)

This function is used to enable the DMA transfer function. 

Note
This function is a master switch used to control whether the data converted by the ADC is transmitted through DMA. If the user configures DMA to transmit the conversion data of the channel during the chain channel configuration process, then the main switch of the DMA transmission must be turned on, otherwise, data transmission cannot be performed.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_DisableDmaTransfer(ADC_Type *base)

This function is used to disable the DMA transfer function. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableSpecificConvChannelDmaTransfer(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s DMA transfer function. 

Note
This function can only turn on the DMA transfer of a specific channel, before using the DMA transfer, the user needs to turn on the global DMA transfer by using the function ADC_EnableDmaTransfer.


Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the DMA transfer function. 







static inline void ADC_DisableSpecificConvChannelDmaTransfer(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s DMA transfer function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the DMA transfer function. 







static inline void ADC_EnableSpecificConvChannelPresample(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s pre-sample function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the pre-sample function. 







static inline void ADC_DisableSpecificConvChannelPresample(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s pre-sample function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the pre-sample function. 







void ADC_SetAnalogWdgConfig(ADC_Type *base, const adc_wdg_config_t *config)

This function is used to configure the analog watchdog. 
The analog watchdogs are used to monitor the conversion result to see if it is within defined limits, specified by a higher and a lower threshold value. After the conversion of the selected channel, a comparison is performed between the converted value and the threshold values. If the converted value is outside the threshold values, then a corresponding threshold violation interrupt is generated.

Parameters:

base – ADC peripheral base address. 
config – Pointer to the analog watchdog configuration structure, please refer to adc_wdg_config_t for details. 







static inline void ADC_EnableSpecificConvChannelAnalogWdg(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s analog watchdog function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Conversion channel index to enable the analog watchdog function. 







static inline void ADC_DisableSpecificConvChannelAnalogWdg(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s analog watchdog function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Conversion channel index to disable the analog watchdog function. 







static inline bool ADC_CheckSpecificConvChannelOutofRange(ADC_Type *base, uint8_t channelIndex)

This function is used to check whether the specific conversion channel’s converted data is out of range. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to check the converted data out of range status.


Returns:
Converted data out of range status of the specific conversion channel.

true Channel converted data is out of range.
false Channel converted data is in range. 








static inline void ADC_ClearSpecificConvChannelOutofRange(ADC_Type *base, uint8_t channelIndex)

This function is used to clear the specific conversion channel’s converted data out-of-range flag. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to clear the converted data out of range flag. 







static inline void ADC_EnableWdgThresholdInt(ADC_Type *base, uint32_t mask)

This function is used to enable the analog watchdog threshold low or/and high interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the analog watchdog threshold low or/and high interrupts, please refer to _adc_wdg_threshold_int_enable for details. 







static inline void ADC_DisableWdgThresholdInt(ADC_Type *base, uint32_t mask)

This function is used to disable the analog watchdog threshold low or/and high interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the analog watchdog threshold low or/and high interrupts, please refer to _adc_wdg_threshold_int_enable for details. 







static inline uint32_t ADC_GetWdgThresholdIntStatus(ADC_Type *base)

This function is used to get the analog watchdog threshold interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
Analog watchdog threshold interrupts status mask. 






static inline void ADC_ClearWdgThresholdIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the analog watchdog threshold low or/and high interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_wdg_threshold_int_flag for details. 







bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config)

This function is used to do the calibration. 
The calibration is used to reduce or eliminate the various errors. In the calibration process, the calibration values for offset, gain, and capacitor mismatch are obtained. These calibration values (except gain calibration) are used in a result post-processing step to reduce or eliminate the various errors contribution effects. The gain calibration is used during the sample phase to define the additional charge to be loaded in order to compensate for the gain failure. Calibration must be performed after every power-up reset and whenever required in runtime operation. It is also recommended to run calibration if the operating conditions (particularly VrefH) change. Never apply functional reset during the calibration process. If applied, calibration must be rerun after exiting a reset condition; otherwise, the calibration-generated values and conversion results may be unspecified.

Note
This function executes a calibration sequence, it is recommended to run this sequence before using the ADC converter. The maximum clock frequency for the calibration is 40 MHz. Before calling this function, the user needs to ensure that the input clock is within 40MHz. The results of individual steps are also updated in the CALSTAT register (CALSTAT[STAT_n]). The result of the last failed step is dynamically updated in the same register.


Parameters:

base – ADC peripheral base address. 
config – Pointer to the calibration configuration structure, please refer to adc_calibration_config_t for details.


Returns:
Status whether calibration is running passed or failed.

true Calibration successful.
false Calibration unsuccessful. 








void ADC_SetUserOffsetAndGainConfig(ADC_Type *base, const adc_user_offset_gain_config_t *config)

This function is used to configure the user gain and offset. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the user offset and gain configuration structure, please refer to adc_user_offset_gain_config_t for details. 







void ADC_SetSelfTestConfig(ADC_Type *base, const adc_self_test_config_t *config)

This function is used to configure the ADC self-test. 
The self-test is used to check at regular intervals whether ADC is operating correctly. When self-test is enabled, ADC automatically checks its components and flags any errors it finds. The test can be enabled to check the supply voltage (VDD), reference voltage (VrefH), and calibrated values.

Note
Before calling this function, please ensure the functional conversion is one-shot conversion mode normal conversion type and the operating clock are equal to bus frequency. ADC self-test should be run with MCR[ADCLKSE] bit set to 1. Self-test with ADCLKSE bit set to 0 can give erroneous results.


Parameters:

base – ADC peripheral base address. 
config – Pointer to the self-test configuration structure, please refer to adc_self_test_config_t for details. 







void ADC_SetSelfTestWdgConfig(ADC_Type *base, const adc_self_test_wdg_config_t *config)

This function is used to configure the ADC self-test watchdog. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the self-test watchdog configuration structure, please refer to adc_self_test_wdg_config_t for details. 







void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result)

This function is used to get the test result for the last failed test. 

Parameters:

base – ADC peripheral base address. 
result – Points to a 16-bit signed variable, and it is used to store the test result for the last failing test. 







static inline uint16_t ADC_GetCalibrationStepsStatus(ADC_Type *base)

This function is used to get the status of the calibration steps. 

Note
The status of calibration steps (step 0 to step 12) is stored in the CALSTAT register, and only the lower 12 bits are available in the returned result.


Parameters:

base – ADC peripheral base address.


Returns:
ADC self-test interrupt status mask. 






static inline void ADC_EnableSelfTest(ADC_Type *base)

This function is used to enable the ADC self-test. 
Decides whether to enable the ADC self-test. The self-test test is enabled by setting STCR2[EN], this field must be set before starting normal conversion and should not be changed while the conversion is in process. This field should only be reset after the end-of-conversion of the last self-test channel has been received.

Note
ADC self-test should be run with MCR[ADCLKSE] bit set to 1. Self-test with ADCLKSE bit set to 0 can give erroneous results. In the case of Inject Conversion mode, test channel conversion is not performed. It is performed only during normal conversions.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_DisableSelfTest(ADC_Type *base)

This function is used to disable the ADC self-test. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID)

This function is used to enable the ADC self-test watchdog threshold for algorithm S step 0/1/2 and algorithm C. 
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 0; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 1; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 2; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm C; Other enumerations in adc_self_test_wdg_threshold_t have no use.

Parameters:

base – ADC peripheral base address. 
wdgID – Watchdog threshold index to enable, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_DisableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID)

This function is used to disable the ADC self-test watchdog threshold for algorithm S step 0/1/2 and algorithm C. 
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 0; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 1; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 2; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm C; Other enumerations in adc_self_test_wdg_threshold_t have no use.

Parameters:

base – ADC peripheral base address. 
wdgID – Watchdog threshold index to disable, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_EnableSelfTestWdgTimer(ADC_Type *base, adc_alg_type_t wdgTimerType)

This function is used to enable the ADC self-test watchdog timer for algorithm S or/and algorithm C. 
The user can pass kADC_SelfTestForAlgS as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm S; pass kADC_SelfTestForAlgC as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm C; pass kADC_SelfTestForAlgSAndC as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm S and C.

Parameters:

base – ADC peripheral base address. 
wdgTimerType – Watchdog timer type to enable, please refer to adc_alg_type_t for details. 







static inline void ADC_DisableSelfTestWdgTimer(ADC_Type *base, adc_alg_type_t wdgTimerType)

This function is used to disable the ADC self-test watchdog timer. 
The user can pass kADC_SelfTestForAlgS as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm S; pass kADC_SelfTestForAlgC as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm C; pass kADC_SelfTestForAlgSAndC as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm S and C.

Parameters:

base – ADC peripheral base address. 
wdgTimerType – Watchdog timer type to disable, please refer to adc_alg_type_t for details. 







static inline void ADC_SetSelfTestWdgTimerVal(ADC_Type *base, adc_wdg_timer_val_t wdgTimerVal)

This function is used to set the ADC self-test watchdog timer value. 

Parameters:

base – ADC peripheral base address. 
wdgTimerVal – Watchdog timer value, please refer to adc_wdg_timer_val_t for details. 







static inline uint16_t ADC_GetSelfTestChannelConvFailedData(ADC_Type *base, adc_self_test_wdg_threshold_t type)

This function is used to get the ADC self-test channel converted data when ERR_S0/ERR_S1_INTEGER/ ERR_S1_FRACTION/ERR_S2/ERR_C occurred. 

Note
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘type’ to get the converted data when ERR_S0 occurred; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘type’ to get the converted data when ERR_S1_INTEGER occurred; pass kADC_SelfTestWdgThresholdForAlgSStep1Fraction as parameter ‘type’ to get the converted data when ERR_S1_FRACTION occurred; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘type’ to get the converted data when ERR_S2 occurred; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘type’ to get the converted data when ERR_C occurred; Other enumerations in adc_self_test_wdg_threshold_t have no use.


Parameters:

base – ADC peripheral base address. 
type – Watchdog threshold index to get the ADC self-test channel converted data, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_EnableSelfTestInt(ADC_Type *base, uint32_t mask)

This function is used to enable the ADC self-test-related interrupts. 

Note
Watchdog timer feature is applicable only for scan operation mode and not for one-shot operation mode.


Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the ADC self-test related interrupts, please refer to _adc_self_test_int_enable for details. 







static inline void ADC_DisableSelfTestInt(ADC_Type *base, uint32_t mask)

This function is used to disable the ADC self-test interrupt. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the ADC self-test related interrupts, please refer to _adc_self_test_int_enable for details. 







static inline uint32_t ADC_GetSelfTestIntStatus(ADC_Type *base)

This function is used to get the ADC self-test interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC self-test related interrupts status mask. 






static inline void ADC_ClearSelfTestIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the ADC self-test interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_self_test_int_flag for details. 







bool ADC_GetChannelConvResult(ADC_Type *base, adc_conv_result_t *result, uint8_t channelIndex)

This function is used to get the specific ADC channel’s conversion result. 
CDR[VALID] indicates whether a new conversion is available, this field is automatically reset to 0 when the data is read. CDR[OVERW] Indicates whether the previous conversion data was overwritten without having been read, in which case the overwritten data is lost.

Parameters:

base – SAR ADC peripheral base address. 
result – Pointer to SAR ADC channels conversion result structure, please refer to adc_conv_result_t for details. 
channelIndex – Channel index to get the conversion result.


Returns:
Indicates whether the acquisition of the specific channel conversion result is successful or not.

true Obtaining the specific channel conversion result successfully, and the conversion result is stored in the input parameter result.
false Obtaining the specific channel conversion result failed. 








bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t *result)

This function is used to get the test channel converted data when algorithm S step 0, algorithm S step 2, or algorithm C step executes. 

Parameters:

base – ADC peripheral base address. 
result – Pointer to the SAR ADC self-test channel conversion result structure, please refer to adc_self_test_conv_result_t for details.


Returns:
Indicates whether the acquisition of the self-test channel conversion result is successful or not.

true Obtaining the self-test channel conversion result successfully, and the conversion result is stored in the input parameter ‘result’.
false Obtaining the self-test channel conversion result failed. 








bool ADC_GetSelfTestChannelConvDataForAlgSStep1(ADC_Type *base, adc_self_test_conv_result_t *result)

This function is used to get the test channel converted data when algorithm S step 1 executes. 

Parameters:

base – ADC peripheral base address. 
result – Pointer to the SAR ADC self-test channel conversion result structure, please refer to adc_self_test_conv_result_t for details.


Returns:
Indicates whether the acquisition of the self-test channel conversion result is successful or not.

true Obtaining the self-test channel conversion result successfully, and the conversion result is stored in the input parameter ‘result’.
false Obtaining the self-test channel conversion result failed. 








FSL_SAR_ADC_DRIVER_VERSION

SAR ADC driver version 2.3.0. 




enum _adc_conv_int_enable

This enumeration provides the mask for the ADC end-of-conversion and end-of-chain interrupts enabling. 
Values:


enumerator kADC_NormalConvChainEndIntEnable

Enable end of normal chain conversion interrupt. 




enumerator kADC_NormalConvEndIntEnable

Enable end of normal conversion interrupt. 




enumerator kADC_InjectConvChainEndIntEnable

Enable end of inject chain conversion interrupt. 




enumerator kADC_InjectConvEndIntEnable

Enable end of inject conversion interrupt. 






enum _adc_wdg_threshold_int_enable

This enumeration provides the mask for the ADC analog watchdog threshold interrupts enabling. 
Values:


enumerator kADC_wdg0LowThresholdIntEnable

Enable watchdog 0 low threshold interrupt. 




enumerator kADC_wdg0HighThresholdIntEnable

Enable watchdog 0 high threshold interrupt. 




enumerator kADC_wdg1LowThresholdIntEnable

Enable watchdog 1 low threshold interrupt. 




enumerator kADC_wdg1HighThresholdIntEnable

Enable watchdog 1 high threshold interrupt. 




enumerator kADC_wdg2LowThresholdIntEnable

Enable watchdog 2 low threshold interrupt. 




enumerator kADC_wdg2HighThresholdIntEnable

Enable watchdog 2 high threshold interrupt. 




enumerator kADC_wdg3LowThresholdIntEnable

Enable watchdog 3 low threshold interrupt. 




enumerator kADC_wdg3HighThresholdIntEnable

Enable watchdog 3 high threshold interrupt. 




enumerator kADC_wdg4LowThresholdIntEnable

Enable watchdog 4 low threshold interrupt. 




enumerator kADC_wdg4HighThresholdIntEnable

Enable watchdog 4 high threshold interrupt. 




enumerator kADC_wdg5LowThresholdIntEnable

Enable watchdog 5 low threshold interrupt. 




enumerator kADC_wdg5HighThresholdIntEnable

Enable watchdog 5 high threshold interrupt. 




enumerator kADC_wdg6LowThresholdIntEnable

Enable watchdog 6 low threshold interrupt. 




enumerator kADC_wdg6HighThresholdIntEnable

Enable watchdog 6 high threshold interrupt. 




enumerator kADC_wdg7LowThresholdIntEnable

Enable watchdog 7 low threshold interrupt. 




enumerator kADC_wdg7HighThresholdIntEnable

Enable watchdog 7 high threshold interrupt. 






enum _adc_self_test_int_enable

This enumeration provides the mask for the ADC self-test related interrupts enabling. 
Values:


enumerator kADC_AlgSStep0ErrIntEnable

Enable self-test algorithm S step0 error interrupt. 




enumerator kADC_AlgSStep1ErrIntEnable

Enable self-test algorithm S step1 error interrupt. 




enumerator kADC_AlgSStep2ErrIntEnable

Enable self-test algorithm S step2 error interrupt. 




enumerator kADC_AlgCErrIntEnable

Enable self-test algorithm C error interrupt. 




enumerator kADC_AlgSEndIntEnable

Enable self-test algorithm S end interrupt. 




enumerator kADC_AlgCEndIntEnable

Enable self-test algorithm C end interrupt. 




enumerator kADC_ConvEndIntEnable

Enable self-test conversion end interrupt. 




enumerator kADC_WdgTimeErrIntEnable

Enable watchdog time error interrupt. 




enumerator kADC_WdgSequenceErrIntEnable

Enable watchdog sequence error interrupt. 






enum _adc_conv_int_flag

This enumeration provides the mask for the ADC end-of-conversion and end-of-chain interrupts flag. 
Values:


enumerator kADC_NormalConvChainEndIntFlag

Indicates whether the end of normal chain conversion interrupt has occurred. 




enumerator kADC_NormalConvEndIntFlag

Indicates whether the end of conversion interrupt has occurred. 




enumerator kADC_InjectConvChainEndIntFlag

Indicates whether the end of inject chain conversion interrupt has occurred. 




enumerator kADC_InjectConvEndIntFlag

Indicates whether the end of inject conversion interrupt has occurred. 






enum _adc_wdg_threshold_int_flag

This enumeration provides the mask for the ADC analog watchdog threshold interrupts flag. 
Values:


enumerator kADC_wdg0LowThresholdIntFlag

Indicates whether the watchdog 0 low threshold interrupt has occurred. 




enumerator kADC_wdg0HighThresholdIntFlag

Indicates whether the watchdog 0 high threshold interrupt has occurred. 




enumerator kADC_wdg1LowThresholdIntFlag

Indicates whether the watchdog 1 low threshold interrupt has occurred. 




enumerator kADC_wdg1HighThresholdIntFlag

Indicates whether the watchdog 1 high threshold interrupt has occurred. 




enumerator kADC_wdg2LowThresholdIntFlag

Indicates whether the watchdog 2 low threshold interrupt has occurred. 




enumerator kADC_wdg2HighThresholdIntFlag

Indicates whether the watchdog 2 high threshold interrupt has occurred. 




enumerator kADC_wdg3LowThresholdIntFlag

Indicates whether the watchdog 3 low threshold interrupt has occurred. 




enumerator kADC_wdg3HighThresholdIntFlag

Indicates whether the watchdog 3 high threshold interrupt has occurred. 




enumerator kADC_wdg4LowThresholdIntFlag

Indicates whether the watchdog 4 low threshold interrupt has occurred. 




enumerator kADC_wdg4HighThresholdIntFlag

Indicates whether the watchdog 4 high threshold interrupt has occurred. 




enumerator kADC_wdg5LowThresholdIntFlag

Indicates whether the watchdog 5 low threshold interrupt has occurred. 




enumerator kADC_wdg5HighThresholdIntFlag

Indicates whether the watchdog 5 high threshold interrupt has occurred. 




enumerator kADC_wdg6LowThresholdIntFlag

Indicates whether the watchdog 6 low threshold interrupt has occurred. 




enumerator kADC_wdg6HighThresholdIntFlag

Indicates whether the watchdog 6 high threshold interrupt has occurred. 




enumerator kADC_wdg7LowThresholdIntFlag

Indicates whether the watchdog 7 low threshold interrupt has occurred. 




enumerator kADC_wdg7HighThresholdIntFlag

Indicates whether the watchdog 7 high threshold interrupt has occurred. 






enum _adc_self_test_int_flag

This enumeration provides the mask for the ADC self-test-related interrupts flag. 
Values:


enumerator kADC_AlgSStep0ErrIntFlag

Indicates whether the self-test algorithm S step0 error interrupt has occurred. 




enumerator kADC_AlgSStep1ErrIntFlag

Indicates whether the self-test algorithm S step1 error interrupt has occurred. 




enumerator kADC_AlgSStep2ErrIntFlag

Indicates whether the self-test algorithm S step2 error interrupt has occurred. 




enumerator kADC_AlgCErrIntFlag

Indicates whether the self-test algorithm C error interrupt has occurred. 




enumerator kADC_AlgSEndIntFlag

Indicates whether the algorithm S end interrupt has completed. 




enumerator kADC_AlgCEndIntFlag

Indicates whether the algorithm C end interrupt has completed. 




enumerator kADC_SelfTestConvEndIntFlag

Indicates whether the self-test end-of-conversion interrupt has completed. 




enumerator kADC_OverWriteErrIntFlag

Indicates whether the overwrite error interrupt has occurred. 




enumerator kADC_WdgTimeErrIntFlag

Indicates whether the watchdog time error interrupt has occurred. 




enumerator kADC_WdgSequenceErrIntFlag

Indicates whether the watchdog sequence error interrupt has occurred. 






enum _adc_ext_trig

This enumeration provides the selection of the ADC external trigger type. 
Values:


enumerator kADC_ExtTrigDisable

Normal trigger input does not start a conversion. 




enumerator kADC_ExtTrigFallingEdge

Normal trigger (falling edge) input starts a conversion. 




enumerator kADC_ExtTrigRisingEdge

Normal trigger (rising edge) input starts a conversion. 






enum _adc_state

This enumeration provides the selection of the ADC state. 
Values:


enumerator kADC_AdcIdle

Indicates the ADC is in the IDLE state. 




enumerator kADC_AdcPowerdown

Indicates the ADC is in the power-down state. 




enumerator kADC_AdcWait

Indicates the ADC is in the wait state. 




enumerator kADC_AdcBusyInCalibration

Indicates the ADC is in the calibration busy state. 




enumerator kADC_AdcSample

Indicates the ADC is in the sample state. 




enumerator kADC_AdcConv

Indicates the ADC is in the conversion state. 






enum _adc_conv_mode

This enumeration provides the selection of the ADC conversion mode, including normal conversion one-shot mode, normal conversion scan mode, and inject conversion one-shot mode. 
Values:


enumerator kADC_NormalConvOneShotMode

Normal conversion one-shot mode. 




enumerator kADC_NormalConvScanMode

Normal conversion scan mode. 




enumerator kADC_InjectConvOneShotMode

Inject conversion one-shot mode. 






enum _adc_clock_frequency

This enumeration provides the selection of the ADC operating clock frequency, including half-bus frequency and full bus frequency. 
Values:


enumerator kADC_HalfBusFrequency

Half of bus clock frequency. 




enumerator kADC_FullBusFrequency

Equal to bus clock frequency. 






enum _adc_conv_data_align

This enumeration provides the selection of the ADC conversion data alignment, including the right alignment and left alignment. 
Values:


enumerator kADC_ConvDataRightAlign

Conversion data is right aligned. 




enumerator kADC_ConvDataLeftAlign

Conversion data is left aligned. 






enum _adc_presample_voltage_src

This enumeration provides the selection of the ADC internal analog input voltage sources for pre-sample, including DVDD0P8/2, AVDD1P8/4, VREFL_1p8 and VREFH_1p8. 
Values:


enumerator kADC_PresampleVoltageSrcVREL

Use VREL as pre-sample voltage source. 




enumerator kADC_PresampleVoltageSrcVREH

Use VREH as pre-sample voltage source. 






enum _adc_dma_request_clear_src

This enumeration provides the selection of the DMA request clear sources, including clear by acknowledgment from the DMA controller and clear on a read of the data register. 
Values:


enumerator kADC_DMARequestClearByAck

DMA request cleared by acknowledgment from DMA controller. 




enumerator kADC_DMARequestClearOnRead

DMA request cleared on a read of the data register. 






enum _adc_average_sample_numbers

This enumeration provides the selection of the ADC calibration averaging sample numbers, including 16, 32, 128, and 512 averaging samples. 
Values:


enumerator kADC_AverageSampleNumbers16

Use 16 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers32

Use 32 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers128

Use 128 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers512

Use 512 averaging samples during calibration. 






enum _adc_sample_time

This enumeration provides the selection of the ADC sample time of calibration conversions, including 22, 8, 16 and 32 cycles of ADC_CLK. 
Values:


enumerator kADC_SampleTime22

Use 22 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime8

Use 8 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime16

Use 16 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime32

Use 32 cycles of ADC_CLK as sample time of calibration conversions. 






enum _adc_wdg_threshold_int

This enumeration provides the selection of the ADC analog watchdog threshold low and high interrupt enable. 
Values:


enumerator kADC_LowHighThresholdIntDisable

Enable the ADC analog watchdog low and high threshold interrupts. 




enumerator kADC_LowThresholdIntEnable

Enable the ADC analog watchdog low threshold interrupt. 




enumerator kADC_HighThresholdIntEnable

Enable the ADC analog watchdog high threshold interrupt. 




enumerator kADC_LowHighThresholdIntEnable

Enable the ADC analog watchdog low and high threshold interrupts. 






enum _adc_alg_type

This enumeration provides the selection of the ADC self-test algorithm type, including algorithm S, algorithm C and algorithm S and C. 

Note
The meaning of enumeration member ‘kADC_SelfTestForAlgSAndC’ in different conversion modes is different, in the one-shot conversion mode, it means executing algorithm S; in the scan conversion mode, it means executing algorithm S and C. 

Values:


enumerator kADC_SelfTestForAlgS

Use algorithm S for self-test. 




enumerator kADC_SelfTestForAlgC

Use algorithm C for self-test. 




enumerator kADC_SelfTestForAlgSAndC

Use algorithm S for one-shot conversion mode self-test, use algorithm S and algorithm C for scan conversion mode self-test. 






enum _adc_self_test_wdg_threshold

This enumeration provides the selection of the ADC self-test watchdog thresholds for algorithm S step 0 - 2, and watchdog thresholds for algorithm C step 0 and step x (x = 1 - 11). 
Values:


enumerator kADC_SelfTestWdgThresholdForAlgSStep0

Self-test watchdog threshold for the algorithm S step 0. 




enumerator kADC_SelfTestWdgThresholdForAlgSStep1

Self-test watchdog threshold for the algorithm S step 1 fraction part. 




enumerator kADC_SelfTestWdgThresholdForAlgSStep2

Self-test watchdog threshold for the algorithm S step 2. 




enumerator kADC_SelfTestWdgThresholdForAlgCStep0

Self-test watchdog threshold for the algorithm C step 0. 




enumerator kADC_SelfTestWdgThresholdForAlgCStepx

Self-test watchdog threshold for the algorithm C step x. 






enum _adc_wdg_timer_val

This enumeration provides the selection of the ADC self-test watchdog timer value, including 0.1ms, 0.5ms, 1ms, 2ms, 5ms, 10ms, 20ms and 50ms. 
Values:


enumerator kADC_SelfTestWdgTimerVal0

0.1ms ((0008h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal1

0.5ms ((0027h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal2

1ms ((004Eh × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal3

2ms ((009Ch × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal4

5ms ((0187h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal5

10ms ((030Dh × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal6

20ms ((061Ah × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal7

50ms ((0F42h × Prescaler) cycles at 80 MHz). 






typedef enum _adc_ext_trig adc_ext_trig_t

This enumeration provides the selection of the ADC external trigger type. 




typedef enum _adc_state adc_state_t

This enumeration provides the selection of the ADC state. 




typedef enum _adc_conv_mode adc_conv_mode_t

This enumeration provides the selection of the ADC conversion mode, including normal conversion one-shot mode, normal conversion scan mode, and inject conversion one-shot mode. 




typedef enum _adc_clock_frequency adc_clock_frequency_t

This enumeration provides the selection of the ADC operating clock frequency, including half-bus frequency and full bus frequency. 




typedef enum _adc_conv_data_align adc_conv_data_align_t

This enumeration provides the selection of the ADC conversion data alignment, including the right alignment and left alignment. 




typedef enum _adc_presample_voltage_src adc_presample_voltage_src_t

This enumeration provides the selection of the ADC internal analog input voltage sources for pre-sample, including DVDD0P8/2, AVDD1P8/4, VREFL_1p8 and VREFH_1p8. 




typedef enum _adc_dma_request_clear_src adc_dma_request_clear_src_t

This enumeration provides the selection of the DMA request clear sources, including clear by acknowledgment from the DMA controller and clear on a read of the data register. 




typedef enum _adc_average_sample_numbers adc_average_sample_numbers_t

This enumeration provides the selection of the ADC calibration averaging sample numbers, including 16, 32, 128, and 512 averaging samples. 




typedef enum _adc_sample_time adc_sample_time_t

This enumeration provides the selection of the ADC sample time of calibration conversions, including 22, 8, 16 and 32 cycles of ADC_CLK. 




typedef enum _adc_wdg_threshold_int adc_wdg_threshold_int_t

This enumeration provides the selection of the ADC analog watchdog threshold low and high interrupt enable. 




typedef enum _adc_alg_type adc_alg_type_t

This enumeration provides the selection of the ADC self-test algorithm type, including algorithm S, algorithm C and algorithm S and C. 

Note
The meaning of enumeration member ‘kADC_SelfTestForAlgSAndC’ in different conversion modes is different, in the one-shot conversion mode, it means executing algorithm S; in the scan conversion mode, it means executing algorithm S and C. 





typedef enum _adc_self_test_wdg_threshold adc_self_test_wdg_threshold_t

This enumeration provides the selection of the ADC self-test watchdog thresholds for algorithm S step 0 - 2, and watchdog thresholds for algorithm C step 0 and step x (x = 1 - 11). 




typedef enum _adc_wdg_timer_val adc_wdg_timer_val_t

This enumeration provides the selection of the ADC self-test watchdog timer value, including 0.1ms, 0.5ms, 1ms, 2ms, 5ms, 10ms, 20ms and 50ms. 




typedef struct _adc_config adc_config_t

This structure is used to configure the ADC module. 




typedef struct _adc_channel_config adc_channel_config_t

This structure is used to configure the ADC conversion channel. 




typedef struct _adc_chain_config adc_chain_config_t

This structure is used to configure the ADC conversion chain. 




typedef struct _adc_wdg_config adc_wdg_config_t

This structure is used to configure the ADC analog watchdog. 




typedef struct _adc_calibration_config adc_calibration_config_t

This structure is used to configure the ADC calibration. 




typedef struct _adc_user_offset_gain_config adc_user_offset_gain_config_t

This structure is used to configure the ADC user offset and gain. 




typedef struct _adc_self_test_config adc_self_test_config_t

This structure is used to configure the ADC self-test. 




typedef struct _adc_self_test_wdg_config adc_self_test_wdg_config_t

This structure is used to configure the ADC self-test watchdog for algorithm steps. 

Note
The algorithm S step 2 only has the ‘LowThrsholdVal’. 





typedef struct _adc_conv_result adc_conv_result_t

This structure is used to save the result information when obtaining the conversion result. 




typedef struct _adc_self_test_conv_result adc_self_test_conv_result_t

This structure is used to save the result information when obtaining the self-test channel conversion result. 

Note
The member ‘convData’ is used to store self-test channel conversion results. Only when executing step 1 of algorithm S, member ‘convDataFraction’ will be used to store the fractional part data. When executing other algorithms, this member will not be used. 





ADC_GROUP_COUNTS





ADC_THRESHOLD_COUNTS





ADC_SELF_TEST_THRESHOLD_COUNTS





GET_REGINDEX(channelIndex)





GET_BITINDEX(channelIndex)





REGISTER_READWRITE(baseRegister, shiftIndex)





REGISTER_READONLY(baseRegister, shiftIndex)





NCMR_IO(base, registerIndex)





JCMR_IO(base, registerIndex)





PSR_IO(base, registerIndex)





DMAR_IO(base, registerIndex)





CWSELR_IO(base, registerIndex)





CWENR_IO(base, registerIndex)





CIMR_IO(base, registerIndex)





CEOCFR_IO(base, registerIndex)





AWORR_IO(base, registerIndex)





STAWR_IO(base, registerIndex)





CEOCFR_I(base, registerIndex)





AWORR_I(base, registerIndex)





CDR_I(base, registerIndex)





WDG_SELECT_MASK(shiftIndex)





WDG_SELECT_SHIFT(shiftIndex)





WDG_SELECT(val, shiftIndex)





ADC_CDR_VALID_MASK





ADC_CDR_VALID_SHIFT





ADC_CDR_OVERW_MASK





ADC_CDR_OVERW_SHIFT





ADC_CDR_RESULT_MASK





ADC_CDR_RESULT_SHIFT





ADC_CDR_CDATA_MASK





ADC_CDR_CDATA_SHIFT





ADC_STAWR_AWDE_MASK





ADC_STAWR_THRL_MASK





ADC_STAWR_THRL_SHIFT





ADC_STAWR_THRL(val)





ADC_STAWR_THRH_MASK





ADC_STAWR_THRH_SHIFT





ADC_STAWR_THRH(val)





ADC_CALSTAT_MAX





ADC_CALSTAT_SIGN





struct _adc_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC module. 

Public Members


bool enableAutoClockOff

Decides whether to enable the ADC auto clock-off function, when set to true, the internal ADC clock is automatically switched off during IDLE mode to reduce power consumption (without going into power-down mode). 




bool enableOverWrite

Decides whether to enable the latest conversion to overwrite the current value in the data registers. 




bool enableConvertPresampleVal

Decides whether to convert the pre-sampled value, if enabled, pre-sampling is followed by the conversion, sampling will be bypassed and conversion of the pre-sampled data will be done. 




adc_ext_trig_t extTrig

Specifies whether the normal trigger (with trigger type) input starts a conversion. 




adc_conv_data_align_t convDataAlign

Selects the conversion data alignment. 




adc_clock_frequency_t clockFrequency

Selects the ADC clock frequency. 




adc_dma_request_clear_src_t dmaRequestClearSrc

Selects DMA request clear source. 




adc_presample_voltage_src_t presampleVoltageSrc[1]

Selects analog input voltages for group 0 (corresponding to channel 0 to channel 31) and group 32 (corresponding to channel 32 to channel 63) pre-sampling. 




uint8_t samplePhaseDuration[1]

Sets the sample phase duration in terms of the ADC controller clock for group 0 (corresponding to channel 0 to channel 31) and group 32 (corresponding to channel 32 to channel 63), the minimum acceptable value is 8, configuring to a value lower than 8 sets the sample period to 8 cycles. 







struct _adc_channel_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC conversion channel. 

Public Members


uint8_t channelIndex

Sets the conversion channel index. 




bool enableInt

Decides Whether to enable the interrupt function of the current conversion channel. 




bool enablePresample

Decides whether to enable the pre-sample function of the current conversion channel. 




bool enableDmaTransfer

Decides whether to enable the DMA transfer function of the current conversion channel. 




bool enableWdg

Decides whether to enable the analog watchdog function of the current conversion channel. 




uint8_t wdgIndex

Indicates which analog watchdog to provide the low and high threshold value. 







struct _adc_chain_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC conversion chain. 

Public Members


adc_conv_mode_t convMode

Selects conversion mode. 




bool enableGlobalChannelConvEndInt

Global control function to determine whether to enable the interrupt function of conversion channels. 




bool enableChainConvEndInt

Decides whether to enable the current chain end-of-conversion interrupt. 




uint8_t channelCount

Indicates the channel counts. 




adc_channel_config_t *channelConfig

Chain channels configuration. 







struct _adc_wdg_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC analog watchdog. 

Public Members


uint8_t wdgIndex

Indicates the analog watchdog index 




adc_wdg_threshold_int_t wdgThresholdInt

Selects watchdog threshold low or/and high interrupt to enable/disable. 




uint16_t lowThresholdVal

Sets the ADC analog watchdog low threshold value. 




uint16_t highThresholdVal

Sets the ADC analog watchdog high threshold value. 







struct _adc_calibration_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC calibration. 

Public Members


bool enableAverage

Decides whether to enable averaging of calibration time. 




adc_sample_time_t sampleTime

Selects sample time of calibration conversions. 




adc_average_sample_numbers_t averageSampleNumbers

Selects calibration averaging sample numbers. 







struct _adc_user_offset_gain_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC user offset and gain. 

Public Members


int8_t userOffset

Sets user defined gain value. 




int16_t userGain

Sets user defined offset value. 







struct _adc_self_test_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC self-test. 

Public Members


adc_alg_type_t algType

Selects the self-test algorithm. 




uint8_t algSteps

Sets the self-test algorithm steps, it should be programmed to zero in scan mode. 




uint8_t algSSamplePhaseDuration

Sets the self-test algorithm S conversion sampling phase duration. 




uint8_t algCSamplePhaseDuration

Sets the self-test algorithm C conversion sampling phase duration. 




uint8_t baudRate

Sets the baud rate for the selected algorithm in scan mode, must write to this field before enabling a self-test channel. 







struct _adc_self_test_wdg_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC self-test watchdog for algorithm steps. 

Note
The algorithm S step 2 only has the ‘LowThrsholdVal’. 


Public Members


adc_self_test_wdg_threshold_t wdgThresholdId

Indicates the self-test watchdog index 




uint16_t lowThrsholdVal

Sets the self-test watchdog low threshold value. 




uint16_t highThrsholdVal

Sets the self-test watchdog high threshold value. 







struct _adc_conv_result


#include <fsl_sar_adc.h>
This structure is used to save the result information when obtaining the conversion result. 

Public Members


bool overWrittenFlag

Indicates when conversion data was overwritten by a newer result, the new data is written or discarded according to MCR[OWREN]. 




uint8_t convMode

Indicates the mode of conversion for the corresponding channel. 




uint16_t convData

Stores the conversion data corresponding to the internal channel. 







struct _adc_self_test_conv_result


#include <fsl_sar_adc.h>
This structure is used to save the result information when obtaining the self-test channel conversion result. 

Note
The member ‘convData’ is used to store self-test channel conversion results. Only when executing step 1 of algorithm S, member ‘convDataFraction’ will be used to store the fractional part data. When executing other algorithms, this member will not be used. 


Public Members


bool overWrittenFlag

Indicates when conversion data is overwritten by a newer result. 




uint16_t convData

Stores the conversion data corresponding to the internal self-test channel. 




uint16_t convDataFraction

This field is only used to store the fractional part conversion result. 







SEMA42: Hardware Semaphores Driver#


FSL_SEMA42_DRIVER_VERSION

SEMA42 driver version. 





SEMA42 status return codes. 
Values:


enumerator kStatus_SEMA42_Busy

SEMA42 gate has been locked by other processor. 




enumerator kStatus_SEMA42_Reseting

SEMA42 gate reseting is ongoing. 






enum _sema42_gate_status

SEMA42 gate lock status. 
Values:


enumerator kSEMA42_Unlocked

The gate is unlocked. 




enumerator kSEMA42_LockedByProc0

The gate is locked by processor 0. 




enumerator kSEMA42_LockedByProc1

The gate is locked by processor 1. 




enumerator kSEMA42_LockedByProc2

The gate is locked by processor 2. 




enumerator kSEMA42_LockedByProc3

The gate is locked by processor 3. 




enumerator kSEMA42_LockedByProc4

The gate is locked by processor 4. 




enumerator kSEMA42_LockedByProc5

The gate is locked by processor 5. 




enumerator kSEMA42_LockedByProc6

The gate is locked by processor 6. 




enumerator kSEMA42_LockedByProc7

The gate is locked by processor 7. 




enumerator kSEMA42_LockedByProc8

The gate is locked by processor 8. 




enumerator kSEMA42_LockedByProc9

The gate is locked by processor 9. 




enumerator kSEMA42_LockedByProc10

The gate is locked by processor 10. 




enumerator kSEMA42_LockedByProc11

The gate is locked by processor 11. 




enumerator kSEMA42_LockedByProc12

The gate is locked by processor 12. 




enumerator kSEMA42_LockedByProc13

The gate is locked by processor 13. 




enumerator kSEMA42_LockedByProc14

The gate is locked by processor 14. 






typedef enum _sema42_gate_status sema42_gate_status_t

SEMA42 gate lock status. 




void SEMA42_Init(SEMA42_Type *base)

Initializes the SEMA42 module. 
This function initializes the SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA42_ResetGate or SEMA42_ResetAllGates function.

Parameters:

base – SEMA42 peripheral base address. 







void SEMA42_Deinit(SEMA42_Type *base)

De-initializes the SEMA42 module. 
This function de-initializes the SEMA42 module. It only disables the clock.

Parameters:

base – SEMA42 peripheral base address. 







status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)

Tries to lock the SEMA42 gate. 
This function tries to lock the specific SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to lock. 
procNum – Current processor number.


Return values:

kStatus_Success – Lock the sema42 gate successfully. 
kStatus_SEMA42_Busy – Sema42 gate has been locked by another processor. 







status_t SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)

Locks the SEMA42 gate. 
This function locks the specific SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.
If SEMA42_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to lock. 
procNum – Current processor number.


Return values:

kStatus_Success – The gate was successfully locked. 
kStatus_Timeout – Timeout occurred while waiting for the gate to be unlocked. 


Returns:
status_t 






static inline void SEMA42_Unlock(SEMA42_Type *base, uint8_t gateNum)

Unlocks the SEMA42 gate. 
This function unlocks the specific SEMA42 gate. It only writes unlock value to the SEMA42 gate register. However, it does not check whether the SEMA42 gate is locked by the current processor or not. As a result, if the SEMA42 gate is not locked by the current processor, this function has no effect.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to unlock. 







static inline sema42_gate_status_t SEMA42_GetGateStatus(SEMA42_Type *base, uint8_t gateNum)

Gets the status of the SEMA42 gate. 
This function checks the lock status of a specific SEMA42 gate.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number.


Returns:
status Current status. 






status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum)

Resets the SEMA42 gate to an unlocked status. 
This function resets a SEMA42 gate to an unlocked status.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number.


Return values:

kStatus_Success – SEMA42 gate is reset successfully. 
kStatus_SEMA42_Reseting – Some other reset process is ongoing. 







static inline status_t SEMA42_ResetAllGates(SEMA42_Type *base)

Resets all SEMA42 gates to an unlocked status. 
This function resets all SEMA42 gate to an unlocked status.

Parameters:

base – SEMA42 peripheral base address.


Return values:

kStatus_Success – SEMA42 is reset successfully. 
kStatus_SEMA42_Reseting – Some other reset process is ongoing. 







SEMA42_GATE_NUM_RESET_ALL

The number to reset all SEMA42 gates. 




SEMA42_GATEn(base, n)

SEMA42 gate n register address. 
The SEMA42 gates are sorted in the order 3, 2, 1, 0, 7, 6, 5, 4, … not in the order 0, 1, 2, 3, 4, 5, 6, 7, … The macro SEMA42_GATEn gets the SEMA42 gate based on the gate index.
The input gate index is XOR’ed with 3U: 0 ^ 3 = 3 1 ^ 3 = 2 2 ^ 3 = 1 3 ^ 3 = 0 4 ^ 3 = 7 5 ^ 3 = 6 6 ^ 3 = 5 7 ^ 3 = 4 … 




SEMA42_BUSY_POLL_COUNT

Maximum polling iterations for SEMA42 waiting loops. 
This parameter defines the maximum number of iterations for any polling loop in the SEMA42 driver code before timing out and returning an error.
It applies to all waiting loops in SEMA42 driver, such as waiting for a gate to be unlocked, waiting for a reset to complete, or waiting for a resource to become available.
This is a count of loop iterations, not a time-based value.
If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if hardware doesn’t respond or if a resource is never released. 




SINC: SINC Filter#


void SINC_Init(SINC_Type *base, const sinc_config_t *config)

Initialize selected SINC instance, including clock options and channel options. 

Parameters:

base – SINC peripheral base address. 
config – The pointer to sinc_config_t structure. 







void SINC_Deinit(SINC_Type *base)

De-initialize selected SINC instance. 

Parameters:

base – SINC peripheral base address. 







void SINC_GetDefaultConfig(sinc_config_t *config)

Get default configuration. 
config->clockPreDivider = kSINC_ClkPrescale1;
config->modClkDivider   = 2UL;
config->disableModClk0Output = false;
config->disableModClk1Output = false;
config->disableModClk2Output = false;

config->channelsConfigArray[4] = {NULL, NULL, NULL, NULL};

config->disableDozeMode      = false;
config->enableMaster         = false;



Parameters:

config – The pointer to sinc_config_t structure, must not be NULL. 







static inline void SINC_EnableMaster(SINC_Type *base, bool enable)

Enable/disable all function blocks enabled in their respective registers. 

Parameters:

base – SINC peripheral base address. 
enable – Used to enable/disable all function blocks:

true Enable all function blocks, please note that clock must be configured previously;
false Disable all function blocks. 









static inline void SINC_DoSoftwareReset(SINC_Type *base)

Reset all function blocks(except for the clock blocks), interrupt statuses. 

Parameters:

base – SINC peripheral base address. 







static inline void SINC_DisableDozeMode(SINC_Type *base, bool disable)

Disable/enable SINC module when the chip enters Doze or Stop mode. 

Parameters:

base – SINC peripheral base address. 
disable – Used to control if module functional when the chip enters Doze and Stop mode:

true Disable SINC when the chip enters Doze or Stop mode;
false Enable SINC when the chip enters Doze or stop mode. 









static inline bool SINC_CheckModulatorClockReady(SINC_Type *base, uint32_t modClkMasks)

Check whether selected modulator clocks are ready. 

Note
The result of this APIs means all selected modulator clocks are (not) ready.


Parameters:

base – SINC peripheral base address. 
modClkMasks – The mask of modulator clocks, please refer to _sinc_modulator_clock.


Return values:

true – The input mask of modulator clocks are ready. 
false – The input mask of modulator clocks are not ready. 







static inline void SINC_DisableModulatorClockOutput(SINC_Type *base, uint32_t modClkMasks, bool disable)

Disable/enable modulator clocks’ output. 

Note
By default, modulator clock’s output is enabled.


Parameters:

base – SINC peripheral base address. 
modClkMasks – The mask of modulator clocks, please refer to _sinc_modulator_clock. 
disable – Used to enable/disable clock output:

true Disable modulator clocks’ output;
false Enable modulator clocks’ output. 









static inline void SINC_SetClkPrescale(SINC_Type *base, sinc_clock_prescale_t clkPrescale)

Set the clock divider ratio for the modulator clock. 

Parameters:

base – SINC peripheral base address. 
clkPrescale – Clock prescale value, please refer to sinc_clock_prescale_t. 







static inline void SINC_SetModulatorClockDivider(SINC_Type *base, uint32_t modClkDivider)

Set modulator clock divider value. 

Note
IMCLK0 = PRE_CLK / modClkDivider, the minimum clock divider ration is 2.


Parameters:

base – SINC peripheral base address. 
modClkDivider – Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output, write an even value to modClkDivider . 







void SINC_SetChannelConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_config_t *chConfig)

Set channel configurations, including input options, conversion options and protection options. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
chConfig – Pointer to sinc_channel_config_t structure, must not be NULL. 







void SINC_SetChannelInputOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_input_option_t *chInputOption)

Set channel input options, including input bit format, input bit source, input bit delay, input clock source, input clock edge. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
chInputOption – Pointer to sinc_channel_input_option_t structure, must not be NULL. 







void SINC_SetChannelConversionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_conv_option_t *chConvOption)

Set channel conversion options, including conversion mode, trigger source, and primary filter settings. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
chConvOption – Pointer to sinc_channel_conv_option_t structure, must not be NULL. 







void SINC_SetChannelProtectionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_protection_option_t *chProtection)

Set channel protection options, including limit check, short-circuit detector, clock-absence detector, and zero-crossing detector. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
chProtection – Pointer to sinc_channel_protection_option_t, must not be NULL. 







static inline uint32_t SINC_ReadChannelResultData(SINC_Type *base, sinc_channel_id_t chId)

Read selected channel’s result data. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t.


Returns:
Result data of the selected channel, 24 bits width. 






static inline void SINC_EnableChannelFIFO(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable FIFO transfers for the primary filter. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable channl FIFO:

true Enable channel FIFO.
false Disable channle FIFO. 









static inline void SINC_SetChannelFifoWatermark(SINC_Type *base, sinc_channel_id_t chId, uint8_t fifoWaterMark)

Set the FIFO watermark. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
fifoWaterMark – Specify the fifo watermark, range from 0 to 15. 







static inline void SINC_EnableChannel(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable selected channel:

true Enable selected channel;
false Disable selected channel. 









static inline void SINC_EnableChannelPrimaryDma(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel’s primary DMA transfers when the channel’s FIFO exceeds its watermark. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable primary DMA :

true Enable primary DMA;
false Disable primary DMA. 









static inline void SINC_SetChannelAltDmaSource(SINC_Type *base, sinc_channel_id_t chId, sinc_alternate_dma_source_t altDmaSource)

Set selected channel’s alternate DMA source selection. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
altDmaSource – Specify the trigger source for alternate DMA, please refer to sinc_alternate_dma_source_t. 







static inline void SINC_SetChannelResultDataFormat(SINC_Type *base, sinc_channel_id_t chId, sinc_result_data_format_t dataFormat)

Set selected channel’s result data format. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
dataFormat – Specify the result data format, please refer to sinc_result_data_format_t. 







static inline uint8_t SINC_GetChannelFifoCount(SINC_Type *base, sinc_channel_id_t chId)

Get the number of remaining data entries in the FIFO. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t.


Returns:
The number of remaining data entries in the FIFO. 






static inline bool SINC_CheckChannelResultDataReady(SINC_Type *base, sinc_channel_id_t chId)

Check whether the data in selected channel’s result data register is stable when FIFO is disabled. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Data in selected channel’s result data regiter is stable. 
false – Data in selected channel’s result data register is not stable. 







static inline bool SINC_CheckChannelFifoEmpty(SINC_Type *base, sinc_channel_id_t chId)

Check whether selected channel’s FIFO is empty. 

Parameters:

base – SINC peripheral base address. 
chId – The id of sinc channel to check.


Return values:

true – Selected channel’s FIFO is empty. 
false – Selected channel’s FIFO is not empty. 







static inline void SINC_AffirmChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)

Trigger selected channel’s conversion. 

Parameters:

base – SINC peripheral base address. 
chMask – The mask of channels to trigger. 







static inline void SINC_NegateChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)

Negate the trigger of selected channel. 

Parameters:

base – SINC peripheral base address. 
chMask – The mask of channels. 







static inline void SINC_SetChannelConversionMode(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_mode_t mode)

Set selected channel’s conversion mode. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
mode – The conversion mode to set, please refer to sinc_conv_mode_t. 







static inline void SINC_SetChannelTriggerSource(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_trigger_source_t triggerSource)

Set selected channel’s trigger source. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
triggerSource – Trigger source to set, please refer to sinc_conv_trigger_source_t. 







static inline void SINC_SetChannelMultipurposeData(SINC_Type *base, sinc_channel_id_t chId, uint32_t data)

Set multipurpose data to selected channel. 

Note
If input bit format is set as ManchesterCode, multipurpose data indicates the Manchester decoder threshold value and is 11 bits width; if input bit format is set as parallel, multipurpose data indicates the parallel 16-bit data and is 16 bits width; if input bit format is set as serial, multipurpose data indicates the serial data and is 32 bits width.


Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
data – Multipurpose data to set. 







static inline void SINC_SetChannelPfOrder(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_order_t pfOrder)

Set selected channel’s PF order. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pfOrder – Primary filter order to set, please refer to sinc_primary_filter_order_t







static inline void SINC_SetChannelPfOsr(SINC_Type *base, sinc_channel_id_t chId, uint16_t pfOsr)

Set selected channel’s PF over sample rate. 

Note
If PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047.


Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pfOsr – Control the channel’s PF OSR, the minimum permissible value is 3, low value produce unpredictable result, the maximum permissible value depend on PF order and the desired data format. 







static inline void SINC_SetChannelPfHpfAlphaCoeff(SINC_Type *base, sinc_channel_id_t chId, sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff)

set selected channel’s HPF DC remover Alpha coefficient. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pfHpfAlphaCoeff – Specify the HPF alpha coefficient or disable HPF as described in sin_primary_filter_hpf_alpha_coeff_t. 







static inline void SINC_SetChannelPfShiftConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_shift_direction_t pfShiftDirection, uint8_t pfShiftBitsNum)

Set the value that shifts the PF data for the correct 24-bit precision. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pfShiftDirection – Specify the PF shift direction, including right and left. 
pfShiftBitsNum – Specify the PF shift value, range from 0 to 15. 







static inline void SINC_SetChannelPfBiasConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_bias_sign_t pfBiasSign, uint32_t pfBiasValue)

Set the bias offset for the selected channel’s PF. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pfBiasSign – Specify the bias sign, please refer to sinc_primary_filter_bias_sign_t for details. 
pfBiasValue – The bias value to subtracted from the output of PF shift block, range from 0 to 0x7FFFFFUL. 







static inline void SINC_EnableChannelPrimaryFilter(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel’s primary filter. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable primary filter:

true Enable channel’s PF;
false Disable channel’s PF. 









static inline bool SINC_CheckChannelParallelSerialDataReady(SINC_Type *base, sinc_channel_id_t chId)

Check whether selected channel’s multipurpose data is ready to write parallel or serial data. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Selected channel’s multipurpose data is ready to write parallel or serial data. 
false – Selected channel’s multipurpose data is not ready to write parallel or serial data. 







static inline bool SINC_CheckChannelPrimaryCICSaturation(SINC_Type *base, sinc_channel_id_t chId)

Check whether primary CIC filter saturation occurred. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Selected channel’s primary CIC filter saturation occurred. 
false – Selected channel’s primary CIC filter saturation did not occurred. 







static inline bool SINC_CheckChannelHPFSaturation(SINC_Type *base, sinc_channel_id_t chId)

Check whether HPF saturation occurred. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Selected channel’s HPF saturation occurred. 
false – Selected channel’s HPF saturation did not occurred. 







static inline bool SINC_CheckChannelShiftSaturation(SINC_Type *base, sinc_channel_id_t chId)

Check whether Shift saturation occurred. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Selected channel’s shift saturation occurred. 
false – Selected channel’s shift saturation did not occurred. 







static inline bool SINC_CheckChannelBiasSaturation(SINC_Type *base, sinc_channel_id_t chId)

Check whether bias saturation occurred. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details.


Return values:

true – Selected channel’s bias saturation occurred. 
false – Selected channel’s bias saturation did not occurred. 







uint8_t SINC_GetChannelConversionCount(SINC_Type *base, sinc_channel_id_t chId)

Get selected channel’s number of conversions. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, refer to sinc_channel_id_t for details. 


Returns:
uint8_t Selected channel’s number of conversions. 






static inline bool SINC_CheckChannelConvProgress(SINC_Type *base, sinc_channel_id_t chId)

Check whether the selected channel is in conversion. 

Parameters:

base – SINC peripheral base address. 
chId – The id of sinc channel to check.


Return values:

false – Selected channel conversion not in progress. 
true – Selected channel conversion in progress. 







static inline bool SINC_CheckChannelReadyForConv(SINC_Type *base, sinc_channel_id_t chId)

Check whether the selected channel is ready for conversion. 

Parameters:

base – SINC peripheral base address. 
chId – The id of sinc channel to check.


Return values:

true – Selected channel is ready for conversion. 
false – Selected channel is not ready for conversion. 







static inline void SINC_SetChannelLowLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t lowLimitThreshold)

Set selected channel’s low-limit threshold value. 

Note
When the data exceeds the low-limit threshold value, a low-limit event occurs, and the limit threshold format is determines by channel’s result data format sinc_result_data_format_t.


Note
Low limit value must lower than high limit value, otherwise the low-limit threshold does not work.


Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
lowLimitThreshold – Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL. 







static inline void SINC_SetChannelHighLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t highLimitThreshold)

Set selected channel’s high-limit threshold value. 

Note
When the data exceeds the high-limit threshold value, a high-limit event occurs, and the limit threshold format is determines by channel’s result data format sinc_result_data_format_t.


Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
highLimitThreshold – Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL. 







static inline void SINC_SetChannelLimitDetectorMode(SINC_Type *base, sinc_channel_id_t chId, sinc_limit_detector_mode_t mode)

Set selected channel’s limit detector mode. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
mode – Specify the mode of limit detector, please refer to sinc_limit_detector_mode_t. 







static inline void SINC_EnableChannelHighLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel’s high limit break signal. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable high limit break signal:

true Enable the automatic assertion of the BREAK_HIGH signal when SINC detects a high-limit event on the selected channel.
false Disable high limit break signal. 









static inline void SINC_EnableChannelWindowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel’s window limit break signal. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable window limit break signal:

true Enable the automatic assertion of the BREAK_WIN signal when SINC detects a window-limit event on the selected channel.
false Disable window limit break signal. 









static inline void SINC_EnableChannelLowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable selected channel’s low limit break signal. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable low limit break signal:

true Enable the automatic assertion of the BREAK_LOW signal when SINC detects a low-limit event on the selected channel.
false Disable low limit break signal. 









static inline void SINC_SetChannelScdOperateMode(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_operate_mode_t opMode)

Set selected channel’s short-circuit detector operate mode. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
opMode – Specify the operate mode to set, please refer to sinc_scd_operate_mode_t. 







static inline void SINC_SetChannelScdLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint8_t u8ScdLimitThreshold)

Set selected channel’s Scd limit threshold. 

Note
The SCD counter tracks the number of received bits with the same repeating value(always 0 or always 1, set by
SINC_SetChannelScdOption()), if that number exceeds the scdLimitThreshold, an SCD event occurs on the associated channel.



Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
u8ScdLimitThreshold – Specify the threshold value for the SCD counter, range from 2 to 255. 







static inline void SINC_SetChannelScdOption(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_option_t option)

Set selected channel’s SDC option. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
option – Specify which repeating bit value increments the SCD counter. 







static inline void SINC_EnableChannelScdBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable the automatic assertion of the BREAK_SCD signal when SINC detects an SCD event on the selected channel. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disable SCD break signal:

true Enable SCD break signal.
false Disable SCD break signal. 









static inline void SINC_SetChannelCadLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, sinc_cad_threshold_t cadLimitThreshold)

Set the threshold value for the CAD counter. 

Note
The CAD counter tracks the number of clock cycles during which SINC does not detect a clock, if that number exceeds the threshold value, a CAD event occurs on the selected channel.


Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
cadLimitThreshold – Specify the threshold value for the CAD counter, please refer to sinc_cad_threshold_t. 







static inline void SINC_EnableChannelCadBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)

Enable/disable the automatic assertion of the BREAK_CAD signal when SINC detects a CAD event on the assoicated channel. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
enable – Used to enable/disble CAD break signal:

true Enable selected channel’s CAD break signal;
false Disable selected channel’s CAD break signal. 









static inline void SINC_SetChannelZcdOperateMode(SINC_Type *base, sinc_channel_id_t chId, sinc_zero_cross_operate_mode_t opMode)

Set selected channel’s zero-crossing detector operate mode. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
opMode – Specify the operate mode, please refer to sinc_zero_cross_operate_mode_t. 







static inline void SINC_SetChannelPulseTriggerMux(SINC_Type *base, sinc_channel_id_t chId, sinc_pulse_trigger_mux_t pulseTrigMux)

Set selected channel’s pulse trigger mux. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
pulseTrigMux – Used to selected the signal for pulse-trigger output. 







static inline void SINC_SetChannelDebugOutput(SINC_Type *base, sinc_channel_id_t chId, sinc_debug_output_t debugOutput)

Set selected channel’s debug output. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 
debugOutput – Used to select debug output, please refer to sinc_debug_output_t. 







static inline void SINC_LatchChannelDebugProceduce(SINC_Type *base, sinc_channel_id_t chId)

Start selected channel’s debug data latch proceduce. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t. 







static inline bool SINC_CheckChannelDebugDataValid(SINC_Type *base, sinc_channel_id_t chId)

Check if the selected channel’s debug data is valid. 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t.


Return values:

true – Data is valid. 
false – Data is invalid. 







static inline uint32_t SINC_GetChannelDebugData(SINC_Type *base, sinc_channel_id_t chId)

Return selected channel’s the debug data that requested by SINC_SetChannelDebugOutput(). 

Parameters:

base – SINC peripheral base address. 
chId – Selected channel id, please refer to sinc_channel_id_t.


Returns:
Selected channel’s debug data. 






static inline void SINC_EnableInterrupts(SINC_Type *base, uint64_t interruptMasks)

Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on. 

Parameters:

base – SINC peripheral base address. 
interruptMasks – Mask of interrupts to enable, should be the OR’ed value of sinc_interrupt_enable_t. 







static inline void SINC_DisableInterrupts(SINC_Type *base, uint64_t interruptMasks)

Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on. 

Parameters:

base – SINC peripheral base address. 
interruptMasks – Mask of interrupts to disable, should be the OR’ed value of sinc_interrupt_enable_t. 







static inline uint64_t SINC_GetInterruptStatus(SINC_Type *base)

Get interrupt status flags. 

Parameters:

base – SINC peripheral base address.


Returns:
SINC module’s interrupt status flags, the OR’ed value of sinc_interrupt_status_t. 






static inline void SINC_ClearInterruptStatus(SINC_Type *base, uint64_t statusMasks)

Clear selected mask of interrupt status flags. 

Parameters:

base – SINC peripheral base address. 
statusMasks – The mask of interrupt status flags to clear, should be the OR’ed value of sinc_interrupt_status_t. 







FSL_SINC_DRIVER_VERSION

lower_component_name driver version 2.1.5. 




enum _sinc_interrupt_enable

The enumeration of SINC module’s interrupts. . 
Values:


enumerator kSINC_CH0ConvCompleteIntEnable





enumerator kSINC_CH1ConvCompleteIntEnable





enumerator kSINC_CH2ConvCompleteIntEnable





enumerator kSINC_CH3ConvCompleteIntEnable





enumerator kSINC_CH0DataReadyIntEnable





enumerator kSINC_CH1DataReadyIntEnable





enumerator kSINC_CH2DataReadyIntEnable





enumerator kSINC_CH3DataReadyIntEnable





enumerator kSINC_CH0ZeroCrossDetectedIntEnable





enumerator kSINC_CH1ZeroCrossDetectedIntEnable





enumerator kSINC_CH2ZeroCrossDetectedIntEnable





enumerator kSINC_CH3ZeroCrossDetectedIntEnable





enumerator kSINC_CH0SCDIntEnable





enumerator kSINC_CH1SCDIntEnable





enumerator kSINC_CH2SCDIntEnable





enumerator kSINC_CH3SCDIntEnable





enumerator kSINC_CH0WindowLimitIntEnable





enumerator kSINC_CH1WindowLimitIntEnable





enumerator kSINC_CH2WindowLimitIntEnable





enumerator kSINC_CH3WindowLimitIntEnable





enumerator kSINC_CH0LowLimitIntEnable





enumerator kSINC_CH1LowLimitIntEnable





enumerator kSINC_CH2LowLimitIntEnable





enumerator kSINC_CH3LowLimitIntEnable





enumerator kSINC_CH0HighLimitIntEnable





enumerator kSINC_CH1HighLimitIntEnable





enumerator kSINC_CH2HighLimitIntEnable





enumerator kSINC_CH3HighLimitIntEnable





enumerator kSINC_CH0FifoUnderflowIntEnable





enumerator kSINC_CH1FifoUnderflowIntEnable





enumerator kSINC_CH2FifoUnderflowIntEnable





enumerator kSINC_CH3FifoUnderflowIntEnable





enumerator kSINC_CH0FifoOverflowIntEnable





enumerator kSINC_CH1FifoOverflowIntEnable





enumerator kSINC_CH2FifoOverflowIntEnable





enumerator kSINC_CH3FifoOverflowIntEnable





enumerator kSINC_CH0CADIntEnable





enumerator kSINC_CH1CADIntEnable





enumerator kSINC_CH2CADIntEnable





enumerator kSINC_CH3CADIntEnable





enumerator kSINC_CH0SaturationIntEnable





enumerator kSINC_CH1SaturationIntEnable





enumerator kSINC_CH2SaturationIntEnable





enumerator kSINC_CH3SaturationIntEnable







enum _sinc_interrupt_status

The enumeration of SINC interrupt status flags. . 
Values:


enumerator kSINC_CH0ConvCompleteIntStatus





enumerator kSINC_CH1ConvCompleteIntStatus





enumerator kSINC_CH2ConvCompleteIntStatus





enumerator kSINC_CH3ConvCompleteIntStatus





enumerator kSINC_CH0DataReadyIntStatus





enumerator kSINC_CH1DataReadyIntStatus





enumerator kSINC_CH2DataReadyIntStatus





enumerator kSINC_CH3DataReadyIntStatus





enumerator kSINC_CH0ZeroCrossDetectedIntStatus





enumerator kSINC_CH1ZeroCrossDetectedIntStatus





enumerator kSINC_CH2ZeroCrossDetectedIntStatus





enumerator kSINC_CH3ZeroCrossDetectedIntStatus





enumerator kSINC_CH0SCDIntStatus





enumerator kSINC_CH1SCDIntStatus





enumerator kSINC_CH2SCDIntStatus





enumerator kSINC_CH3SCDIntStatus





enumerator kSINC_CH0WindowLimitIntStatus





enumerator kSINC_CH1WindowLimitIntStatus





enumerator kSINC_CH2WindowLimitIntStatus





enumerator kSINC_CH3WindowLimitIntStatus





enumerator kSINC_CH0LowLimitIntStatus





enumerator kSINC_CH1LowLimitIntStatus





enumerator kSINC_CH2LowLimitIntStatus





enumerator kSINC_CH3LowLimitIntStatus





enumerator kSINC_CH0HighLimitIntStatus





enumerator kSINC_CH1HighLimitIntStatus





enumerator kSINC_CH2HighLimitIntStatus





enumerator kSINC_CH3HighLimitIntStatus





enumerator kSINC_CH0FifoUnderflowIntStatus





enumerator kSINC_CH1FifoUnderflowIntStatus





enumerator kSINC_CH2FifoUnderflowIntStatus





enumerator kSINC_CH3FifoUnderflowIntStatus





enumerator kSINC_CH0FifoOverflowIntStatus





enumerator kSINC_CH1FifoOverflowIntStatus





enumerator kSINC_CH2FifoOverflowIntStatus





enumerator kSINC_CH3FifoOverflowIntStatus





enumerator kSINC_CH0CADIntStatus





enumerator kSINC_CH1CADIntStatus





enumerator kSINC_CH2CADIntStatus





enumerator kSINC_CH3CADIntStatus





enumerator kSINC_CH0SaturationIntStatus





enumerator kSINC_CH1SaturationIntStatus





enumerator kSINC_CH2SaturationIntStatus





enumerator kSINC_CH3SaturationIntStatus







enum _sinc_channel_id

The enumeration of channel id, the sinc module contains 4 channels. 
Values:


enumerator kSINC_Channel0

Channel 0. 




enumerator kSINC_Channel1

Channel 1. 




enumerator kSINC_Channel2

Channel 2. 




enumerator kSINC_Channel3

Channel 3. 






enum _sinc_modulator_clock

The enumeration of modulator clock name. . 
Values:


enumerator kSINC_ModClk0

Modulator Clock 0 output. 




enumerator kSINC_ModClk1

Modulator Clock 1 output. 




enumerator kSINC_ModClk2

Modulator Clock 2 output. 






enum _sinc_inputClk_source

The enumeration of input clock. 
Values:


enumerator kSINC_InputClk_SourceMclkOut0

MCLK_OUT0 with internal routeback. 




enumerator kSINC_InputClk_SourceMclkOut1

MCLK_OUT1 with internal routeback. 




enumerator kSINC_InputClk_SourceMclkOut2

MCLK_OUT2 with internal routeback. 




enumerator kSINC_InputClk_SourceExternalModulatorClk

External modulator clock dedicated to the selected channel. 




enumerator kSINC_InputClk_SourceAdjacentChannelClk

Grouped clock shared with an adjacent channel. 






enum _sinc_inputClk_edge

The enumeration of clock edge. 
Values:


enumerator kSINC_InputClk_EdgePositive

Positive edge. 




enumerator kSINC_InputClk_EdgeNegative

Negative edge. 




enumerator kSINC_InputClk_EdgeBoth

Both edges. 




enumerator kSINC_InputClk_EdgeOddPositive

Every other odd positive edge. 




enumerator kSINC_InputClk_EdgeEvenPositive

Every other even positive edge. 




enumerator kSINC_InputClk_EdgeOddNegative

Every other odd negative edge. 




enumerator kSINC_InputClk_EdgeEvenNegative

Every other even negative edge. 






enum _sinc_inputBit_format

The enumeration of input bit format. 
Values:


enumerator kSINC_InputBit_FormatExternalBitstream

External bitstream from the MBIT[n] signal. 




enumerator kSINC_InputBit_FormatExternalManchesterCode

External Manchester code. 




enumerator kSINC_InputBit_FormatInternal16bitParallelData

Internal 16-bit parallel data from MPDATA register. 




enumerator kSINC_InputBit_FormatInternal32bitSerialData

Internal 32-bit serial data from MPDATA. 






enum _sinc_inputBit_source

The enumeration of input bit source. 
Values:


enumerator kSINC_InputBit_SourceExternalBitstream

External bitstream from the MBIT[n] signal. 




enumerator kSINC_InputBit_SourceInternalBitstream

Alternate internal bitstream from the INP[n] signal. 




enumerator kSINC_InputBit_SourceAdjacentChannel

Grouped bitstream shared with an adjacent chanel. 






enum _sinc_conv_trigger_source

The enumeration of trigger source. 
Values:


enumerator kSINC_ConvTrig_SoftPosEdge

Positive edge software trigger. 




enumerator kSINC_ConvTrig_SoftHighLevel

High level software trigger. 




enumerator kSINC_ConvTrig_HardPosEdge

Positive edge hardware trigger. 




enumerator kSINC_ConvTrig_HardHighLevel

High level hardware trigger. 




enumerator kSINC_ConvTrig_AdjacentChannel

Grouped hardware trigger shared with an adjacent channel. 






enum _sinc_conv_mode

The enumeration of conversion mode. 
Values:


enumerator kSINC_ConvMode_Single

One conversion that follows an edge or level trigger event. 




enumerator kSINC_ConvMode_Continuous

Multiple conversions that follow a triggering event, a new triggering event cancels and restarts conversion. 




enumerator kSINC_ConvMode_Always

Multiple conversions that follow the first triggering event, SINC ignores the next triggering event. 




enumerator kSINC_ConvMode_FixedNumber

Fixed number conversions that follow the first triggering event, a new triggering event cancels and restarts conversion. 






enum _sinc_pulse_trigger_mux

The enumeration of pulse trigger mux. 
Values:


enumerator kSINC_PulseTrigger_Disabled

Disable pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxHighLimitLevelSignal

Select high limit level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxLowLimitLevelSignal

Select low limit level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxHighLowLimitLevelSignal

Select low or high limit level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxWindowLimitLevelSignal

Select window limit level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxZeroCrossRisingLevelSignal

Select zero cross rising level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxZeroCrossFallingLevelSignal

Select zero cross falling level signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxRsLimHighLevelSignal

Select level signal that indicates a high level from an RS flip-flop or a schmitt trigger for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxRsLimLowLevelSignal

Select level signal that indicates a low level from an RS flip-flop or a schmitt trigger for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxChannelRawInputModBitStream

Select channel raw input modulator bitstream for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxChannelRawInputModClock

Select channel raw input modulator clock for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxChannelRecoveredModBitStream

Select channel output recovered modulator bitstream for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxChannelRecoveredModClock

Select channel output recovered modulator clock for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxHighLimitPulseSignal

Select high limit pulse signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxLowLimitPulseSignal

Select low limit pulse signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxLimitPulseSignal

Select the pulse signal that indicates a high/low/window limit for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxWindowLimitPulseSignal

Select window limit pulse signal for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxHighLowLimitPulseSignal

Select the pulse signal that indicates a high or low limit for pulse trigger output. 




enumerator kSINC_PulseTrigger_MuxZeroCrossRisePulseSignal

Select zero cross rise pulse signal for trigger output. 




enumerator kSINC_PulseTrigger_MuxZeroCrossFallPulseSignal

Select zero cross fall pulse signal for trigger output. 




enumerator kSINC_PulseTrigger_MuxZeroCrossRiseFallPulseSignal

Select zero cross rise/fall pulse signal for trigger output. 




enumerator kSINC_PulseTrigger_MuxFifoWatermarkOkPulseSignal

Select FIFO watermark OK pulse signal for trigger output. 




enumerator kSINC_PulseTrigger_MuxFifoOverflowPulseSignal

Select FIFO overflow pulse signal. 




enumerator kSINC_PulseTrigger_MuxFifoUnderflowPulseSignal

Select FIFO underflow pulse signal. 




enumerator kSINC_PulseTrigger_MuxFifoEmptyPulseSignal

Select FIFO empty pulse signal. 




enumerator kSINC_PulseTrigger_MuxClockMonitorAssertPulseSignal

Select clock monitor assert pulse signal. 




enumerator kSINC_PulseTrigger_MuxShortCircuitAssertPulseSignal

Select short circuit assert pulse signal. 




enumerator kSINC_PulseTrigger_MuxSaturationPulseSignal

Select saturation pulse signal. 




enumerator kSINC_PulseTrigger_MuxConversionCompletePulseSignal

Select conversion complete pulse signal. 






enum _sinc_zero_cross_operate_mode

The enumeration of zero cross detector operate mode. 
Values:


enumerator kSINC_ZCD_BothRiseAndFall

Zero cross detector operate on both rise and fall. 




enumerator kSINC_ZCD_OnlyFall

Zero cross detector operate on fall edge. 




enumerator kSINC_ZCD_OnlyRise

Zero cross detector operate on rise edge. 




enumerator kSINC_ZCD_Disabled

Zero cross detector disabled. 






enum _sinc_primary_filter_order

The enumeration of primary filter order. 
Values:


enumerator kSINC_PF_FastSinc

Fast sinc filter, ORD is 4. 




enumerator kSINC_PF_FirstOrder

First order filter, ORD is 1. 




enumerator kSINC_PF_SecondOrder

Second order filter, ORD is 2. 




enumerator kSINC_PF_ThirdOrder

Third order filter, ORD is 3. 






enum _sinc_clock_prescale

The enumeration of clock prescale that specify the clock divider ratio for the modulator clock. 
Values:


enumerator kSINC_ClkPrescale1

No prescale. 




enumerator kSINC_ClkPrescale2

Modulator clock divider ratio is 2. 




enumerator kSINC_ClkPrescale4

Modulator clock divider ratio is 4. 




enumerator kSINC_ClkPrescale8

Modulator clock divider ratio is 8. 






enum _sinc_primary_filter_shift_direction

The enumeration of primary filter shift direction. 
Values:


enumerator kSINC_PF_ShiftRight

Right shift the raw data. 




enumerator kSINC_PF_ShiftLeft

Left shift the raw data. 






enum _sinc_primary_filter_bias_sign

The enumeration of primary filer bias sign. 
Values:


enumerator kSINC_PF_BiasPositive

The bias sign is positive. 




enumerator kSINC_PF_BiasNegative

The bias sign is negative. 






enum _sinc_primary_filter_hpf_alpha_coeff

The enumeration of HPF DC remover Alpha coefficient. 
Values:


enumerator kSINC_PF_HPFAlphaCoeff0

Disabled HPF. 




enumerator kSINC_PF_HPFAlphaCoeff1

Alpha coefficient = 1 - (2^-5) 




enumerator kSINC_PF_HPFAlphaCoeff2

Alpha coefficient = 1 - (2^-6) 




enumerator kSINC_PF_HPFAlphaCoeff3

Alpha coefficient = 1 - (2^-7) 




enumerator kSINC_PF_HPFAlphaCoeff4

Alpha coefficient = 1 - (2^-8) 




enumerator kSINC_PF_HPFAlphaCoeff5

Alpha coefficient = 1 - (2^-9) 




enumerator kSINC_PF_HPFAlphaCoeff6

Alpha coefficient = 1 - (2^-10) 




enumerator kSINC_PF_HPFAlphaCoeff7

Alpha coefficient = 1 - (2^-11) 




enumerator kSINC_PF_HPFAlphaCoeff8

Alpha coefficient = 1 - (2^-12) 




enumerator kSINC_PF_HPFAlphaCoeff9

Alpha coefficient = 1 - (2^-13) 




enumerator kSINC_PF_HPFAlphaCoeff10

Alpha coefficient = 1 - (2^-14) 




enumerator kSINC_PF_HPFAlphaCoeff11

Alpha coefficient = 1 - (2^-15) 




enumerator kSINC_PF_HPFAlphaCoeff12

Alpha coefficient = 1 - (2^-16) 




enumerator kSINC_PF_HPFAlphaCoeff13

Alpha coefficient = 1 - (2^-17) 




enumerator kSINC_PF_HPFAlphaCoeff14

Alpha coefficient = 1 - (2^-18) 




enumerator kSINC_PF_HPFAlphaCoeff15

Alpha coefficient = 1 - (2^-19) 






enum _sinc_inputBit_delay

The enumeration of input bit delay. 
Values:


enumerator kSINC_InputBit_DelayDisabled

Input modulator bitstream delay disabled. 




enumerator kSINC_InputBit_Delay1ClkCycle

Input modulator bitstream delay 1 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay2ClkCycle

Input modulator bitstream delay 2 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay3ClkCycle

Input modulator bitstream delay 3 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay4ClkCycle

Input modulator bitstream delay 4 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay5ClkCycle

Input modulator bitstream delay 5 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay6ClkCycle

Input modulator bitstream delay 6 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay7ClkCycle

Input modulator bitstream delay 7 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay8ClkCycle

Input modulator bitstream delay 8 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay9ClkCycle

Input modulator bitstream delay 9 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay10ClkCycle

Input modulator bitstream delay 10 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay11ClkCycle

Input modulator bitstream delay 11 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay12ClkCycle

Input modulator bitstream delay 12 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay13ClkCycle

Input modulator bitstream delay 13 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay14ClkCycle

Input modulator bitstream delay 14 PRE_CLK cycle. 




enumerator kSINC_InputBit_Delay15ClkCycle

Input modulator bitstream delay 15 PRE_CLK cycle. 






enum _sinc_scd_operate_mode

The enumeration of short-circuit detector operate mode. 
Values:


enumerator kSINC_Scd_OperateAtChannelEnabled

SCD operates when the channel is enabled. 




enumerator kSINC_Scd_OperateAtConversion

SCD operates when the PF is performing a conversion. 




enumerator kSINC_Scd_OperateDisabled

Short circuit detect is disabled. 






enum _sinc_scd_option

The enumeration of short-circuit detector option. 
Values:


enumerator kSINC_Scd_DetectRepeating0And1

Both repeating 0 and 1 increment the SCD counter. 




enumerator kSINC_Scd_DetectRepeatingOnly1

Only repeating 1 increment the SCD counter. 




enumerator kSINC_Scd_DetectRepeatingOnly0

Only repeating 1 increment the SCD counter. 






enum _sinc_limit_detector_mode

The mode of limit detector. 

Note
The value of each limit detector contains lot of information: bit[1:0]: limit detection options, bit[2]: low limit break signal. bit[3]: window limit break signal. bit[4]: High limit break signal. bit[7]: Enable/disable limit detector. 

Values:


enumerator kSINC_Lmt_BothHighAndLowLimit

Limit detector is enabled, and compare the filter sample value to high and low limit, if the value larger than high limit will trigger interrupt or break, and if the value lower than low limit will trigger interrupt or break. 




enumerator kSINC_Lmt_OnlyHighLimit

Limit detector is enabled, and compare the filter sample value to high limit, if the value larger than high limit will trigger interrupt or break. 




enumerator kSINC_Lmt_OnlyLowLimit

Limit detector is enabled, and compare the filter sample value to low limit, if the value lower than low limit will trigger interrupt or break. 




enumerator kSINC_Lmt_WindowedValue

Limit detector is enabled, and compare the filter sample value to high and low limit, if the value higher than low limit and lower than high limit will trigger interrupt or break. 




enumerator kSINC_Lmt_Disabled

Limit detector is disabled. 






enum _sinc_cad_threshold

The enumeration of clock-absence threshold. 
Values:


enumerator kSINC_Cad_Disabled

Clock absence detector is disabled. 




enumerator kSINC_Cad_Count1ClkCycle

Clock absence detector threshold is 1 clock cycle. 




enumerator kSINC_Cad_Count2ClkCycle

Clock absence detector threshold is 2 clock cycle. 




enumerator kSINC_Cad_Count3ClkCycle

Clock absence detector threshold is 3 clock cycle. 




enumerator kSINC_Cad_Count4ClkCycle

Clock absence detector threshold is 4 clock cycle. 




enumerator kSINC_Cad_Count5ClkCycle

Clock absence detector threshold is 5 clock cycle. 




enumerator kSINC_Cad_Count6ClkCycle

Clock absence detector threshold is 6 clock cycle. 




enumerator kSINC_Cad_Count7ClkCycle

Clock absence detector threshold is 7 clock cycle. 




enumerator kSINC_Cad_Count8ClkCycle

Clock absence detector threshold is 8 clock cycle. 




enumerator kSINC_Cad_Count9ClkCycle

Clock absence detector threshold is 9 clock cycle. 




enumerator kSINC_Cad_Count10ClkCycle

Clock absence detector threshold is 10 clock cycle. 




enumerator kSINC_Cad_Count11ClkCycle

Clock absence detector threshold is 11 clock cycle. 




enumerator kSINC_Cad_Count12ClkCycle

Clock absence detector threshold is 12 clock cycle. 




enumerator kSINC_Cad_Count13ClkCycle

Clock absence detector threshold is 13 clock cycle. 




enumerator kSINC_Cad_Count14ClkCycle

Clock absence detector threshold is 14 clock cycle. 




enumerator kSINC_Cad_Count15ClkCycle

Clock absence detector threshold is 15 clock cycle. 






enum _sinc_alternate_dma_source

The enumeration of alternate DMA source. 
Values:


enumerator kSINC_AltDma_Disabled

Alternate DMA disabled. 




enumerator kSINC_AltDma_PfConvComplete

Select PF conversion complete for alternate DMA. 




enumerator kSINC_AltDma_PfDataOutputReady

Select PF data output ready for alternate DMA. 




enumerator kSINC_AltDma_ZeroCrossDetected

Select zero crossing detected for alternate DMA. 




enumerator kSINC_AltDma_ShortCircuitDetected

Select short circuit detected for alternate DMA. 




enumerator kSINC_AltDma_WindowLimitDetected

Select window limit detected for alternate DMA. 




enumerator kSINC_AltDma_LowLimitDetected

Select low limit detected for alternate DMA. 




enumerator kSINC_AltDma_HighLimitDetected

Select high limit detected for alternate DMA. 




enumerator kSINC_AltDma_FifoUnderflow

Select FIFO underflow detected for alternate DMA. 




enumerator kSINC_AltDma_FifoOverflow

Select FIFO overflow detected for alternate DMA. 




enumerator kSINC_AltDma_ClockAbsence

Select clock absence detected for alternate DMA. 




enumerator kSINC_AltDma_Saturation

Select channel saturation for alternate DMA. 






enum _sinc_result_data_format

The enumeration of result data format. 
Values:


enumerator kSINC_LeftJustifiedSigned

Left justified, signed. 




enumerator kSINC_LeftJustifiedUnsigned

Left justified, unsigned. 






enum _sinc_debug_output

The enumeration of debug output. 
Values:


enumerator kSINC_Debug_PfFinalData

Final data from PF(24 bits). 




enumerator kSINC_Debug_OffsetData

Offset data(24 bits). 




enumerator kSINC_Debug_PfShiftedData

Shifted data from the PF(24 bits). 




enumerator kSINC_Debug_HpfData

DC remover(HPF) data(32 bits). 




enumerator kSINC_Debug_CicRawData

Raw data from the PF’s CIC filter. 




enumerator kSINC_Debug_ScdHistoricalData

Historical data from SCD. 




enumerator kSINC_Debug_ManchesterDecoderData

Data from the Manchester decoder. 




enumerator kSINC_Debug_CadData

Data from CAD. 




enumerator kSINC_Debug_FifoEntriesNum

Number of available entries in the FIFO. 




enumerator kSINC_Debug_ParallelSerialConverterStatus

Status of the parallel or serial data converter. 






typedef enum _sinc_channel_id sinc_channel_id_t

The enumeration of channel id, the sinc module contains 4 channels. 




typedef enum _sinc_inputClk_source sinc_inputClk_source_t

The enumeration of input clock. 




typedef enum _sinc_inputClk_edge sinc_inputClk_edge_t

The enumeration of clock edge. 




typedef enum _sinc_inputBit_format sinc_inputBit_format_t

The enumeration of input bit format. 




typedef enum _sinc_inputBit_source sinc_inputBit_source_t

The enumeration of input bit source. 




typedef enum _sinc_conv_trigger_source sinc_conv_trigger_source_t

The enumeration of trigger source. 




typedef enum _sinc_conv_mode sinc_conv_mode_t

The enumeration of conversion mode. 




typedef enum _sinc_pulse_trigger_mux sinc_pulse_trigger_mux_t

The enumeration of pulse trigger mux. 




typedef enum _sinc_zero_cross_operate_mode sinc_zero_cross_operate_mode_t

The enumeration of zero cross detector operate mode. 




typedef enum _sinc_primary_filter_order sinc_primary_filter_order_t

The enumeration of primary filter order. 




typedef enum _sinc_clock_prescale sinc_clock_prescale_t

The enumeration of clock prescale that specify the clock divider ratio for the modulator clock. 




typedef enum _sinc_primary_filter_shift_direction sinc_primary_filter_shift_direction_t

The enumeration of primary filter shift direction. 




typedef enum _sinc_primary_filter_bias_sign sinc_primary_filter_bias_sign_t

The enumeration of primary filer bias sign. 




typedef enum _sinc_primary_filter_hpf_alpha_coeff sin_primary_filter_hpf_alpha_coeff_t

The enumeration of HPF DC remover Alpha coefficient. 




typedef enum _sinc_inputBit_delay sinc_inputBit_delay_t

The enumeration of input bit delay. 




typedef enum _sinc_scd_operate_mode sinc_scd_operate_mode_t

The enumeration of short-circuit detector operate mode. 




typedef enum _sinc_scd_option sinc_scd_option_t

The enumeration of short-circuit detector option. 




typedef enum _sinc_limit_detector_mode sinc_limit_detector_mode_t

The mode of limit detector. 

Note
The value of each limit detector contains lot of information: bit[1:0]: limit detection options, bit[2]: low limit break signal. bit[3]: window limit break signal. bit[4]: High limit break signal. bit[7]: Enable/disable limit detector. 





typedef enum _sinc_cad_threshold sinc_cad_threshold_t

The enumeration of clock-absence threshold. 




typedef enum _sinc_alternate_dma_source sinc_alternate_dma_source_t

The enumeration of alternate DMA source. 




typedef enum _sinc_result_data_format sinc_result_data_format_t

The enumeration of result data format. 




typedef enum _sinc_debug_output sinc_debug_output_t

The enumeration of debug output. 




typedef struct _sinc_channel_input_option sinc_channel_input_option_t

The structure of channel input options, including input bit settings and input clock settings. 




typedef struct _sinc_channel_conv_option sinc_channel_conv_option_t

The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings, bias settings and so on. 




typedef struct _sinc_channel_protection_option sinc_channel_protection_option_t

The structure of channel protection options, including limit check settings, short-circuit settings, clock-absence settings, and zero-crossing settings. 




typedef struct _sinc_channel_config sinc_channel_config_t

The structure of channel configurations, including channel input option, channel conversion options, channel protection options, and so on. 




typedef struct _sinc_config sinc_config_t

The structure of sinc configurations, including clock settings anc channels’ settings. 




SINC_CHANNEL_COUNT





SINC_NORMAL_INT_REG_ID





SINC_NORMAL_INT_NAME_COCIE





SINC_NORMAL_INT_NAME_CHFIE





SINC_NORMAL_INT_NAME_ZCDIE





SINC_ERROR_INT_REG_ID





SINC_ERROR_INT_NAME_SCDIE





SINC_ERROR_INT_NAME_WLMTIE





SINC_ERROR_INT_NAME_LLMTIE





SINC_ERROR_INT_NAME_HLMTIE





SINC_FIFO_CAD_INT_REG_ID





SINC_FIFO_CAD_INT_FUNFIE





SINC_FIFO_CAD_INT_FOVFIE





SINC_FIFO_CAD_INT_CADIE





SINC_FIFO_CAD_INT_SATIE





SINC_ENCODE_INTERRUPT(regId, name, channelId)





SINC_DECODE_INTERRUPT(interruptMask)





SINC_FIND_INT_FIELD_VALUE(mask, name)





SINC_FIND_STATUS_FIELD_VALUE(statusValue, name)





struct _sinc_channel_input_option


#include <fsl_sinc.h>
The structure of channel input options, including input bit settings and input clock settings. 

Public Members


sinc_inputBit_format_t inputBitFormat

Specify input bit format, please refer to sinc_inputBit_format_t. 




sinc_inputBit_source_t inputBitSource

Specify input bit source, please refer to sinc_inputBit_source_t. 




sinc_inputBit_delay_t inputBitDelay

Specify input bit delay, please refer to sinc_inputBit_delay_t. 




sinc_inputClk_source_t inputClkSource

Specify input clock source, please refer to sinc_inputClk_source_t. 




sinc_inputClk_edge_t inputClkEdge

Specify input clock edge, please refer to sinc_inputClk_edge_t. 







struct _sinc_channel_conv_option


#include <fsl_sinc.h>
The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings, bias settings and so on. 

Public Members


sinc_conv_mode_t convMode

Specify conversion mode, please refer to sinc_conv_mode_t. 




sinc_conv_trigger_source_t convTriggerSource

Specify conversion trigger source, please refer to sinc_conv_trigger_source_t. 




bool enableChPrimaryFilter

Enable/disable channel’s primary filter. 




sinc_primary_filter_order_t pfOrder

Specify the order of primary filter, please refer to sinc_primary_filter_order_t. 




uint16_t u16pfOverSampleRatio

Control primary filter’s OSR, the minimum permissible value is 3, low value produce unpredictable result, the maximum permissible value depend on PF order and the desired data format, if PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047. Please note that the OSR for equation is u16pfOverSampleRatio + 1 




sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff

Specify HPF’s alpha coeff, please refer to sin_primary_filter_hpf_alpha_coeff_t. 




sinc_primary_filter_shift_direction_t pfShiftDirection

Select shift direction, right or left. 




uint8_t u8pfShiftBitsNum

Specify the number of bits to shift the data, ranges from 0 to 15. 




sinc_primary_filter_bias_sign_t pfBiasSign

Select bias sign, please refer to sinc_primary_filter_bias_sign_t. 




uint32_t u32pfBiasValue

Range from 0 to 0x7FFFFFUL. 







struct _sinc_channel_protection_option


#include <fsl_sinc.h>
The structure of channel protection options, including limit check settings, short-circuit settings, clock-absence settings, and zero-crossing settings. 

Public Members


sinc_limit_detector_mode_t limitDetectorMode

Specify limit detector mode, please refer to sinc_limit_detector_mode_t. 




bool bEnableLmtBreakSignal

Enable/disable limit break signal, the details of break signal is depended on detector mode. 




uint32_t u32LowLimitThreshold

Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL. 




uint32_t u32HighLimitThreshold

Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL. 




sinc_scd_operate_mode_t scdOperateMode

Enable/disable scd, and set SCD operate timming. 




uint8_t u8ScdLimitThreshold

Range from 2 to 255, 0 and 1 are prohibited. 




sinc_scd_option_t scdOption

Specify SCD options, please refer to sinc_scd_option_t. 




bool bEnableScdBreakSignal

Enable/disable SCD break signal. 




sinc_cad_threshold_t cadLimitThreshold

Specify the threshold value for the CAD counter. 




bool bEnableCadBreakSignal

Enable/disable CAD break signal. 




sinc_zero_cross_operate_mode_t zcdOperateMode

Specify zero cross detector operate mode. 







struct _sinc_channel_config


#include <fsl_sinc.h>
The structure of channel configurations, including channel input option, channel conversion options, channel protection options, and so on. 

Public Members


bool bEnableChannel

Enable/disable channel. 




bool bEnableFifo

Enable/disable channel’s FIFO. 




uint8_t u8FifoWaterMark

Specify the fifo watermark, range from 0 to 15. 




bool bEnablePrimaryDma

Used to enable/disable primary DMA. 




sinc_alternate_dma_source_t altDmaSource

Set channel’s alternate DMA source, please refer to sinc_alternate_dma_source_t. 




sinc_result_data_format_t dataFormat

Set channel’s result data format, please refer to sinc_result_data_format_t. 




sinc_channel_input_option_t *chInputOption

The pointer to sinc_channel_input_option_t that contains channel input options. 




sinc_channel_conv_option_t *chConvOption

The pointer to sinc_channel_conv_option_t that contains channel conversion options. 




sinc_channel_protection_option_t *chProtectionOption

The pointer to sinc_channel_protection_option_t that contains channel protection options. 







struct _sinc_config


#include <fsl_sinc.h>
The structure of sinc configurations, including clock settings anc channels’ settings. 

Public Members


sinc_clock_prescale_t clockPreDivider

Specify modulator clock pre divider, please refer to sinc_clock_prescale_t. 




uint32_t modClkDivider

Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output, write an even value to 




bool disableModClk0Output

Disable/enable modulator clock0 output. 




bool disableModClk1Output

Disable/enable modulator clock1 output. 




bool disableModClk2Output

Disable/enable modulator clock2 output. 




sinc_channel_config_t *channelsConfigArray[(1)]

The array that contains 4 elements, and the type of each element is sinc_channel_config_t *, channelsConfigArray[0] corresponding to channel0, channelsConfigArray[1] corresponding to channel1, channelsConfigArray[2] corresponding to channel2, channelsConfigArray[3] corresponding to channel3, if some channels are not used, the corresponding elements should be set as NULL. 




bool disableDozeMode

Disable/enable SINC module when the chip enters Doze or stop mode. 




bool enableMaster

Enable/disable all function blocks of SINC module. 







Sramctl#


FSL_SRAMCTL_DRIVER_VERSION

SRAMCTL driver version. 




enum sramctl_address_type_t

Determines whether RAMIAS/RAMIAE are system or local addresses. 
Values:


enumerator kSRAMCTL_AddressTypeLocal

Local address. 




enumerator kSRAMCTL_AddressTypeSystem

System address. 






enum sramctl_initialization_wait_states_t

Specifies the number of wait cycles between memory writes during initialization. 
Values:


enumerator kSRAMCTL_ZeroWaitCycle

0 wait cycles. 




enumerator kSRAMCTL_OneWaitCycle

1 wait cycle. 




enumerator kSRAMCTL_TwoWaitCycles

2 wait cycles. 




enumerator kSRAMCTL_ThreeWaitCycles

3 wait cycles. 






enum sramctl_status_flags_t

SRAMCTL status flags (RAMSR bits). 
Values:


enumerator kSRAMCTL_InitializationDone

IDONE (W1C). 




enumerator kSRAMCTL_BusError

BUSERR (W1C). 




enumerator kSRAMCTL_InitializationPending

IPEND (RO). 




enumerator kSRAMCTL_AddressValid

AVALID (W1C). 




enumerator kSRAMCTL_EccAddressError

AERR (W1C). 




enumerator kSRAMCTL_EccMultiBitError

MLTERR (W1C). 




enumerator kSRAMCTL_EccSingleBitError

SGLERR (W1C, captures latest). 




enumerator kSRAMCTL_SecureRegion

SEC (RO). 




enumerator kSRAMCTL_AllW1CFlags

All W1C bits that software is allowed to clear. 




enumerator kSRAMCTL_AllFlags

All RAMSR bits (including RO bits). 






status_t SRAMCTL_Init(SRAMCTL_Type *base, sramctl_config_t const *config)

Initialize SRAM for the configured address range. 

Parameters:

base – SRAMCTL peripheral base address. 
config – Pointer to the configuration structure. 


Return values:

kStatus_Success – Initialization completed. 
kStatus_InvalidArgument – Invalid argument. 







void SRAMCTL_SetRamMaximumAddress(SRAMCTL_Type *base, uint32_t address)

Set the maximum valid address for SRAM access. 

Parameters:

base – SRAMCTL peripheral base address. 
address – Maximum address value. 







void SRAMCTL_EnableExclusiveMonitor(SRAMCTL_Type *base, bool enable)

Enable or disable the exclusive monitor. 

Parameters:

base – SRAMCTL peripheral base address. 
enable – true to enable exclusive monitor; false to disable it. 







static inline uint32_t SRAMCTL_GetStatusFlags(SRAMCTL_Type *base)

Get SRAMCTL status flags. 

Parameters:

base – SRAMCTL peripheral base address. 


Returns:
Status flags. This is a logical OR of sramctl_status_flags_t. 






status_t SRAMCTL_ClearStatusFlags(SRAMCTL_Type *base, uint32_t mask)

Clear SRAMCTL status flags. 
This function clears W1C flags in RAMSR.

Parameters:

base – SRAMCTL peripheral base address. 
mask – Mask of flags to clear. This is a logical OR of sramctl_status_flags_t. Only W1C flags are allowed; RO flags (such as IPEND/SEC) are rejected. 


Return values:

kStatus_Success – Clear completed. 
kStatus_InvalidArgument – Mask contains RO flags. 







void SRAMCTL_GetErrorInfo(SRAMCTL_Type *base, sramctl_error_info_t *info)

Get SRAMCTL error information. 

Parameters:

base – SRAMCTL peripheral base address. 
info – Pointer to the error information structure. 







void SRAMCTL_ConfigErrorInjectionAddress(SRAMCTL_Type *base, const sramctl_error_injection_address_t *config)

Configure address filtering for error injection. 

Parameters:

base – SRAMCTL peripheral base address. 
config – Pointer to address injection configuration. 







void SRAMCTL_ConfigErrorInjectionData(SRAMCTL_Type *base, const sramctl_error_injection_data_t *config)

Configure data masks for error injection. 

Parameters:

base – SRAMCTL peripheral base address. 
config – Pointer to data injection configuration. 







void SRAMCTL_EnableErrorInjectionForSafetyAlarm(SRAMCTL_Type *base, bool enable)

Enable or disable error injection into the pipeline to cause a safety alarm. 

Parameters:

base – SRAMCTL peripheral base address. 
enable – true to enable; false to disable. 







void SRAMCTL_InitMem(SRAMCTL_Type *base, uint32_t start_addr, uint32_t end_addr)

Initialize memory range by instance index. 


Deprecated:
Prefer SRAMCTL_Init. 




Parameters:

base – SRAMCTL peripheral base address. 
start_addr – Start address. 
end_addr – End address.







struct sramctl_config_t


#include <fsl_sramctl.h>
SRAMCTL configuration structure. 

Public Members


sramctl_address_type_t addressType

Address type for RAMIAS/RAMIAE. See sramctl_address_type_t. 




sramctl_initialization_wait_states_t initializationWaitStates

Initialization wait states. 




uint32_t addressStart

RAM Initialization Address Start (RAMIAS). 




uint32_t addressEnd

RAM Initialization Address End (RAMIAE). 







struct sramctl_error_info_t


#include <fsl_sramctl.h>
SRAMCTL error information structure. 

Public Members


uint8_t eccSyndromeValue

Syndrome value (RAMSR[SYND]). 




uint8_t ramStatusEventInfo

Event info (RAMSR[EINFO]). 




uint8_t ramCorrectableErrorCount

Correctable error count (RAMECCNT[ECCNT]). 




uint16_t ramEccAddressBankId

Bank ID (RAMMEMA[BANK]). 




uint32_t ramEccAddressBankAddress

Bank address (RAMMEMA[MEMA]). 




uint32_t ramSystemAddress

System address (RAMSYSA). 







struct sramctl_error_injection_address_t


#include <fsl_sramctl.h>
SRAMCTL error injection address configuration structure. 

Public Members


bool ramErrorInjectionAddressEnable

true: enable address filtering using base/mask. 




uint32_t ramErrorInjectionBaseAddress

Base address (RAMEIA). 




uint32_t ramErrorInjectionAddressMask

Address mask (RAMEIAM). 







struct sramctl_error_injection_data_t


#include <fsl_sramctl.h>
SRAMCTL error injection data configuration structure. 

Public Members


bool ramErrorInjectionDataEnable

true: enable data injection driven by local registers. 




uint8_t ramErrorInjectionDataCheckbits

Checkbits mask (RAMEIDC[EID_CKB]). 




uint32_t ramErrorInjectionData0

Lower word mask (RAMEID0). 




uint32_t ramErrorInjectionData1

Upper word mask (RAMEID1). 







SRC_driver#


bool SRC_MixInit(uint32_t srcMixIdx)

Initialize SRC MIX LPM configuration and ISOs

This function performs initial configuration (AUTHEN_CTRL, LPM, ISO, Retention etc.) for SRC MIX.

Parameters:

srcMixIdx – [in] SRC MIX identifier


Returns:
Returns true if the configuration is applied successfully, otherwise false. 






bool SRC_MixLpmModeSet(uint32_t srcMixIdx, bool gpcLpmCtrl)

Configure SRC MIX LPM mode (SW vs HW/GPC control)

This function sets SRC MIX LPM mode (SW vs HW).

Parameters:

srcMixIdx – [in] SRC MIX identifier 
gpcLpmCtrl – [in] Flag for MIX LPM mode (0=SW, 1=HW)


Returns:
Returns true if the LPM mode is set successfully, otherwise false. 






bool SRC_MixCpuLpmSet(uint32_t srcMixIdx, uint32_t cpuIdx, uint32_t cpuLpmSetting)

Configure CPU LPM response for specified power domain

This function sets CPU LPM setting if the given srcMixIdx supports LPM mode.

Parameters:

srcMixIdx – [in] SRC MIX identifier 
cpuIdx – [in] CPU identified 
cpuLpmSetting – [in] CPU LPM setting


Returns:
Returns true if the LPM setting for CPU is set successfully, otherwise false. 






bool SRC_MixCpuLpmGet(uint32_t srcMixIdx, uint32_t cpuIdx, uint32_t *cpuLpmSetting)

Get CPU LPM response for specified power domain

This function gets LPM setting for the given CPU from SRC MIX slice.

Parameters:

srcMixIdx – [in] SRC MIX identifier 
cpuIdx – [in] CPU identified 
cpuLpmSetting – [out] CPU LPM setting


Returns:
Returns true if the LPM setting for CPU is retrieved, otherwise false. 






bool SRC_MemRetentionModeSet(uint32_t srcMixIdx, uint32_t memRetMask)

Configure retention mode of MEM slice

This function iterates through MEM slices within a MIX (skipping memory slices that are always retained) set in memRetMask and configures their LPM mode to retention mode.

Parameters:

srcMixIdx – [in] SRC MIX identifier 
memRetMask – [in] MEM slices retention mask


Returns:
Returns true if the MEM slices retention mode is set successfully, otherwise false. 






bool SRC_MemMaskGet(uint32_t srcMixIdx, uint32_t *retMask)

Get mask reflecting memory slices within the MIX

This function queries the bitmask representing the MEM slice instances within the specified MIX.

Parameters:

srcMixIdx – [in] SRC MIX identifier 
retMask – [out] MEM slices retention mask


Returns:
Returns true if the MEM slice bitmask could be queried, otherwise false. 






void SRC_MixSoftPowerDown(uint32_t srcMixIdx)

Software-controlled power down of MIX slice

This function allows caller to execute software controlled power-down sequence using MIX’s SLICE_SW_CTRL register. It takes care of setting MIX’s LPM mode and various handshakes required to perform software controlled power-down of MIX. 

Parameters:

srcMixIdx – [in] SRC MIX identifier







bool SRC_MixSoftPowerUp(uint32_t srcMixIdx)

Software-controlled power up of MIX slice

This function allows caller to execute software controlled power-up sequence using MIX’s SLICE_SW_CTRL register. It takes care of setting MIX’s LPM mode and various handshakes required to perform software controlled power-up of the MIX.

Parameters:

srcMixIdx – [in] SRC MIX identifier


Returns:
Returns true if software controlled power-up executed successfully, otherwise false. 






bool SRC_MixIsPwrSwitchOn(uint32_t srcMixIdx)

Check MIX slice power switch status

This function allows caller to get power switch status of the MIX.

Parameters:

srcMixIdx – [in] SRC MIX identifier


Returns:
Returns true if MIX is powered, otherwise false. 






bool SRC_MixIsPwrReady(uint32_t srcMixIdx)

Check if MIX power up sequence is complete

This function allows caller to get power up sequence completion status of MIX.

Parameters:

srcMixIdx – [in] SRC MIX identifier


Returns:
Returns true if MIX power up sequence is completed, otherwise false. 






bool SRC_MixRstExit(uint32_t srcMixIdx, uint32_t timeoutUsec)

Block until MIX slice reset phase exits

This function allows caller to block until the MIX reset phase has exited or timeout has been reached.

Parameters:

srcMixIdx – [in] SRC MIX identifier 
timeoutUsec – [in] timeout in usec


Returns:
Returns true if MIX reset sequence has exited within the specified timeout, otherwise false. 






bool SRC_MixSetResetLine(uint32_t lineIdx, uint32_t resetType)

Configure reset signal of MIX slice

This function allows caller to configure reset signal of the MIX slice to given resetType (DEASSERT/ASSERT/TOGGLE).

Parameters:

lineIdx – [in] Reset line identifier 
resetType – [in] Reset type


Returns:
Returns true if reset signal is configured successfully, otherwise false. 






bool SRC_MixGetResetLine(uint32_t lineIdx, uint32_t *resetType)

Read reset signal of MIX slice

This function allows caller to get reset signal of the MIX slice (ASSERTED/DEASSERTED) based on the assert direction of signal.

Parameters:

lineIdx – [in] Reset line identifier 
resetType – [out] Reset type


Returns:
Returns true if reset signal if MIX slice is read successfully, otherwise false. 






SRC_MIX_A55_HDSK_ACK_IGNORE





SRC_MIX_A55_HDSK_ACK_WAIT





TPM: Timer PWM Module#


uint32_t TPM_GetInstance(TPM_Type *base)

Gets the instance from the base address. 

Parameters:

base – TPM peripheral base address 


Returns:
The TPM instance 






void TPM_Init(TPM_Type *base, const tpm_config_t *config)

Ungates the TPM clock and configures the peripheral for basic operation. 

Note
This API should be called at the beginning of the application using the TPM driver.


Parameters:

base – TPM peripheral base address 
config – Pointer to user’s TPM config structure. 







void TPM_Deinit(TPM_Type *base)

Stops the counter and gates the TPM clock. 

Parameters:

base – TPM peripheral base address 







void TPM_GetDefaultConfig(tpm_config_t *config)

Fill in the TPM config struct with the default settings. 
The default values are: 
     config->prescale = kTPM_Prescale_Divide_1;
     config->useGlobalTimeBase = false;
     config->syncGlobalTimeBase = false;
     config->dozeEnable = false;
     config->dbgMode = false;
     config->enableReloadOnTrigger = false;
     config->enableStopOnOverflow = false;
     config->enableStartOnTrigger = false;
#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
     config->enablePauseOnTrigger = false;
#endif
     config->triggerSelect = kTPM_Trigger_Select_0;
#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
     config->triggerSource = kTPM_TriggerSource_External;
     config->extTriggerPolarity = kTPM_ExtTrigger_Active_High;
#endif
#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
     config->chnlPolarity = 0U;
#endif


 

Parameters:

config – Pointer to user’s TPM config structure. 







tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)

Calculates the counter clock prescaler. 
This function calculates the values for SC[PS].

return Calculated clock prescaler value. 

Parameters:

base – TPM peripheral base address 
counterPeriod_Hz – The desired frequency in Hz which corresponding to the time when the counter reaches the mod value 
srcClock_Hz – TPM counter clock in Hz







static inline void TPM_Reset(TPM_Type *base)

Performs a software reset on the TPM module. 
Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.

Note
TPM software reset is available on certain SoC’s only


Parameters:

base – TPM peripheral base address 







status_t TPM_SetupPwm(TPM_Type *base, const tpm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, tpm_pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)

Configures the PWM signal parameters. 
User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this function to configure all the TPM channels that will be used to output a PWM signal

Parameters:

base – TPM peripheral base address 
chnlParams – Array of PWM channel parameters to configure the channel(s) 
numOfChnls – Number of channels to configure, this should be the size of the array passed in 
mode – PWM operation mode, options available in enumeration tpm_pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz 
srcClock_Hz – TPM counter clock in Hz


Returns:
kStatus_Success PWM setup successful kStatus_Error PWM setup failed kStatus_Timeout PWM setup timeout when write register CnV or MOD 






status_t TPM_UpdatePwmDutycycle(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_pwm_mode_t currentPwmMode, uint8_t dutyCyclePercent)

Update the duty cycle of an active PWM signal. 

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number. In combined mode, this represents the channel pair number 
currentPwmMode – The current PWM mode set during PWM setup 
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle) 


Returns:
kStatus_Success if the PWM setup was successful, kStatus_Error on failure 






void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level)

Update the edge level selection for a channel. 

Note
When the TPM has PWM pause level select feature (FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT = 1), the PWM output cannot be turned off by selecting the output level. In this case, must use TPM_DisableChannel API to close the PWM output.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
level – The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. See the appropriate SoC reference manual for details about this field. 







static inline uint8_t TPM_GetChannelContorlBits(TPM_Type *base, tpm_chnl_t chnlNumber)

Get the channel control bits value (mode, edge and level bit fields). 


Deprecated:
Please use TPM_GetChannelControlBits() instead.




Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t. 






static inline uint8_t TPM_GetChannelControlBits(TPM_Type *base, tpm_chnl_t chnlNumber)

Get the channel control bits value (mode, edge and level bit fields). 

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
The control bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t. 






static inline status_t TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber)

Dsiable the channel. 
This function disable the channel by clear all mode and level control bits.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






static inline status_t TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control)

Enable the channel according to mode and level configs. 
This function enable the channel output according to input mode/level config parameters.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
control – The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode)

Enables capturing an input signal on the channel using the function parameters. 
When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into the CnV register. The user has to read the CnV register separately to get this value.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
captureMode – Specifies which edge to capture 







status_t TPM_SetupOutputCompare(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_output_compare_mode_t compareMode, uint32_t compareValue)

Configures the TPM to generate timed pulses. 
When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel output is changed based on what is specified in the compareMode argument.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
compareMode – Action to take on the channel output when the compare condition is met 
compareValue – Value to be programmed in the CnV register. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnV 






void TPM_SetupDualEdgeCapture(TPM_Type *base, tpm_chnl_t chnlPairNumber, const tpm_dual_edge_capture_param_t *edgeParam, uint32_t filterValue)

Configures the dual edge capture mode of the TPM. 
This function allows to measure a pulse width of the signal on the input of channel of a channel pair. The filter function is disabled if the filterVal argument passed is zero.

Parameters:

base – TPM peripheral base address 
chnlPairNumber – The TPM channel pair number; options are 0, 1, 2, 3 
edgeParam – Sets up the dual edge capture function 
filterValue – Filter value, specify 0 to disable filter. 







void TPM_SetupQuadDecode(TPM_Type *base, const tpm_phase_params_t *phaseAParams, const tpm_phase_params_t *phaseBParams, tpm_quad_decode_mode_t quadMode)

Configures the parameters and activates the quadrature decode mode. 

Parameters:

base – TPM peripheral base address 
phaseAParams – Phase A configuration parameters 
phaseBParams – Phase B configuration parameters 
quadMode – Selects encoding mode used in quadrature decoder mode 







static inline void TPM_SetChannelPolarity(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)

Set the input and output polarity of each of the channels. 

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
enable – true: Set the channel polarity to active high; false: Set the channel polarity to active low; 







static inline void TPM_EnableChannelExtTrigger(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)

Enable external trigger input to be used by channel. 
In input capture mode, configures the trigger input that is used by the channel to capture the counter value. In output compare or PWM mode, configures the trigger input used to modulate the channel output. When modulating the output, the output is forced to the channel initial value whenever the trigger is not asserted.

Note
No matter how many external trigger sources there are, only input trigger 0 and 1 are used. The even numbered channels share the input trigger 0 and the odd numbered channels share the second input trigger 1.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
enable – true: Configures trigger input 0 or 1 to be used by channel; false: Trigger input has no effect on the channel 







void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask)

Enables the selected TPM interrupts. 

Parameters:

base – TPM peripheral base address 
mask – The interrupts to enable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t







void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask)

Disables the selected TPM interrupts. 

Parameters:

base – TPM peripheral base address 
mask – The interrupts to disable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t







uint32_t TPM_GetEnabledInterrupts(TPM_Type *base)

Gets the enabled TPM interrupts. 

Parameters:

base – TPM peripheral base address


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration tpm_interrupt_enable_t






void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback)

Register callback. 
If channel or overflow interrupt is enabled by the user, then a callback can be registered which will be invoked when the interrupt is triggered.

Parameters:

base – TPM peripheral base address 
callback – Callback function 







void TPM_DriverIRQHandler(uint32_t instance)

TPM driver IRQ handler common entry. 
This function provides the common IRQ request entry for TPM.

Parameters:

instance – TPM instance. 







static inline uint32_t TPM_GetChannelValue(TPM_Type *base, tpm_chnl_t chnlNumber)

Gets the TPM channel value. 

Note
The TPM channel value contain the captured TPM counter value for the input modes or the match value for the output modes.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
The channle CnV regisyer value. 






static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)

Gets the TPM status flags. 

Parameters:

base – TPM peripheral base address


Returns:
The status flags. This is the logical OR of members of the enumeration tpm_status_flags_t






static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)

Clears the TPM status flags. 

Parameters:

base – TPM peripheral base address 
mask – The status flags to clear. This is a logical OR of members of the enumeration tpm_status_flags_t







static inline status_t TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)

Sets the timer period in units of ticks. 
Timers counts from 0 until it equals the count value set here. The count value is written to the MOD register.

Note

This API allows the user to use the TPM module as a timer. Do not mix usage of this API with TPM’s PWM setup API’s.
Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.




Parameters:

base – TPM peripheral base address 
ticks – A timer period in units of ticks, which should be equal or greater than 1. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)

Reads the current timer counting value. 
This function returns the real-time timer counting value in a range from 0 to a timer period.

Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.


Parameters:

base – TPM peripheral base address


Returns:
The current counter value in ticks 






static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)

Starts the TPM counter. 

Parameters:

base – TPM peripheral base address 
clockSource – TPM clock source; once clock source is set the counter will start running 







static inline status_t TPM_StopTimer(TPM_Type *base)

Stops the TPM counter. 

Parameters:

base – TPM peripheral base address 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






FSL_TPM_DRIVER_VERSION

TPM driver version 2.5.0. 




enum _tpm_chnl

List of TPM channels. 

Note
Actual number of available channels is SoC dependent 

Values:


enumerator kTPM_Chnl_0

TPM channel number 0 




enumerator kTPM_Chnl_1

TPM channel number 1 




enumerator kTPM_Chnl_2

TPM channel number 2 




enumerator kTPM_Chnl_3

TPM channel number 3 




enumerator kTPM_Chnl_4

TPM channel number 4 




enumerator kTPM_Chnl_5

TPM channel number 5 




enumerator kTPM_Chnl_6

TPM channel number 6 




enumerator kTPM_Chnl_7

TPM channel number 7 






enum _tpm_pwm_mode

TPM PWM operation modes. 
Values:


enumerator kTPM_EdgeAlignedPwm

Edge aligned PWM 




enumerator kTPM_CenterAlignedPwm

Center aligned PWM 




enumerator kTPM_CombinedPwm

Combined PWM (Edge-aligned, center-aligned, or asymmetrical PWMs can be obtained in combined mode using different software configurations) 






enum _tpm_pwm_level_select

TPM PWM output pulse mode: high-true, low-true or no output. 

Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output. 

Values:


enumerator kTPM_HighTrue

High true pulses 




enumerator kTPM_LowTrue

Low true pulses 






enum _tpm_pwm_pause_level_select

TPM PWM output when first enabled or paused: set or clear. 
Values:


enumerator kTPM_ClearOnPause

Clear Output when counter first enabled or paused. 




enumerator kTPM_SetOnPause

Set Output when counter first enabled or paused. 






enum _tpm_chnl_control_bit_mask

List of TPM channel modes and level control bit mask. 
Values:


enumerator kTPM_ChnlELSnAMask

Channel ELSA bit mask. 




enumerator kTPM_ChnlELSnBMask

Channel ELSB bit mask. 




enumerator kTPM_ChnlMSAMask

Channel MSA bit mask. 




enumerator kTPM_ChnlMSBMask

Channel MSB bit mask. 






enum _tpm_trigger_select

Trigger sources available. 
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)

Note
The actual trigger sources available is SoC-specific. 

Values:


enumerator kTPM_Trigger_Select_0





enumerator kTPM_Trigger_Select_1





enumerator kTPM_Trigger_Select_2





enumerator kTPM_Trigger_Select_3





enumerator kTPM_Trigger_Select_4





enumerator kTPM_Trigger_Select_5





enumerator kTPM_Trigger_Select_6





enumerator kTPM_Trigger_Select_7





enumerator kTPM_Trigger_Select_8





enumerator kTPM_Trigger_Select_9





enumerator kTPM_Trigger_Select_10





enumerator kTPM_Trigger_Select_11





enumerator kTPM_Trigger_Select_12





enumerator kTPM_Trigger_Select_13





enumerator kTPM_Trigger_Select_14





enumerator kTPM_Trigger_Select_15







enum _tpm_trigger_source

Trigger source options available. 

Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger. 

Values:


enumerator kTPM_TriggerSource_External

Use external trigger input 




enumerator kTPM_TriggerSource_Internal

Use internal trigger (channel pin input capture) 






enum _tpm_ext_trigger_polarity

External trigger source polarity. 

Note
Selects the polarity of the external trigger source. 

Values:


enumerator kTPM_ExtTrigger_Active_High

External trigger input is active high 




enumerator kTPM_ExtTrigger_Active_Low

External trigger input is active low 






enum _tpm_output_compare_mode

TPM output compare modes. 
Values:


enumerator kTPM_NoOutputSignal

No channel output when counter reaches CnV 




enumerator kTPM_ToggleOnMatch

Toggle output 




enumerator kTPM_ClearOnMatch

Clear output 




enumerator kTPM_SetOnMatch

Set output 




enumerator kTPM_HighPulseOutput

Pulse output high 




enumerator kTPM_LowPulseOutput

Pulse output low 






enum _tpm_input_capture_edge

TPM input capture edge. 
Values:


enumerator kTPM_RisingEdge

Capture on rising edge only 




enumerator kTPM_FallingEdge

Capture on falling edge only 




enumerator kTPM_RiseAndFallEdge

Capture on rising or falling edge 






enum _tpm_quad_decode_mode

TPM quadrature decode modes. 

Note
This mode is available only on some SoC’s. 

Values:


enumerator kTPM_QuadPhaseEncode

Phase A and Phase B encoding mode 




enumerator kTPM_QuadCountAndDir

Count and direction encoding mode 






enum _tpm_phase_polarity

TPM quadrature phase polarities. 
Values:


enumerator kTPM_QuadPhaseNormal

Phase input signal is not inverted 




enumerator kTPM_QuadPhaseInvert

Phase input signal is inverted 






enum _tpm_clock_source

TPM clock source selection. 
Values:


enumerator kTPM_SystemClock

System clock 




enumerator kTPM_ExternalClock

External TPM_EXTCLK pin clock 




enumerator kTPM_ExternalInputTriggerClock

Selected external input trigger clock 






enum _tpm_clock_prescale

TPM prescale value selection for the clock source. 
Values:


enumerator kTPM_Prescale_Divide_1

Divide by 1 




enumerator kTPM_Prescale_Divide_2

Divide by 2 




enumerator kTPM_Prescale_Divide_4

Divide by 4 




enumerator kTPM_Prescale_Divide_8

Divide by 8 




enumerator kTPM_Prescale_Divide_16

Divide by 16 




enumerator kTPM_Prescale_Divide_32

Divide by 32 




enumerator kTPM_Prescale_Divide_64

Divide by 64 




enumerator kTPM_Prescale_Divide_128

Divide by 128 






enum _tpm_interrupt_enable

List of TPM interrupts. 
Values:


enumerator kTPM_Chnl0InterruptEnable

Channel 0 interrupt. 




enumerator kTPM_Chnl1InterruptEnable

Channel 1 interrupt. 




enumerator kTPM_Chnl2InterruptEnable

Channel 2 interrupt. 




enumerator kTPM_Chnl3InterruptEnable

Channel 3 interrupt. 




enumerator kTPM_Chnl4InterruptEnable

Channel 4 interrupt. 




enumerator kTPM_Chnl5InterruptEnable

Channel 5 interrupt. 




enumerator kTPM_Chnl6InterruptEnable

Channel 6 interrupt. 




enumerator kTPM_Chnl7InterruptEnable

Channel 7 interrupt. 




enumerator kTPM_TimeOverflowInterruptEnable

Time overflow interrupt. 






enum _tpm_status_flags

List of TPM flags. 
Values:


enumerator kTPM_Chnl0Flag

Channel 0 flag 




enumerator kTPM_Chnl1Flag

Channel 1 flag 




enumerator kTPM_Chnl2Flag

Channel 2 flag 




enumerator kTPM_Chnl3Flag

Channel 3 flag 




enumerator kTPM_Chnl4Flag

Channel 4 flag 




enumerator kTPM_Chnl5Flag

Channel 5 flag 




enumerator kTPM_Chnl6Flag

Channel 6 flag 




enumerator kTPM_Chnl7Flag

Channel 7 flag 




enumerator kTPM_TimeOverflowFlag

Time overflow flag 






typedef enum _tpm_chnl tpm_chnl_t

List of TPM channels. 

Note
Actual number of available channels is SoC dependent 





typedef enum _tpm_pwm_mode tpm_pwm_mode_t

TPM PWM operation modes. 




typedef enum _tpm_pwm_level_select tpm_pwm_level_select_t

TPM PWM output pulse mode: high-true, low-true or no output. 

Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output. 





typedef enum _tpm_pwm_pause_level_select tpm_pwm_pause_level_select_t

TPM PWM output when first enabled or paused: set or clear. 




typedef enum _tpm_chnl_control_bit_mask tpm_chnl_control_bit_mask_t

List of TPM channel modes and level control bit mask. 




typedef struct _tpm_chnl_pwm_signal_param tpm_chnl_pwm_signal_param_t

Options to configure a TPM channel’s PWM signal. 




typedef enum _tpm_trigger_select tpm_trigger_select_t

Trigger sources available. 
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)

Note
The actual trigger sources available is SoC-specific. 





typedef enum _tpm_trigger_source tpm_trigger_source_t

Trigger source options available. 

Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger. 





typedef enum _tpm_ext_trigger_polarity tpm_ext_trigger_polarity_t

External trigger source polarity. 

Note
Selects the polarity of the external trigger source. 





typedef enum _tpm_output_compare_mode tpm_output_compare_mode_t

TPM output compare modes. 




typedef enum _tpm_input_capture_edge tpm_input_capture_edge_t

TPM input capture edge. 




typedef struct _tpm_dual_edge_capture_param tpm_dual_edge_capture_param_t

TPM dual edge capture parameters. 

Note
This mode is available only on some SoC’s. 





typedef enum _tpm_quad_decode_mode tpm_quad_decode_mode_t

TPM quadrature decode modes. 

Note
This mode is available only on some SoC’s. 





typedef enum _tpm_phase_polarity tpm_phase_polarity_t

TPM quadrature phase polarities. 




typedef struct _tpm_phase_param tpm_phase_params_t

TPM quadrature decode phase parameters. 




typedef enum _tpm_clock_source tpm_clock_source_t

TPM clock source selection. 




typedef enum _tpm_clock_prescale tpm_clock_prescale_t

TPM prescale value selection for the clock source. 




typedef struct _tpm_config tpm_config_t

TPM config structure. 
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 




typedef enum _tpm_interrupt_enable tpm_interrupt_enable_t

List of TPM interrupts. 




typedef enum _tpm_status_flags tpm_status_flags_t

List of TPM flags. 




typedef void (*tpm_callback_t)(TPM_Type *base)

TPM callback function pointer. 

Param base:
TPM peripheral base address. 






TPM_TIMEOUT

Max loops to wait for writing register. 
When writing MOD CnV CnSC and SC register, driver will wait until register is updated. This parameter defines how many loops to check completion before return timeout. If defined as 0, driver will wait forever until completion. 




TPM_MAX_COUNTER_VALUE(x)

Help macro to get the max counter value. 




struct _tpm_chnl_pwm_signal_param


#include <fsl_tpm.h>
Options to configure a TPM channel’s PWM signal. 

Public Members


tpm_chnl_t chnlNumber

TPM channel to configure. In combined mode (available in some SoC’s), this represents the channel pair number 




tpm_pwm_pause_level_select_t pauseLevel

PWM output level when counter first enabled or paused 




tpm_pwm_level_select_t level

PWM output active level select 




uint8_t dutyCyclePercent

PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle) 




uint8_t firstEdgeDelayPercent

Used only in combined PWM mode to generate asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure, leave as 0. Should be specified as percentage of the PWM period, (dutyCyclePercent + firstEdgeDelayPercent) value should be not greate than 100. 




bool enableComplementary

Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals; 




tpm_pwm_pause_level_select_t secPauseLevel

Used only in combined PWM mode. Define the second channel output level when counter first enabled or paused 




uint8_t deadTimeValue[2]

The dead time value for channel n and n+1 in combined complementary PWM mode. Deadtime insertion is disabled when this value is zero, otherwise deadtime insertion for channel n/n+1 is configured as (deadTimeValue * 4) clock cycles. deadTimeValue’s available range is 0 ~ 15. 







struct _tpm_dual_edge_capture_param


#include <fsl_tpm.h>
TPM dual edge capture parameters. 

Note
This mode is available only on some SoC’s. 


Public Members


bool enableSwap

true: Use channel n+1 input, channel n input is ignored; false: Use channel n input, channel n+1 input is ignored 




tpm_input_capture_edge_t currChanEdgeMode

Input capture edge select for channel n 




tpm_input_capture_edge_t nextChanEdgeMode

Input capture edge select for channel n+1 







struct _tpm_phase_param


#include <fsl_tpm.h>
TPM quadrature decode phase parameters. 

Public Members


uint32_t phaseFilterVal

Filter value, filter is disabled when the value is zero 




tpm_phase_polarity_t phasePolarity

Phase polarity 







struct _tpm_config


#include <fsl_tpm.h>
TPM config structure. 
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 

Public Members


tpm_clock_prescale_t prescale

Select TPM clock prescale value 




bool useGlobalTimeBase

true: The TPM channels use an external global time base (the local counter still use for generate overflow interrupt and DMA request); false: All TPM channels use the local counter as their timebase 




bool syncGlobalTimeBase

true: The TPM counter is synchronized to the global time base; false: disabled 




tpm_trigger_select_t triggerSelect

Input trigger to use for controlling the counter operation 




tpm_trigger_source_t triggerSource

Decides if we use external or internal trigger. 




tpm_ext_trigger_polarity_t extTriggerPolarity

when using external trigger source, need selects the polarity of it. 




bool enableDoze

true: TPM counter is paused in doze mode; false: TPM counter continues in doze mode 




bool enableDebugMode

true: TPM counter continues in debug mode; false: TPM counter is paused in debug mode 




bool enableReloadOnTrigger

true: TPM counter is reloaded on trigger; false: TPM counter not reloaded 




bool enableStopOnOverflow

true: TPM counter stops after overflow; false: TPM counter continues running after overflow 




bool enableStartOnTrigger

true: TPM counter only starts when a trigger is detected; false: TPM counter starts immediately 




bool enablePauseOnTrigger

true: TPM counter will pause while trigger remains asserted; false: TPM counter continues running 




uint8_t chnlPolarity

Defines the input/output polarity of the channels in POL register 







TSTMR: Timestamp Timer Driver#


void TSTMR_Init(TSTMR_Type *base)

Init TSTMR. 
This function initializes the TSTMR module.

Parameters:

base – TSTMR peripheral base address. 







void TSTMR_Deinit(TSTMR_Type *base)

Deinit TSTMR. 
This function deinitializes the TSTMR module.

Parameters:

base – TSTMR peripheral base address. 







FSL_TSTMR_DRIVER_VERSION

Version 2.1.0 




static inline uint64_t TSTMR_ReadTimeStamp(TSTMR_Type *base)

Reads the time stamp. 
This function reads the low and high registers and returns the 56-bit free running counter value. This can be read by software at any time to determine the software ticks. TSTMR registers can be read with 32-bit accesses only. The TSTMR LOW read should occur first, followed by the TSTMR HIGH read.

Parameters:

base – TSTMR peripheral base address.


Returns:
The 56-bit time stamp value. 






void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs)

Delays for a specified number of microseconds. 
This function repeatedly reads the timestamp register and waits for the user-specified delay value.

Parameters:

base – TSTMR peripheral base address. 
delayInUs – Delay value in microseconds. 







Xbar#


void XBAR_Init(xbar_instance_t xbarInstance)

Initializes the XBAR modules. 
This function un-gates the XBAR clock.

Parameters:

xbarInstance – XBAR peripheral address. 







void XBAR_Deinit(xbar_instance_t xbarInstance)

Shutdown the XBAR modules. 
This function disables XBAR clock.

Parameters:

xbarInstance – XBAR peripheral address. 







status_t XBAR_SetSignalsConnection(xbar_input_signal_t input, xbar_output_signal_t output)

Set connection between the selected XBAR_IN[*] input and the XBAR_OUT[*] output signal. 
This function connects the XBAR input to the selected XBAR output. If more than one XBAR module is available, only the inputs and outputs from the same module can be connected.
Example: 
XBAR_SetSignalsConnection(kXBAR_DSC1_InputLogicLow, kXBAR_DSC1_OutputTriggerSyncIn0);




Parameters:

input – XBAR input signal. 
output – XBAR output signal. 


Return values:

kStatus_Success – Signal connection set successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







status_t XBAR_ClearOutputStatusFlag(xbar_output_signal_t output)

Clears the edge detection status flags. 

Parameters:

output – XBAR output signal. 


Return values:

kStatus_Success – Signal connection set successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







status_t XBAR_GetOutputStatusFlag(xbar_output_signal_t output, bool *flag)

Gets the active edge detection status. 
This function gets the active edge detect status of all XBAR_OUTs. If the active edge occurs, the return value is asserted. When the interrupt or the DMA functionality is enabled for the XBAR_OUTx, this field is 1 when the interrupt or DMA request is asserted and 0 when the interrupt or DMA request has been cleared.

Parameters:

output – XBAR output signal. 
flag – get XBAR output status flag. 


Return values:

kStatus_Success – Signal connection set successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







status_t XBAR_SetOutputSignalConfig(xbar_output_signal_t output, const xbar_control_config_t *controlConfig)

Configures the XBAR control register. 
This function configures an XBAR control register. The active edge detection and the DMA/IRQ function on the corresponding XBAR output can be set.
Example: 
xbar_control_config_t userConfig;
userConfig.activeEdge = kXBAR_EdgeRising;
userConfig.requestType = kXBAR_RequestInterruptEnable;
XBAR_SetOutputSignalConfig(kXBARA_OutputDMAMUX18, &userConfig);




Parameters:

output – XBAR output signal. 
controlConfig – Pointer to structure that keeps configuration of control register. 


Return values:

kStatus_Success – Signal connection set successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







status_t XBAR_LockSelReg(xbar_output_signal_t output)

Lock the XBAR SEL register. 
When locked, the register can’t be written until reset the XBAR module.

Parameters:

output – XBAR output signal. 


Return values:

kStatus_Success – Register locked successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







status_t XBAR_LockCtrlReg(xbar_output_signal_t output)

Lock the XBAR CTRL register. 
When locked, the register can’t be written until reset the XBAR module.

Parameters:

output – XBAR output signal. 


Return values:

kStatus_Success – Register locked successfully. 
kStatus_InvalidArgument – Failed because of invalid argument. 







enum _xbar_active_edge

XBAR active edge for detection. 
Values:


enumerator kXBAR_EdgeNone

Edge detection status bit never asserts. 




enumerator kXBAR_EdgeRising

Edge detection status bit asserts on rising edges. 




enumerator kXBAR_EdgeFalling

Edge detection status bit asserts on falling edges. 




enumerator kXBAR_EdgeRisingAndFalling

Edge detection status bit asserts on rising and falling edges. 




enumerator kXBAR_EdgeMax

Max value. 






enum _xbar_request

Defines the XBAR DMA and interrupt configurations. 
Values:


enumerator kXBAR_RequestDisable

Interrupt and DMA are disabled. 




enumerator kXBAR_RequestDMAEnable

DMA enabled, interrupt disabled. 




enumerator kXBAR_RequestInterruptEnable

Interrupt enabled, DMA disabled. 




enumerator kXBAR_RequestMax

Max value. 






typedef uint16_t xbar_reg_t





typedef enum _xbar_active_edge xbar_active_edge_t

XBAR active edge for detection. 




typedef enum _xbar_request xbar_request_t

Defines the XBAR DMA and interrupt configurations. 




typedef struct _xbar_control_config xbar_control_config_t

Defines the configuration structure of the XBAR control register. 
This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers. 




FSL_XBAR_DRIVER_VERSION





struct xbar_info_t


#include <fsl_xbar.h>
Find the instance index from base address and register offset mappings. 




struct _xbar_control_config


#include <fsl_xbar.h>
Defines the configuration structure of the XBAR control register. 
This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers. 

Public Members


xbar_active_edge_t activeEdge

Active edge to be detected. 




xbar_request_t requestType

Selects DMA/Interrupt request. 







CACHE: CACHE Memory Controller#


uint32_t XCACHE_GetInstanceByAddr(uint32_t address)

brief Returns an instance number given physical memory address.
param address The physical memory address. 

Returns:
XCACHE instance number starting from 0. 






void XCACHE_EnableCache(XCACHE_Type *base)

Enables the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_DisableCache(XCACHE_Type *base)

Disables the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_InvalidateCache(XCACHE_Type *base)

Invalidates the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







void XCACHE_CleanCache(XCACHE_Type *base)

Cleans the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_CleanCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size. 







void XCACHE_CleanInvalidateCache(XCACHE_Type *base)

Cleans and invalidates the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and invalidate cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size. 







static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates instruction cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Clean data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size. 







FSL_CACHE_DRIVER_VERSION

cache driver version. 




XCACHE_LINESIZE_BYTE

cache line size. 




XSPI: Serial Peripheral Interface Driver#



Status structure of XSPI. 
Values:


enumerator kStatus_XSPI_Busy

XSPI is Busy 




enumerator kStatus_XSPI_IpCommandUsageError

XSPI Ip Command Usage Error 




enumerator kStatus_XSPI_IpCommandtriggerError

XSPI Ip Command Trigger Error 




enumerator kStatus_XSPI_IllegalInstructionError

XSPI Illegal Instruction Error 




enumerator kStatus_XSPI_SequenceExecutionTimeout

XSPI Sequence Execution Timeout 




enumerator kStatus_XSPI_FradCheckError

XSPI Frad Check Error 




enumerator kStatus_XSPI_TgQueueWritingError

XSPI Tg Queue Writing Error 




enumerator kStatus_XSPI_IpsBusTransError

XSPI Ip Bus Transfer Error 




enumerator kStatus_XSPI_AhbReadAccessAsserted

AHB read access is asserted. 




enumerator kStatus_XSPI_AhbWriteAccessAsserted

AHB write access is asserted. 




enumerator kStatus_XSPI_IPAccessAsserted

IP access is asserted. 




enumerator kStatus_XSPI_AhbSubBufferFactorError

Wrong sub buffer factor input. 




enumerator kStatus_XSPI_RegWriteLocked

Fail to write register due to write operation is locked. 




enumerator kStatus_XSPI_WaterMarkIllegal

The watermark value to set is not in multiple of 4 bytes. 




enumerator kStatus_XSPI_PageProgramWaitFlagAsserted

The page program wait flag already asserted. 




enumerator kStatus_XSPI_IpAccessAddrSettingInvalid

The input address for Ip access is invalid. 




enumerator kStatus_XSPI_RxBufferEntriesCountError

The count of entries of RX buffer is incorrect. 




enumerator kStatus_XSPI_IpAccessIPCRInvalid

Access attributes to write IPCR are not correct. 




enumerator kStatus_XSPI_IpAccessNotGranted

IP request not granted by arbiter. 




enumerator kStatus_XSPI_IpReadFinished

Finish IP read all data stored in buffer. 




enumerator kStatus_XSPI_IpWriteFinished

Finish IP write operation. 




enumerator kStatus_XSPI_TxBufferUnderrun

XSPI attempted to pull data when the TX buffer is empty. 




enumerator kStatus_XSPI_ArbiterGranted

XSPI arbiter granted. 






enum _xspi_lut_instr

CMD definition of XSPI, use to form LUT instruction, xspi_lut_instr_t. 
Values:


enumerator kXSPI_Command_STOP

Stop execution, de-assert CS. 




enumerator kXSPI_Command_SDR

Transmit Command code to Flash, using SDR mode. 




enumerator kXSPI_Command_RADDR_SDR

Transmit Row Address to Flash, using SDR mode. 




enumerator kXSPI_Command_DUMMY_SDR

Leave data lines un-driven by xSPI controller, using SDR mode. 




enumerator kXSPI_Command_MODE_SDR

Transmit 8-bit Mode bits to Flash, using SDR mode. 




enumerator kXSPI_Command_MODE2_SDR

Transmit 2-bit Mode bits to Flash, using SDR mode. 




enumerator kXSPI_Command_MODE4_SDR

Transmit 4-bit Mode bits to Flash, using SDR mode. 




enumerator kXSPI_Command_READ_SDR

Receive Read Data from Flash, using SDR mode. 




enumerator kXSPI_Command_WRITE_SDR

Transmit Programming Data to Flash, using SDR mode. 




enumerator kXSPI_Command_JMP_ON_CS

Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence 




enumerator kXSPI_Command_RADDR_DDR

Transmit Row Address to Flash, using DDR mode. 




enumerator kXSPI_Command_MODE_DDR

Transmit 8-bit Mode bits to Flash, using DDR mode. 




enumerator kXSPI_Command_MODE2_DDR

Transmit 2-bit Mode bits to Flash, using DDR mode. 




enumerator kXSPI_Command_MODE4_DDR

Transmit 4-bit Mode bits to Flash, using DDR mode. 




enumerator kXSPI_Command_READ_DDR

Receive Read Data from Flash, using DDR mode. 




enumerator kXSPI_Command_WRITE_DDR

Transmit Programming Data to Flash, using DDR mode. 




enumerator kXSPI_Command_LEARN_DDR

Receive Read Data or Preamble bit from Flash, DDR mode. 




enumerator kXSPI_Command_DDR

Transmit Command code to Flash, using DDR mode. 




enumerator kXSPI_Command_CADDR_SDR

Transmit Column Address to Flash, using SDR mode. 




enumerator kXSPI_Command_CADDR_DDR

Transmit Column Address to Flash, using DDR mode. 




enumerator kXSPI_Command_JUMP_TO_SEQ

Jump the LUT sequence pointed to by the operand. 






enum _xspi_pad

pad definition of XSPI, use to form LUT instruction. 
Values:


enumerator kXSPI_1PAD

Transmit command/address and transmit/receive data only through DATA0/DATA1. 




enumerator kXSPI_2PAD

Transmit command/address and transmit/receive data only through DATA[1:0]. 




enumerator kXSPI_4PAD

Transmit command/address and transmit/receive data only through DATA[3:0]. 




enumerator kXSPI_8PAD

Transmit command/address and transmit/receive data only through DATA[7:0]. 






enum _xspi_flags

XSPI interrupt status flags. 


Deprecated:
For Error flag please use xspi_error_flag_t as instead, for cmd execution and arbitration flag please use xspi_cmd_execution_arbitration_flag_t as instead. 



Values:


enumerator kXSPI_DataLearningFailedFlag

Data learning failed. 




enumerator kXSPI_DllAbortFlag

DLL Abort. 




enumerator kXSPI_DllUnlockFlag

This field is set whenever DLL unlock event occurs, irrespective of flash memory access. 




enumerator kXSPI_TxBufferFillFlag

If the field remains cleared, the TX buffer can be considered as full. 




enumerator kXSPI_TxBufferUnderrunFlag

This field is set if the module tries to pull data when the TX buffer is empty 




enumerator kXSPI_RxBufferOverflowFlag

This field is set when no more data can be pushed into the RX buffer from the serial flash memory device. 




enumerator kXSPI_RxBufferDrainFlag

This field is set if SR[RXWE] is asserted. 




enumerator kXSPI_AhbAbortErrorFlag

This flag can be set when AHB transaction error 




enumerator kXSPI_AhbIllegalTransactionErrorFlag





enumerator kXSPI_AhbIllegalBurstSizeErrorFlag

The total burst size is more than prefetch size. 




enumerator kXSPI_AhbBufferOverflowFlag

The size of the AHB access exceed the size of the AHB buffer. 




enumerator kXSPI_AhbPerformanceMonitorOverflowFlag

AHB performance hit or miss counter overflow. 




enumerator kXSPI_AhbReadAddressErrorFlag

The master send an AHB read address to that buffer is not within the address range of any sub-buffers or the address within multiple sub-buffers. 




enumerator kXSPI_IllegalInstructionErrorFlag

This field is set when an illegal instruction is encountered by the controller in any of the sequences. 




enumerator kXSPI_IpCmdtriggerErrorFlag

Write access to Rx buffer control reg when IP-triggered command is executing. 




enumerator kXSPI_PageProgramWaitFlag

Indicates assertion of the page-program wait flag after writing to flash memory. 




enumerator kXSPI_IpCommandExecutionDoneFlag

Indicates XSPI has completed a running IP command. 




enumerator kXSPI_SequenceExecutionTimeoutFlag

Sequence execution timeout. 




enumerator kXSPI_FradMatchErrorFlag





enumerator kXSPI_Frad0AccessErrorFlag





enumerator kXSPI_Frad1AccessErrorFlag





enumerator kXSPI_Frad2AccessErrorFlag





enumerator kXSPI_Frad3AccessErrorFlag





enumerator kXSPI_Frad4AccessErrorFlag





enumerator kXSPI_Frad5AccessErrorFlag





enumerator kXSPI_Frad6AccessErrorFlag





enumerator kXSPI_Frad7AccessErrorFlag





enumerator kXSPI_Frad8AccessErrorFlag





enumerator kXSPI_Frad9AccessErrorFlag





enumerator kXSPI_Frad10AccessErrorFlag





enumerator kXSPI_Frad11AccessErrorFlag





enumerator kXSPI_Frad12AccessErrorFlag





enumerator kXSPI_Frad13AccessErrorFlag





enumerator kXSPI_Frad14AccessErrorFlag





enumerator kXSPI_Frad15AccessErrorFlag





enumerator kXSPI_FradnAccErrorFlag

ORed value of all frad error flag,. 




enumerator kXSPI_IpsErrorFlag





enumerator kXSPI_TgnSfarErrorFlag





enumerator kXSPI_TgnIpcrErrorFlag





enumerator kXSPI_LockRegErrorFlag





enumerator kXSPI_ArbLockTimeoutFlag





enumerator kXSPI_ArbWinEventFlag







enum _xspi_error_flag

The enumeration of error flags. . 
Values:


enumerator kXSPI_ErrorNoFradMatch

The transaction address does not lie within the address range of any FRAD. 




enumerator kXSPI_ErrorFrad0Access

The transaction address lies within the address range of the FRAD0 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad1Access

The transaction address lies within the address range of the FRAD1 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad2Access

The transaction address lies within the address range of the FRAD2 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad3Access

The transaction address lies within the address range of the FRAD3 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad4Access

The transaction address lies within the address range of the FRAD4 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad5Access

The transaction address lies within the address range of the FRAD5 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad6Access

The transaction address lies within the address range of the FRAD6 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad7Access

The transaction address lies within the address range of the FRAD7 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock by another manager. 




enumerator kXSPI_ErrorFrad8Access





enumerator kXSPI_ErrorFrad9Access





enumerator kXSPI_ErrorFrad10Access





enumerator kXSPI_ErrorFrad11Access





enumerator kXSPI_ErrorFrad12Access





enumerator kXSPI_ErrorFrad13Access





enumerator kXSPI_ErrorFrad14Access





enumerator kXSPI_ErrorFrad15Access





enumerator kXSPI_ErrorIpBusTransfer

A common error has occurred and XSPI has generated an IPS bus transfer error. 




enumerator kXSPI_ErrorTg0Sfar

An SFAR write trigger an error while written to the TG0. 




enumerator kXSPI_ErrorTg0Ipcr

An IPCR write trigger an error while written to the TG0. 




enumerator kXSPI_ErrorTimeout

A flash memory transaction has triggered a timeout error and has been terminated by SFP. 




enumerator kXSPI_ArbitrationWin

The target group request was granted access. 




enumerator kXSPI_ErrorArbitrationLock

Arbitration lock has timed out. 




enumerator kXSPI_ErrorWriteLockedReg

An attempt to write a locked register. 




enumerator kXSPI_ErrorAllFlags







enum _xspi_cmd_execution_arbitration_flag

The enumeration of cmd execution and arbitration. . 
Values:


enumerator kXSPI_FlagIpCmdFinished

IP command transaction finished flag. 




enumerator kXSPI_FlagAhbReadAddrError

Wrong AHB read address, XSPI return AHB error payload. 




enumerator kXSPI_FlagAhbPerformanceMonitorOverflow

Buffer hit or miss counter overflow. 




enumerator kXSPI_FlagIpCmdTriggerFail

Fail when set IP RX buffer watermark. 




enumerator kXSPI_FlagPageProgramWait

Indicate assertion of the page-program wait flag after writing to flash memory. 




enumerator kXSPI_FlagAhbBufferOverflow

The size of the AHB access exceeds the size of AHB buffer. 




enumerator kXSPI_FlagAhbIllegalBurstSizeError

The total burst size of the AHB transacton is greater than the prefetch data size. 




enumerator kXSPI_FlagAhbIllegalTransactionError

XSPI has not generated a response to the AHB bus due to an illegal transaction and expiration of the watchdog timer. 




enumerator kXSPI_FlagAhbTransactionError

AHB transaction error. 




enumerator kXSPI_FlagRxBufferWatermarkExceeded

The RX buffer watermark has been exceeded. 




enumerator kXSPI_FlagRxBufferOverflow

The RX buffer cannot receive any more data from the SFM device. 




enumerator kXSPI_FlagIllegalInstrError

The xspi encountered an illegal instruction in any sequence. 




enumerator kXSPI_FlagDllUnlock

DLL unlock. 




enumerator kXSPI_FlagTxBufferUnderRun

XSPI attempt to pull data when the TX buffer is empty. 




enumerator kXSPI_FlagTxBufferFill

The TX buffer is filling. 




enumerator kXSPI_FlagDllAbort

DLL terminate. 




enumerator kXSPI_FlagDataLearningPatternFailure

The XSPI encountered a DATA_LEARN instruction in a sequence, but no sampling point is found for the data learning pattern. 






enum _xspi_interrupt_enable


Values:


enumerator kXSPI_TransactionFinishIntEnable

Enable generation of an interrupt when an IP command transaction completes. 




enumerator kXSPI_AhbReadAddrErrorIntEnable

Enable generation of an interrupt on occurrence of an AHB read address error. 




enumerator kXSPI_AhbPerformanceMonitorOverflowIntEnable

Enable generation of an interrupt on a buffer hit or miss counter overflow. 




enumerator kXSPI_IpCmdTrigFailErrorIntEnable

IP command trigger fail error interrupt enable. 




enumerator kXSPI_PageProgramWaitIntEnable

Enable generation of an interrupt on page-program wait. 




enumerator kXSPI_AhbBufferOverflowIntEnable

Enable generation of an interrupt on occurrence of an AHB buffer overflow. 




enumerator kXSPI_AhbIllegalBurstSizeErrorIntEnable

Enable generation of an interrupt on occurrence of an AHB illegal burst size error. 




enumerator kXSPI_AhbIllegalTransactionErrorIntEnable

Enable generation of an interrupt of an AHB illegal transaction error. 




enumerator kXSPI_AhbAbortErrorIntEnable

Enable generation of an interrupt on occurrence of an AHB abort error. 




enumerator kXSPI_RxBufferDrainIntEnable

Enable generation of an interrupt on occurrence of RX buffer drain. 




enumerator kXSPI_RxBufferOverflowIntEnable

Enable generation of an interrupt on occurrence of RX buffer overflow. 




enumerator kXSPI_IllegalInstrErrorIntEnable

Enable generation of an interrupt on occurrence of an illegal instruction error. 




enumerator kXSPI_DllUnlockIntEnable

Enable generation of an interrupt on a DLL unlock event. 




enumerator kXSPI_TxBufferUnderrunIntEnable

Enable generation of an interrupt on TX buffer underrun. 




enumerator kXSPI_TxBufferFillIntEnable

Enable generation of an interrupt on TX buffer fill. 




enumerator kXSPI_DataLearningPatternFailIntEnable

Enable generation of an interrupt on data learning pattern failure. 




enumerator kXSPI_NoFradMatchErrorIntEnable

Enable the interrupt generated when the transaction address does not lie within the address range of any FRAD. 




enumerator kXSPI_Frad0AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD0 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad1AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD1 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad2AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD2 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad3AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD3 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad4AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD4 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad5AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD5 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad6AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD6 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad7AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD7 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad8AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD0 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad9AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD9 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad10AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD10 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad11AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD11 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad12AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD12 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad13AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD13 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad14AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD14 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_Frad15AccessErrorIntEnable

Enable the interrupt generated when the transaction address lies within the address range of the FRAD15 but it does not pass the access permission checks for the FRAD or the FRAD is under exclusive lock. 




enumerator kXSPI_IpsErrIntEnable

Enable the interrupt generated when a common error has occurred an XSPI has generated an IPS bus transfer error. 




enumerator kXSPI_Tg0SfarErrIntEnable

Enable the interrupt generated when an SFAR write triggers an error while being written to the target group 0. 




enumerator kXSPI_Tg0IpcrErrIntEnable

Enable the interrupt generated when an IPCR write triggers an error while being written to the target group 0. 




enumerator kXSPI_TimeoutErrIntEnable

Enable the interrupt generated when a flash memory transaction triggers a timeout error and has been terminated by SFP. 




enumerator kXSPI_ArbitrationWinIntEnable

Enable the interrupt generated when the target group queue request is granted access. 




enumerator kXSPI_ArbitrationLockTimeoutErrIntEnable

Enable the interrupt generated when a flash memory transaction triggers a timeout error and has been terminated by SFP. 




enumerator kXSPI_LockRegWriteErrIntEnable

Enable the interrupt generated by an attempt to write a locked register. 






enum _xspi_external_signal

The enumeration of Idle signal drive IOFA[3] and IOFA[2]. 
Values:


enumerator XSPI_SignalIOFA2

Idle signal drive IOFA[2]. 




enumerator XSPI_SignalIOFA3

Idle signal drive IOFA[3]. 






enum _xspi_dll_mode

Dll Mode enumerations. 
Values:


enumerator kXSPI_AutoUpdateMode

Dll mode : Auto update mode. 




enumerator kXSPI_BypassMode

Dll mode : Bypass mode. 






enum _xspi_sample_clk_source

The enumeration of sample clock source which is used to sample data from external devices. 

Note
If external device support Data strobe signal, the sample clock should selected as kXSPI_SampleClkFromExternalDQS. 

Values:


enumerator kXSPI_SampleClkFromNonInvertedFullySpeedDummyPadLoopback

Sample clock from non inverted fully speed dummy pad loopback. 




enumerator kXSPI_SampleClkFromInvertedFullySpeedDummyPadLoopback

Sample clock from inverted fully speed dummy pad loopback. 




enumerator kXSPI_SampleClkFromHalfSpeedDummyPadLoopback

Sample clock from half fully speed dummy pad loopback. 




enumerator kXSPI_SampleClkFromDqsPadLoopback

Sample clock from Dqs pad loopback. 




enumerator kXSPI_SampleClkFromExternalDQS

Sample clock from external DQS signal. 






enum _xspi_data_learning_pad_select

The selection of data learning pad. 
Values:


enumerator kXSPI_OnlyIO1

IO1 selected as pad to use for pattern matching IO. 




enumerator kXSPI_BothIO1IO3

IO1 and IO3 selected as pad to use for pattern matching IO. 






enum _xspi_device_addr_mode

External device’s address mode. 
Values:


enumerator kXSPI_DeviceByteAddressable

Byte addressable. 




enumerator kXSPI_Device2ByteAddressable

Two bytes addressable. 




enumerator kXSPI_Device4ByteAddressable

Four bytes addressable. 






enum _xspi_device_interface_type

The enumeration of external device’s interface type, hyper bus or SPI(including strandard and extended). 

Note
Different interface result different settings. 

Values:


enumerator kXSPI_StrandardExtendedSPI

External device follow SPI protocol, DQS_OUT_EN must be 0 




enumerator kXSPI_HyperBus

External device follow hyper Bus protocol, DQS_OUT_EN must be 1 






enum _xspi_hyper_bus_x16_mode

The enumeration of hyper bus X16 mode. 
Values:


enumerator kXSPI_x16ModeDisable

X16 mode is disabled. 




enumerator kXSPI_x16ModeEnabledOnlyData

X16 mode is enabled only for data. 




enumerator kXSPI_x16ModeEnabledAddrCmdData

X16 mode is enabled for address, command, and data. 






enum _xspi_ddr_data_aligned_clk

Enumeration defining the alignment modes of XSPI DDR data with respect to the internal reference clock. 
Values:


enumerator kXSPI_DDRDataAlignedWithInternalRefClk

DDR data aligned with internal reference clock. 




enumerator kXSPI_DDRDataAlignedWith2xInternalRefClk

DDR data aligned with 2X internal reference clock. 






enum _xspi_command_type

Command type. 
Values:


enumerator kXSPI_Command

XSPI operation: Only command, both TX and Rx buffer are ignored. 




enumerator kXSPI_Config

XSPI operation: Configure device mode, the TX fifo size is fixed in LUT. 




enumerator kXSPI_Read

XSPI operation: Read, only Rx Buffer is effective. 




enumerator kXSPI_Write

XSPI operation: Read, only Tx Buffer is effective. 






enum _xspi_mdad_mask_type

The enumeration of SFP MDAD mask type. 
Values:


enumerator kXSPI_MdadMaskTypeAnd

Target master is mask & reference. 




enumerator kXSPI_MdadMaskTypeOr

Target master is mask | reference. 






enum _xspi_mdad_error_reason

The enumeration of MDAD error reasons. 
Values:


enumerator kXSPI_ErrorOnlyDataSize

Error reason: Only Data size without required attributes. 




enumerator kXSPI_ErrorOnlySeqId

Error reason: Only sequence ID without required attributes. 




enumerator kXSPI_ErrorBothDataSizeSeqId

Error reason: Both Data size and sequence ID without required attributes. 






enum _xspi_exclusive_access_lock_mode

Exclusive access lock. 
Values:


enumerator kXSPI_ExclusiveAccessLockDisabled

Write permissions available for all masters based on their MDxACP evaluation. 




enumerator kXSPI_ExclusiveAccessLockEnabled

Write permissions revoked for all domains, Any write transaction coming to this flash address will result in an error.. 




enumerator kXSPI_ExclusiveAccessLockExceptMasterId

Write permissions are revoked for all masters except the master ID specified by FRADn_WORD2[EALO] fields. 






enum _xspi_secure_attribute

XSPI defines the secure attribute selection criteria for entry into descriptor queue… 
Values:


enumerator kXSPI_AttributeMasterNonsecureOnly

Allow the bus attribute for this master to non-secure only 




enumerator kXSPI_AttributeMasterSecureOnly

Allow the bus attribute for this master to secure only 




enumerator kXSPI_AttributeMasterNonsecureSecureBoth

Allow the bus master’s attribute: Both secure and non-secure 






enum _xspi_descriptor_lock

Descriptor lock. 
Values:


enumerator kXSPI_DescriptorLockDisabled

Descriptor registers can be written by any master 




enumerator kXSPI_DescriptorLockEnabledTillHardReset

FRAD descriptor is read-only till next hard reset. 




enumerator kXSPI_DescriptorLockEnabledExceptMasterId

Descriptors are read-only. MDnACP fields can be programmed only by the master with ID matching the MID. 




enumerator kXSPI_DescriptorLockEnabled

Descriptor registers are read-only. 






enum _xspi_target_group

The enumeration of target group. 
Values:


enumerator kXSPI_TargetGroup0

Target groupe queue 0 




enumerator kXSPI_TargetGroup1

Target groupe queue 1 






enum _xspi_subbuffer_division_factor

Subbuffer division factor. 
Values:


enumerator kXSPI_Division0

division factor 0 




enumerator kXSPI_Division2

division factor 2 subbuffer size/2 




enumerator kXSPI_Division4

division factor 4 subbuffer size/4 




enumerator kXSPI_Division8

division factor 8 subbuffer size/8 




enumerator kXSPI_Division16

division factor 16 subbuffer size/16 






enum _xspi_ahb_sub_buffer_status

The enumeration of sub buffer status, empty, full, or partially full. 
Values:


enumerator kXSPI_AhbSubBufferEmpty

Current sub buffer is empty. 




enumerator kXSPI_AhbSubBufferFull

Current sub buffer is full. 




enumerator kXSPI_AhbSubBufferPartiallyFull

Current sub buffer contains some entries. 






enum _xspi_ppw_flag_clear_policy

The enumeration of XSPI page program waiting flag clear policy. 
Values:


enumerator kXSPI_SoftwareClearPPWFlag

Application should clear the flag manually, after check the WIP of external flag is cleared. 




enumerator kXSPI_HardwareClearPPWFlag

The flag is cleared by hardware automatically, the variable in type of xspi_device_status_reg_info_t should be defined. 






enum _xspi_ahb_split_size

XSPI AHB Split Size These bits are used to control the split size when split function is enabled BFGENCR[SPLITEN] is ‘1’. 
Values:


enumerator kXSPI_AhbSplitSize8b

Enable AHB transaction split and split size is 8 bytes. 




enumerator kXSPI_AhbSplitSize16b

Enable AHB transaction split and split size is 16 bytes. 




enumerator kXSPI_AhbSplitSize32b

Enable AHB transaction split and split size is 32 bytes. 




enumerator kXSPI_AhbSplitSize64b

Enable AHB transaction split and split size is 64 bytes. 




enumerator kXSPI_AhbSplitSizeDisabled

Disable AHB Transaction Split feature. 






enum _xspi_ahb_alignment

XSPI AHB access towards flash is broken if this AHB alignment boundary is crossed. This field is only supported XSPI0 XSPI1. 
Values:


enumerator kXSPI_AhbAlignmentNoLimit

no limit 




enumerator kXSPI_AhbAlignment256BLimit

256B limit 




enumerator kXSPI_AhbAlignment512BLimit

512B limit 




enumerator kXSPI_AhbAlignment1KBLimit

1KB limit 






enum _xspi_ahb_request_suspend_state

The enumeration of AHB request suspend state. 
Values:


enumerator kXSPI_AhbRequestNoSuspended

None of AHB request is suspended. 




enumerator kXSPI_AhbRequestSuspended

The AHB request is suspended. 




enumerator kXSPI_AhbRequestNotApplicable

The AHB request is not applicable. 




enumerator kXSPI_AhbReqestResumed

The AHB request is resumed. 






enum _xspi_otfad_prefetch_boundary

The enumeration of OTFAD prefetch address boundary. 
Values:


enumerator kXSPI_OTFADPrefetchNoBoundary

No prefetch address boundary. 




enumerator kXSPI_OTFADPrefetchBoundary1K

Prefetch address boundary is 1K. 






enum _xspi_byte_order

Byte ordering endianness. 
Values:


enumerator kXSPI_64BitBE

64 bit big endian 




enumerator kXSPI_32BitLE

32 bit little endian 




enumerator kXSPI_32BitBE

32 bit big endian 




enumerator kXSPI_64BitLE

64 bit little endian 






typedef enum _xspi_lut_instr xspi_lut_instr_t

CMD definition of XSPI, use to form LUT instruction, xspi_lut_instr_t. 




typedef enum _xspi_pad xspi_pad_t

pad definition of XSPI, use to form LUT instruction. 




typedef enum _xspi_flags xspi_flags_t

XSPI interrupt status flags. 


Deprecated:
For Error flag please use xspi_error_flag_t as instead, for cmd execution and arbitration flag please use xspi_cmd_execution_arbitration_flag_t as instead. 







typedef struct _xspi_device_status_reg_info xspi_device_status_reg_info_t

The structure of external device’s status register information(location, priority). 

Note
Only useful when AHB write to flash device is enabled, and use hardware to clear ppw flag. 





typedef enum _xspi_dll_mode xspi_dll_mode_t

Dll Mode enumerations. 




typedef union _xspi_dll_para xspi_dll_para_t

The union of user custommed DLL parameters, in case of kXSPI_BypassMode bypassModePara is used, in case of kXSPI_AutoUpdateMode autoUpdateModoPara is used. 




typedef struct _xspi_dll_config xspi_dll_config_t

The structure of Delay-lock-loop configuration. 




typedef enum _xspi_sample_clk_source xspi_sample_clk_source_t

The enumeration of sample clock source which is used to sample data from external devices. 

Note
If external device support Data strobe signal, the sample clock should selected as kXSPI_SampleClkFromExternalDQS. 





typedef enum _xspi_data_learning_pad_select xspi_data_learning_pad_select_t

The selection of data learning pad. 




typedef struct _xspi_data_learning_config xspi_data_learning_config_t

The configuration of data learning. 

Note
Data learning feature only supported in the DQS sampling method(kXSPI_SampleClkFromExternalDQS). 





typedef struct _xspi_sample_clk_config xspi_sample_clk_config_t

Sample clock configuration, which used to sample data from external device. 




typedef enum _xspi_device_addr_mode xspi_device_addr_mode_t

External device’s address mode. 




typedef enum _xspi_device_interface_type xspi_device_interface_type_t

The enumeration of external device’s interface type, hyper bus or SPI(including strandard and extended). 

Note
Different interface result different settings. 





typedef enum _xspi_hyper_bus_x16_mode xspi_hyper_bus_x16_mode_t

The enumeration of hyper bus X16 mode. 




typedef union _xspi_device_interface_settings xspi_device_interface_settings_t

The union of external device’s settings, if external device following hyper bus protocol #hyperBusSettings take effects, if external device following SPI protocol #strandardExtendedSPISettings take effects. 




typedef enum _xspi_ddr_data_aligned_clk xspi_ddr_data_aligned_clk_t

Enumeration defining the alignment modes of XSPI DDR data with respect to the internal reference clock. 




typedef struct _xspi_device_ddr_config xspi_device_ddr_config_t

The structure of device DDR configuration. 




typedef struct _xspi_device_config xspi_device_config_t

External device configuration items. 




typedef enum _xspi_command_type xspi_command_type_t

Command type. 




typedef enum _xspi_mdad_mask_type xspi_mdad_mask_type_t

The enumeration of SFP MDAD mask type. 




typedef enum _xspi_mdad_error_reason xspi_mdad_error_reason_t

The enumeration of MDAD error reasons. 




typedef enum _xspi_exclusive_access_lock_mode xspi_exclusive_access_lock_mode_t

Exclusive access lock. 




typedef enum _xspi_secure_attribute xspi_secure_attribute_t

XSPI defines the secure attribute selection criteria for entry into descriptor queue… 




typedef struct _xspi_mdad_config xspi_mdad_config_t

MDAD configuration. 




typedef struct _xspi_sfp_mdad_config xspi_sfp_mdad_config_t

The structure of SFP MDAD configurations for all target groups. 




typedef enum _xspi_descriptor_lock xspi_descriptor_lock_t

Descriptor lock. 




typedef struct _xspi_frad_tg_config xspi_frad_tg_config_t

FRAD configuration. 




typedef struct _xspi_frad_config_t xspi_frad_config_t

FRAD configuration. 




typedef struct _xspi_sfp_frad_config xspi_sfp_frad_config_t

The structure of SFP FRAD configurations. 




typedef struct _xspi_frad_transaction_info xspi_frad_transaction_info_t

The structure of latest FRAD transaction information. 




typedef struct _xspi_ip_access_config xspi_ip_access_config_t

Configurations of IP access(including IP read and write). 




typedef enum _xspi_target_group xspi_target_group_t

The enumeration of target group. 




typedef struct _xspi_tg_add_write_status xspi_tg_add_write_status_t

The status of latest target group address write operation. 




typedef struct _xspi_transfer xspi_transfer_t

Transfer structure used for XSPI functional interface. 




typedef struct _xspi_handle xspi_handle_t





typedef void (*xspi_transfer_callback_t)(XSPI_Type *base, xspi_handle_t *handle, status_t status, void *userData)

XSPI transfer callback function. 




typedef enum _xspi_subbuffer_division_factor xspi_subbuffer_division_factor_t

Subbuffer division factor. 




typedef struct _xspi_ahbBuffer_sub_buffer_config xspi_ahbBuffer_sub_buffer_config_t

The structure of sub-buffer configurations. 




typedef struct _xspi_ahbBuffer_config xspi_ahbBuffer_config_t

Structure of AHB buffer configurations. 

Note
When an AHB read access comes it is assigned to a buffer based on its master ID. Then it further assigned to a sub-buffer based on which sub-buffer address range this transaction lies into.


Note
When sub-buffer division is hit, in case of a buffer miss the controller will fetch the data equal to the size of that sub-buffer.


Note
If sub-buffer division is enabled for a buffer the hit/miss check is done at sub-buffer level. And if prefetch is enable, the prefetch takes place for individual sub-buffers. 





typedef enum _xspi_ahb_sub_buffer_status xspi_ahb_sub_buffer_status_t

The enumeration of sub buffer status, empty, full, or partially full. 




typedef struct _xspi_ahbBuffer_perf_monitor_result xspi_ahbBuffer_perf_monitor_result_t

The result of AHB buffer performance monitor, including buffer miss count and buffer hit count. 




typedef enum _xspi_ppw_flag_clear_policy xspi_ppw_flag_clear_policy_t

The enumeration of XSPI page program waiting flag clear policy. 




typedef struct _xspi_ahb_write_config xspi_ahb_write_config_t

The configuration of AHB write access. 




typedef enum _xspi_ahb_split_size xspi_ahb_split_size_t

XSPI AHB Split Size These bits are used to control the split size when split function is enabled BFGENCR[SPLITEN] is ‘1’. 




typedef enum _xspi_ahb_alignment xspi_ahb_alignment_t

XSPI AHB access towards flash is broken if this AHB alignment boundary is crossed. This field is only supported XSPI0 XSPI1. 




typedef struct _xspi_ahb_access_config xspi_ahb_access_config_t

The structure of AHB access configurations, including AHB buffer settings, AHB Read Seq ID, AHB write settings. 




typedef struct _xspi_ahb_read_error_info xspi_ahb_read_error_info_t

The structure of information when AHB read error occur. 




typedef enum _xspi_ahb_request_suspend_state xspi_ahb_request_suspend_state_t

The enumeration of AHB request suspend state. 




typedef struct _xspi_ahb_request_suspend_info xspi_ahb_request_suspend_info_t

The structure of information when AHB reqest is suspended. 




typedef enum _xspi_otfad_prefetch_boundary xspi_otfad_prefetch_boundary_t

The enumeration of OTFAD prefetch address boundary. 




typedef enum _xspi_byte_order xspi_byte_order_t

Byte ordering endianness. 




typedef struct _xspi_config xspi_config_t

XSPI configuration structure. 




FSL_XSPI_DRIVER_VERSION





XSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)

Formula to form XSPI instructions in LUT table. 




XSPI_TARGET_GROUP_COUNT





XSPI_SFP_FRAD_COUNT





XSPI_TG_REG_ADDR(base, tg, reg)





XSPI_TG_REG_VAL(base, tg, reg)





XSPI_TG_REG_ADDR_RBDR(base, tg)





XSPI_TG_REG_VAL_RBDR_INDEX(base, tg, i)





XSPI_TG_REG_ADDR_INT_EN(base, tg)





XSPI_TG_REG_ADDR_RSER(base, tg)





XSPI_IP_RX_BUFFER_SIZE





XSPI_IP_TX_BUFFER_SIZE





uint32_t XSPI_GetInstance(XSPI_Type *base)

Get the instance number for XSPI. 

Parameters:

base – XSPI base pointer. 







status_t XSPI_CheckAndClearErrorTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t status)

Check and clear IP command execution errors. 

Parameters:

base – XSPI base pointer. 
tgId – Specify the target group. 
status – interrupt status. 







void XSPI_Init(XSPI_Type *base, const xspi_config_t *ptrConfig)

Initializes the XSPI module and internal state. 
This function configures the XSPI with the input configure parameters. Users should call this function before any XSPI operations.

Parameters:

base – XSPI peripheral base address. 
ptrConfig – XSPI configure structure. 







void XSPI_GetDefaultConfig(xspi_config_t *ptrConfig)

Gets default settings for XSPI. 

Warning
The parameter devconfig will be removed in next release.


Parameters:

base – XSPI peripheral base address. 
ptrConfig – XSPI configuration structure. 







void XSPI_Deinit(XSPI_Type *base)

Deinitialize the XSPI module. 
Clears the XSPI state and XSPI module registers. 

Parameters:

base – XSPI peripheral base address. 
devconfig – Flash configuration parameters. 







void XSPI_UpdateLUT(XSPI_Type *base, uint8_t index, const uint32_t *cmd, uint8_t count)

Updates the LUT table. 

Parameters:

base – XSPI peripheral base address. 
index – From which index start to update. It could be any index of the LUT table, which also allows user to update command content inside a command. Each command consists of up to 10 instructions and occupy 5*32-bit memory. 
cmd – Command sequence array. 
count – Number of instruction-operand pairs 







static inline void XSPI_UpdateByteOrder(XSPI_Type *base, xspi_byte_order_t byteOrder)





static inline void XSPI_EnableModule(XSPI_Type *base, bool enable)

Enable or disable the XSPI module. 

Parameters:

base – XSPI peripheral base address. 
enable – true means enable XSPI, false means disable. 







static inline bool XSPI_CheckModuleEnabled(XSPI_Type *base)

Check if the XSPI module is enabled. 

Parameters:

base – XSPI peripheral base address.


Return values:

true – XSPI module is enabled. 
false – XSPI module is disabled. 







void XSPI_ResetSfmAndAhbDomain(XSPI_Type *base)

Reset Serial flash memory domain and AHB domain at the same time. 

Note
Resetting only the Serial flash memory domain and AHB domain may cause undesirable side effects.


Parameters:

base – XSPI peripheral base address. 







static inline void XSPI_ResetTgQueueTG(XSPI_Type *base, xspi_target_group_t tgId)

Reset IPS target group queue. 

Parameters:

base – XSPI peripheral base address. 
tgId – Target group ID. 







static inline void XSPI_SoftwareReset(XSPI_Type *base)

Software reset flash memory domain, AHB domain, and Target group at the same time. 

Parameters:

base – XSPI peripheral base address. 







static inline bool XSPI_CheckGlobalConfigLocked(XSPI_Type *base)

Check if write access to registers(MGC, MRC, MTO, SFP_ARB_TIMEOUT, SFP_LUT_ENn, LUTn, BFGENCR) is locked. 

Parameters:

base – XSPI peripheral base address.


Return values:

false – Write access to listed registers is not locked. 
true – Write access to listed registers is locked. 







void XSPI_SetHyperBusX16Mode(XSPI_Type *base, xspi_hyper_bus_x16_mode_t x16Mode)

Set Hyper bus X16 mode. 

Parameters:

base – XSPI peripheral base address. 
x16Mode – Specify X16 mode. 







status_t XSPI_UpdateDeviceAddrMode(XSPI_Type *base, xspi_device_addr_mode_t addrMode)

Update address mode to access external device. 

Parameters:

base – XSPI peripheral base address. 
addrMode – Specify the address mode to update.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail to update address mode due to AHB read access asserted. 
kStatus_XSPI_IPAccessAsserted – Fail to update address mode due to a IP access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail to update address mode due to AHB write access asserted. 
kStatus_Success – Successfully to update address mode. 







static inline void XSPI_EnableVariableLatency(XSPI_Type *base, bool enable)

Enable/disable variable latency for XSPI. 

Note
Only useful for hyper bus device. 


Note
It is application responsibility to enable variable latency for external hyper bus device(by change device’s register).


Parameters:

base – XSPI peripheral base address. 
enable – Specify operation:

true Enable variable latency;
false Disable variable latency. 









static inline void XSPI_EnableDozeMode(XSPI_Type *base, bool enable)

Enable/disable Doze mode for XSPI controller. 

Note
Once doze mode is enabled, the XSPI controller will enter disable mode when system in low power modes.


Parameters:

base – XSPI peripheral base address 
enable – Specify operation:

true Enable Doze mode;
false Disable Doze mode. 









static inline void XSPI_SetSignalOutputValue(XSPI_Type *base, uint32_t signalMask, bool outputLogic)

Specify the logic level of the XSPI IOFA[3] and IOFA[2] output in the inactive state. 

Parameters:

base – XSPI peripheral base address 
signalMask – Should be the OR’ed value of _xspi_external_signal. 
outputLogic – Output logic of selected signals,

false Output logic 0;
true Output logic 1. 









static inline void XSPI_EnableInvertedSerialClockOutput(XSPI_Type *base, bool enable)

Enable/disable inverted serial clock output for XSPI controller. 

Note
It is application responsibility to enable CLKn for external device(by change device’s register).


Parameters:

base – [in] XSPI peripheral base address 
enable – [in] Enable/disable inverted serial clock output:

true Enable inverted serial clock output;
false Disable inverted serial clock output. 









void XSPI_UpdateDllValue(XSPI_Type *base, xspi_dll_config_t *ptrDllConfig, bool enableDDR, bool enableX16Mode, uint32_t xspiRootClk)

Update DLL configuration. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrDllConfig – [in] Pointer to the DLL configuration. 
enableDDR – [in] DDR mode is enabled or not. 
enableX16Mode – [in] X16 mode is enabled or not. 
xspiRootClk – [in] The frequency of xspi root clock, the unit is Hz. 







status_t XSPI_SetDataLearningConfig(XSPI_Type *base, xspi_data_learning_config_t *ptrDataLearningConfig)

Set Data learning configurations. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrDataLearningConfig – [in] Pointer to data learning configuration.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail to set data learning configuration due to AHB read access asserted. 
kStatus_XSPI_IPAccessAsserted – Fail to set data learning configuration due to a IP access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail to set data learning configuration due to AHB write access asserted. 
kStatus_Success – Successfully to set Data learning configurations. 







static inline bool XSPI_CheckDataLearningFailure(XSPI_Type *base)

Check if data learning failure has detected. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

true – Data learning has failed. 
false – Data learning not fail. 







static inline void XSPI_GetDataLearningEdgeMatchSignature(XSPI_Type *base, uint8_t *posEdgeMatch, uint8_t *negEdgeMatch)

Get data learning positive and negative edge match signature. 

Parameters:

base – [in] XSPI peripheral base address. 
posEdgeMatch – [out] Pointer to the memory to store positive edge match signature. 
negEdgeMatch – [out] Pointer to the memory to store negative edge match signature. 







status_t XSPI_SetDeviceConfig(XSPI_Type *base, xspi_device_config_t *devConfig)

Set device configuration. 

Parameters:

base – [in] XSPI peripheral base address. 
devConfig – [in] Pointer to device configuration.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail to set device configuration due to AHB read access asserted. 
kStatus_XSPI_IPAccessAsserted – Fail to set device configuration due to a IP access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail to set device configuration due to AHB write access asserted. 
kStatus_Success – Successfully to set device configurations. 







static inline void XSPI_EnableInterruptsTG(XSPI_Type *base, xspi_target_group_t tgId, uint64_t mask)

Enables the XSPI interrupts for specific target group. 

Parameters:

base – XSPI peripheral base address. 
tgId – Target group ID. 
mask – XSPI interrupt source mask. 







static inline void XSPI_DisableInterruptsTG(XSPI_Type *base, xspi_target_group_t tgId, uint64_t mask)

Disables the XSPI interrupts for specific target group. 

Parameters:

base – XSPI peripheral base address. 
tgId – Target group ID. 
mask – XSPI interrupt source mask. 







static inline void XSPI_EnableTxDMATG(XSPI_Type *base, xspi_target_group_t tgId, bool enable)

Enables or disables XSPI IP Tx FIFO DMA requests for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 
enable – [in] Enable flag for transmit DMA request. Pass true for enable, false for disable. 







static inline void XSPI_EnableRxDMATG(XSPI_Type *base, xspi_target_group_t tgId, bool enable)

Enables or disables XSPI IP Rx FIFO DMA requests for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 
enable – [in] Enable flag for receive DMA request. Pass true for enable, false for disable. 







static inline uint32_t XSPI_GetTxFifoAddressTG(XSPI_Type *base, xspi_target_group_t tgId)

Gets XSPI IP tx fifo address for DMA transfer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Returns:
The tx fifo address for the target group. 






static inline uint32_t XSPI_GetRxFifoAddressTG(XSPI_Type *base, xspi_target_group_t tgId)

Gets XSPI IP rx fifo address for DMA transfer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Returns:
The rx fifo address for the target group. 






static inline uint32_t XSPI_GetErrorStatusFlagsTG(XSPI_Type *base, xspi_target_group_t tgId)

Get error status flags for specific target group. 

Parameters:

base – XSPI peripheral base address. 
tgId – Target group ID.


Returns:
All asserted error status flags for the target group. Should be the OR’ed value of xspi_error_flag_t. 






static inline void XSPI_ClearErrorStatusFlagsTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t flags)

Clear input error status flags for specific target group. 

Parameters:

base – XSPI peripheral base address. 
tgId – Target group ID. 
flags – Error flags to clear. Should be the OR’ed value of xspi_error_flag_t. 







static inline bool XSPI_CheckIpRequestGrantedTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if the IP access request was granted access for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – The IP access is granted arbitration for the target group. 
false – No IP access is queued for the target group. 







static inline bool XSPI_GetBusIdleStatusTG(XSPI_Type *base, xspi_target_group_t tgId)

Return whether the bus is idle for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – Bus is idle for the target group. 
false – Bus is busy for the target group. 







static inline uint32_t XSPI_GetCmdExecutionArbitrationStatusFlagsTG(XSPI_Type *base, xspi_target_group_t tgId)

Get asserted flags about SFM command execution and arbitration for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Returns:
The assert flags about SFM command execution and arbitration for the target group. should be the OR’ed value of xspi_cmd_execution_arbitration_flag_t. 






static inline void XSPI_ClearCmdExecutionArbitrationStatusFlagsTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t flags)

Clear asserted flags about SFM command execution and arbitration for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 
flags – [in] The mask of flags to clear. 







static inline bool XSPI_GetBusIdleStatus(XSPI_Type *base)

Return whether the bus is idle. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

true – Bus is idle. 
false – Bus is busy. 







static inline bool XSPI_CheckAhbReadAccessAsserted(XSPI_Type *base)

Check if AHB read access has been requested or is ongoing. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

true – AHB read access is requested or is ongoing. 
false – AHB read access is not requested and is not ongoing. 







static inline bool XSPI_CheckAhbWriteAccessAsserted(XSPI_Type *base)

Check if AHB write access has been requested or is ongoing. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

true – AHB read access is requested or is ongoing. 
false – AHB read access is not requested and is not ongoing. 







static inline void XSPI_ResetTxRxBufferTG(XSPI_Type *base, xspi_target_group_t tgId, bool txFifo, bool rxFifo)

Clear the XSPI IP TX/RX buffer logic. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 
txFifo – [in] Pass true to reset TX FIFO. 
rxFifo – [in] Pass true to reset RX FIFO. 







static inline void XSPI_ClearTxBufferTG(XSPI_Type *base, xspi_target_group_t tgId)

Clear TX buffer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 







static inline bool XSPI_CheckTxBuffLockOpenTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if IP manager can write to TX buffer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – Tx buffer lock is open. 
false – Tx buffer lock is not open. 







static inline void XSPI_WriteTxBufferTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t data)

Writes data into IPS TX Buffer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address 
tgId – [in] Target group ID. 
data – [in] The data bytes to send. 







status_t XSPI_UpdateTxBufferWaterMarkTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t waterMark)

Update watermark for TX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 
waterMark – [in] The watermark to set, the unit is byte, should be the multiple of 4 byte.


Return values:

kStatus_XSPI_IPAccessAsserted – Fail to update watermark for Tx buffer, due to IP access is asserted. 
kStatus_XSPI_WaterMarkIllegal – Fail to update watermark for Tx buffer, due to input watermark is not the multiple of 4 bytes. 
kStatus_Success – Successful to update watermark. 







static inline void XSPI_ClearRxBufferTG(XSPI_Type *base, xspi_target_group_t tgId)

Clear RX buffer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 







static inline uint32_t XSPI_ReadRxBufferTG(XSPI_Type *base, xspi_target_group_t tgId, uint8_t fifoIndex)

Receive data from IPX RX FIFO for specific target group. 

Parameters:

base – [in] XSPI peripheral base address 
tgId – [in] Target group ID. 
fifoIndex – [in] Source fifo index.


Returns:
The data in the FIFO. 






static inline void XSPI_TriggerRxBufferPopEventTG(XSPI_Type *base, xspi_target_group_t tgId)

Trigger a pop event for RX buffer pop event for specific target group. 

Note
Each pop event discard watermark + 1 enties from RX buffer.


Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID. 







static inline bool XSPI_CheckRxBufferWaterMarkExceedTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if RX buffer watermark is exceed for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – The RX buffer watermark has been excceded. 
false – The RX buffer watermark has not been exceeded. 







static inline uint32_t XSPI_GetRxBufferAvailableBytesCountTG(XSPI_Type *base, xspi_target_group_t tgId)

Get RX buffer aviailable bytes count for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Returns:
The available counts if bytes in RX buffer. 






static inline uint32_t XSPI_GetRxBufferRemovedBytesCountTG(XSPI_Type *base, xspi_target_group_t tgId)

Get counts of bytes already removed from RX buffer for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Returns:
Counts of removed bytes. 






static inline bool XSPI_CheckIpWriteTriggeredTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if IP write access is triggered for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – The IP write access is granted arbitration. 
false – No IP write access is queued. 







static inline bool XSPI_CheckIpReadTriggeredTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if IP read access is triggered for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – The IP read access is granted arbitration. 
false – No IP read access is queued. 







static inline bool XSPI_CheckFSMValidTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if IPS transfer is granted arbitration or execution for specific target group. 

Note
The FSMSTAT[VLD] goes to 0 once the IPS transfer is completed and XSPI is IDLE.


Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

true – Valid, the IPS transfer is granted arbitration or execution. 
false – Not valid, no IPS transfer is queued. 







static inline bool XSPI_CheckIPAccessAssertedTG(XSPI_Type *base, xspi_target_group_t tgId)

Check if IP access is asserted for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Target group ID.


Return values:

false – The Access triggered by IP bus is not asserted. 
true – The Access triggered by IP bus is asserted. 







static inline bool XSPI_CheckIPAccessAsserted(XSPI_Type *base)

Check if IP access is asserted. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

false – The Access triggered by IP bus is not asserted. 
true – The Access triggered by IP bus is asserted. 







status_t XSPI_UpdateRxBufferWaterMarkTG(XSPI_Type *base, xspi_target_group_t tgId, uint32_t waterMark)

Update watermark for RX buffer. 
Set watermark as 4 bytes:
XSPI_UpdateRxBufferWaterMarkTG(XSPI0, tgId, 4UL);
Set watermark as 8 bytes:
XSPI_UpdateRxBufferWaterMarkTG(XSPI0, tgId, 8UL);



Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group. 
waterMark – [in] Specify the number of bytes in the RX buffer which causes XSPI to assert the watermark exceeded flag, should be in multiple of 4 bytes.


Return values:

kStatus_XSPI_IPAccessAsserted – Fail to update watermark for Rx buffer, due to IP access is asserted. 
kStatus_XSPI_WaterMarkIllegal – Fail to update watermark for Tx buffer, due to input watermark is not the multiple of 4 bytes. 
kStatus_Success – Successful to update watermark. 







void XSPI_SetSFPFradEALModeTG(XSPI_Type *base, xspi_target_group_t tgId, xspi_exclusive_access_lock_mode_t ealMode, uint8_t fradId)

Set exclusive access lock mode for the specific frad. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group. 
ealMode – [in] Specify the exclusive access lock mode. 
fradId – [in] Specify the frad. 







void XSPI_GetFradLastTransactionsInfo(XSPI_Type *base, xspi_target_group_t tgId, xspi_frad_transaction_info_t *ptrInfo, uint8_t fradId)

Get FARD latest transaction information. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group. 
ptrInfo – [out] Pointer to the variable in type of xspi_frad_transaction_info_t to store information. 
fradId – [in] Specify the frad Id. 







void XSPI_UpdateSFPConfig(XSPI_Type *base, xspi_sfp_mdad_config_t *ptrSfpMdadConfig, xspi_sfp_frad_config_t *ptrSfpFradConfig)

Update SFP configurations, including MDAD configurations and FRAD configurations. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrMdadConfig – [in] Pointer to the SFP MDAD configuration. 
ptrFradConfig – [in] Pointer to the SFP FRAD configuration. 







static inline bool XSPI_CheckSFPFradEnabled(XSPI_Type *base)

Check if SFP FRAD check is enabled for IP write access. 

Parameters:

base – [in] XSPI peripheral base address.


Return values:

false – SFP FRAD check is disabled. 
true – SFP FRAD check is enabled for IP write access. 







xspi_mdad_error_reason_t XSPI_GetMdadErrorReason(XSPI_Type *base, xspi_target_group_t tgId)

Get MDAD check error reason for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group.


Returns:
The details of MDAD error reason, in type of xspi_mdad_error_reason_t. 






status_t XSPI_UpdateSFPArbitrationLockTimeoutCounter(XSPI_Type *base, uint32_t countValue)

Update SFP arbitration lock timeout counter. 

Note
The SFP arbitration lock time out counter starts when Page program wait flag asserted.


Parameters:

base – [in] XSPI peripheral base address. 
countValue – [in] The count value, specify the time in IPS clock cycles.


Return values:

kStatus_XSPI_RegWriteLocked – Write operation to related register is locked. 
kStatus_Success – Success to update timeout counter. 







void XSPI_ClearTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId)

Clear address write status for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group to clear address write status. 







void XSPI_GetTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId, xspi_tg_add_write_status_t *ptrStatus)

Get address write status for specific target group. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group. 
ptrStatus – [out] Pointer to the variable in type of xspi_tg_add_write_status_t to store address write status. 







void XSPI_UnlockIpAccessArbitrationTG(XSPI_Type *base, xspi_target_group_t tgId)

Unlock Ip access arbitration. 

Parameters:

base – [in] XSPI peripheral base address. 
tgId – [in] Specify the target group. 







static inline void XSPI_ClearIPAccessSeqPointer(XSPI_Type *base)

Clear Ip access sequence pointer. 

Parameters:

base – [in] XSPI peripheral base address. 







status_t XSPI_UpdateIPAccessTimeoutCounter(XSPI_Type *base, uint32_t countValue)

Update the count of SFP access timeout counter. 

Note
The counter starts when any IP access pass SFP check(if enabled), and request is granted by XSPI arbiter and XSPI is IDLE.


Note
The counter does not start in case of IP access was granted by XSPI is not IDLE.


Parameters:

base – XSPI peripheral base address. 
countValue – The count value, specify the time in IPS clock cycles.


Return values:

kStatus_XSPI_RegWriteLocked – Write operation to related register is locked. 
kStatus_Success – Success to update timeout counter. 







status_t XSPI_StartIpAccess(XSPI_Type *base, uint32_t addr, uint8_t seqIndex, size_t byteSize, xspi_target_group_t tgId, bool lockArbitration)

Start IP access(including read and write) in blocking way. 

Parameters:

base – [in] XSPI peripheral base address. 
addr – [in] Address of external device to read/write. 
seqIndex – [in] Sequence Id of the pre-programmed LUT. 
byteSize – [in] Size of data to read/write, the unit of byte. 
tgId – [in] Specify the target group used to write/read. 
lockArbitration – [in] Lock arbitration or not.


Return values:

kStatus_XSPI_IpAccessAddrSettingInvalid – Wrong Address input. 
kStatus_XSPI_IpAccessIPCRInvalid – Wrong seqindex or bytesize input. 
kStatus_Success – Success to start Ip access. 







status_t XSPI_StartIpAccessNonBlocking(XSPI_Type *base, uint32_t addr, uint8_t seqIndex, size_t byteSize, xspi_target_group_t tgId, bool lockArbitration)

Start IP access in non-blocking way. 

Parameters:

base – [in] XSPI peripheral base address. 
addr – [in] Address of external device to read/write. 
seqIndex – [in] Sequence Id of the pre-programmed LUT. 
byteSize – [in] Size of data to transfer, the unit of byte. 
tgId – [in] Specify the target group to use. 
lockArbitration – [in] Lock arbitration or not.


Return values:

kStatus_Success – Success to start Ip access. 
kStatus_XSPI_IpAccessIPCRInvalid – Invalid to set IPCR register. 
kStatus_XSPI_IpAccessAddrSettingInvalid – Invalid to set SFAR register. 







status_t XSPI_SetIpAccessConfig(XSPI_Type *base, xspi_ip_access_config_t *ptrIpAccessConfig)

Set IP access configurations, including SFP configurations, sfp arbitration lock timeout value, Ip access timeout value. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrIpAccessConfig – [in] Pointer to the variable which contains Ip access configurations.


Return values:

kStatus_XSPI_RegWriteLocked – Write operation to related register is locked. 
kStatus_Success – Success to update timeout counter. 







status_t XSPI_WriteBlockingTG(XSPI_Type *base, xspi_target_group_t tgId, uint8_t *buffer, size_t size)

Sends a buffer of data bytes using blocking method for specific target group. 

Note
This function blocks via polling until all bytes have been sent. 


Parameters:

base – XSPI peripheral base address 
tgId – Target group ID 
buffer – The data bytes to send 
size – The number of data bytes to send 


Return values:

kStatus_Success – write success without error 
kStatus_XSPI_SequenceExecutionTimeout – sequence execution timeout 
kStatus_XSPI_IpCommandSequenceError – IP command sequence error detected 
kStatus_XSPI_IpCommandGrantTimeout – IP command grant timeout detected 







status_t XSPI_ReadBlockingTG(XSPI_Type *base, xspi_target_group_t tgId, uint8_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method for specific target group. 

Note
This function blocks via polling until all bytes have been sent. 


Parameters:

base – XSPI peripheral base address 
tgId – Target group ID 
buffer – The data bytes to send 
size – The number of data bytes to receive 


Return values:

kStatus_Success – read success without error 
kStatus_XSPI_SequenceExecutionTimeout – sequence execution timeout 
kStatus_XSPI_IpCommandSequenceError – IP command sequence error detected 
kStatus_XSPI_IpCommandGrantTimeout – IP command grant timeout detected 







void XSPI_TransferCreateHandle(XSPI_Type *base, xspi_handle_t *handle, xspi_transfer_callback_t callback, void *userData, xspi_target_group_t targetGroup)

Initializes the XSPI handle for specific target group which is used in transactional functions. 

Parameters:

base – XSPI peripheral base address. 
handle – pointer to xspi_handle_t structure to store the transfer state. 
callback – pointer to user callback function. 
userData – user parameter passed to the callback function. 
targetGroup – target group ID for this handle. 







status_t XSPI_TransferBlocking(XSPI_Type *base, xspi_transfer_t *xfer)

Execute command to transfer a buffer data bytes using a blocking method. 

Note
In case of flash page program, if WEL(Write enable) automatically cleared after program operation, then WEL should be asserted before invoking this API and the transfer size should not bigger than page size.


Parameters:

base – [in] XSPI peripheral base address 
xfer – [in] pointer to the transfer structure.


Return values:

kStatus_Success – command transfer success without error 
kStatus_XSPI_SequenceExecutionTimeout – sequence execution timeout 
kStatus_XSPI_IpCommandSequenceError – IP command sequence error detected 
kStatus_XSPI_IpCommandGrantTimeout – IP command grant timeout detected 







status_t XSPI_TransferNonBlocking(XSPI_Type *base, xspi_handle_t *handle, xspi_transfer_t *xfer)

Perform a interrupt non-blocking transfer on the XSPI bus. 

Note
Calling the API returns immediately after transfer initiates. The user needs to call XSPI_GetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_XSPI_Busy, the transfer is finished. For XSPI_Read, the dataSize should be multiple of rx watermark level, or XSPI could not read data properly.


Parameters:

base – [in] XSPI peripheral base address. 
handle – [in] pointer to xspi_handle_t structure which stores the transfer state. 
xfer – [in] pointer to xspi_transfer_t structure.


Return values:

kStatus_Success – Successfully start the data transmission. 
kStatus_XSPI_Busy – Previous transmission still not finished. 







status_t XSPI_TransferGetCount(XSPI_Type *base, xspi_handle_t *handle, size_t *count)

Get the master transfer status during a interrupt non-blocking transfer. 

Parameters:

base – [in] XSPI peripheral base address. 
handle – [in] pointer to xspi_handle_t structure which stores the transfer state. 
count – [out] Number of bytes transferred so far by the non-blocking transaction.


Return values:

kStatus_InvalidArgument – count is Invalid. 
kStatus_Success – Successfully return the count. 







void XSPI_TransferAbort(XSPI_Type *base, xspi_handle_t *handle)

Abort an interrupt non-blocking transfer early. 

Note
This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – [in] XSPI peripheral base address. 
handle – [in] pointer to xspi_handle_t structure which stores the transfer state 







static inline void XSPI_ClearAhbBuffer(XSPI_Type *base)

Blocks to clear AHB buffer and abort ongoing prefetch transaction(if prefetch is enabled.) 

Note
The function return only after all AHB buffer pointers are cleared.


Parameters:

base – [in] XSPI peripheral base address. 







status_t XSPI_EnableAhbBufferWriteFlush(XSPI_Type *base, bool enable)

Enable/disable the clearing of AHB read prefetch buffers when the same flash address is written by an AHB or IP command. 

Parameters:

base – [in] XSPI peripheral base address. 
enable – [in] Used to enable/disable write flush.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted. 
kStatus_Success – Successfully to enable/disable AHB buffer write flush. 







status_t XSPI_SetAhbBufferConfig(XSPI_Type *base, xspi_ahbBuffer_config_t *ptrBuffer0Config, xspi_ahbBuffer_config_t *ptrBuffer1Config, xspi_ahbBuffer_config_t *ptrBuffer2Config, xspi_ahbBuffer_config_t *ptrBuffer3Config)

Set AHB buffer configurations. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrBuffer0Config – [in] Pointer to the variable which contain buffer0 configurations. 
ptrBuffer1Config – [in] Pointer to the variable which contain buffer1 configurations. 
ptrBuffer2Config – [in] Pointer to the variable which contain buffer2 configurations. 
ptrBuffer3Config – [in] Pointer to the variable which contain buffer3 configurations.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted. 
kStatus_Success – Success to set AHB buffer configurations. 







status_t XSPI_UpdateAhbBufferSize(XSPI_Type *base, uint16_t buf0Size, uint16_t buf1Size, uint16_t buf2Size, uint16_t buf3Size)

Set Buffer size for all 4 AHB buffers. 

Parameters:

base – [in] XSPI peripheral base address. 
buf0Size – [in] Specify size of AHB buffer0, range of 512, 256, 128, 64, 32, 16, 8, 4, 2, 0. 
buf1Size – [in] Specify size of AHB buffer1, range of 512, 256, 128, 64, 32, 16, 8, 4, 2, 0. 
buf2Size – [in] Specify size of AHB buffer2, range of 512, 256, 128, 64, 32, 16, 8, 4, 2, 0. 
buf3Size – [in] Specify size of AHB buffer3, range of 512, 256, 128, 64, 32, 16, 8, 4, 2, 0.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted. 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted. 
kStatus_Success – Success to set AHB buffer size. 







xspi_ahb_sub_buffer_status_t XSPI_GetAhbSubBufferStatus(XSPI_Type *base, uint8_t ahbBufferId, uint8_t subBufferId)

Get status of AHB sub buffer. 

Note
This function only useful when sub-division feature of the selected AHB buffer is enabled.


Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] The Id of AHB buffer, range from 0 to 3. 
subBufferId – [in] The Id of AHB buffer sub division, range from 0 to 3.


Returns:
Current status of selected AHB sub buffer, in type of xspi_ahb_sub_buffer_status_t. 






static inline void XSPI_StartAhbBufferPerfMonitor(XSPI_Type *base)

Start AHB buffer performance monitor. 

Parameters:

base – [in] XSPI peripheral base address. 







void XSPI_EnableAhbBufferPerfMonitor(XSPI_Type *base, uint8_t ahbBufferId, uint8_t subBufferId)

Enable AHB buffer performance monitor for selected AHB buffer’s sub buffer. 

Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] Specify the selected AHB buffer. 
subBufferId – [in] Specify the selected sub-buffer. 







static inline void XSPI_DisableAhbBufferPerfMonitor(XSPI_Type *base, uint8_t ahbBufferId)

Disable AHB buffer performance monitor for selected AHB buffer. 

Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] Specify the selected AHB buffer. 







static inline void XSPI_StopAhbBufferPerfMonitor(XSPI_Type *base)

Stop AHB buffer performance monitor. 

Parameters:

base – [in] XSPI peripheral base address. 







static inline void XSPI_GetAhbBufferPerfMonitorResult(XSPI_Type *base, uint8_t ahbBufferId, xspi_ahbBuffer_perf_monitor_result_t *ptrPerfMonitorResult)

Get AHB buffer performance monitor result. 

Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] Specify AHB buffer Id. 
ptrPerfMonitorResult – [out] Pointer to the variable to store selected AHB buffer’s performance monitor result. 







static inline bool XSPI_CheckAhbBufferPerfMonitorTimeCounterOverflow(XSPI_Type *base)

Check if AHB buffer performance monitor timeout counter is overflow. 

Parameters:

base – XSPI peripheral base address.


Return values:

false – AHB buffer performance monitor timeout counter is not overflow. 
true – AHB buffer performance monitor timeout counter is overflow. 







static inline bool XSPI_CheckAhbBufferPerfMonitorHitOverflow(XSPI_Type *base, uint8_t ahbBufferId)

Check if AHB buffer performance monitor buffer hit counter is overflow. 

Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] Specify the AHB buffer Id.


Return values:

false – Overflow not detected. 
true – Overflow is detected. 







static inline bool XSPI_CheckAhbBufferPerfMonitorMissOverflow(XSPI_Type *base, uint8_t ahbBufferId)

Check if AHB buffer performance monitor buffer miss counter is overflow. 

Parameters:

base – [in] XSPI peripheral base address. 
ahbBufferId – [in] Specify the AHB buffer Id.


Return values:

false – Overflow not detected. 
true – Overflow is detected. 







static inline uint32_t XSPI_GetAhbBufferPerfMonitorTimeCounter(XSPI_Type *base)

Get AHB buffer performance monitor timeout value. 

Parameters:

base – [in] XSPI peripheral base address.


Returns:
The value of time counter, in AHB clock cycles, since the performance monitor was running. 






status_t XSPI_SetAhbAccessSplitSize(XSPI_Type *base, xspi_ahb_split_size_t ahbSplitSize)

Set AHB transaction(read/write) split size. 

Note
For AHB write, if enable split feature(ahbSplitSize not set as kXSPI_AhbSplitSizeDisabled), XSPI will split one single AHB write burst into smaller bursts on external device side.


Note
For AHB read, if enable split feature, HW will realign the prefetch size to split size and in that way split a single read burst into smaller bursts.


Parameters:

base – [in] XSPI peripheral base address. 
ahbSplitSize – [in] Specify the AHB split size.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB access split size. 







status_t XSPI_SetAhbAccessBoundary(XSPI_Type *base, xspi_ahb_alignment_t alignment)

Set AHB transaction(read/write) boundary. 

Note
For AHB write, XSPI keeps track of the start address and then compares it with the address of subsequent transaction receive on the AHB bus, when the input alignment is reached, XSPI negates AHB HREADY to block new accesses. This signal will be kept low until all the previous received write data is written to external memory and chip select is de-asserted. After that it allows next AHB write data to be received by making HREADY high thus ensuring that transaction is split at address boundary on external memory.


Note
For AHB read, XSPI checks the start address and end address to see if it is crossing the address boundary specified by input alignment. If the transaction crosses the address boundary, then it reduces the transaction size such that the data pre-fetch is stopped before the address boundary. Now if the AHB master is reading the data sequentially it will get buffer hits up to the input alignment boundary. When it reaches the next address boundary it will get a buffer miss and a new data pre-fetch will be launched towards the external memory device.


Parameters:

base – [in] XSPI peripheral base address. 
alignment – [in] Specify the AHB alignment, in type of xspi_ahb_alignment_t.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB access boundary. 







status_t XSPI_SetAhbReadDataSeqId(XSPI_Type *base, uint8_t seqId)

Set AHB read sequence Id. 

Parameters:

base – [in] XSPI peripheral base address. 
seqId – [in] Specify the sequence Id in LUT used for AHB read.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB read sequence Id. 







status_t XSPI_SetAhbWriteDataSeqId(XSPI_Type *base, uint8_t seqId)

Set AHB write sequence Id. 

Parameters:

base – [in] XSPI peripheral base address. 
seqId – [in] Specify the sequence Id in LUT used for AHB write.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB write sequence Id. 







status_t XSPI_UpdateAhbHreadyTimeOutValue(XSPI_Type *base, uint16_t timeoutValue)

Specify how long XSPI can hold HEADY low while waiting for response to an AHB transfer. 

Note
If the specified time out value expired, an AHB illegal transaction error will be triggerred.


Parameters:

base – [in] XSPI peripheral base address. 
timeoutValue – [in] In multiples of 50000 AHB clock cycles, default value is 3, it means waiting for 150000 AHB clock cycles.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_Success – Success to set AHB HREADY timeout value. 







status_t XSPI_SetAhbErrorPayload(XSPI_Type *base, uint32_t highPayload, uint32_t lowPayload)

Pre-define error payload which will be provided on the read data bus when the HEADY timeout counter expires. 

Note
If the incoming AHB read request master is not mapped to any of the AHB buffer, the XSPI will keep the AHB HREADY signal low and will provided this pre-defined error payload on the AHB read data bus when the HEADY timeout counter expires.


Parameters:

base – [in] XSPI peripheral base address. 
highPayload – [in] High 32bits payload to set. 
lowPayload – [in] Low 32bits payload to set.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_Success – Success to set AHB HREADY timeout value. 







xspi_ahb_read_error_info_t XSPI_ReturnAhbReadErrorInfo(XSPI_Type *base)

Return AHB read error information. 

Parameters:

base – [in] XSPI peripheral base address.


Returns:
Latest AHB read error information, in type of xspi_ahb_read_error_info_t. 






static inline void XSPI_ClearAhbAccessSeqPointer(XSPI_Type *base)

Clear AHB access sequence pointer. 

Parameters:

base – [in] XSPI peripheral base address. 







void XSPI_GetAhbRequestSuspendInfo(XSPI_Type *base, xspi_ahb_request_suspend_info_t *ptrSuspendInfo)

Get Ahb request suspend information if priority mechanism is enabled. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrSuspendInfo – [out] Contain latest suspend info, the value may be 0xFF if the item is invalid in current suspend state. 







static inline void XSPI_EnableAhbReadPrefetch(XSPI_Type *base, bool enable)

Enable/disable AHB Read Prefetch feature. 

Parameters:

base – [in] XSPI peripheral base address. 
enable – [in] Used to enable/disable AHB read prefetch:

false Disable AHB read prefetch;
true Enable AHB read prefetch. 









status_t XSPI_BlockAccessAfterAhbWrite(XSPI_Type *base, bool blockSequentWrite, bool blockRead)

Block access(write and read) after the AHB write operation. 

Note
If external flash support RWW, read should not be blocked: 
XSPI_BlockAccessAfterAhbWrite(XSPI0, true, false);





Note
If either of access is blocked, the page program wait flag will be asserted after an AHB write sequence completed. The assertion of flag will lock the arbitration and all access to the external memory are blocked. And the internal “page wait time” counter starts(Invoke XSPI_UpdatePageWaitTimeCounter to update counter value). After this counter reaches the value, a read is triggered by the XSPI module to read external device’s status register(The seq id should be pre-defined by XSPI_SetAhbReadStatusRegSeqId), and the value is stored in the XSPI internal regsiter. And there are two options(Invoke XSPI_SelectPPWFlagClearPolicy to select) to clear the asserted page program wait flag.

Automatic cleared by XSPI hardware;
Cleared by software.




Note
As soon as the page program wait flag is asserted, another counter(SFP arbitration
lock counter) also started, if the flag not cleared in desired counter value the arbitration lock timeout error will be generated.



Parameters:

base – [in] XSPI peripheral base address. 
blockSequentWrite – [in] Block sequence write or not. 
blockRead – [in] Block read or not.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_Success – Success to set related registers.. 







status_t XSPI_SelectPPWFlagClearPolicy(XSPI_Type *base, xspi_ppw_flag_clear_policy_t policy)

Set Page program wait flag clear policy. 

Note
If set as hardware policy, the device’s WIP information should be set by invoking XSPI_SetSFMStatusRegInfo()


Parameters:

base – [in] XSPI peripheral base address. 
policy – [in] Specify the policy to clear page program wait flag.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set PPW flag clear policy. 







status_t XSPI_UpdatePageWaitTimeCounter(XSPI_Type *base, uint32_t countValue)

Update page wait timeout counter. 

Parameters:

base – [in] XSPI peripheral base address. 
countValue – [in] The value of counter, in AHB clock cycles.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_PageProgramWaitFlagAsserted – Page program wait flag already asserted. 
kStatus_Success – Successfully to update page wait timeout counter. 







status_t XSPI_SetAhbReadStatusRegSeqId(XSPI_Type *base, uint8_t seqId)

Set AHB read status register sequence Id. 

Note
The read status sequence only triggerred when the page wait time counter expired.


Parameters:

base – [in] XSPI peripheral base address. 
seqId – [in] Specify the sequence Id in LUT used for AHB read status register.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB read status register sequence Id. 







static inline uint16_t XSPI_GetSFMStatusRegValue(XSPI_Type *base)

Get external serial flash’s status register value. 

Note
This function is only useful after the Page program wait flag is asserted due to either wait/read access is blocked after the AHB write operation.


Parameters:

base – [in] XSPI peripheral base address.


Returns:
The status regsiter value of external device. 






status_t XSPI_SetSFMStatusRegInfo(XSPI_Type *base, xspi_device_status_reg_info_t *ptrStatusRegInfo)

Set Serial flash memory status register information. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrStatusRegInfo – [in] Pointer to the variable which contain status register information.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_PageProgramWaitFlagAsserted – Page program wait flag already asserted. 
kStatus_Success – Successfully to set status register information. 







status_t XSPI_EnableAhbWriteTerminate(XSPI_Type *base, bool enable)

Enable or disable AHB write terminate functionality. 

Parameters:

base – XSPI peripheral base address. 
enable – True to enable AHB write terminate, false to disable.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_Success – Success to enable/disable AHB write terminate functionality. 







status_t XSPI_SetAhbAccessConfig(XSPI_Type *base, xspi_ahb_access_config_t *ptrAhbAccessConfig)

Set AHB access configuration. 

Parameters:

base – [in] XSPI peripheral base address. 
ptrAhbAccessConfig – [in] Pointer to the variable which contains AHB access configurations.


Return values:

kStatus_XSPI_AhbReadAccessAsserted – Fail due to an AHB read access already asserted 
kStatus_XSPI_AhbWriteAccessAsserted – Fail due to an AHB write access already asserted 
kStatus_XSPI_RegWriteLocked – Fail due to write operation to related registers is locked. 
kStatus_Success – Success to set AHB read status register sequence Id. 







static inline void XSPI_EnableTxDMA(XSPI_Type *base, bool enable)

Enables or disables XSPI IP Tx FIFO DMA requests. 

Parameters:

base – [in] XSPI peripheral base address. 
enable – [in] Enable flag for transmit DMA request. Pass true for enable, false for disable. 







static inline void XSPI_EnableRxDMA(XSPI_Type *base, bool enable)

Enables or disables XSPI IP Rx FIFO DMA requests. 

Parameters:

base – [in] XSPI peripheral base address. 
enable – [in] Enable flag for receive DMA request. Pass true for enable, false for disable. 







static inline uint32_t XSPI_GetTxFifoAddress(XSPI_Type *base)

Gets XSPI IP tx fifo address for DMA transfer. 

Parameters:

base – [in] XSPI peripheral base address. 


Returns:
The tx fifo address. 






static inline uint32_t XSPI_GetRxFifoAddress(XSPI_Type *base)

Gets XSPI IP rx fifo address for DMA transfer. 

Parameters:

base – [in] XSPI peripheral base address. 


Returns:
The rx fifo address. 






static inline uint32_t XSPI_GetErrorStatusFlags(XSPI_Type *base)

Get error status flags. 

Parameters:

base – XSPI peripheral base address.


Returns:
All asserted error status flags for the target group. Should be the OR’ed value of xspi_error_flag_t. 






static inline void XSPI_ClearErrorStatusFlags(XSPI_Type *base, uint32_t flags)

Clear input error status flags. 

Parameters:

base – XSPI peripheral base address. 
flags – Error flags to clear. Should be the OR’ed value of xspi_error_flag_t. 







static inline uint32_t XSPI_GetInterruptStatusFlags(XSPI_Type *base)

Get the XSPI interrupt status flags. 


Deprecated:
Please use XSPI_GetErrorStatusFlags() as instead. 




Parameters:

base – [in] XSPI peripheral base address. 


Returns:
interrupt status flag, use status flag to AND xspi_flags_t could get the related status. 






static inline bool XSPI_CheckIpRequestGranted(XSPI_Type *base)

Check if the IP access request was granted access. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – IP request granted. 
false – IP request not granted. 







static inline uint32_t XSPI_GetCmdExecutionArbitrationStatusFlags(XSPI_Type *base)

Get asserted flags about SFM command execution and arbitration. 

Parameters:

base – [in] XSPI peripheral base address.


Returns:
The assert flags about SFM command execution and arbitration, should be the OR’ed value of xspi_cmd_execution_arbitration_flag_t. 






static inline void XSPI_ClearCmdExecutionArbitrationStatusFlags(XSPI_Type *base, uint32_t flags)

Clear asserted flags about SFM command execution and arbitration. 

Parameters:

base – [in] XSPI peripheral base address. 
flags – [in] The mask of flags to clear. 







static inline void XSPI_ClearTxBuffer(XSPI_Type *base)

Clear TX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 







static inline void XSPI_ClearRxBuffer(XSPI_Type *base)

Clear RX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 







static inline void XSPI_ResetTxRxBuffer(XSPI_Type *base, bool txFifo, bool rxFifo)

Clear the XSPI IP TX/RX buffer logic. 

Parameters:

base – [in] XSPI peripheral base address. 
txFifo – [in] Pass true to reset TX FIFO. 
rxFifo – [in] Pass true to reset RX FIFO. 







static inline status_t XSPI_UpdateRxBufferWaterMark(XSPI_Type *base, uint32_t waterMark)

Update watermark for RX buffer. 
Set watermark as 4 bytes:
XSPI_UpdateRxBufferWaterMark(XSPI0, 4UL);
Set watermark as 8 bytes:
XSPI_UpdateRxBufferWaterMark(XSPI0, 8UL);



Parameters:

base – [in] XSPI peripheral base address. 
waterMark – [in] Specify the number of bytes in the RX buffer which causes XSPI to assert the watermark exceeded flag, should be in multiple of 4 bytes.


Return values:

kStatus_XSPI_IPAccessAsserted – Fail to update watermark for Rx buffer, due to IP access is asserted. 
kStatus_XSPI_WaterMarkIllegal – Fail to update watermark for Tx buffer, due to input watermark is not the multiple of 4 bytes. 
kStatus_Success – Successful to update watermark. 







static inline status_t XSPI_UpdateTxBufferWaterMark(XSPI_Type *base, uint32_t waterMark)

Update watermark for TX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 
waterMark – [in] The watermark to set. 


Returns:
Status of the operation. 






static inline void XSPI_UnlockIpAccessArbitration(XSPI_Type *base)

Unlock IP access arbitration. 

Parameters:

base – [in] XSPI peripheral base address. 







static inline status_t XSPI_CheckAndClearError(XSPI_Type *base, uint32_t status)

Check and clear IP command execution errors. 

Parameters:

base – XSPI peripheral base address. 
status – Interrupt status. 


Returns:
Status of the operation. 






static inline void XSPI_WriteTxBuffer(XSPI_Type *base, uint32_t data)

Writes data into IPS TX Buffer. 

Parameters:

base – [in] XSPI peripheral base address. 
data – [in] The data bytes to send. 







static inline uint32_t XSPI_ReadRxBuffer(XSPI_Type *base, uint8_t fifoIndex)

Receive data from IPX RX FIFO. 

Parameters:

base – [in] XSPI peripheral base address. 
fifoIndex – [in] Source fifo index. 


Returns:
The data in the FIFO. 






static inline void XSPI_TriggerRxBufferPopEvent(XSPI_Type *base)

Trigger a pop event for RX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 







static inline bool XSPI_CheckRxBufferWaterMarkExceed(XSPI_Type *base)

Check if RX buffer watermark is exceeded. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – The RX buffer watermark has been exceeded. 
false – The RX buffer watermark has not been exceeded. 







static inline uint32_t XSPI_GetRxBufferAvailableBytesCount(XSPI_Type *base)

Get RX buffer available bytes count. 

Parameters:

base – [in] XSPI peripheral base address. 


Returns:
The available counts of bytes in RX buffer. 






static inline uint32_t XSPI_GetRxBufferRemovedBytesCount(XSPI_Type *base)

Get counts of bytes already removed from RX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 


Returns:
Counts of removed bytes. 






static inline bool XSPI_CheckIPAccessGranted(XSPI_Type *base)

Check if IP access is granted by XSPI arbitration. 


Deprecated:
Use XSPI_CheckIpRequestGranted() as instead 




Parameters:

base – XSPI peripheral base address.


Return values:

true – The IP access is granted arbitration. 
false – No IP access is queued. 







static inline bool XSPI_CheckIpWriteTriggered(XSPI_Type *base)

Check if IP write access is triggered. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – The IP write access is granted arbitration. 
false – No IP write access is queued. 







static inline bool XSPI_CheckIpReadTriggered(XSPI_Type *base)

Check if IP read access is triggered. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – The IP read access is granted arbitration. 
false – No IP read access is queued. 







static inline bool XSPI_CheckFSMValid(XSPI_Type *base)

Check if IPS transfer is granted arbitration or execution. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – Valid, the IPS transfer is granted. 
false – Not valid, no IPS transfer is queued. 







static inline bool XSPI_CheckTxBuffLockOpen(XSPI_Type *base)

Check if IP manager can write to TX buffer. 

Parameters:

base – [in] XSPI peripheral base address. 


Return values:

true – TX buffer lock is open. 
false – TX buffer lock is not open. 







static inline void XSPI_EnableInterrupts(XSPI_Type *base, uint64_t mask)

Enables the XSPI interrupts. 

Parameters:

base – XSPI peripheral base address. 
mask – XSPI interrupt source mask. 







static inline void XSPI_DisableInterrupts(XSPI_Type *base, uint64_t mask)

Disables the XSPI interrupts. 

Parameters:

base – XSPI peripheral base address. 
mask – XSPI interrupt source mask. 







static inline void XSPI_SetSFPFradEALMode(XSPI_Type *base, xspi_exclusive_access_lock_mode_t ealMode, uint8_t fradId)

Set exclusive access lock mode for the specific FRAD. 

Parameters:

base – [in] XSPI peripheral base address. 
ealMode – [in] Specify the exclusive access lock mode. 
fradId – [in] Specify the FRAD. 







static inline status_t XSPI_WriteBlocking(XSPI_Type *base, uint8_t *buffer, size_t size)

Sends a buffer of data bytes using blocking method. 

Parameters:

base – XSPI peripheral base address. 
buffer – The data bytes to send. 
size – The number of data bytes to send. 


Returns:
Status of the operation. 






static inline status_t XSPI_ReadBlocking(XSPI_Type *base, uint8_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method. 

Parameters:

base – XSPI peripheral base address. 
buffer – The data bytes to receive. 
size – The number of data bytes to receive. 


Returns:
Status of the operation. 






struct _xspi_device_status_reg_info


#include <fsl_xspi.h>
The structure of external device’s status register information(location, priority). 

Note
Only useful when AHB write to flash device is enabled, and use hardware to clear ppw flag. 


Public Members


uint8_t wipLocation

WIP bit field’s location. 




bool upperHalfWordSelected

Specify which half word(upper or lower) is selected. 




bool value1Expired

Specify the value to be check o selected wip location to determine if the page progame wait period is expired, true means expected value is 1, false means expected value is 0. 







union _xspi_dll_para


#include <fsl_xspi.h>
The union of user custommed DLL parameters, in case of kXSPI_BypassMode bypassModePara is used, in case of kXSPI_AutoUpdateMode autoUpdateModoPara is used. 

Public Members


struct _xspi_dll_para bypassModePara





struct _xspi_dll_para autoUpdateModoPara








struct _xspi_dll_config


#include <fsl_xspi.h>
The structure of Delay-lock-loop configuration. 

Public Members


xspi_dll_mode_t dllMode

Dll mode auto update mode or bypass mode 




bool useRefValue

Specify to use reference value or not, if the reference code do not satisfy the specific usecase, it is application’s responsibility to set custom parameters

true: following inputs are ignored, use the reference values provided by NXP as instead;
false: following inputs take effect. 






xspi_dll_para_t dllCustomPara

User custommed parameter to configure DLL, different DLL mode corresponding to different parameters, please refer to the union xspi_dll_para_t. 




uint8_t dllCustomDelayTapNum

User custommed number of delay elements for each delay tap. 




bool enableCdl8

Enable course delay line 8. 







struct _xspi_data_learning_config


#include <fsl_xspi.h>
The configuration of data learning. 

Note
Data learning feature only supported in the DQS sampling method(kXSPI_SampleClkFromExternalDQS). 


Public Members


uint32_t pattern

Pre-defined pattern to match. 




bool deviceSupported

Specify if external device support data learning feature. 




xspi_data_learning_pad_select_t padSelected

Used to select pad which use for pattern matching IO. 







struct _xspi_sample_clk_config


#include <fsl_xspi.h>
Sample clock configuration, which used to sample data from external device. 

Public Members


xspi_sample_clk_source_t sampleClkSource

Specify the sample clock source. 




bool enableDQSLatency

Enable DQS latency or not. 




xspi_dll_config_t dllConfig

Specify the DLL configuration, to improve data accuracy, please adjust DLL settings based on specific use. 







union _xspi_device_interface_settings


#include <fsl_xspi.h>
The union of external device’s settings, if external device following hyper bus protocol hyperBusSettings take effects, if external device following SPI protocol strandardExtendedSPISettings take effects. 

Public Members


struct _xspi_device_interface_settings strandardExtendedSPISettings





struct _xspi_device_interface_settings hyperBusSettings








struct _xspi_device_ddr_config


#include <fsl_xspi.h>
The structure of device DDR configuration. 

Public Members


bool enableDdr

Used to enable/disable DDR mode. 




xspi_ddr_data_aligned_clk_t ddrDataAlignedClk

Specify the DDR data aligned clock. 




bool enableByteSwapInOctalMode

Swap byte order in octal mode. 







struct _xspi_device_config


#include <fsl_xspi.h>
External device configuration items. 

Public Members


uint32_t xspiRootClk

XSPI serial root clock. 




bool enableCknPad

Enable/disable clock on differential CKN pad for flash memory A. 




xspi_device_interface_type_t deviceInterface

Type of external device’s interface: hyperBus or Strandard/Extended SPI. 




xspi_device_interface_settings_t interfaceSettings

Settings of specified interface. 




uint8_t CSHoldTime

CS line hold time. 




uint8_t CSSetupTime

CS line setup time. 




xspi_sample_clk_config_t sampleClkConfig

Configuration of sample clock. 




xspi_device_ddr_config_t *ptrDeviceDdrConfig

Set as NULL to set device as SDR mode, to change to DDR mode, this member should be populated. 




xspi_device_addr_mode_t addrMode

Address mode of external device. 




uint8_t columnAddrWidth

Width of column address. 




bool enableCASInterleaving

Usually enabled in dual-die device. 




uint32_t deviceSize[XSPI_SFAD_COUNT2]

Size of external device, the unit is KB. 




xspi_device_status_reg_info_t *ptrDeviceRegInfo

Pointer to the structure to store external device’s WIP register information, should set as NULL if AHB page write is not used or if AHB page write is used but use software policy to clear flag. 







struct _xspi_mdad_config


#include <fsl_xspi.h>
MDAD configuration. 

Public Members


bool assignIsValid

Specify if the MDAD configuration for the target group is valid 




bool enableDescriptorLock

This field provides a means to make the MDAD descriptor read-only. Once written ‘1’ this field will remain ‘1’ until hard reset 




uint8_t maskType

0b - ANDed mask 1b - ORed mask 




uint8_t mask

Defines the 6-bit mask value for the ID-Match comparison 




uint8_t masterIdReference

Specifies the reference value of the Master-ID for MID-comparison 




xspi_secure_attribute_t secureAttribute

Defines the secure attribute selection criteria for entry into descriptor queue 







struct _xspi_sfp_mdad_config


#include <fsl_xspi.h>
The structure of SFP MDAD configurations for all target groups. 

Public Members


xspi_mdad_config_t tgMdad[(2U)]

Specify MDAD configurations for each target group. 







struct _xspi_frad_tg_config


#include <fsl_xspi.h>
FRAD configuration. 

Public Members


uint8_t tgMasterAccess[(2U)]

This field define the access restrictions for respective Master Domain corresponding to this FRAD region. Access permissions are decided based on secure an privilege attributes of current transaction. Read access is not restricted. 




bool assignIsValid

This field indicates whether the FRAD Descriptor for a specific flash region is valid. 




xspi_descriptor_lock_t descriptorLock

This field enables masking of accidental write on FRAD registers. Lock is enabled/disabled by Secure/ Privileged master. 




xspi_exclusive_access_lock_mode_t exclusiveAccessLock

This field provides exclusive write lock over a FRAD region based on MDnACP. 







struct _xspi_frad_config_t


#include <fsl_xspi.h>
FRAD configuration. 

Public Members


uint32_t startAddress

Specifies the specific flash memory region starting address 




uint32_t endAddress

Specifies the specific flash memory region end address 







struct _xspi_sfp_frad_config


#include <fsl_xspi.h>
The structure of SFP FRAD configurations. 

Public Members


xspi_frad_config_t fradConfig[(8U)]

Specify FRAD configuration for each item. 







struct _xspi_frad_transaction_info


#include <fsl_xspi.h>
The structure of latest FRAD transaction information. 

Public Members


uint32_t startAddr

Latest IP access start address. 




uint8_t masterId

Latest IP access master Id. 




bool isSecureAccess

Latest IP access is secure access or not. 




bool isPrivilegeAccess

Latest IP access is privilege access or not. 




bool isCompError

Indicates the error status of the flash region specific comparision check for the latest transaction. 




bool isCompValid

Indicates availability of the result or status of a flash region-specific comparison check. 







struct _xspi_ip_access_config


#include <fsl_xspi.h>
Configurations of IP access(including IP read and write). 

Public Members


xspi_sfp_mdad_config_t *ptrSfpMdadConfig

Pointer to the variable in type of xspi_sfp_mdad_config_t to set SFP MDAD feature, set as NULL to disable SFP MDAD feature. 




xspi_sfp_frad_config_t *ptrSfpFradConfig

Pointer to the variable in type of xspi_sfp_frad_config_t to set SFP FRAD feature, set as NULL to disable SFP FRAD 




uint32_t sfpArbitrationLockTimeoutValue

Specify the time in IPS clock cycles before an unreleased arbitration triggers a timeout error. 




uint32_t ipAccessTimeoutValue

Specify the maximum time in IPS clock cycles for XSPI to wait fro an ongoing write or read command to complete before terminating the command. 







struct _xspi_tg_add_write_status


#include <fsl_xspi.h>
The status of latest target group address write operation. 

Public Members


uint8_t managerId

Manager Id of TG address write operation. 




bool secureWrite

TG address write operation is secure write. 




bool privilegedWrite

TG address write operation is privileged. 







struct _xspi_transfer


#include <fsl_xspi.h>
Transfer structure used for XSPI functional interface. 

Public Members


uint32_t deviceAddress

Operation device address. 




xspi_command_type_t cmdType

Execution command type. 




uint8_t seqIndex

Sequence ID for command. 




uint32_t *data

Data buffer. 




size_t dataSize

Data size in bytes. 




xspi_target_group_t targetGroup

Target group. 







struct _xspi_handle


#include <fsl_xspi.h>
Transfer handle structure for XSPI. 

Public Members


uint32_t state

Internal state for XSPI transfer 




xspi_target_group_t tgId

Target Group. 




uint8_t *data

Data buffer. 




size_t dataSize

Remaining Data size in bytes. 




size_t transferTotalSize

Total Data size in bytes. 




xspi_transfer_callback_t completionCallback

Callback for users while transfer finish or error occurred 




void *userData

XSPI callback function parameter. 




size_t curTransferSize

Transfer size of current IP access. 







struct _xspi_ahbBuffer_sub_buffer_config


#include <fsl_xspi.h>
The structure of sub-buffer configurations. 

Public Members


xspi_subbuffer_division_factor_t divFactor

Specify the divide factor for current sub-buffer. 




uint32_t startAddr

Specify the start address of current sub-buffer. 




uint32_t endAddr

Specify the end address of current sub-buffer. 




bool enableAhbMonitor

Enable/disable AHB performance monitor for current sub-buffer. 







struct _xspi_ahbBuffer_config


#include <fsl_xspi.h>
Structure of AHB buffer configurations. 

Note
When an AHB read access comes it is assigned to a buffer based on its master ID. Then it further assigned to a sub-buffer based on which sub-buffer address range this transaction lies into.


Note
When sub-buffer division is hit, in case of a buffer miss the controller will fetch the data equal to the size of that sub-buffer.


Note
If sub-buffer division is enabled for a buffer the hit/miss check is done at sub-buffer level. And if prefetch is enable, the prefetch takes place for individual sub-buffers. 


Public Members


uint8_t masterId

Specify the ID of the AHB master to be associated with buffer. 




xspi_ahbBuffer_sub_buffer_config_t *ptrSubBuffer0Config

Pointer to sub buffer0’s configuration. 




xspi_ahbBuffer_sub_buffer_config_t *ptrSubBuffer1Config

Pointer to sub buffer1’s configuration. 




xspi_ahbBuffer_sub_buffer_config_t *ptrSubBuffer2Config

Pointer to sub buffer2’s configuration. 




xspi_ahbBuffer_sub_buffer_config_t *ptrSubBuffer3Config

Pointer to sub buffer3’s configuration. 







struct _xspi_ahbBuffer_perf_monitor_result


#include <fsl_xspi.h>
The result of AHB buffer performance monitor, including buffer miss count and buffer hit count. 

Public Members


uint16_t bufferMissCount

Count of AHB read buffer miss events. 




uint16_t bufferHitCount

Count of AHB read buffer hit events. 







struct _xspi_ahb_write_config


#include <fsl_xspi.h>
The configuration of AHB write access. 

Public Members


bool blockSequenceWrite

Enable/disable sequence write operation after page program start. 




bool blockRead

Enable/disable read operation after page program start, can be false for RWW extern device. 




xspi_ppw_flag_clear_policy_t policy

Specify the policy to clear ppw flag, hardware or software. 




uint32_t pageWaitTimeoutValue

Specify, in AHB clock cycles, how long XSPI waits before triggering a read of the device status register, only useful in hardare policy. 




uint8_t AWRSeqIndex

Specify the sequence index for AHB write. 




uint8_t ARDSRSeqIndex

Specify the sequence index for AHB read status, only useful if either sequence write or read is blocked. 







struct _xspi_ahb_access_config


#include <fsl_xspi.h>
The structure of AHB access configurations, including AHB buffer settings, AHB Read Seq ID, AHB write settings. 

Public Members


xspi_ahbBuffer_config_t buffer[4]

AHB buffer size. 




uint8_t ARDSeqIndex

Specify the sequence index for AHB read data. 




bool enableAHBPrefetch

Enable/disable AHB read prefetch feature, when enabled, XSPI will fetch more data than current AHB burst. 




bool enableAHBBufferWriteFlush

Set true to enable flush of AHB buffer, due to either AHB write or IP access to avoid stable data in AHB buffer. 




xspi_ahb_split_size_t ahbSplitSize

Specify ahb split size, set as kXSPI_AhbSplitSizeDisabled if do not want to use this feature. 




xspi_ahb_alignment_t ahbAlignment

AHB access towards flash is broken if this AHB alignment boundary is crossed, only support XSPI0 XSPI1 




xspi_ahb_write_config_t *ptrAhbWriteConfig

Set as NULL if AHB write feature is not used. 




bool enableWriteTerminate

True to enable an AHB transaction can terminate the ongoing AHB read-prefetch, in default it is enabled. 







struct _xspi_ahb_read_error_info


#include <fsl_xspi.h>
The structure of information when AHB read error occur. 

Public Members


uint32_t errorAddr

AHB read error address. 




uint8_t errMasterId

AHB read error master Id. 







struct _xspi_ahb_request_suspend_info


#include <fsl_xspi.h>
The structure of information when AHB reqest is suspended. 

Public Members


xspi_ahb_request_suspend_state_t state

Current AHB request state. 




uint8_t subBufferId

Suspended AHB request’s sub buffer Id. 




uint8_t ahbBufferId

Suspended AHB request’s buffer Id. 




uint16_t dataLeft

How many data left to transfer. 




uint32_t address

Current address of suspended AHB request. 







struct _xspi_config


#include <fsl_xspi.h>
XSPI configuration structure. 

Public Members


xspi_byte_order_t byteOrder

Byte ordering endianness 




bool enableDoze

Enable/disable doze mode support. 




xspi_ahb_access_config_t *ptrAhbAccessConfig

Pointer to AHB access configuration, can be NULL is AHB access is not used. 




xspi_ip_access_config_t *ptrIpAccessConfig

Pointer to IP access configuration, can be NULL is IP access is not used. 







struct bypassModePara


Public Members


uint16_t delayElementCoarseValue

Delay element coarse adjustment value, range from 0 to 15. 




uint16_t delayElementFineValue

Delay element fine adjustment value, range from 0 to 7. 




uint16_t offsetDelayElementCount

Specify the number of offset delay elements, range from 0 to 15. 




uint16_t enableHighFreq

If set as true, high frequency used for delay chain operations, otherwise low frequency is used. 




uint16_t bypassModeReserved

Reserved. 







struct autoUpdateModoPara


Public Members


uint16_t referenceCounter

Specify count of interval for DLL phase detection, range from 0 to 15. 




uint16_t resolution

Specify minimum resolution for the DLL phase detctor, range from 0 to 15. 




uint16_t offsetDelayElementCount

Specify the number of offset delay elements, range from 0 to 15. 




uint16_t tDiv16OffsetDelayElementCount

Specify the number of T/16 offset elements in the incoming DQS, range from 0 to 15. 




uint16_t enableHighFreq

If set as true, high frequency used for delay chain operations, otherwise low frequency is used. 







struct strandardExtendedSPISettings


Public Members


uint32_t pageSize

The size of page to program, the unit is byte. 







struct hyperBusSettings


Public Members


xspi_hyper_bus_x16_mode_t x16Mode

Specify hyper bus X16 mode. 




bool enableVariableLatency

If enabled, the count of latency is depends on hyper bus device. 




bool forceBit10To1

Force bit 10 to logic one or not. 




uint32_t pageSize

The size of page to program, the unit is byte. 







union enaPri


Public Members


bool enablePriority

High Priority Enable, it can be written ‘1’ only when OTFAD is disabled, the AHB prefetch feature must be enabled if priority mechanism is enabled. 




bool enableAllMaster

When set, buffer3 acts as an all-master buffer.buff[i] routed to buffer3 







struct ahbErrorPayload


Public Members


uint32_t highPayload

High 32bit error payload. 




uint32_t lowPayload

Low 32bit error payload. 







XSPI eDMA Driver#


enum _xspi_edma_ntransfer_size

eDMA transfer configuration 
Values:


enumerator kXSPI_EDMAnSize1Bytes

Source/Destination data transfer size is 1 byte every time 




enumerator kXSPI_EDMAnSize2Bytes

Source/Destination data transfer size is 2 bytes every time 




enumerator kXSPI_EDMAnSize4Bytes

Source/Destination data transfer size is 4 bytes every time 




enumerator kXSPI_EDMAnSize8Bytes

Source/Destination data transfer size is 8 bytes every time 




enumerator kXSPI_EDMAnSize32Bytes

Source/Destination data transfer size is 32 bytes every time 






typedef struct _xspi_edma_handle xspi_edma_handle_t





typedef void (*xspi_edma_callback_t)(XSPI_Type *base, xspi_edma_handle_t *handle, status_t status, void *userData)

XSPI eDMA transfer callback function for finish and error. 




typedef enum _xspi_edma_ntransfer_size xspi_edma_transfer_nsize_t

eDMA transfer configuration 




FSL_XSPI_EDMA_DRIVER_VERSION

XSPI EDMA driver version 2.0.5. 




void XSPI_TransferCreateHandleEDMA(XSPI_Type *base, xspi_edma_handle_t *handle, xspi_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)

Initializes the XSPI handle for transfer which is used in transactional functions and set the callback. 

Parameters:

base – XSPI peripheral base address 
handle – Pointer to xspi_edma_handle_t structure 
callback – XSPI callback, NULL means no callback. 
userData – User callback function data. 
txDmaHandle – User requested DMA handle for TX DMA transfer. 
rxDmaHandle – User requested DMA handle for RX DMA transfer. 







void XSPI_TransferUpdateSizeEDMA(XSPI_Type *base, xspi_edma_handle_t *handle, xspi_edma_transfer_nsize_t nsize)

Update XSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE). 

See also
xspi_edma_transfer_nsize_t . 



Parameters:

base – XSPI peripheral base address 
handle – Pointer to xspi_edma_handle_t structure 
nsize – XSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is kFLEXPSI_EDMAnSize1Bytes(one byte). 







status_t XSPI_TransferEDMA(XSPI_Type *base, xspi_edma_handle_t *handle, xspi_transfer_t *xfer)

Transfers XSPI data using an eDMA non-blocking method. 
This function writes/receives data to/from the XSPI transmit/receive FIFO. This function is non-blocking. 

Parameters:

base – XSPI peripheral base address. 
handle – Pointer to xspi_edma_handle_t structure 
xfer – XSPI transfer structure. 


Return values:

kStatus_XSPI_Busy – XSPI is busy transfer. 
kStatus_InvalidArgument – The watermark configuration is invalid, the watermark should be power of 2 to do successfully EDMA transfer. 
kStatus_Success – XSPI successfully start edma transfer. 







void XSPI_TransferAbortEDMA(XSPI_Type *base, xspi_edma_handle_t *handle)

Aborts the transfer data using eDMA. 
This function aborts the transfer data using eDMA.

Parameters:

base – XSPI peripheral base address. 
handle – Pointer to xspi_edma_handle_t structure 







status_t XSPI_TransferGetTransferCountEDMA(XSPI_Type *base, xspi_edma_handle_t *handle, size_t *count)

Gets the transferred counts of transfer. 

Parameters:

base – XSPI peripheral base address. 
handle – Pointer to xspi_edma_handle_t structure. 
count – Bytes transfer. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







edma_handle_t *txDmaHandle

eDMA handler for XSPI Tx. 




edma_handle_t *rxDmaHandle

eDMA handler for XSPI Rx. 




size_t transferSize

Bytes need to transfer. 




xspi_edma_transfer_nsize_t nsize

eDMA SSIZE/DSIZE in each transfer. 




uint32_t nbytes

eDMA minor byte transfer count initially configured. 




uint8_t count

The transfer data count in a DMA request. 




uint32_t state

Internal state for XSPI eDMA transfer. 




xspi_edma_callback_t completionCallback

A callback function called after the eDMA transfer is finished. 




void *userData

User callback parameter 




struct _xspi_edma_handle


#include <fsl_xspi_edma.h>
XSPI DMA transfer handle, users should not touch the content of the handle.

MIMX94398

Contents

MIMX94398#

AOI: Crossbar AND/OR/INVERT Driver#

Battery-Backed Non-Secure Module#

BiSS: BiSS Interface#

CACHE: ARMV7-M7 CACHE Memory Controller#

Clock Driver#

DCIF: Display control Interface#

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

eDMA core Driver#

eDMA soc Driver#

EnDat2.2: EnDat2.2 Interface#

Endat3: Endat3 encoder Driver#

EQDC: Enhanced Quadrature Encoder/Decoder#

EWM: External Watchdog Monitor Driver#

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

FlexCAN eDMA Driver#

FlexIO: FlexIO Driver#

Flexio_a-format#

FlexIO Driver#

FlexIO eDMA I2S Driver#

FlexIO eDMA SPI Driver#

FlexIO eDMA UART Driver#

FlexIO I2C Master Driver#

FlexIO I2S Driver#

FlexIO SPI Driver#

Flexio_t-format#

FlexIO UART Driver#

FlexPWM: Enhanced Flex Pulse Width Modulator#

GPT: General Purpose Timer#

Hiperface: Hiperface encoder Driver#

I3C: I3C Driver#

I3C Common Driver#

I3C Master Driver#

I3C Master DMA Driver#

I3C Slave Driver#

I3C Slave DMA Driver#

IGF: Input Glitch Filter#

IOMUXC: IOMUX Controller#

IRQSTEER: Interrupt Request Steering Driver#

Common Driver#

LPI2C: Low Power Inter-Integrated Circuit Driver#

LPI2C Master Driver#

LPI2C Master DMA Driver#

LPI2C Slave Driver#

LPIT: Low-Power Interrupt Timer#

LPSPI: Low Power Serial Peripheral Interface#

LPSPI Peripheral driver#

LPSPI eDMA Driver#

LPTMR: Low-Power Timer#

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver#

LPUART Driver#

LPUART eDMA Driver#

MCM: Miscellaneous Control Module#

MSGINTR: Message Unit#

MSGINTR Driver#

MU: Messaging Unit#

MX943_RST_driver#

NETC driver#

Abbreviation in NETC driver#

API layer#

NETC Endpoint (EP) Driver#

Endpoint (EP) Generic Configuration#

Endpoint (EP) data path#

Endpoint (EP) Interrupt Module#

Endpoint (EP) Table Management Module#

Endpoint (EP) PSI/VSI#

Endpoint (EP) Ingress data path configuration#

Endpoint (EP) Statistic Module#

Endpoint (EP) Egress data path configuration#

Endpoint (EP) Transmit/Receive#

Hardware layer#

Hardware Common Functions#

Hardware ENETC#

Hardware Port#

Hardware Port MAC#

Hardware Port Rx#