ISSDK  1.8
IoT Sensing Software Development Kit
board.h
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _BOARD_H_
9 #define _BOARD_H_
10 
11 #include "clock_config.h"
12 #include "fsl_common.h"
13 #include "fsl_gpio.h"
14 
15 /*******************************************************************************
16  * Definitions
17  ******************************************************************************/
18 /*! @brief The board name */
19 #define BOARD_NAME "MIMXRT1020-EVK"
20 
21 /* The UART to use for debug messages. */
22 #define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
23 #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24 #define BOARD_DEBUG_UART_INSTANCE 1U
25 
26 #define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27 
28 #define BOARD_UART_IRQ LPUART1_IRQn
29 #define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30 
31 #ifndef BOARD_DEBUG_UART_BAUDRATE
32 #define BOARD_DEBUG_UART_BAUDRATE (115200U)
33 #endif /* BOARD_DEBUG_UART_BAUDRATE */
34 
35 /* @Brief Board accelerator sensor configuration */
36 #define BOARD_ACCEL_I2C_BASEADDR LPI2C4
37 #define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38 #define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39 #define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40 
41 #define BOARD_CODEC_I2C_BASEADDR LPI2C1
42 #define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
43 #define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
44 #define BOARD_CODEC_I2C_CLOCK_FREQ ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER + 1U))
45 
46 /*! @brief The USER_LED used for board */
47 #define LOGIC_LED_ON (0U)
48 #define LOGIC_LED_OFF (1U)
49 #ifndef BOARD_USER_LED_GPIO
50 #define BOARD_USER_LED_GPIO GPIO1
51 #endif
52 #ifndef BOARD_USER_LED_GPIO_PIN
53 #define BOARD_USER_LED_GPIO_PIN (5U)
54 #endif
55 
56 #define USER_LED_INIT(output) \
57  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
58  BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
59 #define USER_LED_ON() \
60  GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
61 #define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
62 #define USER_LED_TOGGLE() \
63  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
64  0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
65 
66 /*! @brief Define the port interrupt number for the board switches */
67 #ifndef BOARD_USER_BUTTON_GPIO
68 #define BOARD_USER_BUTTON_GPIO GPIO5
69 #endif
70 #ifndef BOARD_USER_BUTTON_GPIO_PIN
71 #define BOARD_USER_BUTTON_GPIO_PIN (0U)
72 #endif
73 #define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
74 #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
75 #define BOARD_USER_BUTTON_NAME "SW4"
76 
77 /*! @brief The hyper flash size */
78 #define BOARD_FLASH_SIZE (0x800000U)
79 
80 /*! @brief The ENET PHY address. */
81 #define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
82 
83 /* USB PHY condfiguration */
84 #define BOARD_USB_PHY_D_CAL (0x0CU)
85 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
86 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
87 
88 #define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
89 #define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
90 #define BOARD_ARDUINO_I2C_INDEX (4)
91 #define BOARD_USDHC1_BASEADDR USDHC1
92 #define BOARD_USDHC2_BASEADDR USDHC2
93 #define BOARD_USDHC_CD_GPIO_BASE GPIO2
94 #define BOARD_USDHC_CD_GPIO_PIN 28
95 #define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
96 #define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
97 
98 #define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
99 
100 #define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
101 #define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
102 
103 #define BOARD_USDHC_CD_GPIO_INIT() \
104  { \
105  gpio_pin_config_t sw_config = { \
106  kGPIO_DigitalInput, 0, kGPIO_IntFallingEdge, \
107  }; \
108  GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
109  GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
110  GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
111  }
112 
113 #define BOARD_HAS_SDCARD (1U)
114 #define BOARD_SD_POWER_RESET_GPIO (GPIO1)
115 #define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
116 
117 #define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
118 
119 #define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
120 
121 #define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
122  { \
123  gpio_pin_config_t sw_config = { \
124  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
125  }; \
126  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
127  GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
128  }
129 
130 #define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
131  { \
132  gpio_pin_config_t sw_config = { \
133  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
134  }; \
135  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
136  }
137 
138 #define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
139  (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
140 
141 #define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
142 #define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
143 
144 #define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
145 #define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
146 #define BOARD_SD_HOST_IRQ USDHC1_IRQn
147 
148 #define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
149 #define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
150 #define BOARD_MMC_HOST_IRQ USDHC2_IRQn
151 #define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
152 #define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
153 /* we are using the BB SD socket to DEMO the MMC example,but the
154 * SD socket provide 4bit bus only, so we define this macro to avoid
155 * 8bit data bus test
156 */
157 #define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
158 
159 #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
160 #define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
161 /* define for SD/MMC config IO driver strength dynamic */
162 #define BOARD_SD_PIN_CONFIG(speed, strength) \
163  { \
164  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, \
165  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
166  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
167  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
168  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
169  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, \
170  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
171  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
172  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
173  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, \
174  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
175  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
176  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
177  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
178  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, \
179  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
180  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
181  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
182  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
183  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, \
184  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
185  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
186  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
187  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
188  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, \
189  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
190  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
191  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
192  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
193  }
194 
195 #define BOARD_MMC_PIN_CONFIG(speed, strength) \
196  { \
197  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, \
198  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
199  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
200  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
201  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
202  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, \
203  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
204  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
205  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
206  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, \
207  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
208  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
209  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
210  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
211  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, \
212  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
213  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
214  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
215  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
216  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, \
217  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
218  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
219  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
220  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
221  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, \
222  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
223  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
224  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
225  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
226  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4, \
227  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
228  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
229  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
230  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
231  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5, \
232  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
233  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
234  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
235  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
236  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6, \
237  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
238  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
239  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
240  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
241  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7, \
242  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
243  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
244  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
245  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
246  }
247 
248 /*! @brief The WIFI-QCA shield pin. */
249 #define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
250 #define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
251 #define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
252 #define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
253 #define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
254 #define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
255 #define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
256 
257 #define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
258 #define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
259 #define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
260 #define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
261 #define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
262 #define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
263 #define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
264 
265 #if defined(__cplusplus)
266 extern "C" {
267 #endif /* __cplusplus */
268 
269 /*******************************************************************************
270  * API
271  ******************************************************************************/
272 uint32_t BOARD_DebugConsoleSrcFreq(void);
273 
274 void BOARD_InitDebugConsole(void);
275 void BOARD_ConfigMPU(void);
276 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
277 void BOARD_InitDebugConsole(void);
278 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
279 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
280  uint8_t deviceAddress,
281  uint32_t subAddress,
282  uint8_t subaddressSize,
283  uint8_t *txBuff,
284  uint8_t txBuffSize);
285 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
286  uint8_t deviceAddress,
287  uint32_t subAddress,
288  uint8_t subaddressSize,
289  uint8_t *rxBuff,
290  uint8_t rxBuffSize);
291 void BOARD_Accel_I2C_Init(void);
292 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
293 status_t BOARD_Accel_I2C_Receive(
294  uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
295 void BOARD_Codec_I2C_Init(void);
296 status_t BOARD_Codec_I2C_Send(
297  uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
298 status_t BOARD_Codec_I2C_Receive(
299  uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
300 #endif /* SDK_I2C_BASED_COMPONENT_USED */
301 
302 #if defined(__cplusplus)
303 }
304 #endif /* __cplusplus */
305 
306 #endif /* _BOARD_H_ */
BOARD_InitDebugConsole
void BOARD_InitDebugConsole(void)
Definition: board.c:15
BOARD_DebugConsoleSrcFreq
uint32_t BOARD_DebugConsoleSrcFreq(void)
Definition: board.c:25
BOARD_ConfigMPU
void BOARD_ConfigMPU(void)
Definition: board.c:52
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