ISSDK  1.8
IoT Sensing Software Development Kit
board.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  *
7  * SPDX-License-Identifier: BSD-3-Clause
8  */
9 
10 #ifndef _BOARD_H_
11 #define _BOARD_H_
12 
13 #include "clock_config.h"
14 #include "fsl_common.h"
15 #include "fsl_gpio.h"
16 
17 /*******************************************************************************
18  * Definitions
19  ******************************************************************************/
20 /*! @brief The board name */
21 #define BOARD_NAME "IMXRT1050-EVKB"
22 
23 /* The UART to use for debug messages. */
24 #define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
25 #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
26 #define BOARD_DEBUG_UART_INSTANCE 1U
27 
28 #define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
29 
30 #define BOARD_UART_IRQ LPUART1_IRQn
31 #define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
32 
33 #ifndef BOARD_DEBUG_UART_BAUDRATE
34 #define BOARD_DEBUG_UART_BAUDRATE (115200U)
35 #endif /* BOARD_DEBUG_UART_BAUDRATE */
36 
37 /*! @brief The USER_LED used for board */
38 #define LOGIC_LED_ON (0U)
39 #define LOGIC_LED_OFF (1U)
40 #ifndef BOARD_USER_LED_GPIO
41 #define BOARD_USER_LED_GPIO GPIO1
42 #endif
43 #ifndef BOARD_USER_LED_GPIO_PIN
44 #define BOARD_USER_LED_GPIO_PIN (9U)
45 #endif
46 
47 #define USER_LED_INIT(output) \
48  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
49  BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
50 #define USER_LED_ON() \
51  GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
52 #define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
53 #define USER_LED_TOGGLE() \
54  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
55  0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
56 
57 /*! @brief Define the port interrupt number for the board switches */
58 #ifndef BOARD_USER_BUTTON_GPIO
59 #define BOARD_USER_BUTTON_GPIO GPIO5
60 #endif
61 #ifndef BOARD_USER_BUTTON_GPIO_PIN
62 #define BOARD_USER_BUTTON_GPIO_PIN (0U)
63 #endif
64 #define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
65 #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
66 #define BOARD_USER_BUTTON_NAME "SW8"
67 
68 /*! @brief The Enet instance used for board. */
69 #define BOARD_ENET_BASEADDR ENET
70 
71 /*! @brief The ENET PHY address. */
72 #define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
73 
74 /* USB PHY condfiguration */
75 #define BOARD_USB_PHY_D_CAL (0x0CU)
76 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
77 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
78 
79 #define BOARD_USDHC1_BASEADDR USDHC1
80 #define BOARD_USDHC2_BASEADDR USDHC2
81 #define BOARD_USDHC_CD_GPIO_BASE GPIO2
82 #define BOARD_USDHC_CD_GPIO_PIN 28
83 #define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
84 #define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
85 
86 #define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
87 
88 #define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
89 #define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
90 
91 #define BOARD_USDHC_CD_GPIO_INIT() \
92  { \
93  gpio_pin_config_t sw_config = { \
94  kGPIO_DigitalInput, 0, kGPIO_IntFallingEdge, \
95  }; \
96  GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
97  GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
98  GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
99  }
100 
101 #define BOARD_SD_POWER_RESET_GPIO (GPIO1)
102 #define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
103 
104 #define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
105 
106 #define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
107 
108 #define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
109  { \
110  gpio_pin_config_t sw_config = { \
111  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
112  }; \
113  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
114  GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
115  }
116 
117 #define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
118  { \
119  gpio_pin_config_t sw_config = { \
120  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
121  }; \
122  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
123  }
124 
125 #define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
126  (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
127 
128 #define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
129 #define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
130 
131 #define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
132 #define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
133 #define BOARD_SD_HOST_IRQ USDHC1_IRQn
134 
135 #define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
136 #define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
137 #define BOARD_MMC_HOST_IRQ USDHC2_IRQn
138 #define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
139 #define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
140 /* we are using the BB SD socket to DEMO the MMC example,but the
141 * SD socket provide 4bit bus only, so we define this macro to avoid
142 * 8bit data bus test
143 */
144 #define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
145 
146 #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
147 #define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
148 /* define for SD/MMC config IO driver strength dynamic */
149 #define BOARD_SD_PIN_CONFIG(speed, strength) \
150  { \
151  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, \
152  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
153  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
154  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
155  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
156  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, \
157  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
158  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
159  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
160  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, \
161  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
162  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
163  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
164  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
165  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, \
166  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
167  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
168  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
169  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
170  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, \
171  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
172  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
173  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
174  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
175  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, \
176  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
177  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
178  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
179  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
180  }
181 
182 #define BOARD_MMC_PIN_CONFIG(speed, strength) \
183  { \
184  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, \
185  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
186  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
187  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
188  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
189  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, \
190  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
191  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
192  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
193  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, \
194  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
195  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
196  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
197  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
198  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, \
199  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
200  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
201  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
202  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
203  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, \
204  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
205  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
206  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
207  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
208  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, \
209  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
210  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
211  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
212  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
213  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4, \
214  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
215  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
216  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
217  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
218  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5, \
219  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
220  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
221  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
222  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
223  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6, \
224  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
225  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
226  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
227  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
228  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7, \
229  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
230  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
231  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
232  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
233  }
234 
235 /*! @brief The WIFI-QCA shield pin. */
236 #define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
237 #define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
238 #define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
239 #define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
240 #define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
241 #define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
242 #define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
243 
244 #define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
245 #define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
246 #define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
247 #define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
248 #define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
249 #define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
250 #define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
251 
252 #if defined(__cplusplus)
253 extern "C" {
254 #endif /* __cplusplus */
255 
256 /*******************************************************************************
257  * API
258  ******************************************************************************/
259 uint32_t BOARD_DebugConsoleSrcFreq(void);
260 
261 void BOARD_InitDebugConsole(void);
262 
263 #if defined(__cplusplus)
264 }
265 #endif /* __cplusplus */
266 
267 #endif /* _BOARD_H_ */
BOARD_InitDebugConsole
void BOARD_InitDebugConsole(void)
Definition: board.c:15
BOARD_DebugConsoleSrcFreq
uint32_t BOARD_DebugConsoleSrcFreq(void)
Definition: board.c:25
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