ISSDK  1.8
IoT Sensing Software Development Kit
board.h
Go to the documentation of this file.
1 /*
2  * Copyright 2018 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef _BOARD_H_
10 #define _BOARD_H_
11 
12 #include "clock_config.h"
13 #include "fsl_common.h"
14 #include "fsl_gpio.h"
15 
16 /*******************************************************************************
17  * Definitions
18  ******************************************************************************/
19 /*! @brief The board name */
20 #define BOARD_NAME "MIMXRT1060-EVK"
21 
22 /* The UART to use for debug messages. */
23 #define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
24 #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
25 #define BOARD_DEBUG_UART_INSTANCE 1U
26 
27 #define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
28 
29 #define BOARD_UART_IRQ LPUART1_IRQn
30 #define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
31 
32 #ifndef BOARD_DEBUG_UART_BAUDRATE
33 #define BOARD_DEBUG_UART_BAUDRATE (115200U)
34 #endif /* BOARD_DEBUG_UART_BAUDRATE */
35 
36 /*! @brief The USER_LED used for board */
37 #define LOGIC_LED_ON (0U)
38 #define LOGIC_LED_OFF (1U)
39 #ifndef BOARD_USER_LED_GPIO
40 #define BOARD_USER_LED_GPIO GPIO1
41 #endif
42 #ifndef BOARD_USER_LED_GPIO_PIN
43 #define BOARD_USER_LED_GPIO_PIN (9U)
44 #endif
45 
46 #define USER_LED_INIT(output) \
47  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
48  BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
49 #define USER_LED_ON() \
50  GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
51 #define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
52 #define USER_LED_TOGGLE() \
53  GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
54  0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
55 
56 /*! @brief Define the port interrupt number for the board switches */
57 #ifndef BOARD_USER_BUTTON_GPIO
58 #define BOARD_USER_BUTTON_GPIO GPIO5
59 #endif
60 #ifndef BOARD_USER_BUTTON_GPIO_PIN
61 #define BOARD_USER_BUTTON_GPIO_PIN (0U)
62 #endif
63 #define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
64 #define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
65 #define BOARD_USER_BUTTON_NAME "SW8"
66 
67 /*! @brief The hyper flash size */
68 #define BOARD_FLASH_SIZE (0x4000000U)
69 
70 /*! @brief The Enet instance used for board. */
71 #define BOARD_ENET_BASEADDR ENET
72 
73 /*! @brief The ENET PHY address. */
74 #define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
75 
76 /* USB PHY condfiguration */
77 #define BOARD_USB_PHY_D_CAL (0x0CU)
78 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
79 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
80 
81 #define BOARD_USDHC1_BASEADDR USDHC1
82 #define BOARD_USDHC2_BASEADDR USDHC2
83 #define BOARD_USDHC_CD_GPIO_BASE GPIO2
84 #define BOARD_USDHC_CD_GPIO_PIN 28
85 #define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
86 #define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
87 
88 #define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
89 
90 #define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
91 #define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
92 
93 #define BOARD_USDHC_CD_GPIO_INIT() \
94  { \
95  gpio_pin_config_t sw_config = { \
96  kGPIO_DigitalInput, 0, kGPIO_IntFallingEdge, \
97  }; \
98  GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
99  GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
100  GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
101  }
102 
103 #define BOARD_SD_POWER_RESET_GPIO (GPIO1)
104 #define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
105 
106 #define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
107 
108 #define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
109 
110 #define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
111  { \
112  gpio_pin_config_t sw_config = { \
113  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
114  }; \
115  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
116  GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
117  }
118 
119 #define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
120  { \
121  gpio_pin_config_t sw_config = { \
122  kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
123  }; \
124  GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
125  }
126 
127 #define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
128  (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
129 
130 #define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
131 #define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
132 
133 #define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
134 #define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
135 #define BOARD_SD_HOST_IRQ USDHC1_IRQn
136 
137 #define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
138 #define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
139 #define BOARD_MMC_HOST_IRQ USDHC2_IRQn
140 #define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
141 #define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
142 /* we are using the BB SD socket to DEMO the MMC example,but the
143 * SD socket provide 4bit bus only, so we define this macro to avoid
144 * 8bit data bus test
145 */
146 #define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
147 
148 #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
149 #define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
150 /* define for SD/MMC config IO driver strength dynamic */
151 #define BOARD_SD_PIN_CONFIG(speed, strength) \
152  { \
153  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, \
154  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
155  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
156  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
157  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
158  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, \
159  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
160  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
161  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
162  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, \
163  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
164  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
165  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
166  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
167  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, \
168  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
169  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
170  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
171  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
172  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, \
173  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
174  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
175  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
176  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
177  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, \
178  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
179  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
180  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
181  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
182  }
183 
184 #define BOARD_MMC_PIN_CONFIG(speed, strength) \
185  { \
186  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD, \
187  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
188  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
189  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
190  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
191  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK, \
192  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
193  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | \
194  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
195  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0, \
196  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
197  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
198  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
199  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
200  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1, \
201  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
202  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
203  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
204  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
205  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2, \
206  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
207  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
208  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
209  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
210  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3, \
211  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
212  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
213  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
214  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
215  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4, \
216  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
217  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
218  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
219  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
220  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5, \
221  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
222  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
223  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
224  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
225  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6, \
226  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
227  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
228  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
229  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
230  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7, \
231  IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | \
232  IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
233  IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | \
234  IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); \
235  }
236 
237 /*! @brief The WIFI-QCA shield pin. */
238 #define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
239 #define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
240 #define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
241 #define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
242 #define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
243 #define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
244 #define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
245 
246 #define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
247 #define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
248 #define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
249 #define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
250 #define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
251 #define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
252 #define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
253 
254 #if defined(__cplusplus)
255 extern "C" {
256 #endif /* __cplusplus */
257 
258 /*******************************************************************************
259  * API
260  ******************************************************************************/
261 uint32_t BOARD_DebugConsoleSrcFreq(void);
262 
263 void BOARD_InitDebugConsole(void);
264 
265 #if defined(__cplusplus)
266 }
267 #endif /* __cplusplus */
268 
269 #endif /* _BOARD_H_ */
BOARD_InitDebugConsole
void BOARD_InitDebugConsole(void)
Definition: board.c:15
BOARD_DebugConsoleSrcFreq
uint32_t BOARD_DebugConsoleSrcFreq(void)
Definition: board.c:25
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