ISSDK  1.8
IoT Sensing Software Development Kit
pin_mux.c
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1 /*
2  * Copyright 2019 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 
13 /* clang-format off */
14 /*
15  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16 !!GlobalInfo
17 product: Pins v5.0
18 processor: MIMXRT685S
19 package_id: MIMXRT685SEVKA
20 mcu_data: ksdk2_0
21 processor_version: 0.0.0
22  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
23  */
24 /* clang-format on */
25 
26 #include "fsl_common.h"
27 #include "fsl_iopctl.h"
28 #include "pin_mux.h"
29 
30 /* FUNCTION ************************************************************************************************************
31  *
32  * Function Name : BOARD_InitBootPins
33  * Description : Calls initialization functions.
34  *
35  * END ****************************************************************************************************************/
36 void BOARD_InitBootPins(void)
37 {
38  BOARD_InitPins();
39 }
40 
41 /* clang-format off */
42 /*
43  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
44 BOARD_InitPins:
45 - options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
46 - pin_list:
47  - {pin_num: G2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/SEC_P0_1, direction: OUTPUT, pupdena: disabled,
48  pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
49  - {pin_num: G4, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/SEC_P0_2, direction: INPUT, pupdena: disabled,
50  pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
51  - {pin_num: D7, peripheral: FLEXCOMM2, signal: CTS_SDA_SSEL0, pin_signal: PIO0_17/FC2_CTS_SDA_SSEL0/SCT0_PIN_INP3/SCT0_OUT3/CTIMER2_MAT3/FC5_SSEL2/SEC_P0_17, pupdena: enabled,
52  pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled}
53  - {pin_num: B7, peripheral: FLEXCOMM2, signal: RTS_SCL_SSEL1, pin_signal: PIO0_18/FC2_RTS_SCL_SSEL1/SCT0_PIN_INP6/SCT0_OUT6/CTIMER_INP4/FC5_SSEL3/SEC_P0_18, direction: OUTPUT,
54  pupdena: enabled, pupdsel: pullUp, ibena: enabled, slew_rate: normal, drive: full, amena: disabled, odena: enabled, iiena: disabled}
55  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
56  */
57 /* clang-format on */
58 
59 /* FUNCTION ************************************************************************************************************
60  *
61  * Function Name : BOARD_InitPins
62  * Description : Configures pin routing and optionally pin electrical features.
63  *
64  * END ****************************************************************************************************************/
65 /* Function assigned for the Cortex-M33 */
66 void BOARD_InitPins(void)
67 {
68 
69  const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
70  IOPCTL_PIO_FUNC1 |
71  /* Disable pull-up / pull-down function */
72  IOPCTL_PIO_PUPD_DI |
73  /* Enable pull-down function */
74  IOPCTL_PIO_PULLDOWN_EN |
75  /* Disable input buffer function */
76  IOPCTL_PIO_INBUF_DI |
77  /* Normal mode */
78  IOPCTL_PIO_SLEW_RATE_NORMAL |
79  /* Normal drive */
80  IOPCTL_PIO_FULLDRIVE_DI |
81  /* Analog mux is disabled */
82  IOPCTL_PIO_ANAMUX_DI |
83  /* Pseudo Output Drain is disabled */
84  IOPCTL_PIO_PSEDRAIN_DI |
85  /* Input function is not inverted */
86  IOPCTL_PIO_INV_DI);
87  /* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */
88  IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
89 
90  const uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
91  IOPCTL_PIO_FUNC1 |
92  /* Disable pull-up / pull-down function */
93  IOPCTL_PIO_PUPD_DI |
94  /* Enable pull-down function */
95  IOPCTL_PIO_PULLDOWN_EN |
96  /* Enables input buffer function */
97  IOPCTL_PIO_INBUF_EN |
98  /* Normal mode */
99  IOPCTL_PIO_SLEW_RATE_NORMAL |
100  /* Normal drive */
101  IOPCTL_PIO_FULLDRIVE_DI |
102  /* Analog mux is disabled */
103  IOPCTL_PIO_ANAMUX_DI |
104  /* Pseudo Output Drain is disabled */
105  IOPCTL_PIO_PSEDRAIN_DI |
106  /* Input function is not inverted */
107  IOPCTL_PIO_INV_DI);
108  /* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */
109  IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
110 }
111 
112 /* clang-format off */
113 /*
114  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
115 I2C4_InitPins:
116 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
117 - pin_list:
118  - {pin_num: C11, peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_30/FC4_RXD_SDA_MOSI_DATA/CTIMER4_MAT2/SEC_P0_30, pupdena: enabled, pupdsel: pullUp,
119  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: enabled, iiena: disabled}
120  - {pin_num: B10, peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_29/FC4_TXD_SCL_MISO_WS/CTIMER4_MAT1/SEC_P0_29, pupdena: enabled, pupdsel: pullUp,
121  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: enabled, iiena: disabled}
122  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
123  */
124 /* clang-format on */
125 
126 /* FUNCTION ************************************************************************************************************
127  *
128  * Function Name : I2C4_InitPins
129  * Description : Configures pin routing and optionally pin electrical features.
130  *
131  * END ****************************************************************************************************************/
132 /* Function assigned for the Cortex-M33 */
133 void I2C2_InitPins(void)
134 {
135 
136  const uint32_t port0_pin17_config = (/* Pin is configured as FC2_CTS_SDA_SSEL0 */
137  IOPCTL_PIO_FUNC1 |
138  /* Enable pull-up / pull-down function */
139  IOPCTL_PIO_PUPD_EN |
140  /* Enable pull-up function */
141  IOPCTL_PIO_PULLUP_EN |
142  /* Enables input buffer function */
143  IOPCTL_PIO_INBUF_EN |
144  /* Normal mode */
145  IOPCTL_PIO_SLEW_RATE_NORMAL |
146  /* Full drive enable */
147  IOPCTL_PIO_FULLDRIVE_EN |
148  /* Analog mux is disabled */
149  IOPCTL_PIO_ANAMUX_DI |
150  /* Pseudo Output Drain is enabled */
151  IOPCTL_PIO_PSEDRAIN_EN |
152  /* Input function is not inverted */
153  IOPCTL_PIO_INV_DI);
154  /* PORT0 PIN17 (coords: D7) is configured as FC2_CTS_SDA_SSEL0 */
155  IOPCTL_PinMuxSet(IOPCTL, 0U, 17U, port0_pin17_config);
156 
157  const uint32_t port0_pin18_config = (/* Pin is configured as FC2_RTS_SCL_SSEL1 */
158  IOPCTL_PIO_FUNC1 |
159  /* Enable pull-up / pull-down function */
160  IOPCTL_PIO_PUPD_EN |
161  /* Enable pull-up function */
162  IOPCTL_PIO_PULLUP_EN |
163  /* Enables input buffer function */
164  IOPCTL_PIO_INBUF_EN |
165  /* Normal mode */
166  IOPCTL_PIO_SLEW_RATE_NORMAL |
167  /* Full drive enable */
168  IOPCTL_PIO_FULLDRIVE_EN |
169  /* Analog mux is disabled */
170  IOPCTL_PIO_ANAMUX_DI |
171  /* Pseudo Output Drain is enabled */
172  IOPCTL_PIO_PSEDRAIN_EN |
173  /* Input function is not inverted */
174  IOPCTL_PIO_INV_DI);
175  /* PORT0 PIN18 (coords: B7) is configured as FC2_RTS_SCL_SSEL1 */
176  IOPCTL_PinMuxSet(IOPCTL, 0U, 18U, port0_pin18_config);
177 }
178 
179 /* clang-format off */
180 /*
181  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
182 I2C4_DeinitPins:
183 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
184 - pin_list:
185  - {pin_num: C11, peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_30/FC4_RXD_SDA_MOSI_DATA/CTIMER4_MAT2/SEC_P0_30, pupdena: enabled, pupdsel: pullUp,
186  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: enabled, iiena: disabled}
187  - {pin_num: B10, peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_29/FC4_TXD_SCL_MISO_WS/CTIMER4_MAT1/SEC_P0_29, pupdena: enabled, pupdsel: pullUp,
188  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: enabled, iiena: disabled}
189  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
190  */
191 /* clang-format on */
192 
193 /* FUNCTION ************************************************************************************************************
194  *
195  * Function Name : I2C4_DeinitPins
196  * Description : Configures pin routing and optionally pin electrical features.
197  *
198  * END ****************************************************************************************************************/
199 /* Function assigned for the Cortex-M33 */
200 void I2C2_DeinitPins(void)
201 {
202 
203  const uint32_t port0_pin17_config = (/* Pin is configured as FC2_CTS_SDA_SSEL0 */
204  IOPCTL_PIO_FUNC1 |
205  /* Disable pull-up / pull-down function */
206  IOPCTL_PIO_PUPD_DI |
207  /* Enable pull-down function */
208  IOPCTL_PIO_PULLDOWN_EN |
209  /* Disable input buffer function */
210  IOPCTL_PIO_INBUF_DI |
211  /* Normal mode */
212  IOPCTL_PIO_SLEW_RATE_NORMAL |
213  /* Normal drive */
214  IOPCTL_PIO_FULLDRIVE_DI |
215  /* Analog mux is disabled */
216  IOPCTL_PIO_ANAMUX_DI |
217  /* Pseudo Output Drain is disabled */
218  IOPCTL_PIO_PSEDRAIN_DI |
219  /* Input function is not inverted */
220  IOPCTL_PIO_INV_DI);
221  /* PORT0 PIN17 (coords: D7) is configured as FC2_CTS_SDA_SSEL0 */
222  IOPCTL_PinMuxSet(IOPCTL, 0U, 17U, port0_pin17_config);
223 
224  const uint32_t port0_pin18_config = (/* Pin is configured as FC2_RTS_SCL_SSEL1 */
225  IOPCTL_PIO_FUNC1 |
226  /* Disable pull-up / pull-down function */
227  IOPCTL_PIO_PUPD_DI |
228  /* Enable pull-down function */
229  IOPCTL_PIO_PULLDOWN_EN |
230  /* Disable input buffer function */
231  IOPCTL_PIO_INBUF_DI |
232  /* Normal mode */
233  IOPCTL_PIO_SLEW_RATE_NORMAL |
234  /* Normal drive */
235  IOPCTL_PIO_FULLDRIVE_DI |
236  /* Analog mux is disabled */
237  IOPCTL_PIO_ANAMUX_DI |
238  /* Pseudo Output Drain is disabled */
239  IOPCTL_PIO_PSEDRAIN_DI |
240  /* Input function is not inverted */
241  IOPCTL_PIO_INV_DI);
242  /* PORT0 PIN18 (coords: B7) is configured as FC2_RTS_SCL_SSEL1 */
243  IOPCTL_PinMuxSet(IOPCTL, 0U, 18U, port0_pin18_config);
244 }
245 
246 /* clang-format off */
247 /*
248  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
249 SPI5_InitPins:
250 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
251 - pin_list:
252  - {pin_num: G16, peripheral: FLEXCOMM5, signal: SCK, pin_signal: PIO1_3/FC5_SCK, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal, drive: normal,
253  amena: disabled, odena: disabled, iiena: disabled}
254  - {pin_num: G17, peripheral: FLEXCOMM5, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_4/FC5_TXD_SCL_MISO_WS, pupdena: disabled, pupdsel: pullDown, ibena: enabled, slew_rate: normal,
255  drive: normal, amena: disabled, odena: disabled, iiena: disabled}
256  - {pin_num: J16, peripheral: FLEXCOMM5, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_5/FC5_RXD_SDA_MOSI_DATA, pupdena: disabled, pupdsel: pullDown, ibena: enabled,
257  slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
258  - {pin_num: J17, peripheral: FLEXCOMM5, signal: CTS_SDA_SSEL0, pin_signal: PIO1_6/FC5_CTS_SDA_SSEL0/SCT0_PIN_INP4/SCT0_OUT4/FC4_SSEL2, pupdena: disabled, pupdsel: pullDown,
259  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
260  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
261  */
262 /* clang-format on */
263 
264 /* FUNCTION ************************************************************************************************************
265  *
266  * Function Name : SPI5_InitPins
267  * Description : Configures pin routing and optionally pin electrical features.
268  *
269  * END ****************************************************************************************************************/
270 /* Function assigned for the Cortex-M33 */
271 void SPI5_InitPins(void)
272 {
273 
274  const uint32_t port1_pin3_config = (/* Pin is configured as FC5_SCK */
275  IOPCTL_PIO_FUNC1 |
276  /* Disable pull-up / pull-down function */
277  IOPCTL_PIO_PUPD_DI |
278  /* Enable pull-down function */
279  IOPCTL_PIO_PULLDOWN_EN |
280  /* Enables input buffer function */
281  IOPCTL_PIO_INBUF_EN |
282  /* Normal mode */
283  IOPCTL_PIO_SLEW_RATE_NORMAL |
284  /* Normal drive */
285  IOPCTL_PIO_FULLDRIVE_DI |
286  /* Analog mux is disabled */
287  IOPCTL_PIO_ANAMUX_DI |
288  /* Pseudo Output Drain is disabled */
289  IOPCTL_PIO_PSEDRAIN_DI |
290  /* Input function is not inverted */
291  IOPCTL_PIO_INV_DI);
292  /* PORT1 PIN3 (coords: G16) is configured as FC5_SCK */
293  IOPCTL_PinMuxSet(IOPCTL, 1U, 3U, port1_pin3_config);
294 
295  const uint32_t port1_pin4_config = (/* Pin is configured as FC5_TXD_SCL_MISO_WS */
296  IOPCTL_PIO_FUNC1 |
297  /* Disable pull-up / pull-down function */
298  IOPCTL_PIO_PUPD_DI |
299  /* Enable pull-down function */
300  IOPCTL_PIO_PULLDOWN_EN |
301  /* Enables input buffer function */
302  IOPCTL_PIO_INBUF_EN |
303  /* Normal mode */
304  IOPCTL_PIO_SLEW_RATE_NORMAL |
305  /* Normal drive */
306  IOPCTL_PIO_FULLDRIVE_DI |
307  /* Analog mux is disabled */
308  IOPCTL_PIO_ANAMUX_DI |
309  /* Pseudo Output Drain is disabled */
310  IOPCTL_PIO_PSEDRAIN_DI |
311  /* Input function is not inverted */
312  IOPCTL_PIO_INV_DI);
313  /* PORT1 PIN4 (coords: G17) is configured as FC5_TXD_SCL_MISO_WS */
314  IOPCTL_PinMuxSet(IOPCTL, 1U, 4U, port1_pin4_config);
315 
316  const uint32_t port1_pin5_config = (/* Pin is configured as FC5_RXD_SDA_MOSI_DATA */
317  IOPCTL_PIO_FUNC1 |
318  /* Disable pull-up / pull-down function */
319  IOPCTL_PIO_PUPD_DI |
320  /* Enable pull-down function */
321  IOPCTL_PIO_PULLDOWN_EN |
322  /* Enables input buffer function */
323  IOPCTL_PIO_INBUF_EN |
324  /* Normal mode */
325  IOPCTL_PIO_SLEW_RATE_NORMAL |
326  /* Normal drive */
327  IOPCTL_PIO_FULLDRIVE_DI |
328  /* Analog mux is disabled */
329  IOPCTL_PIO_ANAMUX_DI |
330  /* Pseudo Output Drain is disabled */
331  IOPCTL_PIO_PSEDRAIN_DI |
332  /* Input function is not inverted */
333  IOPCTL_PIO_INV_DI);
334  /* PORT1 PIN5 (coords: J16) is configured as FC5_RXD_SDA_MOSI_DATA */
335  IOPCTL_PinMuxSet(IOPCTL, 1U, 5U, port1_pin5_config);
336 
337  const uint32_t port1_pin6_config = (/* Pin is configured as FC5_CTS_SDA_SSEL0 */
338  IOPCTL_PIO_FUNC1 |
339  /* Disable pull-up / pull-down function */
340  IOPCTL_PIO_PUPD_DI |
341  /* Enable pull-down function */
342  IOPCTL_PIO_PULLDOWN_EN |
343  /* Enables input buffer function */
344  IOPCTL_PIO_INBUF_EN |
345  /* Normal mode */
346  IOPCTL_PIO_SLEW_RATE_NORMAL |
347  /* Normal drive */
348  IOPCTL_PIO_FULLDRIVE_DI |
349  /* Analog mux is disabled */
350  IOPCTL_PIO_ANAMUX_DI |
351  /* Pseudo Output Drain is disabled */
352  IOPCTL_PIO_PSEDRAIN_DI |
353  /* Input function is not inverted */
354  IOPCTL_PIO_INV_DI);
355  /* PORT1 PIN6 (coords: J17) is configured as FC5_CTS_SDA_SSEL0 */
356  IOPCTL_PinMuxSet(IOPCTL, 1U, 6U, port1_pin6_config);
357 }
358 
359 /* clang-format off */
360 /*
361  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
362 SPI5_DeinitPins:
363 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
364 - pin_list:
365  - {pin_num: G16, peripheral: GPIO, signal: 'PIO1, 3', pin_signal: PIO1_3/FC5_SCK, pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal, drive: normal,
366  amena: disabled, odena: disabled, iiena: disabled}
367  - {pin_num: G17, peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC5_TXD_SCL_MISO_WS, pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal,
368  drive: normal, amena: disabled, odena: disabled, iiena: disabled}
369  - {pin_num: J17, peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC5_CTS_SDA_SSEL0/SCT0_PIN_INP4/SCT0_OUT4/FC4_SSEL2, pupdena: disabled, pupdsel: pullDown,
370  ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
371  - {pin_num: J16, peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC5_RXD_SDA_MOSI_DATA, pupdena: disabled, pupdsel: pullDown, ibena: disabled, slew_rate: normal,
372  drive: normal, amena: disabled, odena: disabled, iiena: disabled}
373  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
374  */
375 /* clang-format on */
376 
377 /* FUNCTION ************************************************************************************************************
378  *
379  * Function Name : SPI5_DeinitPins
380  * Description : Configures pin routing and optionally pin electrical features.
381  *
382  * END ****************************************************************************************************************/
383 /* Function assigned for the Cortex-M33 */
384 void SPI5_DeinitPins(void)
385 {
386 
387  const uint32_t port1_pin3_config = (/* Pin is configured as PIO1_3 */
388  IOPCTL_PIO_FUNC0 |
389  /* Disable pull-up / pull-down function */
390  IOPCTL_PIO_PUPD_DI |
391  /* Enable pull-down function */
392  IOPCTL_PIO_PULLDOWN_EN |
393  /* Disable input buffer function */
394  IOPCTL_PIO_INBUF_DI |
395  /* Normal mode */
396  IOPCTL_PIO_SLEW_RATE_NORMAL |
397  /* Normal drive */
398  IOPCTL_PIO_FULLDRIVE_DI |
399  /* Analog mux is disabled */
400  IOPCTL_PIO_ANAMUX_DI |
401  /* Pseudo Output Drain is disabled */
402  IOPCTL_PIO_PSEDRAIN_DI |
403  /* Input function is not inverted */
404  IOPCTL_PIO_INV_DI);
405  /* PORT1 PIN3 (coords: G16) is configured as PIO1_3 */
406  IOPCTL_PinMuxSet(IOPCTL, 1U, 3U, port1_pin3_config);
407 
408  const uint32_t port1_pin4_config = (/* Pin is configured as PIO1_4 */
409  IOPCTL_PIO_FUNC0 |
410  /* Disable pull-up / pull-down function */
411  IOPCTL_PIO_PUPD_DI |
412  /* Enable pull-down function */
413  IOPCTL_PIO_PULLDOWN_EN |
414  /* Disable input buffer function */
415  IOPCTL_PIO_INBUF_DI |
416  /* Normal mode */
417  IOPCTL_PIO_SLEW_RATE_NORMAL |
418  /* Normal drive */
419  IOPCTL_PIO_FULLDRIVE_DI |
420  /* Analog mux is disabled */
421  IOPCTL_PIO_ANAMUX_DI |
422  /* Pseudo Output Drain is disabled */
423  IOPCTL_PIO_PSEDRAIN_DI |
424  /* Input function is not inverted */
425  IOPCTL_PIO_INV_DI);
426  /* PORT1 PIN4 (coords: G17) is configured as PIO1_4 */
427  IOPCTL_PinMuxSet(IOPCTL, 1U, 4U, port1_pin4_config);
428 
429  const uint32_t port1_pin5_config = (/* Pin is configured as PIO1_5 */
430  IOPCTL_PIO_FUNC0 |
431  /* Disable pull-up / pull-down function */
432  IOPCTL_PIO_PUPD_DI |
433  /* Enable pull-down function */
434  IOPCTL_PIO_PULLDOWN_EN |
435  /* Disable input buffer function */
436  IOPCTL_PIO_INBUF_DI |
437  /* Normal mode */
438  IOPCTL_PIO_SLEW_RATE_NORMAL |
439  /* Normal drive */
440  IOPCTL_PIO_FULLDRIVE_DI |
441  /* Analog mux is disabled */
442  IOPCTL_PIO_ANAMUX_DI |
443  /* Pseudo Output Drain is disabled */
444  IOPCTL_PIO_PSEDRAIN_DI |
445  /* Input function is not inverted */
446  IOPCTL_PIO_INV_DI);
447  /* PORT1 PIN5 (coords: J16) is configured as PIO1_5 */
448  IOPCTL_PinMuxSet(IOPCTL, 1U, 5U, port1_pin5_config);
449 
450  const uint32_t port1_pin6_config = (/* Pin is configured as PIO1_6 */
451  IOPCTL_PIO_FUNC0 |
452  /* Disable pull-up / pull-down function */
453  IOPCTL_PIO_PUPD_DI |
454  /* Enable pull-down function */
455  IOPCTL_PIO_PULLDOWN_EN |
456  /* Disable input buffer function */
457  IOPCTL_PIO_INBUF_DI |
458  /* Normal mode */
459  IOPCTL_PIO_SLEW_RATE_NORMAL |
460  /* Normal drive */
461  IOPCTL_PIO_FULLDRIVE_DI |
462  /* Analog mux is disabled */
463  IOPCTL_PIO_ANAMUX_DI |
464  /* Pseudo Output Drain is disabled */
465  IOPCTL_PIO_PSEDRAIN_DI |
466  /* Input function is not inverted */
467  IOPCTL_PIO_INV_DI);
468  /* PORT1 PIN6 (coords: J17) is configured as PIO1_6 */
469  IOPCTL_PinMuxSet(IOPCTL, 1U, 6U, port1_pin6_config);
470 }
471 
472 /* clang-format off */
473 /*
474  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
475 USART0_InitPins:
476 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
477 - pin_list:
478  - {pin_num: G4, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/SEC_P0_2, pupdena: disabled, pupdsel: pullDown,
479  ibena: enabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
480  - {pin_num: G2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/SEC_P0_1, pupdena: disabled, pupdsel: pullDown,
481  ibena: disabled, slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
482  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
483  */
484 /* clang-format on */
485 
486 /* FUNCTION ************************************************************************************************************
487  *
488  * Function Name : USART0_InitPins
489  * Description : Configures pin routing and optionally pin electrical features.
490  *
491  * END ****************************************************************************************************************/
492 /* Function assigned for the Cortex-M33 */
493 void USART0_InitPins(void)
494 {
495 
496  const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
497  IOPCTL_PIO_FUNC1 |
498  /* Disable pull-up / pull-down function */
499  IOPCTL_PIO_PUPD_DI |
500  /* Enable pull-down function */
501  IOPCTL_PIO_PULLDOWN_EN |
502  /* Disable input buffer function */
503  IOPCTL_PIO_INBUF_DI |
504  /* Normal mode */
505  IOPCTL_PIO_SLEW_RATE_NORMAL |
506  /* Normal drive */
507  IOPCTL_PIO_FULLDRIVE_DI |
508  /* Analog mux is disabled */
509  IOPCTL_PIO_ANAMUX_DI |
510  /* Pseudo Output Drain is disabled */
511  IOPCTL_PIO_PSEDRAIN_DI |
512  /* Input function is not inverted */
513  IOPCTL_PIO_INV_DI);
514  /* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */
515  IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
516 
517  const uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
518  IOPCTL_PIO_FUNC1 |
519  /* Disable pull-up / pull-down function */
520  IOPCTL_PIO_PUPD_DI |
521  /* Enable pull-down function */
522  IOPCTL_PIO_PULLDOWN_EN |
523  /* Enables input buffer function */
524  IOPCTL_PIO_INBUF_EN |
525  /* Normal mode */
526  IOPCTL_PIO_SLEW_RATE_NORMAL |
527  /* Normal drive */
528  IOPCTL_PIO_FULLDRIVE_DI |
529  /* Analog mux is disabled */
530  IOPCTL_PIO_ANAMUX_DI |
531  /* Pseudo Output Drain is disabled */
532  IOPCTL_PIO_PSEDRAIN_DI |
533  /* Input function is not inverted */
534  IOPCTL_PIO_INV_DI);
535  /* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */
536  IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
537 }
538 
539 /* clang-format off */
540 /*
541  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
542 USART0_DeinitPins:
543 - options: {callFromInitBoot: 'false', coreID: cm33, enableClock: 'true'}
544 - pin_list:
545  - {pin_num: G4, peripheral: GPIO, signal: 'PIO0, 2', pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/SEC_P0_2, pupdena: disabled, pupdsel: pullDown, ibena: disabled,
546  slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
547  - {pin_num: G2, peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/SEC_P0_1, pupdena: disabled, pupdsel: pullDown, ibena: disabled,
548  slew_rate: normal, drive: normal, amena: disabled, odena: disabled, iiena: disabled}
549  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
550  */
551 /* clang-format on */
552 
553 /* FUNCTION ************************************************************************************************************
554  *
555  * Function Name : USART0_DeinitPins
556  * Description : Configures pin routing and optionally pin electrical features.
557  *
558  * END ****************************************************************************************************************/
559 /* Function assigned for the Cortex-M33 */
560 void USART0_DeinitPins(void)
561 {
562 
563  const uint32_t port0_pin1_config = (/* Pin is configured as PIO0_1 */
564  IOPCTL_PIO_FUNC0 |
565  /* Disable pull-up / pull-down function */
566  IOPCTL_PIO_PUPD_DI |
567  /* Enable pull-down function */
568  IOPCTL_PIO_PULLDOWN_EN |
569  /* Disable input buffer function */
570  IOPCTL_PIO_INBUF_DI |
571  /* Normal mode */
572  IOPCTL_PIO_SLEW_RATE_NORMAL |
573  /* Normal drive */
574  IOPCTL_PIO_FULLDRIVE_DI |
575  /* Analog mux is disabled */
576  IOPCTL_PIO_ANAMUX_DI |
577  /* Pseudo Output Drain is disabled */
578  IOPCTL_PIO_PSEDRAIN_DI |
579  /* Input function is not inverted */
580  IOPCTL_PIO_INV_DI);
581  /* PORT0 PIN1 (coords: G2) is configured as PIO0_1 */
582  IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
583 
584  const uint32_t port0_pin2_config = (/* Pin is configured as PIO0_2 */
585  IOPCTL_PIO_FUNC0 |
586  /* Disable pull-up / pull-down function */
587  IOPCTL_PIO_PUPD_DI |
588  /* Enable pull-down function */
589  IOPCTL_PIO_PULLDOWN_EN |
590  /* Disable input buffer function */
591  IOPCTL_PIO_INBUF_DI |
592  /* Normal mode */
593  IOPCTL_PIO_SLEW_RATE_NORMAL |
594  /* Normal drive */
595  IOPCTL_PIO_FULLDRIVE_DI |
596  /* Analog mux is disabled */
597  IOPCTL_PIO_ANAMUX_DI |
598  /* Pseudo Output Drain is disabled */
599  IOPCTL_PIO_PSEDRAIN_DI |
600  /* Input function is not inverted */
601  IOPCTL_PIO_INV_DI);
602  /* PORT0 PIN2 (coords: G4) is configured as PIO0_2 */
603  IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
604 }
605 /***********************************************************************************************************************
606  * EOF
607  **********************************************************************************************************************/
IOPCTL_PIO_FULLDRIVE_DI
#define IOPCTL_PIO_FULLDRIVE_DI
Normal drive.
Definition: pin_mux.h:142
I2C2_InitPins
void I2C2_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:516
IOPCTL_PIO_PULLDOWN_EN
#define IOPCTL_PIO_PULLDOWN_EN
Enable pull-down function.
Definition: pin_mux.h:147
IOPCTL_PIO_INBUF_DI
#define IOPCTL_PIO_INBUF_DI
Disable input buffer function.
Definition: pin_mux.h:144
IOPCTL_PIO_FUNC1
#define IOPCTL_PIO_FUNC1
Selects pin function 1.
Definition: pin_mux.h:126
IOPCTL_PIO_PULLUP_EN
#define IOPCTL_PIO_PULLUP_EN
Enable pull-up function.
Definition: pin_mux.h:71
IOPCTL_PIO_PSEDRAIN_DI
#define IOPCTL_PIO_PSEDRAIN_DI
Pseudo Output Drain is disabled.
Definition: pin_mux.h:146
SPI5_InitPins
void SPI5_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:570
IOPCTL_PIO_INV_DI
#define IOPCTL_PIO_INV_DI
Input function is not inverted.
Definition: pin_mux.h:145
IOPCTL_PIO_FUNC0
#define IOPCTL_PIO_FUNC0
Selects pin function 0.
Definition: pin_mux.h:143
IOPCTL_PIO_FULLDRIVE_EN
#define IOPCTL_PIO_FULLDRIVE_EN
Full drive enable.
Definition: pin_mux.h:61
IOPCTL_PIO_ANAMUX_DI
#define IOPCTL_PIO_ANAMUX_DI
Analog mux is disabled.
Definition: pin_mux.h:141
IOPCTL_PIO_PSEDRAIN_EN
#define IOPCTL_PIO_PSEDRAIN_EN
Pseudo Output Drain is enabled.
Definition: pin_mux.h:65
IOPCTL_PIO_PUPD_DI
#define IOPCTL_PIO_PUPD_DI
Disable pull-up / pull-down function.
Definition: pin_mux.h:148
I2C2_DeinitPins
void I2C2_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:562
IOPCTL_PIO_SLEW_RATE_NORMAL
#define IOPCTL_PIO_SLEW_RATE_NORMAL
Normal mode.
Definition: pin_mux.h:149
BOARD_InitBootPins
void BOARD_InitBootPins(void)
Calls initialization functions.
Definition: pin_mux.c:36
IOPCTL_PIO_PUPD_EN
#define IOPCTL_PIO_PUPD_EN
Enable pull-up / pull-down function.
Definition: pin_mux.h:72
USART0_DeinitPins
void USART0_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:157
IOPCTL_PIO_INBUF_EN
#define IOPCTL_PIO_INBUF_EN
Enables input buffer function.
Definition: pin_mux.h:128
BOARD_InitPins
void BOARD_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:47
SPI5_DeinitPins
void SPI5_DeinitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:654
USART0_InitPins
void USART0_InitPins(void)
Configures pin routing and optionally pin electrical features.
Definition: pin_mux.c:110
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