ISSDK
1.8
IoT Sensing Software Development Kit
boardkit
frdm-k32l3a6
RTE_Device.h
Go to the documentation of this file.
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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/* Driver name mapping. */
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//#define RTE_I2C0 1
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//#define RTE_I2C0_DMA_EN 0
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#define RTE_I2C3 1
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#define RTE_I2C3_DMA_EN 0
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#define RTE_SPI0 1
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#define RTE_SPI0_DMA_EN 0
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#define RTE_USART0 1
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#define RTE_USART0_DMA_EN 0
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#define RTE_USART1 1
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#define RTE_USART1_DMA_EN 0
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/* UART configuration. */
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#define USART_RX_BUFFER_LEN 64
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#define USART0_RX_BUFFER_ENABLE 1
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#define USART1_RX_BUFFER_ENABLE 1
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#define RTE_USART0_DMA_TX_CH 0
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#define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx
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#define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_TX_DMA_BASE DMA0
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#define RTE_USART0_DMA_RX_CH 1
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#define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx
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#define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART0_DMA_RX_DMA_BASE DMA0
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#define RTE_USART1_DMA_TX_CH 0
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#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx
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#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_TX_DMA_BASE DMA0
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#define RTE_USART1_DMA_RX_CH 1
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#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx
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#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_USART1_DMA_RX_DMA_BASE DMA0
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/* I2C configuration. */
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#define RTE_I2C0_DMA_TX_CH 0
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#define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Tx
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#define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_I2C0_DMA_TX_DMA_BASE DMA0
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#define RTE_I2C0_DMA_RX_CH 1
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#define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Rx
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#define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_I2C0_DMA_RX_DMA_BASE DMA0
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#define RTE_I2C3_DMA_TX_CH 0
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#define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C3Tx
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#define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX1
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#define RTE_I2C3_DMA_TX_DMA_BASE DMA1
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#define RTE_I2C3_DMA_RX_CH 1
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#define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C3Rx
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#define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX1
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#define RTE_I2C3_DMA_RX_DMA_BASE DMA1
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/* SPI configuration. */
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#define RTE_SPI0_PCS_TO_SCK_DELAY 1000
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#define RTE_SPI0_SCK_TO_PSC_DELAY 1000
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#define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000
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#define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs2)
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#define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs2)
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#define RTE_SPI0_DMA_TX_CH 0
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#define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Tx
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#define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_RX_CH 1
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#define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Rx
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#define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0
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#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
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#endif
/* __RTE_DEVICE_H */
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