Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	MU_CLOCKS
	Clock ip name array for MU. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	RGPIO_CLOCKS
	Clock ip name array for RGPIO. More...

#define	FTM_CLOCKS
	Clock ip name array for FTM. More...

#define	GPT_CLOCKS
	Clock ip name array for GPT. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	FLEXSPI_CLOCKS
	Clock ip name array for FLEXSPI. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	LPADC_CLOCKS
	Clock ip name array for LPADC. More...

#define	INTMUX_CLOCKS
	Clock ip name array for INTMUX. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	SEMA42_CLOCKS
	Clock ip name array for SEMA42. More...

#define	TPM_CLOCKS
	Clock ip name array for TPM. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	ESAI_CLOCKS
	Clock ip name array for ESAI. More...

#define	ISI_CLOCKS
	Clock ip name array for ISI. More...

#define	MIPI_CSI2RX_CLOCKS
	Clock ip name array for MIPI CSI2 RX. More...

#define	MIPI_DSI_HOST_CLOCKS
	Clock ip name array for MIPI DSI host. More...

#define	ENET_CLOCKS
	Clock ip name array for ENET. More...

#define	EMVSIM_CLOCKS
	Clock ip name array for EMVSIM. More...

#define	DPU_CLOCKS
	Clock ip name array for DPU. More...

#define	LDB_CLOCKS
	Clock ip name array for LVDS display bridge(LDB). More...

#define	LPCG_TUPLE(rsrc, base) ((uint32_t)((((base) >> 12U) << 10U) \| rsrc))
	LPCG TUPLE macors to map corresponding ip clock name, SCFW API resource index and LPCG Register base address. More...

#define	LPCG_TUPLE_REG_BASE(tuple) ((volatile uint32_t *)((((uint32_t)(tuple) >> 10U) & 0xFFFFFU) << 12U))
	Get the LPCG REG base address. More...

#define	LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU))
	Get the resource index. More...

#define	NV (0U)
	LPCG Cell not available. More...

Enumerations
enum	clock_ip_src_t { kCLOCK_IpSrcNone = 0U, kCLOCK_IpSrcDummy = 1U }
	Clock source for peripherals that support various clock selections. More...

enum	clock_name_t { kCLOCK_CoreSysClk, kCLOCK_CONECTIVITY_AhbClk }
	Clock name used to get clock frequency. More...

enum	clock_ip_name_t
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. More...

Functions
void	CLOCK_Init (sc_ipc_t ipc)
	Initialize Clock module. More...

void	CLOCK_Deinit (void)
	Deinitialize Clock module.

bool	CLOCK_EnableClockExt (clock_ip_name_t name, uint32_t gate)
	Enable the clock for specific IP, with gate setting. More...

static bool	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

bool	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

uint32_t	CLOCK_SetIpFreq (clock_ip_name_t name, uint32_t freq)
	Set the clock frequency for specific IP module. More...

uint32_t	CLOCK_GetIpFreq (clock_ip_name_t name)
	Get the clock frequency for a specific IP module. More...

uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Get the core clock or system clock frequency. More...

void	CLOCK_ConfigLPCG (clock_ip_name_t name, uint32_t swGate, uint32_t hwGate)
	Config the LPCG cell for specific IP. More...

void	CLOCK_SetLpcgGate (volatile uint32_t *regBase, uint32_t swGate, uint32_t hwGate, uint32_t bitsMask)
	Set LPCG gate for specific LPCG. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
	CLOCK driver version 2.1.0. More...

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))

#define MU_CLOCKS

#define GPIO_CLOCKS

Value:

{                        \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
        kCLOCK_HSIO_Gpio,    \
        kCLOCK_LSIO_Gpio0,   \
        kCLOCK_LSIO_Gpio1,   \
        kCLOCK_LSIO_Gpio2,   \
        kCLOCK_LSIO_Gpio3,   \
        kCLOCK_LSIO_Gpio4,   \
        kCLOCK_LSIO_Gpio5,   \
        kCLOCK_LSIO_Gpio6,   \
        kCLOCK_LSIO_Gpio7,   \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
        kCLOCK_IpInvalid,    \
    }

#define RGPIO_CLOCKS

Value:

{                        \
        kCLOCK_M4_0_Rgpio,   \
        kCLOCK_M4_1_Rgpio,   \
    }

#define FTM_CLOCKS

Value:

{                       \
        kCLOCK_DMA_Ftm0,    \
        kCLOCK_DMA_Ftm1,    \
    }

#define GPT_CLOCKS

Value:

{                       \
        kCLOCK_AUDIO_Gpt0,  \
        kCLOCK_AUDIO_Gpt1,  \
        kCLOCK_AUDIO_Gpt2,  \
        kCLOCK_AUDIO_Gpt3,  \
        kCLOCK_AUDIO_Gpt4,  \
        kCLOCK_AUDIO_Gpt5,  \
        kCLOCK_LSIO_Gpt0,   \
        kCLOCK_LSIO_Gpt1,   \
        kCLOCK_LSIO_Gpt2,   \
        kCLOCK_LSIO_Gpt3,   \
        kCLOCK_LSIO_Gpt4,   \
    }

#define FLEXCAN_CLOCKS

Value:

{                       \
        kCLOCK_DMA_Can0,    \
        kCLOCK_DMA_Can1,    \
        kCLOCK_DMA_Can2,    \
    }

#define FLEXSPI_CLOCKS

Value:

{                         \
        kCLOCK_LSIO_Flexspi0, \
        kCLOCK_LSIO_Flexspi1, \
    }

#define LPUART_CLOCKS

Value:

{                       \
        kCLOCK_M4_0_Lpuart, \
        kCLOCK_M4_1_Lpuart, \
        kCLOCK_DMA_Lpuart0, \
        kCLOCK_DMA_Lpuart1, \
        kCLOCK_DMA_Lpuart2, \
        kCLOCK_DMA_Lpuart3, \
        kCLOCK_DMA_Lpuart4, \
        kCLOCK_SCU_Lpuart,  \
    }

#define LPADC_CLOCKS

Value:

{                       \
        kCLOCK_DMA_Lpadc0,  \
        kCLOCK_DMA_Lpadc1,  \
    }

#define INTMUX_CLOCKS

Value:

{                        \
        kCLOCK_M4_0_Intmux,  \
        kCLOCK_M4_1_Intmux,  \
        kCLOCK_IpInvalid,    \
    }

#define SAI_CLOCKS

Value:

{                       \
        kCLOCK_AUDIO_Sai0,  \
        kCLOCK_AUDIO_Sai1,  \
        kCLOCK_AUDIO_Sai2,  \
        kCLOCK_AUDIO_Sai3,  \
        kCLOCK_AUDIO_Sai4,  \
        kCLOCK_AUDIO_Sai5,  \
        kCLOCK_AUDIO_Sai6,  \
        kCLOCK_AUDIO_Sai7,  \
    }

#define SEMA42_CLOCKS

Value:

{                       \
        kCLOCK_M4_0_Sema42, \
        kCLOCK_M4_1_Sema42,  \
        kCLOCK_SCU_Sema42,  \
    }

#define TPM_CLOCKS

Value:

{                       \
        kCLOCK_M4_0_Tpm,    \
        kCLOCK_M4_1_Tpm,    \
        kCLOCK_SCU_Tpm,     \
    }

#define LPIT_CLOCKS

Value:

{                       \
        kCLOCK_M4_0_Lpit,   \
        kCLOCK_M4_1_Lpit,   \
        kCLOCK_SCU_Lpit,    \
    }

#define LPI2C_CLOCKS

Value:

{                         \
        kCLOCK_M4_0_Lpi2c,    \
        kCLOCK_M4_1_Lpi2c,    \
        kCLOCK_HDMI_Lpi2c0,   \
        kCLOCK_LVDS_0_Lpi2c1, \
        kCLOCK_LVDS_0_Lpi2c0, \
        kCLOCK_LVDS_1_Lpi2c1, \
        kCLOCK_LVDS_1_Lpi2c0, \
        kCLOCK_MIPI_0_Lpi2c0, \
        kCLOCK_MIPI_0_Lpi2c1, \
        kCLOCK_MIPI_1_Lpi2c0, \
        kCLOCK_MIPI_1_Lpi2c1, \
        kCLOCK_DMA_Lpi2c0,    \
        kCLOCK_DMA_Lpi2c1,    \
        kCLOCK_DMA_Lpi2c2,    \
        kCLOCK_DMA_Lpi2c3,    \
        kCLOCK_DMA_Lpi2c4,    \
        kCLOCK_CSI_0_Lpi2c0,  \
        kCLOCK_CSI_1_Lpi2c0,  \
        kCLOCK_HDMI_RX_Lpi2c0,\
        kCLOCK_SCU_Lpi2c,     \
    }

#define LPSPI_CLOCKS

Value:

{                       \
        kCLOCK_DMA_Lpspi0,  \
        kCLOCK_DMA_Lpspi1,  \
        kCLOCK_DMA_Lpspi2,  \
        kCLOCK_DMA_Lpspi3,  \
    }

#define EDMA_CLOCKS

Value:

{                       \
        kCLOCK_DMA_Dma0,   \
    }

#define ESAI_CLOCKS

Value:

{                       \
        kCLOCK_AUDIO_Esai0,  kCLOCK_AUDIO_Esai1  \
    }

#define ISI_CLOCKS

Value:

{                           \
        kCLOCK_IMAGING_Isi0, kCLOCK_IMAGING_Isi1, kCLOCK_IMAGING_Isi2, kCLOCK_IMAGING_Isi3, \
        kCLOCK_IMAGING_Isi4, kCLOCK_IMAGING_Isi5, kCLOCK_IMAGING_Isi6, kCLOCK_IMAGING_Isi7, \
    }

#define MIPI_CSI2RX_CLOCKS

Value:

{                       \
        kCLOCK_MipiCsi2Rx0, \
        kCLOCK_MipiCsi2Rx1  \
    }

#define MIPI_DSI_HOST_CLOCKS

Value:

{                         \
        kCLOCK_MipiDsiHost0,  \
        kCLOCK_MipiDsiHost1   \
    }

#define ENET_CLOCKS

Value:

{                         \
        kCLOCK_CONNECTIVITY_Enet0,  \
        kCLOCK_CONNECTIVITY_Enet1   \
    }

#define EMVSIM_CLOCKS

Value:

{                         \
        kCLOCK_DMA_EmvSim0,   \
        kCLOCK_DMA_EmvSim1,   \
    }

#define DPU_CLOCKS

Value:

{                  \
        kCLOCK_Dpu0,   \
        kCLOCK_Dpu1,   \
    }

#define LDB_CLOCKS

Value:

{                 \
        kCLOCK_Ldb0,  \
        kCLOCK_Ldb1   \
    }

#define LPCG_TUPLE	(	rsrc,
		base
	)	((uint32_t)((((base) >> 12U) << 10U) \| rsrc))

The LPCG base should be 4KB aligned, if not it will be truncated.

#define LPCG_TUPLE_REG_BASE ( tuple ) ((volatile uint32_t *)((((uint32_t)(tuple) >> 10U) & 0xFFFFFU) << 12U))

#define LPCG_TUPLE_RSRC ( tuple ) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU))

#define NV (0U)

Enumeration Type Documentation

enum clock_ip_src_t

Enumerator
kCLOCK_IpSrcNone	Clock is off.
kCLOCK_IpSrcDummy	Clock option 1.

enum clock_name_t

Enumerator
kCLOCK_CoreSysClk	Core/system clock for M4.
kCLOCK_CONECTIVITY_AhbClk	AHB clock in Connectivity subsystem.

enum clock_ip_name_t

It is defined as the corresponding register address.

Function Documentation

void CLOCK_Init ( sc_ipc_t ipc )

Parameters

ipc	IPC handle for communication with SCU, see sc_ipc_t.

bool CLOCK_EnableClockExt	(	clock_ip_name_t	name,
		uint32_t	gate
	)

Parameters

name	Which clock to enable, see clock_ip_name_t.
gate	0: clock always on, 1: HW auto clock gating.

Returns: true if success, false if failure.

static bool CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

Returns: true for success, false for failure.

bool CLOCK_DisableClock ( clock_ip_name_t name )

Parameters

name	Which clock to disable, see clock_ip_name_t.

Returns: true for success, false for failure.

uint32_t CLOCK_SetIpFreq	(	clock_ip_name_t	name,
		uint32_t	freq
	)

This function sets the IP module clock frequency.

Parameters

name	Which peripheral to check, see clock_ip_name_t.
freq	Target clock frequency value in hertz.

Returns: the Real clock frequency value in hertz, or 0 if failed

uint32_t CLOCK_GetIpFreq ( clock_ip_name_t name )

This function gets the IP module clock frequency.

Parameters

name	Which peripheral to get, see clock_ip_name_t.

Returns: Clock frequency value in hertz, or 0 if failed

uint32_t CLOCK_GetFreq ( clock_name_t name )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Clock frequency in Hz.

void CLOCK_ConfigLPCG	(	clock_ip_name_t	name,
		uint32_t	swGate,
		uint32_t	hwGate
	)

Parameters

name	Which clock to enable, see clock_ip_name_t.
swGate	Software clock gating. 0: clock is gated; 1: clock is enabled
swGate	Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled

void CLOCK_SetLpcgGate	(	volatile uint32_t *	regBase,
		uint32_t	swGate,
		uint32_t	hwGate,
		uint32_t	bitsMask
	)

Parameters

regBase	LPCG register base address.
swGate	Software clock gating. 0: clock is gated; 1: clock is enabled
swGate	Hardware auto gating. 0: disable the HW clock gate control; 1: HW clock gating is enabled
bitsMask	The available bits in LPCG register. Each bit indicate the corresponding bit is available or not.

Overview

Macros

Enumerations

Functions

Driver version

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation