Overview

The SDK provides a peripheral driver for the DPU.

The DPU module consists of many processing units, such as FetchDecode, LayerBlend, and so on. The SDK DPU driver provides separate functions for these processing units.

For a processing unit, there are three kinds of functions:

The initialize functions. These functions are named as DPU_InitXxx. For example, DPU_InitStore. These functions should only be used before display started to initialize the processing units.
The configure functions. These functions are named as DPU_XxxSetYyyConfig. For example, DPU_SetStoreDstBufferConfig. These functions can be used before the display starts to setup configuration. Additionally, they can be used after the display starts to make some runtime changes.
The function to get default configuration.

In the DPU driver, the pipeline is also treated as a processing unit. For example, the unit kDPU_PipelineExtDst0 means the pipeline with unit ExtDst0 as its endpoint. Accordingly, there are functions to initialize the pipeline and configure the pipeline.

Program model

The DPU module provides the shadow registers. The software can write to shadow registers instead of to the active configuration. When a new configuration is completed, the software can trigger the shadowed configuration to be the active configuration.
The DPU driver uses this feature. The shadow load function is enabled during the unit initialization. After all configurations in a pipeline are finished, the function DPU_TriggerPipelineShadowLoad can be called to activate the shadowed configurations. After this, the upper layer should monitor the interrupt status to make sure the shadow load is finished before a new configuration.
The program workflow is like this:

For the blit engine, the driver supports two kinds of methods.

Method 1: Configure and start operation when a previous process finishes. The software workflow is:

Configure the blit engine units.
Trigger the blit engine pipeline shadow load using DPU_TriggerPipelineShadowLoad.
Start the process using DPU_StartStore.
Monitor the DPU store frame complete interrupt.
Repeat from step 1 for a new process.

The workflow flow is:

Method 2: Set the new configuration when the previous process is still on-going. In this case, the software cannot use the store frame complete interrupt to make sure all processes are finished because the software cannot distinguish which frame completion asserts this interrupts. The function DPU_TriggerPipelineCompleteInterrupt should be used in this case. The workflow is:

Configure the blit engine units.
Trigger the blit engine pipeline shadow load using DPU_TriggerPipelineShadowLoad.
Start process using DPU_StartStore.
Monitor the DPU pipeline shadow load interrupt.
If there is new process, then repeat from step 1.
If there is not a new process or the software wants to make sure all processes are finished, call DPU_TriggerPipelineCompleteInterrupt and monitor the pipeline sequence complete interrupt.

The workflow flow is:

Path configuration

The DPU consists of many processing units. The pipeline path should configured carefully for special use cases.
The blit engine diagram is:

The display controller block diagram is:

Processing units have their primary input (named src or prim) connected to the top side and their secondary input port (named sec), if present, connected to the left or right side in the diagram. The ROP#9 unit has its secondary input right and tertiary (named tert) left side connected.

Note: An active unit must at least have its primary port connected, while secondary and tertiary ports are optional

Note: When both horizontal and vertical scaling is active, then the sequence of both units in the Pixelbus configuration should be
-> HScaler -> VScaler -> when down-scaling horizontally
-> VScaler -> HScaler -> when up-scaling horizontally

The default path configuration after reset is:

Data Structures
struct	dpu_fetch_unit_config_t
	Configuration structure for fetch units. More...

struct	dpu_coordinates_config_t
	Configuration structure for the arbitrary warping re-sampling coordinates. More...

struct	dpu_warp_config_t
	Warp configuration structure for FetchWarp unit. More...

struct	dpu_src_buffer_config_t
	Fetch unit source buffer configuration structure. More...

struct	dpu_clip_window_config_t
	Fetch unit clip window configuration structure. More...

struct	dpu_dst_buffer_config_t
	Store unit Destination buffer configuration structure. More...

struct	dpu_layer_blend_config_t
	LayerBlend unit configuration structure. More...

struct	dpu_blit_blend_config_t
	BlitBlend unit configuration structure. More...

struct	dpu_rop_config_t
	ROp unit configuration structure. More...

struct	dpu_const_frame_config_t
	ConstFrame unit configuration structure. More...

struct	dpu_display_timing_config_t
	Display timing configuration structure. More...

struct	dpu_display_config_t
	Display mode configuration structure. More...

struct	dpu_scaler_config_t
	VScaler and HScaler configuration structure. More...

struct	dpu_signature_config_t
	Signature unit static configuration. More...

struct	dpu_signature_window_config_t
	Signature unit evaluation window configuration. More...

Macros
#define	DPU_PALETTE_ENTRY_NUM (256)
	DPU palette entery number. More...

#define	DPU_MAKE_CONST_COLOR(red, green, blue, alpha) ((((uint32_t)(red)) << 24U) \| (((uint32_t)(green)) << 16U) \| (((uint32_t)(blue)) << 8U) \| ((uint32_t)(alpha)))
	Define the const value that write to <unit>_ConstantColor. More...

Enumerations
enum	dpu_unit_t
	DPU units. More...

enum	_dpu_interrupt { kDPU_Group0Store9ShadowLoadInterrupt = (1U << 0U), kDPU_Group0Store9FrameCompleteInterrupt = (1U << 1U), kDPU_Group0Store9SeqCompleteInterrupt = (1U << 2U), kDPU_Group0ExtDst0ShadowLoadInterrupt = (1U << 3U), kDPU_Group0ExtDst0FrameCompleteInterrupt = (1U << 4U), kDPU_Group0ExtDst0SeqCompleteInterrupt = (1U << 5U), kDPU_Group0ExtDst4ShadowLoadInterrupt = (1U << 6U), kDPU_Group0ExtDst4FrameCompleteInterrupt = (1U << 7U), kDPU_Group0ExtDst4SeqCompleteInterrupt = (1U << 8U), kDPU_Group0ExtDst1ShadowLoadInterrupt = (1U << 9U), kDPU_Group0ExtDst1FrameCompleteInterrupt = (1U << 10U), kDPU_Group0ExtDst1SeqCompleteInterrupt = (1U << 11U), kDPU_Group0ExtDst5ShadowLoadInterrupt = (1U << 12U), kDPU_Group0ExtDst5FrameCompleteInterrupt = (1U << 13U), kDPU_Group0ExtDst5SeqCompleteInterrupt = (1U << 14U), kDPU_Group0Display0ShadowLoadInterrupt = (1U << 15U), kDPU_Group0Display0FrameCompleteInterrupt = (1U << 16U), kDPU_Group0Display0SeqCompleteInterrupt = (1U << 17U), kDPU_Group0FrameGen0Int0Interrupt = (1U << 18U), kDPU_Group0FrameGen0Int1Interrupt = (1U << 19U), kDPU_Group0FrameGen0Int2Interrupt = (1U << 20U), kDPU_Group0FrameGen0Int3Interrupt = (1U << 21U), kDPU_Group0Sig0ShadowLoadInterrupt = (1U << 22U), kDPU_Group0Sig0ValidInterrupt = (1U << 23U), kDPU_Group0Sig0ErrorInterrupt = (1U << 24U), kDPU_Group0Display1ShadowLoadInterrupt = (1U << 25U), kDPU_Group0Display1FrameCompleteInterrupt = (1U << 26U), kDPU_Group0Display1SeqCompleteInterrupt = (1U << 27U), kDPU_Group0FrameGen1Int0Interrupt = (1U << 28U), kDPU_Group0FrameGen1Int1Interrupt = (1U << 29U), kDPU_Group0FrameGen1Int2Interrupt = (1U << 30U), kDPU_Group0FrameGen1Int3Interrupt = (1U << 31U), kDPU_Group1Sig1ShadowLoadInterrupt = (1U << 0U), kDPU_Group1Sig1ValidInterrupt = (1U << 1U), kDPU_Group1Sig1ErrorInterrupt = (1U << 2U), kDPU_Group1CmdSeqErrorInterrupt = (1U << 4U), kDPU_Group1SoftwareInt0Interrupt = (1U << 5U), kDPU_Group1SoftwareInt1Interrupt = (1U << 6U), kDPU_Group1SoftwareInt2Interrupt = (1U << 7U), kDPU_Group1SoftwareInt3Interrupt = (1U << 8U), kDPU_Group1FrameGen0PrimSyncOnInterrupt = (1U << 9U), kDPU_Group1FrameGen0PrimSyncOffInterrupt = (1U << 10U), kDPU_Group1FrameGen0SecSyncOnInterrupt = (1U << 11U), kDPU_Group1FrameGen0SecSyncOffInterrupt = (1U << 12U), kDPU_Group1FrameGen1PrimSyncOnInterrupt = (1U << 13U), kDPU_Group1FrameGen1PrimSyncOffInterrupt = (1U << 14U), kDPU_Group1FrameGen1SecSyncOnInterrupt = (1U << 15U), kDPU_Group1FrameGen1SecSyncOffInterrupt = (1U << 16U) }
	DPU interrupt. More...

enum	_dpu_unit_source { kDPU_UnitSrcNone = 0, kDPU_UnitSrcFetchDecode9 = 1U, kDPU_UnitSrcFetchWarp9 = 2U, kDPU_UnitSrcFetchEco9 = 3U, kDPU_UnitSrcRop9 = 4U, kDPU_UnitSrcClut9 = 5U, kDPU_UnitSrcMatrix9 = 6U, kDPU_UnitSrcHScaler9 = 7U, kDPU_UnitSrcVScaler9 = 8U, kDPU_UnitSrcFilter9 = 9U, kDPU_UnitSrcBlitBlend9 = 10U, kDPU_UnitSrcStore9 = 11U, kDPU_UnitSrcConstFrame0 = 12U, kDPU_UnitSrcConstFrame1 = 16U, kDPU_UnitSrcConstFrame4 = 14U, kDPU_UnitSrcConstFrame5 = 18U, kDPU_UnitSrcFetchWarp2 = 20U, kDPU_UnitSrcFetchEco2 = 21U, kDPU_UnitSrcFetchDecode0 = 22U, kDPU_UnitSrcFetchEco0 = 23U, kDPU_UnitSrcFetchDecode1 = 24U, kDPU_UnitSrcFetchEco1 = 25U, kDPU_UnitSrcFetchLayer0 = 26U, kDPU_UnitSrcMatrix4 = 27U, kDPU_UnitSrcHScaler4 = 28U, kDPU_UnitSrcVScaler4 = 29U, kDPU_UnitSrcMatrix5 = 30U, kDPU_UnitSrcHScaler5 = 31U, kDPU_UnitSrcVScaler5 = 32U, kDPU_UnitSrcLayerBlend0 = 33U, kDPU_UnitSrcLayerBlend1 = 34U, kDPU_UnitSrcLayerBlend2 = 35U, kDPU_UnitSrcLayerBlend3 = 36U }
	DPU unit input source. More...

enum	dpu_pixel_format_t { kDPU_PixelFormatGray8 = 0, kDPU_PixelFormatRGB565 = 1, kDPU_PixelFormatARGB8888 = 2, kDPU_PixelFormatRGB888 = 3, kDPU_PixelFormatARGB1555 = 4 }
	DPU pixel format. More...

enum	dpu_warp_coordinate_mode_t { kDPU_WarpCoordinateModePNT = 0U, kDPU_WarpCoordinateModeDPNT = 1U, kDPU_WarpCoordinateModeDDPNT = 2U }
	FetchWarp unit warp coordinate mode. More...

enum	dpu_clip_color_mode_t { kDPU_ClipColorNull, kDPU_ClipColorSublayer }
	Define the color to take for pixels that do not lie inside the clip window of any layer. More...

enum	dpu_alpha_mask_mode_t { kDPU_AlphaMaskPrim, kDPU_AlphaMaskSec, kDPU_AlphaMaskPrimOrSec, kDPU_AlphaMaskPrimAndSec, kDPU_AlphaMaskPrimInv, kDPU_AlphaMaskSecInv, kDPU_AlphaMaskPrimOrSecInv, kDPU_AlphaMaskPrimAndSecInv }
	LayerBlend unit AlphaMask mode. More...

enum	dpu_blend_mode_t { kDPU_BlendZero, kDPU_BlendOne, kDPU_BlendPrimAlpha, kDPU_BlendPrimAlphaInv, kDPU_BlendSecAlpha, kDPU_BlendSecAlphaInv, kDPU_BlendConstAlpha, kDPU_BlendConstAlphaInv }
	LayerBlend unit alpha blend mode. More...

enum	dpu_blit_blend_func_t { kDPU_BlitBlendFuncGlZero = 0, kDPU_BlitBlendFuncGlOne = 1, kDPU_BlitBlendFuncGlSrcColor = 0x0300, kDPU_BlitBlendFuncGlOneMinusSrcColor = 0x0301, kDPU_BlitBlendFuncGlSrcAlpha = 0x0302, kDPU_BlitBlendFuncGlOneMinusSrcAlpha = 0x0303, kDPU_BlitBlendFuncGlDstAlpha = 0x0304, kDPU_BlitBlendFuncGlOneMinusDstAlpha = 0x0305, kDPU_BlitBlendFuncGlDstColor = 0x0306, kDPU_BlitBlendFuncGlOneMinusDstColor = 0x0307, kDPU_BlitBlendFuncGlSrcAlphaSaturate = 0x0308, kDPU_BlitBlendFuncGlConstColor = 0x8001, kDPU_BlitBlendFuncGlOneMinusConstColor = 0x8002, kDPU_BlitBlendFuncGlConstAlpha = 0x8003, kDPU_BlitBlendFuncGlOneMinusConstAlpha = 0x8004 }
	BlitBlend blend function. More...

enum	dpu_blit_blend_mode_t { kDPU_BlitBlendModeGlFuncAdd = 0x8006, kDPU_BlitBlendModeGlMin = 0x8007, kDPU_BlitBlendModeGlMax = 0x8008, kDPU_BlitBlendModeGlFuncSubtract = 0x800A, kDPU_BlitBlendModeGlFuncReverseSubtract = 0x800B, kDPU_BlitBlendModeVgBlendSrc = 0x2000, kDPU_BlitBlendModeVgBlendSrcOver = 0x2001, kDPU_BlitBlendModeVgBlendDstOver = 0x2002, kDPU_BlitBlendModeVgBlendSrcIn = 0x2003, kDPU_BlitBlendModeVgBlendDstIn = 0x2004, kDPU_BlitBlendModeVgBlendMultiply = 0x2005, kDPU_BlitBlendModeVgBlendScreen = 0x2006, kDPU_BlitBlendModeVgBlendDarken = 0x2007, kDPU_BlitBlendModeVgBlendLighten = 0x2008, kDPU_BlitBlendModeVgBlendAdditive = 0x2009 }
	BlitBlend blend mode. More...

enum	dpu_blit_blend_neutral_border_mode_t { kDPU_BlitBlendNeutralBorderPrim = 0, kDPU_BlitBlendNeutralBorderSec = 0 }
	BlitBlend neutral border mode. More...

enum	_dpu_rop_flags { kDPU_RopAddRed, kDPU_RopAddGreen, kDPU_RopAddBlue, kDPU_RopAddAlpha, kDPU_RopTertDiv2 = DPU_ROP_CONTROL_TertDiv2_MASK, kDPU_RopSecDiv2 = DPU_ROP_CONTROL_SecDiv2_MASK, kDPU_RopPrimDiv2 = DPU_ROP_CONTROL_PrimDiv2_MASK }
	ROp unit control flags. More...

enum	_dpu_display_timing_flags { kDPU_DisplayPixelActiveHigh = 0, kDPU_DisplayPixelActiveLow = DPU_DISENGCONF_POLARITYCTRL_PixInv_MASK, kDPU_DisplayDataEnableActiveHigh, kDPU_DisplayDataEnableActiveLow = 0, kDPU_DisplayHsyncActiveHigh = DPU_DISENGCONF_POLARITYCTRL_PolHs_MASK, kDPU_DisplayHsyncActiveLow = 0, kDPU_DisplayVsyncActiveHigh = DPU_DISENGCONF_POLARITYCTRL_PolVs_MASK, kDPU_DisplayVsyncActiveLow = 0 }
	Display timing configuration flags. More...

enum	dpu_display_mode_t { kDPU_DisplayBlackBackground, kDPU_DisplayConstBackground, kDPU_DisplayOnlyPrim, kDPU_DisplayOnlySec, kDPU_DisplayPrimOnTop, kDPU_DisplaySecOnTop, kDPU_DisplayTest }
	Display mode, safety stream is the primary input, content stream is the secondary input. More...

enum	_dpu_signature_window_flags { kDPU_SignatureWindowEnableGlobalPanic = DPU_SIG_EVALCONTROL_EnGlobalPanic_MASK, kDPU_SignatureWindowEnableLocalPanic = DPU_SIG_EVALCONTROL_EnLocalPanic_MASK, kDPU_SignatureWindowEnableAlphaMask = DPU_SIG_EVALCONTROL_AlphaMask_MASK, kDPU_SignatureWindowInvertAlpha = DPU_SIG_EVALCONTROL_AlphaInv_MASK }
	Signature unit evaluation window control flags. More...

enum	_dpu_signature_status { kDPU_SignatureIdle = DPU_SIG_STATUS_StsSigIdle_MASK, kDPU_SignatureValid = DPU_SIG_STATUS_StsSigValid_MASK }
	Signature unit status. More...

Driver version
#define	FSL_DPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
	DPU driver version 2.0.0. More...

Macros for the DPU unit input source.
The DPU unit input source is controlled by the register pixencfg_<unit>_dynamic, the macros DPU_MAKE_SRC_REG1, DPU_MAKE_SRC_REG2, and DPU_MAKE_SRC_REG3 are used to define the register value of pixencfg_<unit>_dynamic. DPU_MAKE_SRC_REG1 defines register for DPU unit that has one input source. Accordingly, DPU_MAKE_SRC_REG2 and DPU_MAKE_SRC_REG3 are used to define the register for units that have two and three input source. See _dpu_unit_source for the input source details.
#define	DPU_MAKE_SRC_REG1(src) (((uint32_t)(src)) & 0x3FU)
	Macro for one input source unit. More...

#define	DPU_MAKE_SRC_REG2(primSrc, secSrc) ((((uint32_t)(primSrc)) & 0x3FU) \| (((((uint32_t)(secSrc)) & 0x3FU) << 0x8U)))
	Macro for two input source unit. More...

#define	DPU_MAKE_SRC_REG3(primSrc, secSrc, tertSrc)
	Macro for three input source unit. More...

Macros define the FrameGen interrupt mode.
These macros are used by the function DPU_SetFrameGenInterruptConfig to set the FrameGen interrupt mode.
#define	DPU_FRAME_GEN_INT_DISABLE 0U
	Disable FrameGen interrupt. More...

#define	DPU_FRAME_GEN_INT_PER_LINE(colNum) ((1U << 31U) \| (1U << 15U) \| (((uint32_t)colNum) & (0x3FFFU)))
	Generate FrameGen interrupt every line at the colnum `colNum`. More...

#define	DPU_FRAME_GEN_INT_PER_FRAME(rowNum) ((1U << 31U) \| (((uint32_t)rowNum) & 0x3FFF0000U))
	Generate FrameGen interrupt every frame at the row `rowNum`. More...

DPU Initialization and de-initialization
void	DPU_Init (IRIS_MVPL_Type *base)
	Initializes the DPU peripheral. More...

void	DPU_Deinit (IRIS_MVPL_Type *base)
	Deinitializes the DPU peripheral. More...

void	DPU_PreparePathConfig (IRIS_MVPL_Type *base)
	Prepare the unit path configuration. More...

DPU interrupts
void	DPU_EnableInterrupts (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Enable the selected DPU interrupts. More...

void	DPU_DisableInterrupts (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Disable the selected DPU interrupts. More...

uint32_t	DPU_GetInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group)
	Get the DPU interrupts pending status. More...

void	DPU_ClearInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Clear the specified DPU interrupts pending status. More...

void	DPU_SetInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Set the specified DPU interrupts pending status. More...

void	DPU_MaskUserInterrupts (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Mask the selected DPU user interrupts. More...

void	DPU_EnableUserInterrupts (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Enable the selected DPU user interrupts. More...

void	DPU_DisableUserInterrupts (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Disable the selected DPU user interrupts. More...

uint32_t	DPU_GetUserInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group)
	Get the DPU user interrupts pending status. More...

void	DPU_ClearUserInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Clear the specified DPU user interrupts pending status. More...

void	DPU_SetUserInterruptsPendingFlags (IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
	Set the specified DPU user interrupts pending status. More...

Shadow load related.
status_t	DPU_EnableShadowLoad (IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
	Enable or disable the register shadowing for the DPU process units. More...

Pipline.
void	DPU_InitPipeline (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Initialize the pipeline. More...

void	DPU_DeinitPipeline (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Deinitializes the pipeline. More...

void	DPU_TriggerPipelineShadowLoad (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Trigger the pipeline shadow load. More...

void	DPU_TriggerPipelineCompleteInterrupt (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Trigger the pipeline. More...

void	DPU_SetUnitSrc (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Set the DPU unit input source selection. More...

Fetch Units
The Fetch unit input frame buffer is used like this: <----------------- frameWidth --------------------> ^ +-------------------------------------------------+ \| \| ^ ^ Frame \| \| \| \| \| \| \| \| \| offsetY \| Clip window offsetY\| \| \| v \| \| \| \|<------->+------------------\|------+----+ \| frameHeight \| \| offsetX \| Source Buffer \| \| \| \| \| \| \| v \| \| \| \| \| \| +----------------------+ \| \| \| \| \|Clip Window \| \| \| \| Clip window offsetX \| \| \| \| \|<-------------------->\| \| \| \| \| \| \| \| \| \| \| \| +----------------------+ \| \| \| \| \| \| \| \| \| +-------------------------+----+ \| \| \| \| \| \| \| v +-------------------------------------------------+
void	DPU_FetchUnitGetDefaultConfig (dpu_fetch_unit_config_t *config)
	Get the default configuration for fetch unit. More...

void	DPU_InitFetchUnit (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_fetch_unit_config_t config)
	Initialize the fetch unit. More...

status_t	DPU_SetColorPaletteIndexWidth (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t indexWidth)
	Set the color palette index width for fetch unit. More...

status_t	DPU_UpdateColorPalette (IRIS_MVPL_Type base, dpu_unit_t unit, uint32_t startIndex, const uint32_t palette, uint32_t count)
	Updates the color palette for fetch unit. More...

void	DPU_EnableColorPalette (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
	Enable or disable color palette for some sublayer. More...

void	DPU_CorrdinatesGetDefaultConfig (dpu_coordinates_config_t *config)
	Get the default configuration structure for arbitrary warping re-sampling coordinates. More...

status_t	DPU_InitWarpCoordinates (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_coordinates_config_t config)
	Initialize the arbitrary warping coordinates. More...

void	DPU_FetcUnitGetDefaultWarpConfig (dpu_warp_config_t *config)
	Get the default warp configuration for FetchWarp unit. More...

status_t	DPU_InitFetchUnitWarp (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_warp_config_t config)
	Initialize the Warp function for FetchWarp unit. More...

void	DPU_SrcBufferGetDefaultConfig (dpu_src_buffer_config_t *config)
	Get default configuration structure for fetch unit source buffer. More...

status_t	DPU_SetFetchUnitSrcBufferConfig (IRIS_MVPL_Type base, dpu_unit_t unit, uint8_t sublayer, const dpu_src_buffer_config_t config)
	Set the fetch unit sublayer source buffer. More...

void	DPU_SetFetchUnitSrcBufferAddr (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_t baseAddr)
	Set the fetch unit sublayer source buffer base address. More...

void	DPU_SetFetchUnitFrameSize (IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t height, uint16_t width)
	Set the fetch unit frame size. More...

void	DPU_SetFetchUnitOffset (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint16_t offsetX, uint16_t offsetY)
	Set the fetch unit sublayer offset. More...

void	DPU_EnableFetchUnitSrcBuffer (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
	Enable or disable fetch unit sublayer source buffer. More...

void	DPU_ClipWindowGetDefaultConfig (dpu_clip_window_config_t *config)
	Get default configuration structure for clip window. More...

void	DPU_SetFetchUnitClipWindowConfig (IRIS_MVPL_Type base, dpu_unit_t unit, uint8_t sublayer, const dpu_clip_window_config_t config)
	Set the fetch unit sublayer clip window. More...

void	DPU_EnableFetchUnitClipWindow (IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
	Enable or disable the fetch unit sublayer clip window. More...

void	DPU_SetFetchUnitClipColor (IRIS_MVPL_Type *base, dpu_unit_t unit, dpu_clip_color_mode_t clipColorMode, uint8_t sublayer)
	Set the fetch unit clip color mode. More...

ExtDst Units
void	DPU_InitExtDst (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Initialize the ExtDst unit. More...

Store Units
The Store unit output buffer is like this: <-------------------- Stride --------------------> <------------- bufferWidth ----------------> ^ +------------------------------------------------+ \| \| ^ \| \| \| \| \| Destination Buffer \| \| \| \| \| offsetY \| \| \| \| v \| \| \| \|<------->+===============+ \| \| bufferHeight \| \| offsetX " " \| \| \| \| " Input Frame " \| \| \| \| " " \| \| \| \| +===============+ \| \| \| \| \| \| \| \| \| \| \| \| \| \| v +------------------------------------------------+
void	DPU_InitStore (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Initialize the Store unit. More...

status_t	DPU_SetStoreDstBufferConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_dst_buffer_config_t config)
	Set the Store unit Destination buffer configuration. More...

void	DPU_DstBufferGetDefaultConfig (dpu_dst_buffer_config_t *config)
	Get the default configuration for Store unit. More...

void	DPU_SetStoreDstBufferAddr (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t baseAddr)
	Set the Store unit Destination buffer base address. More...

void	DPU_SetStoreOffset (IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t offsetX, uint16_t offsetY)
	Set the Store unit output offset. More...

void	DPU_StartStore (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Start the Store unit. More...

Rop units
Rop unit combines up to three input frames to a single output frame, all having the same dimension. It supports: Logic Operations Each bit of the RGBA input code is combined with the same bit from the same pixel from the other inputs by any logical operation (= 3 to 1 bit function). The input and output relationship is: Tertiary Input \| Secondary Input \| Primary Input \| Output ========================================================================== 0 \| 0 \| 0 \| operation index[0] -------------------------------------------------------------------------- 0 \| 0 \| 1 \| operation index[1] -------------------------------------------------------------------------- 0 \| 1 \| 0 \| operation index[2] -------------------------------------------------------------------------- 0 \| 1 \| 1 \| operation index[3] -------------------------------------------------------------------------- 1 \| 0 \| 0 \| operation index[4] -------------------------------------------------------------------------- 1 \| 0 \| 1 \| operation index[5] -------------------------------------------------------------------------- 1 \| 1 \| 0 \| operation index[6] -------------------------------------------------------------------------- 1 \| 1 \| 1 \| operation index[7] ========================================================================== Arithmetic Operations Input RGBA codes can simply be added for each pixel, optionally with an factor 0.5 being applied for averaging two frames.
void	DPU_InitRop (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Initialize the ROp unit. More...

void	DPU_RopGetDefaultConfig (dpu_rop_config_t *config)
	Get the default ROp unit configuration. More...

void	DPU_SetRopConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_rop_config_t config)
	Set the ROp unit configuration. More...

void	DPU_EnableRop (IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
	Enable or disable the ROp unit. More...

BlitBlend units
void	DPU_InitBlitBlend (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Initialize the BlitBlend unit. More...

void	DPU_BlitBlendGetDefaultConfig (dpu_blit_blend_config_t *config)
	Get the default BlitBlend unit configuration. More...

void	DPU_SetBlitBlendConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_blit_blend_config_t config)
	Set the BlitBlend unit configuration. More...

void	DPU_EnableBlitBlend (IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
	Enable or disable the BlitBlend unit. More...

LayerBlend units
void	DPU_LayerBlendGetDefaultConfig (dpu_layer_blend_config_t *config)
	Get default configuration structure for LayerBlend. More...

void	DPU_InitLayerBlend (IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
	Initialize the LayerBlend. More...

void	DPU_SetLayerBlendConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_layer_blend_config_t config)
	Set the LayerBlend unit configuration. More...

void	DPU_EnableLayerBlend (IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
	Enable or disable the LayerBlend unit. More...

ConstFrame units
void	DPU_InitConstFrame (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Initialize the ConstFrame unit. More...

void	DPU_ConstFrameGetDefaultConfig (dpu_const_frame_config_t *config)
	Get default configuration structure for ConstFrame unit. More...

void	DPU_SetConstFrameConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_const_frame_config_t config)
	Set the ConstFrame unit configuration. More...

VScaler and HScaler units
Note When both horizontal and vertical scaling is active, then the sequence of both units in the Pixelbus configuration should be -> HScaler -> VScaler -> when down-scaling horizontally -> VScaler -> HScaler -> when up-scaling horizontally
void	DPU_InitScaler (IRIS_MVPL_Type *base, dpu_unit_t unit)
	Initialize the VScaler or HScaler unit. More...

void	DPU_ScalerGetDefaultConfig (dpu_scaler_config_t *config)
	Get default configuration structure for VScaler and HScaler. More...

void	DPU_SetScalerConfig (IRIS_MVPL_Type base, dpu_unit_t unit, const dpu_scaler_config_t config)
	Set the VScaler or HScaler units configuration. More...

Display engine
void	DPU_DisplayTimingGetDefaultConfig (dpu_display_timing_config_t *config)
	Get default configuration structure for display mode. More...

void	DPU_InitDisplayTiming (IRIS_MVPL_Type base, uint8_t displayIndex, const dpu_display_timing_config_t config)
	Initialize the display timing. More...

void	DPU_DisplayGetDefaultConfig (dpu_display_config_t *config)
	Get default configuration structure for display frame mode. More...

void	DPU_SetDisplayConfig (IRIS_MVPL_Type base, uint8_t displayIndex, const dpu_display_config_t config)
	Set the display mode. More...

void	DPU_StartDisplay (IRIS_MVPL_Type *base, uint8_t displayIndex)
	Start the display. More...

void	DPU_StopDisplay (IRIS_MVPL_Type *base, uint8_t displayIndex)
	Stop the display. More...

void	DPU_SetFrameGenInterruptConfig (IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t interruptIndex, uint32_t intConfig)
	Clear the FrameGen unit status flags. More...

void	DPU_TriggerDisplayShadowLoad (IRIS_MVPL_Type *base, uint8_t displayIndex)
	Trigger the display stream shadow load token. More...

Signature unit
The Signature unit could compute the CRC value of interested region and compare to the reference value to detect incorrect display output. Up to 8 evaluation windows can be setup. Signature computation and reference check is done individually for each window. A pixel of the input frame does not contribute to more than one window. In case of overlapping windows, the window with larger index is on top. Alpha mask could be involved into the signature evaluation, thus any kind of shape could be monitored. Note that the mask is considered for checksum computation only, not for assignment of individual pixels to a certain evaluation window. So, a non-rectangular overlap between different windows is not possible. An evaluation window could be configured as skipped. This provides another method for monitoring non-rectangular windows. For example: +------------------------------------------------+ \| \| \| \| \| +-------------------+ \| \| \| Window 0 /////////\| \| \| \|///////////////////\| \| \| \|////////+-------------------------------+ \| \| \|////////\| Window 1 (Skipped) \| \| \| \|////////\| \| \| \| +--------\| \| \| \| \| \| \| \| +-------------------------------+ \| \| \| +------------------------------------------------+ In this example, windows 1 is skipped, in this case, only the shadow part of window 0 is monitored.
void	DPU_SignatureGetDefaultConfig (dpu_signature_config_t *config)
	Get Signature unit default configuration. More...

void	DPU_InitSignature (IRIS_MVPL_Type base, uint8_t displayIndex, const dpu_signature_config_t config)
	Initialize the Signature unit. More...

void	DPU_SignatureWindowGetDefaultConfig (dpu_signature_window_config_t *config)
	Get Signature unit validate window default configuration. More...

void	DPU_SetSignatureWindowConfig (IRIS_MVPL_Type base, uint8_t displayIndex, uint8_t windowIndex, const dpu_signature_window_config_t config)
	Set the Signature unit evaluation window configuration. More...

void	DPU_EnableSignatureWindowCompute (IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable)
	Enable or disable the Signature unit evaluation window CRC value computation. More...

void	DPU_EnableSignatureWindowCheck (IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable)
	Enable or disable the Signature unit evaluation window CRC value check. More...

void	DPU_GetSignatureWindowCrc (IRIS_MVPL_Type base, uint8_t displayIndex, uint8_t windowIndex, uint32_t redCRC, uint32_t greenCRC, uint32_t blueCRC)
	Get the measured signature value of the evaluation window. More...

void	DPU_SetSignatureWindowRefCrc (IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, uint32_t redCRC, uint32_t greenCRC, uint32_t blueCRC)
	Set the reference signature value of the evaluation window. More...

uint32_t	DPU_GetSignatureStatus (IRIS_MVPL_Type *base, uint8_t displayIndex)
	Get the signature unit status. More...

void	DPU_TriggerSignatureShadowLoad (IRIS_MVPL_Type *base, uint8_t displayIndex)
	Trigger the Signature unit configuration shadow load. More...

Data Structure Documentation

struct dpu_fetch_unit_config_t

Data Fields
uint32_t	srcReg
	This value will be set to register pixengcfg_fetchX_dynamic to set the unit input source, see DPU_MAKE_SRC_REG1. More...

uint16_t	frameHeight
	Frame height. More...

uint16_t	frameWidth
	Frame width. More...

Field Documentation

uint32_t dpu_fetch_unit_config_t::srcReg

uint16_t dpu_fetch_unit_config_t::frameHeight

uint16_t dpu_fetch_unit_config_t::frameWidth

struct dpu_coordinates_config_t

The coordinate layer supports:

32 bpp: 2 x s12.4 (signed fix-point)
24 bpp: 2 x s8.
16 bpp: 2 x s4.4
8 bpp: 2 x s0.4
4 bpp: 2 x s(-2).4 (means total value size = 2 bits and lowest bit = 2^-4)
2 bpp: 2 x s(-3).4
1 bpp: 1 x s(-3).4 (x and y alternating)

Data Fields
uint8_t	bitsPerPixel
	Number of bits per pixel in the source buffer. More...

uint16_t	strideBytes
	Source buffer stride in bytes. More...

uint32_t	baseAddr
	Source buffer base address. More...

uint16_t	frameHeight
	Frame height. More...

uint16_t	frameWidth
	Frame width. More...

Field Documentation

uint8_t dpu_coordinates_config_t::bitsPerPixel

Must be 1, 2, 4, 8, 16, 32.

uint16_t dpu_coordinates_config_t::strideBytes

uint32_t dpu_coordinates_config_t::baseAddr

uint16_t dpu_coordinates_config_t::frameHeight

uint16_t dpu_coordinates_config_t::frameWidth

struct dpu_warp_config_t

Data Fields
uint32_t	srcReg
	This value will be set to register pixengcfg_fetchX_dynamic to set the unit input source, see DPU_MAKE_SRC_REG1. More...

uint16_t	frameHeight
	Frame height. More...

uint16_t	frameWidth
	Frame width. More...

uint8_t	warpBitsPerPixel
	Pixel bits of the coordinate layer. More...

bool	enableSymmetricOffset
	Enables symmetric range for negative and positive coordinate values by adding an offset of +0.03125 internally to all coordinate input values. More...

dpu_warp_coordinate_mode_t	coordMode
	Coordinate layer mode. More...

uint32_t	arbStartX
	X of start point position. More...

uint32_t	arbStartY
	Y of start point position. More...

uint8_t	arbDeltaYY
	Y of vector between start and first sample point. More...

uint8_t	arbDeltaYX
	X of vector between start and first sample point. More...

uint8_t	arbDeltaXY
	Y of vector between first and second sample point. More...

uint8_t	arbDeltaXX
	X of vector between first and second sample point. More...

Field Documentation

uint32_t dpu_warp_config_t::srcReg

uint16_t dpu_warp_config_t::frameHeight

uint16_t dpu_warp_config_t::frameWidth

uint8_t dpu_warp_config_t::warpBitsPerPixel

bool dpu_warp_config_t::enableSymmetricOffset

Recommended for small coordinate formats in DD_PNT mode.

dpu_warp_coordinate_mode_t dpu_warp_config_t::coordMode

uint32_t dpu_warp_config_t::arbStartX

Signed 16.5 fix-point. Used in D_PNT and DD_PNT.

uint32_t dpu_warp_config_t::arbStartY

Signed 16.5 fix-point. Used in D_PNT and DD_PNT.

uint8_t dpu_warp_config_t::arbDeltaYY

Signed 3.5 fix-point. Used in DD_PNT.

uint8_t dpu_warp_config_t::arbDeltaYX

Signed 3.5 fix-point. Used in DD_PNT.

uint8_t dpu_warp_config_t::arbDeltaXY

Signed 3.5 fix-point. Used in DD_PNT.

uint8_t dpu_warp_config_t::arbDeltaXX

Signed 3.5 fix-point. Used in DD_PNT.

struct dpu_src_buffer_config_t

Base address and stride alignment restrictions: 32 bpp: Base address and stride must be a multiple of 4 bytes. 16 bpp: Base address and stride must be a multiple of 2 bytes. others: any byte alignment allowed

Generally, the bitsPerPixel and pixelFormat specify the pixel format in frame buffer, they should match. But when the color palette is used, the bitsPerPixel specify the format in framebuffer, the pixelFormat specify the format in color palette entry.

Data Fields
uint32_t	baseAddr
	Source buffer base address, see alignment restrictions. More...

uint16_t	strideBytes
	Source buffer stride in bytes, see alignment restrictions. More...

uint8_t	bitsPerPixel
	Bits per pixel in frame buffer. More...

dpu_pixel_format_t	pixelFormat
	Pixel format. More...

uint16_t	bufferHeight
	Buffer height. More...

uint16_t	bufferWidth
	Buffer width. More...

uint32_t	constColor
	Const color shown in the region out of frame buffer, see DPU_MAKE_CONST_COLOR. More...

Field Documentation

uint32_t dpu_src_buffer_config_t::baseAddr

uint16_t dpu_src_buffer_config_t::strideBytes

uint8_t dpu_src_buffer_config_t::bitsPerPixel

dpu_pixel_format_t dpu_src_buffer_config_t::pixelFormat

uint16_t dpu_src_buffer_config_t::bufferHeight

uint16_t dpu_src_buffer_config_t::bufferWidth

uint32_t dpu_src_buffer_config_t::constColor

struct dpu_clip_window_config_t

Data Fields
uint16_t	windowOffsetX
	Horizontal offset of the clip window. More...

uint16_t	windowOffsetY
	Vertical offset of the clip window. More...

uint16_t	windowHeight
	Height of the clip window. More...

uint16_t	windowWidth
	Width of the clip window. More...

Field Documentation

uint16_t dpu_clip_window_config_t::windowOffsetX

uint16_t dpu_clip_window_config_t::windowOffsetY

uint16_t dpu_clip_window_config_t::windowHeight

uint16_t dpu_clip_window_config_t::windowWidth

struct dpu_dst_buffer_config_t

Base address and stride alignment restrictions: 32 bpp: Base address and stride must be a multiple of 4 bytes. 16 bpp: Base address and stride must be a multiple of 2 bytes. others: any byte alignment allowed

Data Fields
uint32_t	baseAddr
	Destination buffer base address, see alignment restrictions. More...

uint16_t	strideBytes
	Destination buffer stride in bytes, see alignment restrictions. More...

uint8_t	bitsPerPixel
	Bits per pixel. More...

dpu_pixel_format_t	pixelFormat
	Pixel format. More...

uint16_t	bufferHeight
	Buffer height. More...

uint16_t	bufferWidth
	Buffer width. More...

Field Documentation

uint32_t dpu_dst_buffer_config_t::baseAddr

uint16_t dpu_dst_buffer_config_t::strideBytes

uint8_t dpu_dst_buffer_config_t::bitsPerPixel

dpu_pixel_format_t dpu_dst_buffer_config_t::pixelFormat

uint16_t dpu_dst_buffer_config_t::bufferHeight

uint16_t dpu_dst_buffer_config_t::bufferWidth

struct dpu_layer_blend_config_t

Data Fields
uint8_t	constAlpha
	The const alpha value used in blend. More...

dpu_blend_mode_t	secAlphaBlendMode
	Secondary (overlay) input alpha blending function. More...

dpu_blend_mode_t	primAlphaBlendMode
	Primary (background) input alpha blending function. More...

dpu_blend_mode_t	secColorBlendMode
	Secondary (overlay) input color blending function. More...

dpu_blend_mode_t	primColorBlendMode
	Primary (background) input color blending function. More...

uint32_t	srcReg
	This value will be set to pixengcfg_layerblendX_dynamic to set the unit input source, see DPU_MAKE_SRC_REG2. More...

bool	enableAlphaMask
	Enable AlphaMask feature. More...

dpu_alpha_mask_mode_t	alphaMaskMode
	AlphaMask mode, only valid when enableAlphaMask is true. More...

Field Documentation

uint8_t dpu_layer_blend_config_t::constAlpha

dpu_blend_mode_t dpu_layer_blend_config_t::secAlphaBlendMode

dpu_blend_mode_t dpu_layer_blend_config_t::primAlphaBlendMode

dpu_blend_mode_t dpu_layer_blend_config_t::secColorBlendMode

dpu_blend_mode_t dpu_layer_blend_config_t::primColorBlendMode

uint32_t dpu_layer_blend_config_t::srcReg

bool dpu_layer_blend_config_t::enableAlphaMask

dpu_alpha_mask_mode_t dpu_layer_blend_config_t::alphaMaskMode

struct dpu_blit_blend_config_t

Data Fields
uint8_t	neutralBorderRightPixels
	Number of neutral right border pixels. More...

uint8_t	neutralBorderLeftPixels
	Number of neutral left border pixels. More...

dpu_blit_blend_neutral_border_mode_t	neutralBorderMode
	Neutral border mode. More...

uint32_t	constColor
	Const color used for blit blend, see DPU_MAKE_CONST_COLOR. More...

dpu_blit_blend_func_t	redBlendFuncSrc
	Red component source blend function.

dpu_blit_blend_func_t	redBlendFuncDst
	Red component destination blend function.

dpu_blit_blend_func_t	greenBlendFuncSrc
	Green component source blend function.

dpu_blit_blend_func_t	greenBlendFuncDst
	Green component destination blend function.

dpu_blit_blend_func_t	blueBlendFuncSrc
	Blue component source blend function.

dpu_blit_blend_func_t	blueBlendFuncDst
	Blue component destination blend function.

dpu_blit_blend_func_t	alphaBlendFuncSrc
	Alpha component source blend function.

dpu_blit_blend_func_t	alphaBlendFuncDst
	Alpha component destination blend function.

dpu_blit_blend_mode_t	redBlendMode
	Red component blend mode.

dpu_blit_blend_mode_t	greenBlendMode
	Green component blend mode.

dpu_blit_blend_mode_t	blueBlendMode
	Blue component blend mode.

dpu_blit_blend_mode_t	alphaBlendMode
	Alpha component blend mode.

Field Documentation

uint8_t dpu_blit_blend_config_t::neutralBorderRightPixels

uint8_t dpu_blit_blend_config_t::neutralBorderLeftPixels

dpu_blit_blend_neutral_border_mode_t dpu_blit_blend_config_t::neutralBorderMode

uint32_t dpu_blit_blend_config_t::constColor

struct dpu_rop_config_t

Data Fields
uint32_t	controlFlags
	Control flags, see _dpu_rop_flags. More...

uint8_t	alphaIndex
	Alpha operation index. More...

uint8_t	blueIndex
	Blue operation index. More...

uint8_t	greenIndex
	Green operation index. More...

uint8_t	redIndex
	Red operation index. More...

Field Documentation

uint32_t dpu_rop_config_t::controlFlags

uint8_t dpu_rop_config_t::alphaIndex

uint8_t dpu_rop_config_t::blueIndex

uint8_t dpu_rop_config_t::greenIndex

uint8_t dpu_rop_config_t::redIndex

struct dpu_const_frame_config_t

Data Fields
uint16_t	frameHeight
	Frame height. More...

uint16_t	frameWidth
	Frame width. More...

uint32_t	constColor
	See DPU_MAKE_CONST_COLOR. More...

Field Documentation

uint16_t dpu_const_frame_config_t::frameHeight

uint16_t dpu_const_frame_config_t::frameWidth

uint32_t dpu_const_frame_config_t::constColor

struct dpu_display_timing_config_t

Data Fields
uint16_t	flags
	OR'ed value of _dpu_display_timing_flags. More...

uint16_t	width
	Active width. More...

uint16_t	hsw
	HSYNC pulse width. More...

uint16_t	hfp
	Horizontal front porch. More...

uint16_t	hbp
	Horizontal back porch. More...

uint16_t	height
	Active height. More...

uint16_t	vsw
	VSYNC pulse width. More...

uint16_t	vfp
	Vrtical front porch. More...

uint16_t	vbp
	Vertical back porch. More...

Field Documentation

uint16_t dpu_display_timing_config_t::flags

uint16_t dpu_display_timing_config_t::width

uint16_t dpu_display_timing_config_t::hsw

uint16_t dpu_display_timing_config_t::hfp

uint16_t dpu_display_timing_config_t::hbp

uint16_t dpu_display_timing_config_t::height

uint16_t dpu_display_timing_config_t::vsw

uint16_t dpu_display_timing_config_t::vfp

uint16_t dpu_display_timing_config_t::vbp

struct dpu_display_config_t

Data Fields
bool	enablePrimAlpha
	Enable primary input alpha for screen composition. More...

bool	enableSecAlpha
	Enable secondary input alpha for screen composition. More...

dpu_display_mode_t	displayMode
	Display mode. More...

bool	enablePrimAlphaInPanic
	Enable primary input alpha for screen composition in panic mode. More...

bool	enableSecAlphaInPanic
	Enable secondary input alpha for screen composition in panic mode. More...

dpu_display_mode_t	displayModeInPanic
	Display mode in panic mode. More...

uint16_t	constRed
	Const red value, 10-bit. More...

uint16_t	constGreen
	Const green value, 10-bit. More...

uint16_t	constBlue
	Const green value, 10-bit. More...

uint8_t	constAlpha
	Const alpha value, 1-bit. More...

uint16_t	primAreaStartX
	Primary screen upper left corner, x component. More...

uint16_t	primAreaStartY
	Primary screen upper left corner, y component. More...

uint16_t	secAreaStartX
	Secondary screen upper left corner, x component. More...

uint16_t	secAreaStartY
	Secondary screen upper left corner, y component. More...

Field Documentation

bool dpu_display_config_t::enablePrimAlpha

bool dpu_display_config_t::enableSecAlpha

dpu_display_mode_t dpu_display_config_t::displayMode

bool dpu_display_config_t::enablePrimAlphaInPanic

bool dpu_display_config_t::enableSecAlphaInPanic

dpu_display_mode_t dpu_display_config_t::displayModeInPanic

uint16_t dpu_display_config_t::constRed

uint16_t dpu_display_config_t::constGreen

uint16_t dpu_display_config_t::constBlue

uint8_t dpu_display_config_t::constAlpha

uint16_t dpu_display_config_t::primAreaStartX

14-bit , start from 1.

uint16_t dpu_display_config_t::primAreaStartY

14-bit, start from 1.

uint16_t dpu_display_config_t::secAreaStartX

14-bit, start from 1.

uint16_t dpu_display_config_t::secAreaStartY

14-bit, start from 1.

struct dpu_scaler_config_t

Data Fields
uint32_t	srcReg
	This value will be set to register pixengcfg_slacer_dynamic to set the unit input source, see DPU_MAKE_SRC_REG1. More...

uint16_t	inputSize
	For HScaler, it is frame width, for VScaler, it is frame height. More...

uint16_t	outputSize
	For HScaler, it is frame width, for VScaler, it is frame height. More...

Field Documentation

uint32_t dpu_scaler_config_t::srcReg

When down-scaling horizontally, the path should be -> HScaler -> VScaler ->, When up-scaling horizontally, the path should be -> VScaler -> HScaler ->.

uint16_t dpu_scaler_config_t::inputSize

uint16_t dpu_scaler_config_t::outputSize

struct dpu_signature_config_t

Data Fields
uint8_t	errorThreshold
	Number of frames with signature violation before signature error is set for an evaluation window. More...

uint8_t	errorResetThreshold
	Number of consecutive frames without signature violation before signature error is reset for an evaluation window. More...

uint8_t	panicRed
	Constant color shown in the window when local panic happens. More...

uint8_t	panicGreen
	Constant color shown in the window when local panic happens. More...

uint8_t	panicBlue
	Constant color shown in the window when local panic happens. More...

uint8_t	panicAlpha
	Constant color shown in the window when local panic happens. More...

Field Documentation

uint8_t dpu_signature_config_t::errorThreshold

uint8_t dpu_signature_config_t::errorResetThreshold

uint8_t dpu_signature_config_t::panicRed

uint8_t dpu_signature_config_t::panicGreen

uint8_t dpu_signature_config_t::panicBlue

uint8_t dpu_signature_config_t::panicAlpha

Must be 0 or 1

struct dpu_signature_window_config_t

Data Fields
uint32_t	controlFlags
	Control flags, OR'ed valud of _dpu_signature_window_flags. More...

uint16_t	upperLeftX
	X coordinate of the upper left corner. More...

uint16_t	upperLeftY
	Y coordinate of the upper left corner. More...

uint16_t	lowerRightX
	X coordinate of the lower right corner. More...

uint16_t	lowerRightY
	Y coordinate of the lower right corner. More...

Field Documentation

uint32_t dpu_signature_window_config_t::controlFlags

uint16_t dpu_signature_window_config_t::upperLeftX

uint16_t dpu_signature_window_config_t::upperLeftY

uint16_t dpu_signature_window_config_t::lowerRightX

uint16_t dpu_signature_window_config_t::lowerRightY

Macro Definition Documentation

#define FSL_DPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))

#define DPU_PALETTE_ENTRY_NUM (256)

#define DPU_MAKE_SRC_REG1 ( src ) (((uint32_t)(src)) & 0x3FU)

#define DPU_MAKE_SRC_REG2	(	primSrc,
		secSrc
	)	((((uint32_t)(primSrc)) & 0x3FU) \| (((((uint32_t)(secSrc)) & 0x3FU) << 0x8U)))

#define DPU_MAKE_SRC_REG3	(	primSrc,
		secSrc,
		tertSrc
	)

Value:

((((uint32_t)(primSrc)) & 0x3FU) | ((((uint32_t)(secSrc)) & 0x3FU) << 0x8U) | \

(((((uint32_t)(tertSrc)) & 0x3FU) << 0x10U)))

#define DPU_MAKE_CONST_COLOR	(	red,
		green,
		blue,
		alpha
	)	((((uint32_t)(red)) << 24U) \| (((uint32_t)(green)) << 16U) \| (((uint32_t)(blue)) << 8U) \| ((uint32_t)(alpha)))

#define DPU_FRAME_GEN_INT_DISABLE 0U

#define DPU_FRAME_GEN_INT_PER_LINE ( colNum ) ((1U << 31U) | (1U << 15U) | (((uint32_t)colNum) & (0x3FFFU)))

#define DPU_FRAME_GEN_INT_PER_FRAME ( rowNum ) ((1U << 31U) | (((uint32_t)rowNum) & 0x3FFF0000U))

Enumeration Type Documentation

enum dpu_unit_t

enum _dpu_interrupt

Enumerator
kDPU_Group0Store9ShadowLoadInterrupt	Store9 shadow load interrupt.
kDPU_Group0Store9FrameCompleteInterrupt	Store9 frame complete interrupt.
kDPU_Group0Store9SeqCompleteInterrupt	Store9 sequence complete interrupt.
kDPU_Group0ExtDst0ShadowLoadInterrupt	ExtDst0 shadow load interrupt.
kDPU_Group0ExtDst0FrameCompleteInterrupt	ExtDst0 frame complete interrupt.
kDPU_Group0ExtDst0SeqCompleteInterrupt	ExtDst0 sequence complete interrupt.
kDPU_Group0ExtDst4ShadowLoadInterrupt	ExtDst4 shadow load interrupt.
kDPU_Group0ExtDst4FrameCompleteInterrupt	ExtDst4 frame complete interrupt.
kDPU_Group0ExtDst4SeqCompleteInterrupt	ExtDst4 sequence complete interrupt.
kDPU_Group0ExtDst1ShadowLoadInterrupt	ExtDst1 shadow load interrupt.
kDPU_Group0ExtDst1FrameCompleteInterrupt	ExtDst1 frame complete interrupt.
kDPU_Group0ExtDst1SeqCompleteInterrupt	ExtDst1 sequence complete interrupt.
kDPU_Group0ExtDst5ShadowLoadInterrupt	ExtDst5 shadow load interrupt.
kDPU_Group0ExtDst5FrameCompleteInterrupt	ExtDst5 frame complete interrupt.
kDPU_Group0ExtDst5SeqCompleteInterrupt	ExtDst5 sequence complete interrupt.
kDPU_Group0Display0ShadowLoadInterrupt	Display stream 0 shadow load interrupt.
kDPU_Group0Display0FrameCompleteInterrupt	Display stream 0 frame complete interrupt.
kDPU_Group0Display0SeqCompleteInterrupt	Display stream 0 sequence complete interrupt.
kDPU_Group0FrameGen0Int0Interrupt	FrameGen 0 interrupt 0.
kDPU_Group0FrameGen0Int1Interrupt	FrameGen 0 interrupt 1.
kDPU_Group0FrameGen0Int2Interrupt	FrameGen 0 interrupt 2.
kDPU_Group0FrameGen0Int3Interrupt	FrameGen 0 interrupt 3.
kDPU_Group0Sig0ShadowLoadInterrupt	Sig0 shadow load interrupt.
kDPU_Group0Sig0ValidInterrupt	Sig0 measurement valid interrupt.
kDPU_Group0Sig0ErrorInterrupt	Sig0 error interrupt.
kDPU_Group0Display1ShadowLoadInterrupt	Display stream 1 shadow load interrupt.
kDPU_Group0Display1FrameCompleteInterrupt	Display stream 1 frame complete interrupt.
kDPU_Group0Display1SeqCompleteInterrupt	Display stream 1 sequence complete interrupt.
kDPU_Group0FrameGen1Int0Interrupt	FrameGen 1 interrupt 0.
kDPU_Group0FrameGen1Int1Interrupt	FrameGen 1 interrupt 1.
kDPU_Group0FrameGen1Int2Interrupt	FrameGen 1 interrupt 2.
kDPU_Group0FrameGen1Int3Interrupt	FrameGen 1 interrupt 3.
kDPU_Group1Sig1ShadowLoadInterrupt	Sig1 shadow load interrupt.
kDPU_Group1Sig1ValidInterrupt	Sig1 measurement valid interrupt.
kDPU_Group1Sig1ErrorInterrupt	Sig1 error interrupt.
kDPU_Group1CmdSeqErrorInterrupt	Command sequencer error interrupt.
kDPU_Group1SoftwareInt0Interrupt	Common software interrupt 0.
kDPU_Group1SoftwareInt1Interrupt	Common software interrupt 1.
kDPU_Group1SoftwareInt2Interrupt	Common software interrupt 2.
kDPU_Group1SoftwareInt3Interrupt	Common software interrupt 3.
kDPU_Group1FrameGen0PrimSyncOnInterrupt	Safety stream 0 synchronized interrupt.
kDPU_Group1FrameGen0PrimSyncOffInterrupt	Safety stream 0 loss synchronization interrupt.
kDPU_Group1FrameGen0SecSyncOnInterrupt	Content stream 0 synchronized interrupt.
kDPU_Group1FrameGen0SecSyncOffInterrupt	Content stream 0 loss synchronization interrupt.
kDPU_Group1FrameGen1PrimSyncOnInterrupt	Safety stream 1 synchronized interrupt.
kDPU_Group1FrameGen1PrimSyncOffInterrupt	Safety stream 1 loss synchronization interrupt.
kDPU_Group1FrameGen1SecSyncOnInterrupt	Content stream 1 synchronized interrupt.
kDPU_Group1FrameGen1SecSyncOffInterrupt	Content stream 1 loss synchronization interrupt.

enum _dpu_unit_source

Enumerator
kDPU_UnitSrcNone	Disable the input source.
kDPU_UnitSrcFetchDecode9	The input source is fetch decode 9.
kDPU_UnitSrcFetchWarp9	The input source is fetch warp 9.
kDPU_UnitSrcFetchEco9	The input source is fetch eco 9.
kDPU_UnitSrcRop9	The input source is rop 9.
kDPU_UnitSrcClut9	The input source is CLUT 9.
kDPU_UnitSrcMatrix9	The input source is matrix 9.
kDPU_UnitSrcHScaler9	The input source is HScaler 9.
kDPU_UnitSrcVScaler9	The input source is VScaler 9.
kDPU_UnitSrcFilter9	The input source is Filter 9.
kDPU_UnitSrcBlitBlend9	The input source is BlitBlend 9.
kDPU_UnitSrcStore9	The input source is Store 9.
kDPU_UnitSrcConstFrame0	The input source is ConstFrame 0.
kDPU_UnitSrcConstFrame1	The input source is ConstFrame 1.
kDPU_UnitSrcConstFrame4	The input source is ConstFrame 4.
kDPU_UnitSrcConstFrame5	The input source is ConstFrame 5.
kDPU_UnitSrcFetchWarp2	The input source is FetchWarp 2.
kDPU_UnitSrcFetchEco2	The input source is FetchEco 2.
kDPU_UnitSrcFetchDecode0	The input source is FetchDecode 0.
kDPU_UnitSrcFetchEco0	The input source is FetchEco 0.
kDPU_UnitSrcFetchDecode1	The input source is FetchDecode 1.
kDPU_UnitSrcFetchEco1	The input source is FetchEco 1.
kDPU_UnitSrcFetchLayer0	The input source is FetchLayer 0.
kDPU_UnitSrcMatrix4	The input source is Matrix 4.
kDPU_UnitSrcHScaler4	The input source is HScaler 4.
kDPU_UnitSrcVScaler4	The input source is VScaler 4.
kDPU_UnitSrcMatrix5	The input source is Matrix 5.
kDPU_UnitSrcHScaler5	The input source is HScaler 5.
kDPU_UnitSrcVScaler5	The input source is VScaler 5.
kDPU_UnitSrcLayerBlend0	The input source is LayerBlend 0.
kDPU_UnitSrcLayerBlend1	The input source is LayerBlend 1.
kDPU_UnitSrcLayerBlend2	The input source is LayerBlend 2.
kDPU_UnitSrcLayerBlend3	The input source is LayerBlend 3.

enum dpu_pixel_format_t

To support more pixel format, enhance this enum and the array s_dpuColorComponentFormats.

Enumerator
kDPU_PixelFormatGray8	8-bit gray.
kDPU_PixelFormatRGB565	RGB565, 16-bit per pixel.
kDPU_PixelFormatARGB8888	ARGB8888, 32-bit per pixel.
kDPU_PixelFormatRGB888	RGB888, 24-bit per pixel.
kDPU_PixelFormatARGB1555	ARGB1555, 16-bit per pixel.

enum dpu_warp_coordinate_mode_t

Enumerator
kDPU_WarpCoordinateModePNT	Sample points positions are read from coordinate layer.
kDPU_WarpCoordinateModeDPNT	Sample points start position and delta are read from coordinate layer.
kDPU_WarpCoordinateModeDDPNT	Sample points initial value and delta increase value are read from coordinate layer.

enum dpu_clip_color_mode_t

Enumerator
kDPU_ClipColorNull	Use null color.
kDPU_ClipColorSublayer	Use color of sublayer.

enum dpu_alpha_mask_mode_t

Enumerator
kDPU_AlphaMaskPrim	Areas with primary input alpha > 128 mapped to alpha 255, the rest mapped to 0.
kDPU_AlphaMaskSec	Areas with secondary input alpha > 128 mapped to alpha 255, the rest mapped to 0.
kDPU_AlphaMaskPrimOrSec	Primary and secondary OR'ed together.
kDPU_AlphaMaskPrimAndSec	Primary and secondary AND'ed together.
kDPU_AlphaMaskPrimInv	Primary input alpha inverted.
kDPU_AlphaMaskSecInv	Secondary input alpha inverted.
kDPU_AlphaMaskPrimOrSecInv	Primary and inverted secondary OR'ed together.
kDPU_AlphaMaskPrimAndSecInv	Primary and inverted secondary AND'ed together.

enum dpu_blend_mode_t

Enumerator
kDPU_BlendZero	OUT = IN * 0.
kDPU_BlendOne	OUT = IN * 1.
kDPU_BlendPrimAlpha	OUT = IN * ALPHA_primary.
kDPU_BlendPrimAlphaInv	OUT = IN * (1 - ALPHA_primary).
kDPU_BlendSecAlpha	OUT = IN * ALPHA_secondary.
kDPU_BlendSecAlphaInv	OUT = IN * (1 - ALPHA_secondary).
kDPU_BlendConstAlpha	OUT = IN * ALPHA_const.
kDPU_BlendConstAlphaInv	OUT = IN * (1 - ALPHA_const).

enum dpu_blit_blend_func_t

Enumerator
kDPU_BlitBlendFuncGlZero	GL_ZERO.
kDPU_BlitBlendFuncGlOne	GL_ONE.
kDPU_BlitBlendFuncGlSrcColor	GL_SRC_COLOR.
kDPU_BlitBlendFuncGlOneMinusSrcColor	GL_ONE_MINUS_SRC_COLOR.
kDPU_BlitBlendFuncGlSrcAlpha	GL_SRC_ALPHA.
kDPU_BlitBlendFuncGlOneMinusSrcAlpha	GL_ONE_MINUS_SRC_ALPHA.
kDPU_BlitBlendFuncGlDstAlpha	GL_DST_ALPHA.
kDPU_BlitBlendFuncGlOneMinusDstAlpha	GL_ONE_MINUS_DST_ALPHA.
kDPU_BlitBlendFuncGlDstColor	GL_DST_COLOR.
kDPU_BlitBlendFuncGlOneMinusDstColor	GL_ONE_MINUS_DST_COLOR.
kDPU_BlitBlendFuncGlSrcAlphaSaturate	GL_SRC_ALPHA_SATURATE.
kDPU_BlitBlendFuncGlConstColor	GL_CONSTANT_COLOR.
kDPU_BlitBlendFuncGlOneMinusConstColor	GL_ONE_MINUS_CONSTANT_COLOR.
kDPU_BlitBlendFuncGlConstAlpha	GL_CONSTANT_ALPHA.
kDPU_BlitBlendFuncGlOneMinusConstAlpha	GL_ONE_MINUS_CONSTANT_ALPHA.

enum dpu_blit_blend_mode_t

Enumerator
kDPU_BlitBlendModeGlFuncAdd	GL_FUNC_ADD.
kDPU_BlitBlendModeGlMin	GL_MIN.
kDPU_BlitBlendModeGlMax	GL_MAX.
kDPU_BlitBlendModeGlFuncSubtract	GL_FUNC_SUBTRACT.
kDPU_BlitBlendModeGlFuncReverseSubtract	GL_FUNC_REVERSE_SUBTRACT.
kDPU_BlitBlendModeVgBlendSrc	VG_BLEND_SRC.
kDPU_BlitBlendModeVgBlendSrcOver	VG_BLEND_SRC_OVER.
kDPU_BlitBlendModeVgBlendDstOver	VG_BLEND_DST_OVER.
kDPU_BlitBlendModeVgBlendSrcIn	VG_BLEND_SRC_IN.
kDPU_BlitBlendModeVgBlendDstIn	VG_BLEND_DST_IN.
kDPU_BlitBlendModeVgBlendMultiply	VG_BLEND_MULTIPLY.
kDPU_BlitBlendModeVgBlendScreen	VG_BLEND_SCREEN.
kDPU_BlitBlendModeVgBlendDarken	VG_BLEND_DARKEN.
kDPU_BlitBlendModeVgBlendLighten	VG_BLEND_LIGHTEN.
kDPU_BlitBlendModeVgBlendAdditive	VG_BLEND_ADDITIVE.

enum dpu_blit_blend_neutral_border_mode_t

Enumerator
kDPU_BlitBlendNeutralBorderPrim	Bypasses primary pixel.
kDPU_BlitBlendNeutralBorderSec	Bypasses secondary pixel.

enum _dpu_rop_flags

Enumerator
kDPU_RopAddRed	Set to add the red component, otherwise raster with operation index.
kDPU_RopAddGreen	Set to add the green component, otherwise raster with operation index.
kDPU_RopAddBlue	Set to add the blue component, otherwise raster with operation index.
kDPU_RopAddAlpha	Set to add the alpha component, otherwise raster with operation index.
kDPU_RopTertDiv2	In add mode, set this to divide tertiary port input by 2.
kDPU_RopSecDiv2	In add mode, set this to divide secondary port input by 2.
kDPU_RopPrimDiv2	In add mode, set this to divide primary port input by 2.

enum _dpu_display_timing_flags

Enumerator
kDPU_DisplayPixelActiveHigh	Pixel data active high.
kDPU_DisplayPixelActiveLow	Pixel data active low.
kDPU_DisplayDataEnableActiveHigh	Set to make data enable high active.
kDPU_DisplayDataEnableActiveLow	Set to make data enable high low.
kDPU_DisplayHsyncActiveHigh	Set to make HSYNC high active.
kDPU_DisplayHsyncActiveLow	Set to make HSYNC low active.
kDPU_DisplayVsyncActiveHigh	Set to make VSYNC high active.
kDPU_DisplayVsyncActiveLow	Set to make VSYNC low active.

enum dpu_display_mode_t

Enumerator
kDPU_DisplayBlackBackground	Black background is shown.
kDPU_DisplayConstBackground	Const color background is shown.
kDPU_DisplayOnlyPrim	Only primary input is shown.
kDPU_DisplayOnlySec	Only secondary input is shown.
kDPU_DisplayPrimOnTop	Both inputs overlaid with primary on top.
kDPU_DisplaySecOnTop	Both inputs overlaid with secondary on top.
kDPU_DisplayTest	White background with test pattern shown.

enum _dpu_signature_window_flags

Enumerator
kDPU_SignatureWindowEnableGlobalPanic	When enabled the window error will activate display stream the panic mode.
kDPU_SignatureWindowEnableLocalPanic	When enabled the window error will replace pixels in window to the const panic color.
kDPU_SignatureWindowEnableAlphaMask	When enabled pixels with alpha bit = 0 are ignored for signature computation.
kDPU_SignatureWindowInvertAlpha	When enabled pixels with alpha bit = 1 are ignored for signature computation.

enum _dpu_signature_status

Enumerator
kDPU_SignatureIdle	Signature unit is in idle status.
kDPU_SignatureValid	Signature unit is in idle status.

Function Documentation

void DPU_Init ( IRIS_MVPL_Type * base )

This function ungates the DPU clock.

Parameters

base	DPU peripheral base address.

void DPU_Deinit ( IRIS_MVPL_Type * base )

This function gates the DPU clock.

Parameters

base	DPU peripheral base address.

void DPU_PreparePathConfig ( IRIS_MVPL_Type * base )

The DPU has a default path configuration. Before changing the configuration, this function could be used to break all the original path. This make sure one pixel engine unit is not used in multiple pipelines.

Parameters

base	DPU peripheral base address.

void DPU_EnableInterrupts	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

For example, to enable Store9 shadow load interrupt and Store9 frame complete interrupt, use like this:

DPU_EnableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |

kDPU_Group0Store9FrameCompleteInterrupt);

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupts to enable, this is a logical OR of members in _dpu_interrupt.

Note: Only the members in the same group could be OR'ed, at the same time, the parameter group should be passed in correctly.

void DPU_DisableInterrupts	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

For example, to disable Store9 shadow load interrupt and Store9 frame complete interrupt, use like this:

DPU_DisableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |

kDPU_Group0Store9FrameCompleteInterrupt);

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupts to disable, this is a logical OR of members in _dpu_interrupt.

Note: Only the members in the same group could be OR'ed, at the same time, the parameter group should be passed in correctly.

uint32_t DPU_GetInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group
	)

The pending status are returned as mask. For example, to check the Store9 shadow load interrupt and Store9 frame complete interrupt pending status, use like this.

uint32_t pendingStatus = DPU_GetInterruptsPendingFlags(DPU, 0);
if (pendingStatus & kDPU_Group0Store9ShadowLoadInterrupt)
{
    // Store9 shadow load interrupt occurs, handle it.
}
if (pendingStatus & kDPU_Group0Store9FrameCompleteInterrupt)
{
    // Store9 frame complete interrupt occurs, handle it.
}

Parameters

base	DPU peripheral base address.
group	Interrupt group index.

Returns: The interrupts pending status mask value, see _dpu_interrupt.

void DPU_ClearInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

For example, to disable Store9 shadow load interrupt and Store9 frame complete interrupt pending status, use like this:

DPU_ClearInterruptsPendingFlags(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |

kDPU_Group0Store9FrameCompleteInterrupt);

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupt pending flags to clear, this is a logical OR of members in _dpu_interrupt.

Note: Only the members in the same group could be OR'ed, at the same time, the parameter group should be passed in correctly.

void DPU_SetInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

This function sets the interrupts pending flags, this is a method to trigger interrupts by software.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupt pending flags to set, this is a logical OR of members in _dpu_interrupt.

Note: Only the members in the same group could be OR'ed, at the same time, the parameter group should be passed in correctly.

void DPU_MaskUserInterrupts	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts. All other APIs useage are the same.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupts to mask, this is a logical OR of members in _dpu_interrupt.

void DPU_EnableUserInterrupts	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupts to enable, this is a logical OR of members in _dpu_interrupt.

void DPU_DisableUserInterrupts	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupts to disable, this is a logical OR of members in _dpu_interrupt.

uint32_t DPU_GetUserInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.

Returns: The interrupts pending status mask value, see _dpu_interrupt.

void DPU_ClearUserInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupt pending flags to clear, this is a logical OR of members in _dpu_interrupt.

void DPU_SetUserInterruptsPendingFlags	(	IRIS_MVPL_Type *	base,
		uint8_t	group,
		uint32_t	mask
	)

The only difference between DPU user interrupt and normal interrupt is user interrupts could be masked by DPU_MaskUserInterrupts.

Parameters

base	DPU peripheral base address.
group	Interrupt group index.
mask	The interrupt pending flags to set, this is a logical OR of members in _dpu_interrupt.

status_t DPU_EnableShadowLoad	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		bool	enable
	)

For example:

// To enable the shadowing of all RWS registers of the pipeline with endpoint Store9.

DPU_EnableShadowLoad(DPU, kDPU_PipelineStore9, true);

Parameters

base	DPU peripheral base address.
unit	The unit whose shadow load to enable or disable, see dpu_unit_t.
enable	True to enable, false to disable.

Return values

kStatus_Success	The shadow load is enabled or disabled successfully.
kStatus_InvalidArgument	The unit does not support shadow load.

void DPU_InitPipeline	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

Parameters

base	DPU peripheral base address.
unit	The DPU pipeline unit.

void DPU_DeinitPipeline	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

Power down the pipeline and disable the shadow load feature.

Parameters

base	DPU peripheral base address.
unit	The DPU pipeline unit.

void DPU_TriggerPipelineShadowLoad	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

This function triggers the pipeline reconfiguration.

Parameters

base	DPU peripheral base address.
unit	The DPU pipeline unit.

void DPU_TriggerPipelineCompleteInterrupt	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

This function triggers the pipeline sequence complete interrupt. After triggered, this interrupt occurs when the pipeline is empty and no more operations are pending. It will occur immediately, when this is the case already during activation of the trigger. Generally this is used for the blit operation, to make sure all operations finished.

Parameters

base	DPU peripheral base address.
unit	The DPU pipeline unit.

void DPU_SetUnitSrc	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

Sets the DPU unit input source, the input source is controlled by the register <unit>_dynamic in "Pixel Engin Top Level". This function writes the register <unit>_dynamic directly, please check the reference manual for the register details. This function only changes the input source control bits in register.

Parameters

base	DPU peripheral base address.
unit	The DPU pipeline unit.
srcReg	The value written to register <unit>_dynamic. Could be generated using DPU_MAKE_SRC_REG1, DPU_MAKE_SRC_REG2, and DPU_MAKE_SRC_REG3.

void DPU_FetchUnitGetDefaultConfig ( dpu_fetch_unit_config_t * config )

The default value is:

config->srcReg = 0U;
config->frameHeight = 320U;
config->frameWidth = 480U;

Parameters

config Pointer to the configuration structure.

void DPU_InitFetchUnit	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_fetch_unit_config_t *	config
	)

This function initializes the fetch unit for the basic use, for other use case such as arbitrary warping, use the functions DPU_InitFetchUnitWarp and DPU_InitWarpCoordinates.

The input source of fetch unit could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
config	Pointer to the configuration structure.

status_t DPU_SetColorPaletteIndexWidth	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	indexWidth
	)

The palette index width could be 1 to 8. Note the difference between palette index width and the pixel width in framebuffer.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be FetchDecode or FetchLayer here.
indexWidth	The palette index width.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

status_t DPU_UpdateColorPalette	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	startIndex,
		const uint32_t *	palette,
		uint32_t	count
	)

This function updates the fetch unit color palette, the palette values specified by palette are loaded to fetch unit from startIndex. The load count is specified by count.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be FetchDecode or FetchLayer here.
startIndex	The start index of the fetch unit palette to update.
palette	Pointer to the palette.
count	Count of `palette`.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

void DPU_EnableColorPalette	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		bool	enable
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be FetchDecode or FetchLayer here.
sublayer	Sublayer index, should be 0 to 7.
enable	True to enable, false to disable.

void DPU_CorrdinatesGetDefaultConfig ( dpu_coordinates_config_t * config )

The default value is:

config->bitsPerPixel = 0U;
config->strideBytes = 0x500U;
config->baseAddr = 0U;
config->frameHeight = 320U;
config->frameWidth = 480U;

Parameters

config Pointer to the configuration structure.

status_t DPU_InitWarpCoordinates	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_coordinates_config_t *	config
	)

This function initializes the FetchEco unit, so that it could be used as the arbitrary warping coordinates.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be FetchEco here.
config	Pointer to the configuration structure.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

void DPU_FetcUnitGetDefaultWarpConfig ( dpu_warp_config_t * config )

The default value is:

config->srcReg = 0U;
config->frameHeight = 320U;
config->frameWidth = 480U;
config->warpBitsPerPixel = 0U;
config->enableSymmetricOffset = false;
config->coordMode = kDPU_WarpCoordinateModePNT;
config->arbStartX = 0U;
config->arbStartY = 0U;
config->arbDeltaYY = 0U;
config->arbDeltaYX = 0U;
config->arbDeltaXY = 0U;
config->arbDeltaXX = 0U;

Parameters

config Pointer to the configuration structure.

status_t DPU_InitFetchUnitWarp	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_warp_config_t *	config
	)

This function initializes the FetchWarp unit for the arbitrary warping.

The valid source of fetch warp unit could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be FetchWarp unit here.
config	Pointer to the configuration structure.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

void DPU_SrcBufferGetDefaultConfig ( dpu_src_buffer_config_t * config )

The default value is:

config->baseAddr = 0U;
config->strideBytes = 0x500U;
config->bitsPerPixel = 32U;
config->pixelFormat = kDPU_PixelFormatARGB8888;
config->bufferHeight = 0U;
config->bufferWidth = 0U;
config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);

Parameters

config Pointer to the configuration structure.

status_t DPU_SetFetchUnitSrcBufferConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		const dpu_src_buffer_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
config	Pointer to the configuration structure.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

void DPU_SetFetchUnitSrcBufferAddr	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		uint32_t	baseAddr
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
baseAddr	Source buffer base address.

void DPU_SetFetchUnitFrameSize	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint16_t	height,
		uint16_t	width
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
height	Frame height.
width	Frame width.

void DPU_SetFetchUnitOffset	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		uint16_t	offsetX,
		uint16_t	offsetY
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
offsetX	Horizontal offset.
offsetY	Vertical offset.

void DPU_EnableFetchUnitSrcBuffer	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		bool	enable
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
enable	True to enable, false to disable.

void DPU_ClipWindowGetDefaultConfig ( dpu_clip_window_config_t * config )

The default value is:

config->windowOffsetX = 0U;
config->windowOffsetY = 0U;
config->windowHeight = 0U;
config->windowWidth = 0U;

Parameters

config Pointer to the configuration structure.

void DPU_SetFetchUnitClipWindowConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		const dpu_clip_window_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
config	Pointer to the configuration structure.

void DPU_EnableFetchUnitClipWindow	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint8_t	sublayer,
		bool	enable
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
sublayer	Sublayer index, should be 0 to 7.
enable	True to enable, false to disable.

void DPU_SetFetchUnitClipColor	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		dpu_clip_color_mode_t	clipColorMode,
		uint8_t	sublayer
	)

This function selects which color to take for pixels that do not lie inside the clip window of any layer.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be fetch unit here.
clipColorMode	Select null color or use sublayer color.
sublayer	Select which sublayer's color to use when `clipColorMode` is kDPU_ClipColorSublayer.

void DPU_InitExtDst	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be ExtDst unit here.
srcReg	Input source selecte register value, pixencfg_extdstX_dynamic see DPU_MAKE_SRC_REG1. The valid source: kDPU_UnitSrcNone kDPU_UnitSrcBlitBlend9 kDPU_UnitSrcConstFrame0 kDPU_UnitSrcConstFrame1 kDPU_UnitSrcConstFrame4 kDPU_UnitSrcConstFrame5 kDPU_UnitSrcHScaler4 kDPU_UnitSrcVScaler4 kDPU_UnitSrcHScaler5 kDPU_UnitSrcVScaler5 kDPU_UnitSrcLayerBlend0 kDPU_UnitSrcLayerBlend1 kDPU_UnitSrcLayerBlend2 kDPU_UnitSrcLayerBlend3

void DPU_InitStore	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

The valid input source of the store unit could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Store unit here.
srcReg	Input source selecte register value, pixencfg_extdstX_dynamic see DPU_MAKE_SRC_REG1.

status_t DPU_SetStoreDstBufferConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_dst_buffer_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Store unit here.
config	Pointer to the configuration.

Return values

kStatus_Success	Initialization success.
kStatus_InvalidArgument	Wrong argument.

void DPU_DstBufferGetDefaultConfig ( dpu_dst_buffer_config_t * config )

The default value is:

config->baseAddr = 0U;
config->strideBytes = 0x500U;
config->bitsPerPixel = 32U,
config->pixelFormat = kDPU_PixelFormatARGB8888;
config->bufferHeight = 0U;
config->bufferWidth = 0U;

Parameters

config Pointer to the configuration.

void DPU_SetStoreDstBufferAddr	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	baseAddr
	)

This function is run time used for better performance.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Store unit here.
baseAddr	Base address of the Destination buffer to set.

void DPU_SetStoreOffset	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint16_t	offsetX,
		uint16_t	offsetY
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Store unit here.
offsetX	Horizontal offset.
offsetY	Vertical offset.

Note

The horizontal offset has limitations for some formats. It must be a multiple of  - 8 for 1 bpp buffers

4 for 2 bpp and 18 bpp buffers
2 for 4 bpp buffers

void DPU_StartStore	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

This function starts the Store unit to save the frame to output buffer. When the frame store completed, the interrupt flag kDPU_Group0Store9FrameCompleteInterrupt asserts.

This is an example shows how to use Store unit:

* // Initialize the Store unit, use FetchDecode9 output as its input.
  DPU_InitStore(DPU, kDPU_Store9, DPU_MAKE_SRC_REG1(kDPU_UnitSrcFetchDecode9));
  // Configure the Store unit output buffer.
  DPU_SetStoreDstBufferConfig(DPU, kDPU_Store9, &DstBufferConfig);
  // Configure FetchDecode9 unit, including source buffer setting and so on.
  //
  // CODE FOR FETCHDECODE9
  //
  // Initialize the Store9 pipeline
  DPU_InitPipeline(DPU, kDPU_PipelineStore9);
  DPU_ClearUserInterruptsPendingFlags(DPU, kDPU_Group0Store9ShadowLoadInterrupt);
  // Trigger the shadow load
  DPU_TriggerPipelineShadowLoad(DPU, kDPU_PipelineStore9);
  DPU_ClearUserInterruptsPendingFlags(DPU, kDPU_Group0Store9FrameCompleteInterrupt);
  // Start the Store9 to convert and output.
  DPU_StartStore(DPU, kDPU_Store9);
  // Wait for Store 9 completed, this could also be monitored by interrupt.
  while (!(kDPU_Group0Store9FrameCompleteInterrupt & DPU_GetUserInterruptsPendingFlags(DPU, 0))
  {
  }

For better performance, it is allowed to set next operation while current is still in progress. Upper layer could set next operation immediately after shadow load finished.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Store unit here.

void DPU_InitRop	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

The primary input source of the unit could be:

The secondary input source of the unit could be:

The tert input source of the unit could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Rop unit here.
srcReg	Unit source selection, see DPU_MAKE_SRC_REG3.

void DPU_RopGetDefaultConfig ( dpu_rop_config_t * config )

The default configuration is:

config->controlFlags = 0U;
config->alphaIndex = 0U;
config->blueIndex = 0U;
config->greenIndex = 0U;
config->redIndex = 0U;

Parameters

config Pointer to the configuration structure.

void DPU_SetRopConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_rop_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Rop unit here.
config	Pointer to the configuration structure.

void DPU_EnableRop	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		bool	enable
	)

If disabled, only the primary input is output.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be Rop unit here.
enable	Pass true to enable, false to disable.

void DPU_InitBlitBlend	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

The valid input primary source could be:

The valid input secondary source could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be BlitBlend unit here.
srcReg	Unit source selection, see DPU_MAKE_SRC_REG2.

void DPU_BlitBlendGetDefaultConfig ( dpu_blit_blend_config_t * config )

The default configuration is:

config->neutralBorderRightPixels = 0U;
config->neutralBorderLeftPixels = 0U;
config->neutralBorderMode = kDPU_BlitBlendNeutralBorderPrim;
config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);
config->redBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
config->redBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
config->greenBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
config->greenBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
config->blueBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
config->blueBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
config->alphaBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
config->alphaBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
config->redBlendMode = kDPU_BlitBlendModeGlFuncAdd;
config->greenBlendMode = kDPU_BlitBlendModeGlFuncAdd;
config->blueBlendMode = kDPU_BlitBlendModeGlFuncAdd;
config->alphaBlendMode = kDPU_BlitBlendModeGlFuncAdd;

Parameters

config Pointer to the configuration structure.

void DPU_SetBlitBlendConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_blit_blend_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be BlitBlend unit here.
config	Pointer to the configuration structure.

void DPU_EnableBlitBlend	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		bool	enable
	)

The BlitBlend unit could be runtime enabled or disabled, when disabled, the primary input is output directly.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be BlitBlend unit here.
enable	Pass true to enable, false to disable.

void DPU_LayerBlendGetDefaultConfig ( dpu_layer_blend_config_t * config )

The default value is:

config->constAlpha = 0U;
config->secAlphaBlendMode = kDPU_BlendOne;
config->primAlphaBlendMode = kDPU_BlendZero;
config->secColorBlendMode = kDPU_BlendOne;
config->primColorBlendMode = kDPU_BlendZero;
config->enableAlphaMask = true;
config->alphaMaskMode = kDPU_AlphaMaskPrim;

Parameters

config Pointer to the configuration structure.

void DPU_InitLayerBlend	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		uint32_t	srcReg
	)

The valid primary source:

The valid secondary source:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be LayerBlend unit here.
srcReg	Unit source selection, see DPU_MAKE_SRC_REG2.

void DPU_SetLayerBlendConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_layer_blend_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be LayerBlend unit here.
config	Pointer to the configuration structure.

void DPU_EnableLayerBlend	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		bool	enable
	)

If enabled, the blend result is output, otherwise, the primary input is output.

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be LayerBlend unit here.
enable	Pass true to enable, false to disable.

void DPU_InitConstFrame	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be ConstFrame unit here.

void DPU_ConstFrameGetDefaultConfig ( dpu_const_frame_config_t * config )

The default value is:

config->frameHeight = 320U;
config->frameWidth = 480U;
config->constColor = DPU_MAKE_CONST_COLOR(0xFF, 0xFF, 0xFF, 0xFF);

Parameters

config Pointer to the configuration structure.

void DPU_SetConstFrameConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_const_frame_config_t *	config
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be ConstFrame unit here.
config	Pointer to the configuration structure.

void DPU_InitScaler	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit
	)

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be HScaler or VScaler unit here.

void DPU_ScalerGetDefaultConfig ( dpu_scaler_config_t * config )

The default value is:

config->srcReg = 0U;
config->inputSize = 0U;
config->outputSize = 0U;

Parameters

config Pointer to the configuration structure.

void DPU_SetScalerConfig	(	IRIS_MVPL_Type *	base,
		dpu_unit_t	unit,
		const dpu_scaler_config_t *	config
	)

The valid input source could be:

Parameters

base	DPU peripheral base address.
unit	DPU unit, see dpu_unit_t, must be HScaler or VScaler unit here.
config	Pointer to the configuration structure.

void DPU_DisplayTimingGetDefaultConfig ( dpu_display_timing_config_t * config )

The default value is:

config->flags = kDPU_DisplayDeActiveHigh;
config->width = 320U;
config->hsw = 32U;
config->hfp = 8U;
config->hbp = 40U;
config->height = 240U;
config->vsw = 4U;
config->vfp = 13U;
config->vbp = 6U;

Parameters

config Pointer to the configuration structure.

void DPU_InitDisplayTiming	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		const dpu_display_timing_config_t *	config
	)

Parameters

base	DPU peripheral base address.
displayIndex	Index of the display.
config	Pointer to the configuration structure.

void DPU_DisplayGetDefaultConfig ( dpu_display_config_t * config )

The default value is:

config->enablePrimAlpha = false;
config->enableSecAlpha = false;
config->displayMode = kDPU_DisplayTest;
config->enablePrimAlphaInPanic = false;
config->enableSecAlphaInPanic = false;
config->displayModeInPanic = kDPU_DisplayTest;
config->constRed = 0x3FFU;
config->constGreen = 0x3FFU;
config->constBlue = 0x3FFU;
config->constAlpha = 1U;
config->primAreaStartX = 1U;
config->primAreaStartY = 1U;
config->secAreaStartX = 1U;
config->secAreaStartY = 1U;

Parameters

config Pointer to the configuration structure.

void DPU_SetDisplayConfig	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		const dpu_display_config_t *	config
	)

Parameters

base	DPU peripheral base address.
displayIndex	Index of the display.
config	Pointer to the configuration structure.

void DPU_StartDisplay	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex
	)

Parameters

base	DPU peripheral base address.
displayIndex	Index of the display.

void DPU_StopDisplay	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex
	)

This function stops the display and wait the sequence complete.

Parameters

base	DPU peripheral base address.
displayIndex	Index of the display.

void DPU_SetFrameGenInterruptConfig	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	interruptIndex,
		uint32_t	intConfig
	)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
interruptIndex	Interrupt index, there could be 4 interrupts for each display.
intConfig	Interrupt mode, could be one of DPU_FRAME_GEN_INT_DISABLE, DPU_FRAME_GEN_INT_PER_LINE, and DPU_FRAME_GEN_INT_PER_FRAME.

void DPU_TriggerDisplayShadowLoad	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex
	)

Trigger the display stream shadow load token, then the shadow register will be loaded at the begining of next frame.

Parameters

base	DPU peripheral base address.
displayIndex	Display index.

void DPU_SignatureGetDefaultConfig ( dpu_signature_config_t * config )

The default configuration is:

config->errorThreshold = 0U;
config->errorResetThreshold = 8U;
config->panicRed = 0U;
config->panicGreen = 0U;
config->panicBlue = 0U;
config->panicAlpha = 0U;

Parameters

config Pointer to the configuration.

void DPU_InitSignature	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		const dpu_signature_config_t *	config
	)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
config	Pointer to the configuration.

void DPU_SignatureWindowGetDefaultConfig ( dpu_signature_window_config_t * config )

The default configuration is:

config->controlFlags = 0U;
config->upperLeftX = 0U;
config->upperLeftY = 0U;
config->lowerRightX = 0U;
config->lowerRightY = 0U;

Parameters

config Pointer to the configuration.

void DPU_SetSignatureWindowConfig	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	windowIndex,
		const dpu_signature_window_config_t *	config
	)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
windowIndex	Evaluation window index, should be 0 to 7.
config	Pointer to the configuration.

void DPU_EnableSignatureWindowCompute	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	windowIndex,
		bool	enable
	)

When enabled, a CRC signature is computed for all pixels inside this evaluation window, When disabled, the internal status for this window is reset (StsSigError bit and frame counters)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
windowIndex	Evaluation window index, should be 0 to 7.
enable	Pass true to enable, false to disable.

void DPU_EnableSignatureWindowCheck	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	windowIndex,
		bool	enable
	)

When enabled, the measured signature is checked against a reference value.

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
windowIndex	Evaluation window index, should be 0 to 7.
enable	Pass true to enable, false to disable.

void DPU_GetSignatureWindowCrc	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	windowIndex,
		uint32_t *	redCRC,
		uint32_t *	greenCRC,
		uint32_t *	blueCRC
	)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
windowIndex	Evaluation window index, should be 0 to 7.
redCRC	Measured signature value of red.
greenCRC	Measured signature value of green.
blueCRC	Measured signature value of blue.

void DPU_SetSignatureWindowRefCrc	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex,
		uint8_t	windowIndex,
		uint32_t	redCRC,
		uint32_t	greenCRC,
		uint32_t	blueCRC
	)

Parameters

base	DPU peripheral base address.
displayIndex	Display index.
windowIndex	Evaluation window index, should be 0 to 7.
redCRC	Reference signature value of red.
greenCRC	Referencesignature value of green.
blueCRC	Reference signature value of blue.

uint32_t DPU_GetSignatureStatus	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex
	)

This function returns the signature unit status. The return value could be compared to check the status defined in _dpu_signature_status. For example:

uint32_t status = DPU_GetSignatureStatus(DPU, 0);
if (kDPU_SignatureValid & status)
{
    // signature measure finished, could read the value.
    DPU_GetSignatureWindowCrc(...);
}

The error flags are also returned as an mask value, upper layer could get specific window status by checking the returned bit accordingly. For example,

uint32_t status = DPU_GetSignatureStatus(DPU, 0);
if ((1<<3) & status)
{
    // Window 3 error detected.
}
if ((1<<5) & status)
{
    // Window 5 error detected.
}

Parameters

base	DPU peripheral base address.
displayIndex	Display index.

Returns: Mask value of status.

void DPU_TriggerSignatureShadowLoad	(	IRIS_MVPL_Type *	base,
		uint8_t	displayIndex
	)

When new configuration set by DPU_SetSignatureWindowConfig, DPU_EnableSignatureWindowCheck, DPU_EnableSignatureWindowCompute, and DPU_SetSignatureWindowRefCrc, use this function to trigger the shadow load, then the new configuration takes effect.

Upper layer should monitor the kDPU_Group0Sig0ShadowLoadInterrupt or kDPU_Group1Sig1ShadowLoadInterrupt to wait shadow load finished. New configurations should only be set after shadow load finished.

Parameters

base	DPU peripheral base address.
displayIndex	Display index.

Overview

Program model

Path configuration

Data Structures

Macros

Enumerations

Driver version

Macros for the DPU unit input source.

Macros define the FrameGen interrupt mode.

DPU Initialization and de-initialization

DPU interrupts

Shadow load related.

Pipline.

Fetch Units

ExtDst Units

Store Units

Rop units

BlitBlend units

LayerBlend units

ConstFrame units

VScaler and HScaler units

Display engine

Signature unit

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation