Overview

The SDK provides Peripheral driver for the CACHE Controller of Kinetis devices.

CACHE driver is created to help user to operate the Cache memory more easy. The LPCAC contains code bus cache and system bus cache if the system bus cache is supported (the system bus cache is soc specific). The code bus cache is ranged from 0x00000000 ~ 0x1FFFFFFF and the system bus is ranged from 0x20000000 ~ 0xFFFFFFFF.

The APIs for basic operations are including the following three groups: 1L. The L1 specific cache driver API. This group provides the IP specific cache controller drivers. The L1 caches in this arch is the AHB Low Power Cache Controller (LPCAC). The driver API name in this level is L1 cache controller specific.

2L. The unified L1 cache driver API. For easy of use, we try to unify the L1 cache driver API as much as possible in this group. APIs of this type directly call the L1 specific cache driver API and are unified to the same name. But due to the cache controller specification, there is impossible to provide all L1 cache unified APIs for LPCAC.

3L. The unified cache driver API. This group is provided for unified cache driver APIs for combining L1 and L2 cache maintain operations. This is provided for SDK drivers (DMA, ENET, USDHC etc) which should do the cache maintenance in their transactional APIs. Because in this arch, there is no L2 cache so the unified cache driver API directly call only L1 cache driver APIs.

Function groups

L1 CACHE Operation {#L1CACHE MaintainOperation}

This function group provides Enable/Disable APIs. This function group only provide cache Invalidate operation beacuse the LPCAC is write through mode. By default the cache mode is write through with allocation. The above cache maintains are provided for code bus cache and maybe will provide for system bus cache if it is supported in the future.

The SDK provides Peripheral driver for the CACHE Controller of Kinetis devices.

CACHE driver is created to help user to operate the Cache memory more easy. The LPLMEM contains code bus cache and system bus cache if the system bus cache is supported (the system bus cache is soc specific). The code bus cache is ranged from 0x00000000 ~ 0x1FFFFFFF and the system bus is ranged from 0x20000000 ~ 0xFFFFFFFF.

The APIs for basic operations are including the following three groups: 1L. The L1 specific cache driver API. This group provides the IP specific cache controller drivers. The L1 caches in this arch is the AHB Low Power Local Memory Controller (LPLMEM). The driver API name in this level is L1 cache controller specific.

2L. The unified L1 cache driver API. For easy of use, we try to unify the L1 cache driver API as much as possible in this group. APIs of this type directly call the L1 specific cache driver API and are unified to the same name. But due to the cache controller specification, there is impossible to provide all L1 cache unified APIs for LPLMEM.

3L. The unified cache driver API. This group is provided for unified cache driver APIs for combining L1 and L2 cache maintain operations. This is provided for SDK drivers (DMA, ENET, USDHC etc) which should do the cache maintenance in their transactional APIs. Because in this arch, there is no L2 cache so the unified cache driver API directly call only L1 cache driver APIs.

Function groups

L1 CACHE Operation {#L1CACHE MaintainOperation}

This function group provides Enable/Disable APIs. This function group only provide cache Invalidate operation beacuse the LPLMEM is write through mode. By default the cache mode is write through with allocation. The above cache maintains are provided for code bus cache and maybe will provide for system bus cache if it is supported in the future.

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
	cache driver version 2.0.0. More...

cache control for the L1 low power cache controller
static void	L1CACHE_EnableCodeCache (void)
	Enables the processor code bus cache.

static void	L1CACHE_DisableCodeCache (void)
	Disables the processor code bus cache.

static void	L1CACHE_InvalidateCodeCache (void)
	Invalidates the processor code bus cache.

The unified L1 cache controller
The LPCAC is write-through design, so there is no cache maintain by range control operation. So all cache maintain by range unified functions are directly call the cache maintain all functions since they have the same effect.
void	L1CACHE_InvalidateICacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates L1 instrument cache by range. More...

static void	L1CACHE_InvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates L1 data cache by range. More...

static void	L1CACHE_CleanDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans L1 data cache by range. More...

static void	L1CACHE_CleanInvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates L1 data cache by range. More...

Unified Cache Control for caches in all levels
static void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates instruction cache by range. More...

static void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates data cache by range. More...

static void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Clean data cache by range. More...

static void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates data cache by range. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
	cache driver version 2.0.0. More...

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))

Function Documentation

void L1CACHE_InvalidateICacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

static void L1CACHE_InvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

static void L1CACHE_CleanDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

The cache is write through mode, so there is nothing to do with the cache flush/clean operation.

Parameters

address	The start address of the memory to be cleaned.
size_byte	The memory size.

static void L1CACHE_CleanInvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be clean and invalidated.
size_byte	The memory size.

static void ICACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

static void DCACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

static void DCACHE_CleanByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

static void DCACHE_CleanInvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be Cleaned and Invalidated.

Overview

Function groups

L1 CACHE Operation {#L1CACHE MaintainOperation}

Function groups

L1 CACHE Operation {#L1CACHE MaintainOperation}

Driver version

cache control for the L1 low power cache controller

The unified L1 cache controller

Unified Cache Control for caches in all levels

Driver version

Macro Definition Documentation

Function Documentation