CACHE: CACHE Memory Controller

Overview

The MCUXpresso SDK provides a peripheral driver for the CACHE Controller of MCUXpresso SDK devices.

The CACHE driver is created to help the user more easily operate the cache memory. The APIs for basic operations are including the following three levels: 1L. The local cache driver API. This level provides the caches controller drivers.

2L. The unified cache driver API. This level provides many APIs for unified cache driver APIs for combined L1 and L2 cache maintain operations. This is provided for SDK drivers (DMA, ENET, USDHC, etc) which should do the cache maintenance in their transactional APIs. Because in this arch, there is no L2 cache so the unified cache driver API directly calls local driver APIs.

Function groups

CACHE Operation {#CACHE MaintainOperation}

There are Enable/Disable APIs for cache control and cache maintenance operations as Invalidate/Clean/CleanInvalidate by all and by address range.

Data Structures
struct	cache64_config_t
	CACHE64 configuration structure. More...

Macros
#define	CACHE64_LINESIZE_BYTE   (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
	cache line size. More...
#define	CACHE64_REGION_NUM   (3)
	cache region number. More...
#define	CACHE64_REGION_ALIGNMENT   (0x400U)
	cache region alignment. More...
#define	CACHE64_LINESIZE_BYTE   (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
	cache line size. More...
#define	CACHE64_REGION_NUM   (3)
	cache region number. More...
#define	CACHE64_REGION_ALIGNMENT   (0x400U)
	cache region alignment. More...

Enumerations
enum	cache64_policy_t {   kCACHE64_PolicyNonCacheable = 0,   kCACHE64_PolicyWriteThrough = 1,   kCACHE64_PolicyWriteBack = 2,   kCACHE64_PolicyNonCacheable = 0,   kCACHE64_PolicyWriteThrough = 1,   kCACHE64_PolicyWriteBack = 2 }
	Level 2 cache controller way size. More...
enum	cache64_policy_t {   kCACHE64_PolicyNonCacheable = 0,   kCACHE64_PolicyWriteThrough = 1,   kCACHE64_PolicyWriteBack = 2,   kCACHE64_PolicyNonCacheable = 0,   kCACHE64_PolicyWriteThrough = 1,   kCACHE64_PolicyWriteBack = 2 }
	Level 2 cache controller way size. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
	cache driver version 2.0.1. More...

cache control for cache64
status_t	CACHE64_Init (CACHE64_POLSEL_Type *base, const cache64_config_t *config)
	Initializes an CACHE64 instance with the user configuration structure. More...
void	CACHE64_GetDefaultConfig (cache64_config_t *config)
	Gets the default configuration structure. More...
void	CACHE64_EnableCache (CACHE64_CTRL_Type *base)
	Enables the cache. More...
void	CACHE64_DisableCache (CACHE64_CTRL_Type *base)
	Disables the cache. More...
void	CACHE64_InvalidateCache (CACHE64_CTRL_Type *base)
	Invalidates the cache. More...
void	CACHE64_InvalidateCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates cache by range. More...
void	CACHE64_CleanCache (CACHE64_CTRL_Type *base)
	Cleans the cache. More...
void	CACHE64_CleanCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans cache by range. More...
void	CACHE64_CleanInvalidateCache (CACHE64_CTRL_Type *base)
	Cleans and invalidates the cache. More...
void	CACHE64_CleanInvalidateCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and invalidate cache by range. More...
void	CACHE64_EnableWriteBuffer (CACHE64_CTRL_Type *base, bool enable)
	Enables/disables the write buffer. More...

Unified Cache Control for all caches
static void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates instruction cache by range. More...
static void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates data cache by range. More...
static void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Clean data cache by range. More...
static void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates data cache by range. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
	cache driver version 2.0.1. More...

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Data Structure Documentation

struct cache64_config_t

Data Fields
uint32_t	boundaryAddr [CACHE64_REGION_NUM-1]
	< The cache controller can divide whole memory into 3 regions. More...

Field Documentation

uint32_t cache64_config_t::boundaryAddr

Boundary address is the physical address to split adjacent regions and must be 1KB aligned. The boundary address itself locates in upper region. Cacheable policy for each region.

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))

#define CACHE64_LINESIZE_BYTE   (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)

#define CACHE64_REGION_NUM   (3)

#define CACHE64_REGION_ALIGNMENT   (0x400U)

#define FSL_CACHE_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))

#define CACHE64_LINESIZE_BYTE   (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)

#define CACHE64_REGION_NUM   (3)

#define CACHE64_REGION_ALIGNMENT   (0x400U)

Enumeration Type Documentation

enum cache64_policy_t

Enumerator
kCACHE64_PolicyNonCacheable	Non-cacheable.
kCACHE64_PolicyWriteThrough	Write through.
kCACHE64_PolicyWriteBack	Write back.
kCACHE64_PolicyNonCacheable	Non-cacheable.
kCACHE64_PolicyWriteThrough	Write through.
kCACHE64_PolicyWriteBack	Write back.

enum cache64_policy_t

Enumerator
kCACHE64_PolicyNonCacheable	Non-cacheable.
kCACHE64_PolicyWriteThrough	Write through.
kCACHE64_PolicyWriteBack	Write back.
kCACHE64_PolicyNonCacheable	Non-cacheable.
kCACHE64_PolicyWriteThrough	Write through.
kCACHE64_PolicyWriteBack	Write back.

Function Documentation

status_t CACHE64_Init	(	CACHE64_POLSEL_Type *	base,
		const cache64_config_t *	config
	)

This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function to configure the configuration structure and get the default configuration.

Parameters

base	CACHE64_POLSEL peripheral base address.
config	Pointer to a user-defined configuration structure.

Return values

kStatus_Success

CACHE64 initialize succeed

void CACHE64_GetDefaultConfig

(

cache64_config_t *

config

)

This function initializes the CACHE64 configuration structure to a default value. The default values are first region covers whole cacheable area, and policy set to write back.

Parameters

config

Pointer to a configuration structure.

void CACHE64_EnableCache

(

CACHE64_CTRL_Type *

base

)

Parameters

base	CACHE64_CTRL peripheral base address.

void CACHE64_DisableCache

(

CACHE64_CTRL_Type *

base

)

Parameters

base	CACHE64_CTRL peripheral base address.

void CACHE64_InvalidateCache

(

CACHE64_CTRL_Type *

base

)

Parameters

base	CACHE64_CTRL peripheral base address.

void CACHE64_InvalidateCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be invalidated.

Note

Address and size should be aligned to "CACHE64_LINESIZE_BYTE". The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void CACHE64_CleanCache

(

CACHE64_CTRL_Type *

base

)

Parameters

base	CACHE64_CTRL peripheral base address.

void CACHE64_CleanCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be cleaned.

Note

Address and size should be aligned to "CACHE64_LINESIZE_BYTE". The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void CACHE64_CleanInvalidateCache

(

CACHE64_CTRL_Type *

base

)

Parameters

base	CACHE64_CTRL peripheral base address.

void CACHE64_CleanInvalidateCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be Cleaned and Invalidated.

Note

Address and size should be aligned to "CACHE64_LINESIZE_BYTE". The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void CACHE64_EnableWriteBuffer	(	CACHE64_CTRL_Type *	base,
		bool	enable
	)

Parameters

base	CACHE64_CTRL peripheral base address.
enable	The enable or disable flag. true - enable the write buffer. false - disable the write buffer.

static void ICACHE_InvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note

Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_InvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note

Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note

Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanInvalidateByRange ( uint32_t  address, uint32_t  size_byte  )

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be Cleaned and Invalidated.

Note

Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.