Overview

The MCUXpresso SDK provides a peripheral driver for the Direct Memory Access (DMA) of MCUXpresso SDK devices.

Typical use case

DMA Operation

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/dma

Files
file	fsl_dma.h

file	fsl_dma.h

Data Structures
struct	dma_descriptor_t
	DMA descriptor structure. More...

struct	dma_xfercfg_t
	DMA transfer configuration. More...

struct	dma_channel_trigger_t
	DMA channel trigger. More...

struct	dma_channel_config_t
	DMA channel trigger. More...

struct	dma_transfer_config_t
	DMA transfer configuration. More...

struct	dma_handle_t
	DMA transfer handle structure. More...

Macros
#define	DMA_MAX_TRANSFER_COUNT 0x400U
	DMA max transfer size.

#define	FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
	DMA channel numbers. More...

#define	DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
	DMA head descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
	DMA head descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
	DMA link descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
	DMA link descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width)
	DMA transfer buffer address need to align with the transfer width.

#define	DMA_COMMON_REG_GET(base, channel, reg) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
	DMA linked descriptor address algin size.

#define	DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((uint32_t )((uint32_t)(start) + (inc) (bytes) - (inc) * (width)))
	DMA descriptor end address calculate. More...

#define	DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes)
	DMA channel transfer configurations macro. More...

#define	DMA_MAX_TRANSFER_COUNT 0x400
	DMA max transfer size.

#define	FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
	DMA channel numbers. More...

#define	DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
	DMA head descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
	DMA head descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
	DMA link descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
	DMA link descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor. More...

#define	DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width)
	DMA transfer buffer address need to align with the transfer width.

#define	DMA_COMMON_REG_GET(base, channel, reg) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
	DMA linked descriptor address algin size.

#define	DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void )((uint32_t)(start) + inc bytes - inc * width))
	DMA descriptor end address calculate. More...

#define	DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes)
	DMA channel transfer configurations macro. More...

Typedefs
typedef void(*	dma_callback )(struct _dma_handle handle, void userData, bool transferDone, uint32_t intmode)
	Define Callback function for DMA. More...

typedef void(*	dma_callback )(struct _dma_handle handle, void userData, bool transferDone, uint32_t intmode)
	Define Callback function for DMA. More...

Enumerations
enum	{ kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0) }
	_dma_transfer_status DMA transfer status More...

enum	{ kDMA_AddressInterleave0xWidth = 0U, kDMA_AddressInterleave1xWidth = 1U, kDMA_AddressInterleave2xWidth = 2U, kDMA_AddressInterleave4xWidth = 4U }
	_dma_addr_interleave_size dma address interleave size More...

enum	{ kDMA_Transfer8BitWidth = 1U, kDMA_Transfer16BitWidth = 2U, kDMA_Transfer32BitWidth = 4U }
	_dma_transfer_width dma transfer width More...

enum	dma_priority_t { kDMA_ChannelPriority0 = 0, kDMA_ChannelPriority1, kDMA_ChannelPriority2, kDMA_ChannelPriority3, kDMA_ChannelPriority4, kDMA_ChannelPriority5, kDMA_ChannelPriority6, kDMA_ChannelPriority7, kDMA_ChannelPriority0 = 0, kDMA_ChannelPriority1, kDMA_ChannelPriority2, kDMA_ChannelPriority3, kDMA_ChannelPriority4, kDMA_ChannelPriority5, kDMA_ChannelPriority6, kDMA_ChannelPriority7 }
	DMA channel priority. More...

enum	dma_irq_t { kDMA_IntA, kDMA_IntB, kDMA_IntError, kDMA_IntA, kDMA_IntB, kDMA_IntError }
	DMA interrupt flags. More...

enum	dma_trigger_type_t { kDMA_NoTrigger = 0, kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) \| DMA_CHANNEL_CFG_TRIGTYPE(1), kDMA_HighLevelTrigger, kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), kDMA_RisingEdgeTrigger, kDMA_NoTrigger = 0, kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) \| DMA_CHANNEL_CFG_TRIGTYPE(1), kDMA_HighLevelTrigger, kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), kDMA_RisingEdgeTrigger }
	DMA trigger type. More...

enum	{ kDMA_BurstSize1 = 0U, kDMA_BurstSize2 = 1U, kDMA_BurstSize4 = 2U, kDMA_BurstSize8 = 3U, kDMA_BurstSize16 = 4U, kDMA_BurstSize32 = 5U, kDMA_BurstSize64 = 6U, kDMA_BurstSize128 = 7U, kDMA_BurstSize256 = 8U, kDMA_BurstSize512 = 9U, kDMA_BurstSize1024 = 10U }
	_dma_burst_size DMA burst size More...

enum	dma_trigger_burst_t { kDMA_SingleTransfer = 0, kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer2, kDMA_EdgeBurstTransfer4, kDMA_EdgeBurstTransfer8, kDMA_EdgeBurstTransfer16, kDMA_EdgeBurstTransfer32, kDMA_EdgeBurstTransfer64, kDMA_EdgeBurstTransfer128, kDMA_EdgeBurstTransfer256, kDMA_EdgeBurstTransfer512, kDMA_EdgeBurstTransfer1024, kDMA_SingleTransfer = 0, kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer2, kDMA_EdgeBurstTransfer4, kDMA_EdgeBurstTransfer8, kDMA_EdgeBurstTransfer16, kDMA_EdgeBurstTransfer32, kDMA_EdgeBurstTransfer64, kDMA_EdgeBurstTransfer128, kDMA_EdgeBurstTransfer256, kDMA_EdgeBurstTransfer512, kDMA_EdgeBurstTransfer1024 }
	DMA trigger burst. More...

enum	dma_burst_wrap_t { kDMA_NoWrap = 0, kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), kDMA_SrcAndDstWrap, kDMA_NoWrap = 0, kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), kDMA_SrcAndDstWrap }
	DMA burst wrapping. More...

enum	dma_transfer_type_t { kDMA_MemoryToMemory = 0x0U, kDMA_PeripheralToMemory, kDMA_MemoryToPeripheral, kDMA_StaticToStatic, kDMA_MemoryToMemory = 0x0U, kDMA_PeripheralToMemory, kDMA_MemoryToPeripheral, kDMA_StaticToStatic }
	DMA transfer type. More...

enum	_dma_transfer_status { kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0) }
	DMA transfer status. More...

enum	_dma_addr_interleave_size { kDMA_AddressInterleave0xWidth = 0U, kDMA_AddressInterleave1xWidth = 1U, kDMA_AddressInterleave2xWidth = 2U, kDMA_AddressInterleave4xWidth = 4U }
	dma address interleave size More...

enum	_dma_transfer_width { kDMA_Transfer8BitWidth = 1U, kDMA_Transfer16BitWidth = 2U, kDMA_Transfer32BitWidth = 4U }
	dma transfer width More...

enum	dma_priority_t { kDMA_ChannelPriority0 = 0, kDMA_ChannelPriority1, kDMA_ChannelPriority2, kDMA_ChannelPriority3, kDMA_ChannelPriority4, kDMA_ChannelPriority5, kDMA_ChannelPriority6, kDMA_ChannelPriority7, kDMA_ChannelPriority0 = 0, kDMA_ChannelPriority1, kDMA_ChannelPriority2, kDMA_ChannelPriority3, kDMA_ChannelPriority4, kDMA_ChannelPriority5, kDMA_ChannelPriority6, kDMA_ChannelPriority7 }
	DMA channel priority. More...

enum	dma_irq_t { kDMA_IntA, kDMA_IntB, kDMA_IntError, kDMA_IntA, kDMA_IntB, kDMA_IntError }
	DMA interrupt flags. More...

enum	dma_trigger_type_t { kDMA_NoTrigger = 0, kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) \| DMA_CHANNEL_CFG_TRIGTYPE(1), kDMA_HighLevelTrigger, kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), kDMA_RisingEdgeTrigger, kDMA_NoTrigger = 0, kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) \| DMA_CHANNEL_CFG_TRIGTYPE(1), kDMA_HighLevelTrigger, kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), kDMA_RisingEdgeTrigger }
	DMA trigger type. More...

enum	_dma_burst_size { kDMA_BurstSize1 = 0U, kDMA_BurstSize2 = 1U, kDMA_BurstSize4 = 2U, kDMA_BurstSize8 = 3U, kDMA_BurstSize16 = 4U, kDMA_BurstSize32 = 5U, kDMA_BurstSize64 = 6U, kDMA_BurstSize128 = 7U, kDMA_BurstSize256 = 8U, kDMA_BurstSize512 = 9U, kDMA_BurstSize1024 = 10U }
	DMA burst size. More...

enum	dma_trigger_burst_t { kDMA_SingleTransfer = 0, kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer2, kDMA_EdgeBurstTransfer4, kDMA_EdgeBurstTransfer8, kDMA_EdgeBurstTransfer16, kDMA_EdgeBurstTransfer32, kDMA_EdgeBurstTransfer64, kDMA_EdgeBurstTransfer128, kDMA_EdgeBurstTransfer256, kDMA_EdgeBurstTransfer512, kDMA_EdgeBurstTransfer1024, kDMA_SingleTransfer = 0, kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), kDMA_EdgeBurstTransfer2, kDMA_EdgeBurstTransfer4, kDMA_EdgeBurstTransfer8, kDMA_EdgeBurstTransfer16, kDMA_EdgeBurstTransfer32, kDMA_EdgeBurstTransfer64, kDMA_EdgeBurstTransfer128, kDMA_EdgeBurstTransfer256, kDMA_EdgeBurstTransfer512, kDMA_EdgeBurstTransfer1024 }
	DMA trigger burst. More...

enum	dma_burst_wrap_t { kDMA_NoWrap = 0, kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), kDMA_SrcAndDstWrap, kDMA_NoWrap = 0, kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), kDMA_SrcAndDstWrap }
	DMA burst wrapping. More...

enum	dma_transfer_type_t { kDMA_MemoryToMemory = 0x0U, kDMA_PeripheralToMemory, kDMA_MemoryToPeripheral, kDMA_StaticToStatic, kDMA_MemoryToMemory = 0x0U, kDMA_PeripheralToMemory, kDMA_MemoryToPeripheral, kDMA_StaticToStatic }
	DMA transfer type. More...

Driver version
#define	FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
	DMA driver version. More...

DMA initialization and De-initialization
void	DMA_Init (DMA_Type *base)
	Initializes DMA peripheral. More...

void	DMA_Deinit (DMA_Type *base)
	Deinitializes DMA peripheral. More...

void	DMA_InstallDescriptorMemory (DMA_Type base, void addr)
	Install DMA descriptor memory. More...

DMA Channel Operation
static bool	DMA_ChannelIsActive (DMA_Type *base, uint32_t channel)
	Return whether DMA channel is processing transfer. More...

static bool	DMA_ChannelIsBusy (DMA_Type *base, uint32_t channel)
	Return whether DMA channel is busy. More...

static void	DMA_EnableChannelInterrupts (DMA_Type *base, uint32_t channel)
	Enables the interrupt source for the DMA transfer. More...

static void	DMA_DisableChannelInterrupts (DMA_Type *base, uint32_t channel)
	Disables the interrupt source for the DMA transfer. More...

static void	DMA_EnableChannel (DMA_Type *base, uint32_t channel)
	Enable DMA channel. More...

static void	DMA_DisableChannel (DMA_Type *base, uint32_t channel)
	Disable DMA channel. More...

static void	DMA_EnableChannelPeriphRq (DMA_Type *base, uint32_t channel)
	Set PERIPHREQEN of channel configuration register. More...

static void	DMA_DisableChannelPeriphRq (DMA_Type *base, uint32_t channel)
	Get PERIPHREQEN value of channel configuration register. More...

void	DMA_ConfigureChannelTrigger (DMA_Type base, uint32_t channel, dma_channel_trigger_t trigger)
	Set trigger settings of DMA channel. More...

void	DMA_SetChannelConfig (DMA_Type base, uint32_t channel, dma_channel_trigger_t trigger, bool isPeriph)
	set channel config. More...

uint32_t	DMA_GetRemainingBytes (DMA_Type *base, uint32_t channel)
	Gets the remaining bytes of the current DMA descriptor transfer. More...

static void	DMA_SetChannelPriority (DMA_Type *base, uint32_t channel, dma_priority_t priority)
	Set priority of channel configuration register. More...

static dma_priority_t	DMA_GetChannelPriority (DMA_Type *base, uint32_t channel)
	Get priority of channel configuration register. More...

static void	DMA_SetChannelConfigValid (DMA_Type *base, uint32_t channel)
	Set channel configuration valid. More...

static void	DMA_DoChannelSoftwareTrigger (DMA_Type *base, uint32_t channel)
	Do software trigger for the channel. More...

static void	DMA_LoadChannelTransferConfig (DMA_Type *base, uint32_t channel, uint32_t xfer)
	Load channel transfer configurations. More...

void	DMA_CreateDescriptor (dma_descriptor_t desc, dma_xfercfg_t xfercfg, void srcAddr, void dstAddr, void *nextDesc)
	Create application specific DMA descriptor to be used in a chain in transfer. More...

void	DMA_SetupDescriptor (dma_descriptor_t desc, uint32_t xfercfg, void srcStartAddr, void dstStartAddr, void nextDesc)
	setup dma descriptor More...

void	DMA_SetupChannelDescriptor (dma_descriptor_t desc, uint32_t xfercfg, void srcStartAddr, void dstStartAddr, void nextDesc, dma_burst_wrap_t wrapType, uint32_t burstSize)
	setup dma channel descriptor More...

void	DMA_LoadChannelDescriptor (DMA_Type base, uint32_t channel, dma_descriptor_t descriptor)
	load channel transfer decriptor. More...

DMA Transactional Operation
void	DMA_AbortTransfer (dma_handle_t *handle)
	Abort running transfer by handle. More...

void	DMA_CreateHandle (dma_handle_t handle, DMA_Type base, uint32_t channel)
	Creates the DMA handle. More...

void	DMA_SetCallback (dma_handle_t handle, dma_callback callback, void userData)
	Installs a callback function for the DMA transfer. More...

void	DMA_PrepareTransfer (dma_transfer_config_t config, void srcAddr, void dstAddr, uint32_t byteWidth, uint32_t transferBytes, dma_transfer_type_t type, void nextDesc)
	Prepares the DMA transfer structure. More...

void	DMA_PrepareChannelTransfer (dma_channel_config_t config, void srcStartAddr, void dstStartAddr, uint32_t xferCfg, dma_transfer_type_t type, dma_channel_trigger_t trigger, void *nextDesc)
	Prepare channel transfer configurations. More...

status_t	DMA_SubmitTransfer (dma_handle_t handle, dma_transfer_config_t config)
	Submits the DMA transfer request. More...

void	DMA_SubmitChannelTransferParameter (dma_handle_t handle, uint32_t xfercfg, void srcStartAddr, void dstStartAddr, void nextDesc)
	Submit channel transfer paramter directly. More...

void	DMA_SubmitChannelDescriptor (dma_handle_t handle, dma_descriptor_t descriptor)
	Submit channel descriptor. More...

status_t	DMA_SubmitChannelTransfer (dma_handle_t handle, dma_channel_config_t config)
	Submits the DMA channel transfer request. More...

void	DMA_StartTransfer (dma_handle_t *handle)
	DMA start transfer. More...

void	DMA_IRQHandle (DMA_Type *base)
	DMA IRQ handler for descriptor transfer complete. More...

Driver version
#define	FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
	DMA driver version. More...

Data Structure Documentation

struct dma_descriptor_t

Data Fields
volatile uint32_t	xfercfg
	Transfer configuration.

void *	srcEndAddr
	Last source address of DMA transfer.

void *	dstEndAddr
	Last destination address of DMA transfer.

void *	linkToNextDesc
	Address of next DMA descriptor in chain.

struct dma_xfercfg_t

Data Fields
bool	valid
	Descriptor is ready to transfer.

bool	reload
	Reload channel configuration register after current descriptor is exhausted.

bool	swtrig
	Perform software trigger. More...

bool	clrtrig
	Clear trigger.

bool	intA
	Raises IRQ when transfer is done and set IRQA status register flag.

bool	intB
	Raises IRQ when transfer is done and set IRQB status register flag.

uint8_t	byteWidth
	Byte width of data to transfer.

uint8_t	srcInc
	Increment source address by 'srcInc' x 'byteWidth'.

uint8_t	dstInc
	Increment destination address by 'dstInc' x 'byteWidth'.

uint16_t	transferCount
	Number of transfers.

Field Documentation

bool dma_xfercfg_t::swtrig

Transfer if fired when 'valid' is set

struct dma_channel_trigger_t

Data Fields
dma_trigger_type_t	type
	Select hardware trigger as edge triggered or level triggered. More...

dma_trigger_burst_t	burst
	Select whether hardware triggers cause a single or burst transfer. More...

dma_burst_wrap_t	wrap
	Select wrap type, source wrap or dest wrap, or both. More...

Field Documentation

dma_trigger_type_t dma_channel_trigger_t::type

dma_trigger_burst_t dma_channel_trigger_t::burst

dma_burst_wrap_t dma_channel_trigger_t::wrap

struct dma_channel_config_t

Data Fields
void *	srcStartAddr
	Source data address.

void *	dstStartAddr
	Destination data address.

void *	nextDesc
	Chain custom descriptor.

uint32_t	xferCfg
	channel transfer configurations

dma_channel_trigger_t *	trigger
	DMA trigger type.

bool	isPeriph
	select the request type

struct dma_transfer_config_t

Data Fields
uint8_t *	srcAddr
	Source data address.

uint8_t *	dstAddr
	Destination data address.

uint8_t *	nextDesc
	Chain custom descriptor.

dma_xfercfg_t	xfercfg
	Transfer options.

bool	isPeriph
	DMA transfer is driven by peripheral.

struct dma_handle_t

Data Fields
dma_callback	callback
	Callback function. More...

void *	userData
	Callback function parameter.

DMA_Type *	base
	DMA peripheral base address.

uint8_t	channel
	DMA channel number.

Field Documentation

dma_callback dma_handle_t::callback

Invoked when transfer of descriptor with interrupt flag finishes

Macro Definition Documentation

#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))

Version 2.4.0.

#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)

DMA head link descriptor table align size

#define DMA_ALLOCATE_HEAD_DESCRIPTORS	(	name,
		number
	)	SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE	(	name,
		number
	)	AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_LINK_DESCRIPTORS	(	name,
		number
	)	SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE	(	name,
		number
	)	AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_DESCRIPTOR_END_ADDRESS	(	start,
		inc,
		bytes,
		width
	)	((uint32_t )((uint32_t)(start) + (inc) (bytes) - (inc) * (width)))

Parameters

start,start	address
inc,address	interleave size
bytes,transfer	bytes
width,transfer	width

#define DMA_CHANNEL_XFER	(	reload,
		clrTrig,
		intA,
		intB,
		width,
		srcInc,
		dstInc,
		bytes
	)

Value:

DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \
        DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) |                                     \
        DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) |                                             \
        DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) |   \
        DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) |   \
        DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL)

Parameters

reload,true	is reload link descriptor after current exhaust, false is not
clrTrig,true	is clear trigger status, wait software trigger, false is not
intA,enable	interruptA
intB,enable	interruptB
width,transfer	width
srcInc,source	address interleave size
dstInc,destination	address interleave size
bytes,transfer	bytes

#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))

Version 2.4.0.

#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)

DMA head link descriptor table align size

#define DMA_ALLOCATE_HEAD_DESCRIPTORS	(	name,
		number
	)	SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE	(	name,
		number
	)	AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_LINK_DESCRIPTORS	(	name,
		number
	)	SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE	(	name,
		number
	)	AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)

Parameters

name,allocate	decriptor name.
number,number	of descriptor to be allocated.

#define DMA_DESCRIPTOR_END_ADDRESS	(	start,
		inc,
		bytes,
		width
	)	((void )((uint32_t)(start) + inc bytes - inc * width))

Parameters

start,start	address
inc,address	interleave size
bytes,transfer	bytes
width,transfer	width

#define DMA_CHANNEL_XFER	(	reload,
		clrTrig,
		intA,
		intB,
		width,
		srcInc,
		dstInc,
		bytes
	)

Value:

DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \
        DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) |                                     \
        DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) |                                                   \
        DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) |                                           \
        DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (dstInc - 1) : dstInc) |                                           \
        DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1)

Parameters

reload,true	is reload link descriptor after current exhaust, false is not
clrTrig,true	is clear trigger status, wait software trigger, false is not
intA,enable	interruptA
intB,enable	interruptB
width,transfer	width
srcInc,source	address interleave size
dstInc,destination	address interleave size
bytes,transfer	bytes

Typedef Documentation

typedef void(* dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode)

Enumeration Type Documentation

anonymous enum

Enumerator
kStatus_DMA_Busy	Channel is busy and can't handle the transfer request.

anonymous enum

Enumerator
kDMA_AddressInterleave0xWidth	dma source/destination address no interleave
kDMA_AddressInterleave1xWidth	dma source/destination address interleave 1xwidth
kDMA_AddressInterleave2xWidth	dma source/destination address interleave 2xwidth
kDMA_AddressInterleave4xWidth	dma source/destination address interleave 3xwidth

anonymous enum

Enumerator
kDMA_Transfer8BitWidth	dma channel transfer bit width is 8 bit
kDMA_Transfer16BitWidth	dma channel transfer bit width is 16 bit
kDMA_Transfer32BitWidth	dma channel transfer bit width is 32 bit

enum dma_priority_t

Enumerator
kDMA_ChannelPriority0	Highest channel priority - priority 0.
kDMA_ChannelPriority1	Channel priority 1.
kDMA_ChannelPriority2	Channel priority 2.
kDMA_ChannelPriority3	Channel priority 3.
kDMA_ChannelPriority4	Channel priority 4.
kDMA_ChannelPriority5	Channel priority 5.
kDMA_ChannelPriority6	Channel priority 6.
kDMA_ChannelPriority7	Lowest channel priority - priority 7.
kDMA_ChannelPriority0	Highest channel priority - priority 0.
kDMA_ChannelPriority1	Channel priority 1.
kDMA_ChannelPriority2	Channel priority 2.
kDMA_ChannelPriority3	Channel priority 3.
kDMA_ChannelPriority4	Channel priority 4.
kDMA_ChannelPriority5	Channel priority 5.
kDMA_ChannelPriority6	Channel priority 6.
kDMA_ChannelPriority7	Lowest channel priority - priority 7.

enum dma_irq_t

Enumerator
kDMA_IntA	DMA interrupt flag A.
kDMA_IntB	DMA interrupt flag B.
kDMA_IntError	DMA interrupt flag error.
kDMA_IntA	DMA interrupt flag A.
kDMA_IntB	DMA interrupt flag B.
kDMA_IntError	DMA interrupt flag error.

enum dma_trigger_type_t

Enumerator
kDMA_NoTrigger	Trigger is disabled.
kDMA_LowLevelTrigger	Low level active trigger.
kDMA_HighLevelTrigger	High level active trigger.
kDMA_FallingEdgeTrigger	Falling edge active trigger.
kDMA_RisingEdgeTrigger	Rising edge active trigger.
kDMA_NoTrigger	Trigger is disabled.
kDMA_LowLevelTrigger	Low level active trigger.
kDMA_HighLevelTrigger	High level active trigger.
kDMA_FallingEdgeTrigger	Falling edge active trigger.
kDMA_RisingEdgeTrigger	Rising edge active trigger.

anonymous enum

Enumerator
kDMA_BurstSize1	burst size 1 transfer
kDMA_BurstSize2	burst size 2 transfer
kDMA_BurstSize4	burst size 4 transfer
kDMA_BurstSize8	burst size 8 transfer
kDMA_BurstSize16	burst size 16 transfer
kDMA_BurstSize32	burst size 32 transfer
kDMA_BurstSize64	burst size 64 transfer
kDMA_BurstSize128	burst size 128 transfer
kDMA_BurstSize256	burst size 256 transfer
kDMA_BurstSize512	burst size 512 transfer
kDMA_BurstSize1024	burst size 1024 transfer

enum dma_trigger_burst_t

Enumerator
kDMA_SingleTransfer	Single transfer.
kDMA_LevelBurstTransfer	Burst transfer driven by level trigger.
kDMA_EdgeBurstTransfer1	Perform 1 transfer by edge trigger.
kDMA_EdgeBurstTransfer2	Perform 2 transfers by edge trigger.
kDMA_EdgeBurstTransfer4	Perform 4 transfers by edge trigger.
kDMA_EdgeBurstTransfer8	Perform 8 transfers by edge trigger.
kDMA_EdgeBurstTransfer16	Perform 16 transfers by edge trigger.
kDMA_EdgeBurstTransfer32	Perform 32 transfers by edge trigger.
kDMA_EdgeBurstTransfer64	Perform 64 transfers by edge trigger.
kDMA_EdgeBurstTransfer128	Perform 128 transfers by edge trigger.
kDMA_EdgeBurstTransfer256	Perform 256 transfers by edge trigger.
kDMA_EdgeBurstTransfer512	Perform 512 transfers by edge trigger.
kDMA_EdgeBurstTransfer1024	Perform 1024 transfers by edge trigger.
kDMA_SingleTransfer	Single transfer.
kDMA_LevelBurstTransfer	Burst transfer driven by level trigger.
kDMA_EdgeBurstTransfer1	Perform 1 transfer by edge trigger.
kDMA_EdgeBurstTransfer2	Perform 2 transfers by edge trigger.
kDMA_EdgeBurstTransfer4	Perform 4 transfers by edge trigger.
kDMA_EdgeBurstTransfer8	Perform 8 transfers by edge trigger.
kDMA_EdgeBurstTransfer16	Perform 16 transfers by edge trigger.
kDMA_EdgeBurstTransfer32	Perform 32 transfers by edge trigger.
kDMA_EdgeBurstTransfer64	Perform 64 transfers by edge trigger.
kDMA_EdgeBurstTransfer128	Perform 128 transfers by edge trigger.
kDMA_EdgeBurstTransfer256	Perform 256 transfers by edge trigger.
kDMA_EdgeBurstTransfer512	Perform 512 transfers by edge trigger.
kDMA_EdgeBurstTransfer1024	Perform 1024 transfers by edge trigger.

enum dma_burst_wrap_t

Enumerator
kDMA_NoWrap	Wrapping is disabled.
kDMA_SrcWrap	Wrapping is enabled for source.
kDMA_DstWrap	Wrapping is enabled for destination.
kDMA_SrcAndDstWrap	Wrapping is enabled for source and destination.
kDMA_NoWrap	Wrapping is disabled.
kDMA_SrcWrap	Wrapping is enabled for source.
kDMA_DstWrap	Wrapping is enabled for destination.
kDMA_SrcAndDstWrap	Wrapping is enabled for source and destination.

enum dma_transfer_type_t

Enumerator
kDMA_MemoryToMemory	Transfer from memory to memory (increment source and destination)
kDMA_PeripheralToMemory	Transfer from peripheral to memory (increment only destination)
kDMA_MemoryToPeripheral	Transfer from memory to peripheral (increment only source)
kDMA_StaticToStatic	Peripheral to static memory (do not increment source or destination)
kDMA_MemoryToMemory	Transfer from memory to memory (increment source and destination)
kDMA_PeripheralToMemory	Transfer from peripheral to memory (increment only destination)
kDMA_MemoryToPeripheral	Transfer from memory to peripheral (increment only source)
kDMA_StaticToStatic	Peripheral to static memory (do not increment source or destination)

enum _dma_transfer_status

Enumerator
kStatus_DMA_Busy	Channel is busy and can't handle the transfer request.

enum _dma_addr_interleave_size

Enumerator
kDMA_AddressInterleave0xWidth	dma source/destination address no interleave
kDMA_AddressInterleave1xWidth	dma source/destination address interleave 1xwidth
kDMA_AddressInterleave2xWidth	dma source/destination address interleave 2xwidth
kDMA_AddressInterleave4xWidth	dma source/destination address interleave 3xwidth

enum _dma_transfer_width

Enumerator
kDMA_Transfer8BitWidth	dma channel transfer bit width is 8 bit
kDMA_Transfer16BitWidth	dma channel transfer bit width is 16 bit
kDMA_Transfer32BitWidth	dma channel transfer bit width is 32 bit

enum dma_priority_t

Enumerator
kDMA_ChannelPriority0	Highest channel priority - priority 0.
kDMA_ChannelPriority1	Channel priority 1.
kDMA_ChannelPriority2	Channel priority 2.
kDMA_ChannelPriority3	Channel priority 3.
kDMA_ChannelPriority4	Channel priority 4.
kDMA_ChannelPriority5	Channel priority 5.
kDMA_ChannelPriority6	Channel priority 6.
kDMA_ChannelPriority7	Lowest channel priority - priority 7.
kDMA_ChannelPriority0	Highest channel priority - priority 0.
kDMA_ChannelPriority1	Channel priority 1.
kDMA_ChannelPriority2	Channel priority 2.
kDMA_ChannelPriority3	Channel priority 3.
kDMA_ChannelPriority4	Channel priority 4.
kDMA_ChannelPriority5	Channel priority 5.
kDMA_ChannelPriority6	Channel priority 6.
kDMA_ChannelPriority7	Lowest channel priority - priority 7.

enum dma_irq_t

Enumerator
kDMA_IntA	DMA interrupt flag A.
kDMA_IntB	DMA interrupt flag B.
kDMA_IntError	DMA interrupt flag error.
kDMA_IntA	DMA interrupt flag A.
kDMA_IntB	DMA interrupt flag B.
kDMA_IntError	DMA interrupt flag error.

enum dma_trigger_type_t

Enumerator
kDMA_NoTrigger	Trigger is disabled.
kDMA_LowLevelTrigger	Low level active trigger.
kDMA_HighLevelTrigger	High level active trigger.
kDMA_FallingEdgeTrigger	Falling edge active trigger.
kDMA_RisingEdgeTrigger	Rising edge active trigger.
kDMA_NoTrigger	Trigger is disabled.
kDMA_LowLevelTrigger	Low level active trigger.
kDMA_HighLevelTrigger	High level active trigger.
kDMA_FallingEdgeTrigger	Falling edge active trigger.
kDMA_RisingEdgeTrigger	Rising edge active trigger.

enum _dma_burst_size

Enumerator
kDMA_BurstSize1	burst size 1 transfer
kDMA_BurstSize2	burst size 2 transfer
kDMA_BurstSize4	burst size 4 transfer
kDMA_BurstSize8	burst size 8 transfer
kDMA_BurstSize16	burst size 16 transfer
kDMA_BurstSize32	burst size 32 transfer
kDMA_BurstSize64	burst size 64 transfer
kDMA_BurstSize128	burst size 128 transfer
kDMA_BurstSize256	burst size 256 transfer
kDMA_BurstSize512	burst size 512 transfer
kDMA_BurstSize1024	burst size 1024 transfer

enum dma_trigger_burst_t

Enumerator
kDMA_SingleTransfer	Single transfer.
kDMA_LevelBurstTransfer	Burst transfer driven by level trigger.
kDMA_EdgeBurstTransfer1	Perform 1 transfer by edge trigger.
kDMA_EdgeBurstTransfer2	Perform 2 transfers by edge trigger.
kDMA_EdgeBurstTransfer4	Perform 4 transfers by edge trigger.
kDMA_EdgeBurstTransfer8	Perform 8 transfers by edge trigger.
kDMA_EdgeBurstTransfer16	Perform 16 transfers by edge trigger.
kDMA_EdgeBurstTransfer32	Perform 32 transfers by edge trigger.
kDMA_EdgeBurstTransfer64	Perform 64 transfers by edge trigger.
kDMA_EdgeBurstTransfer128	Perform 128 transfers by edge trigger.
kDMA_EdgeBurstTransfer256	Perform 256 transfers by edge trigger.
kDMA_EdgeBurstTransfer512	Perform 512 transfers by edge trigger.
kDMA_EdgeBurstTransfer1024	Perform 1024 transfers by edge trigger.
kDMA_SingleTransfer	Single transfer.
kDMA_LevelBurstTransfer	Burst transfer driven by level trigger.
kDMA_EdgeBurstTransfer1	Perform 1 transfer by edge trigger.
kDMA_EdgeBurstTransfer2	Perform 2 transfers by edge trigger.
kDMA_EdgeBurstTransfer4	Perform 4 transfers by edge trigger.
kDMA_EdgeBurstTransfer8	Perform 8 transfers by edge trigger.
kDMA_EdgeBurstTransfer16	Perform 16 transfers by edge trigger.
kDMA_EdgeBurstTransfer32	Perform 32 transfers by edge trigger.
kDMA_EdgeBurstTransfer64	Perform 64 transfers by edge trigger.
kDMA_EdgeBurstTransfer128	Perform 128 transfers by edge trigger.
kDMA_EdgeBurstTransfer256	Perform 256 transfers by edge trigger.
kDMA_EdgeBurstTransfer512	Perform 512 transfers by edge trigger.
kDMA_EdgeBurstTransfer1024	Perform 1024 transfers by edge trigger.

enum dma_burst_wrap_t

Enumerator
kDMA_NoWrap	Wrapping is disabled.
kDMA_SrcWrap	Wrapping is enabled for source.
kDMA_DstWrap	Wrapping is enabled for destination.
kDMA_SrcAndDstWrap	Wrapping is enabled for source and destination.
kDMA_NoWrap	Wrapping is disabled.
kDMA_SrcWrap	Wrapping is enabled for source.
kDMA_DstWrap	Wrapping is enabled for destination.
kDMA_SrcAndDstWrap	Wrapping is enabled for source and destination.

enum dma_transfer_type_t

Enumerator
kDMA_MemoryToMemory	Transfer from memory to memory (increment source and destination)
kDMA_PeripheralToMemory	Transfer from peripheral to memory (increment only destination)
kDMA_MemoryToPeripheral	Transfer from memory to peripheral (increment only source)
kDMA_StaticToStatic	Peripheral to static memory (do not increment source or destination)
kDMA_MemoryToMemory	Transfer from memory to memory (increment source and destination)
kDMA_PeripheralToMemory	Transfer from peripheral to memory (increment only destination)
kDMA_MemoryToPeripheral	Transfer from memory to peripheral (increment only source)
kDMA_StaticToStatic	Peripheral to static memory (do not increment source or destination)

Function Documentation

void DMA_Init ( DMA_Type * base )

This function enable the DMA clock, set descriptor table and enable DMA peripheral.

Parameters

base	DMA peripheral base address.

void DMA_Deinit ( DMA_Type * base )

This function gates the DMA clock.

Parameters

base	DMA peripheral base address.

void DMA_InstallDescriptorMemory	(	DMA_Type *	base,
		void *	addr
	)

This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.

Parameters

base	DMA base address.
addr	DMA descriptor address

static bool DMA_ChannelIsActive	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

Returns: True for active state, false otherwise.

static bool DMA_ChannelIsBusy	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

Returns: True for busy state, false otherwise.

static void DMA_EnableChannelInterrupts	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_DisableChannelInterrupts	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_EnableChannel	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_DisableChannel	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_EnableChannelPeriphRq	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_DisableChannelPeriphRq	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

Returns: True for enabled PeriphRq, false for disabled.

void DMA_ConfigureChannelTrigger	(	DMA_Type *	base,
		uint32_t	channel,
		dma_channel_trigger_t *	trigger
	)

Parameters

base	DMA peripheral base address.
channel	DMA channel number.
trigger	trigger configuration.

Parameters

base	DMA peripheral base address.
channel	DMA channel number.
trigger	trigger configuration.

void DMA_SetChannelConfig	(	DMA_Type *	base,
		uint32_t	channel,
		dma_channel_trigger_t *	trigger,
		bool	isPeriph
	)

This function provide a interface to configure channel configuration reisters.

Parameters

base	DMA base address.
channel	DMA channel number.
trigger	channel configurations structure.
isPeriph	true is periph request, false is not.

uint32_t DMA_GetRemainingBytes	(	DMA_Type *	base,
		uint32_t	channel
	)

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

Returns: The number of bytes which have not been transferred yet.

static void DMA_SetChannelPriority	(	DMA_Type *	base,
		uint32_t	channel,
		dma_priority_t	priority
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.
priority	Channel priority value.

static dma_priority_t DMA_GetChannelPriority	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

Returns: Channel priority value.

static void DMA_SetChannelConfigValid	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_DoChannelSoftwareTrigger	(	DMA_Type *	base,
		uint32_t	channel
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.

static void DMA_LoadChannelTransferConfig	(	DMA_Type *	base,
		uint32_t	channel,
		uint32_t	xfer
	)

inlinestatic

Parameters

base	DMA peripheral base address.
channel	DMA channel number.
xfer	transfer configurations.

void DMA_CreateDescriptor	(	dma_descriptor_t *	desc,
		dma_xfercfg_t *	xfercfg,
		void *	srcAddr,
		void *	dstAddr,
		void *	nextDesc
	)

Parameters

desc	DMA descriptor address.
xfercfg	Transfer configuration for DMA descriptor.
srcAddr	Address of last item to transmit
dstAddr	Address of last item to receive.
nextDesc	Address of next descriptor in chain.
desc	DMA descriptor address.
xfercfg	Transfer configuration for DMA descriptor.
srcAddr	Address of last item to transmit
dstAddr	Address of last item to receive.
nextDesc	Address of next descriptor in chain.

void DMA_SetupDescriptor	(	dma_descriptor_t *	desc,
		uint32_t	xfercfg,
		void *	srcStartAddr,
		void *	dstStartAddr,
		void *	nextDesc
	)

Note: This function do not support configure wrap descriptor.

Parameters

desc	DMA descriptor address.
xfercfg	Transfer configuration for DMA descriptor.
srcStartAddr	Start address of source address.
dstStartAddr	Start address of destination address.
nextDesc	Address of next descriptor in chain.

void DMA_SetupChannelDescriptor	(	dma_descriptor_t *	desc,
		uint32_t	xfercfg,
		void *	srcStartAddr,
		void *	dstStartAddr,
		void *	nextDesc,
		dma_burst_wrap_t	wrapType,
		uint32_t	burstSize
	)

Note: This function support configure wrap descriptor.

Parameters

desc	DMA descriptor address.
xfercfg	Transfer configuration for DMA descriptor.
srcStartAddr	Start address of source address.
dstStartAddr	Start address of destination address.
nextDesc	Address of next descriptor in chain.
wrapType	burst wrap type.
burstSize	burst size, reference _dma_burst_size.

void DMA_LoadChannelDescriptor	(	DMA_Type *	base,
		uint32_t	channel,
		dma_descriptor_t *	descriptor
	)

This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, it is useful for the case:

for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly and then call this api to load the configured descriptor to driver descriptor table.
* DMA_Init(DMA0);

* DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL);

* DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL);

* DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc);

* DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL);

* while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL))

* {}

*

Parameters

base	DMA base address.
channel	DMA channel.
descriptor	configured DMA descriptor.

void DMA_AbortTransfer ( dma_handle_t * handle )

This function aborts DMA transfer specified by handle.

Parameters

handle DMA handle pointer.

void DMA_CreateHandle	(	dma_handle_t *	handle,
		DMA_Type *	base,
		uint32_t	channel
	)

This function is called if using transaction API for DMA. This function initializes the internal state of DMA handle.

Parameters

handle	DMA handle pointer. The DMA handle stores callback function and parameters.
base	DMA peripheral base address.
channel	DMA channel number.

void DMA_SetCallback	(	dma_handle_t *	handle,
		dma_callback	callback,
		void *	userData
	)

This callback is called in DMA IRQ handler. Use the callback to do something after the current major loop transfer completes.

Parameters

handle	DMA handle pointer.
callback	DMA callback function pointer.
userData	Parameter for callback function.

void DMA_PrepareTransfer	(	dma_transfer_config_t *	config,
		void *	srcAddr,
		void *	dstAddr,
		uint32_t	byteWidth,
		uint32_t	transferBytes,
		dma_transfer_type_t	type,
		void *	nextDesc
	)

Parameters

config	The user configuration structure of type dma_transfer_t.
srcAddr	DMA transfer source address.
dstAddr	DMA transfer destination address.
byteWidth	DMA transfer destination address width(bytes).
transferBytes	DMA transfer bytes to be transferred.
type	DMA transfer type.
nextDesc	Chain custom descriptor to transfer.

Note: The data address and the data width must be consistent. For example, if the SRC is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in source address error(SAE).

Parameters

config	The user configuration structure of type dma_transfer_t.
srcAddr	DMA transfer source address.
dstAddr	DMA transfer destination address.
byteWidth	DMA transfer destination address width(bytes).
transferBytes	DMA transfer bytes to be transferred.
type	DMA transfer type.
nextDesc	Chain custom descriptor to transfer.

Note: The data address and the data width must be consistent. For example, if the SRC is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in source address error(SAE).

void DMA_PrepareChannelTransfer	(	dma_channel_config_t *	config,
		void *	srcStartAddr,
		void *	dstStartAddr,
		uint32_t	xferCfg,
		dma_transfer_type_t	type,
		dma_channel_trigger_t *	trigger,
		void *	nextDesc
	)

This function used to prepare channel transfer configurations.

Parameters

config	Pointer to DMA channel transfer configuration structure.
srcStartAddr	source start address.
dstStartAddr	destination start address.
xferCfg	xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
type	transfer type.
trigger	DMA channel trigger configurations.
nextDesc	address of next descriptor.

status_t DMA_SubmitTransfer	(	dma_handle_t *	handle,
		dma_transfer_config_t *	config
	)

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time.

Parameters

handle	DMA handle pointer.
config	Pointer to DMA transfer configuration structure.

Return values

kStatus_DMA_Success	It means submit transfer request succeed.
kStatus_DMA_QueueFull	It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy	It means the given channel is busy, need to submit request later.

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time.

Parameters

handle	DMA handle pointer.
config	Pointer to DMA transfer configuration structure.

Return values

kStatus_DMA_Success	It means submit transfer request succeed.
kStatus_DMA_QueueFull	It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy	It means the given channel is busy, need to submit request later.

void DMA_SubmitChannelTransferParameter	(	dma_handle_t *	handle,
		uint32_t	xfercfg,
		void *	srcStartAddr,
		void *	dstStartAddr,
		void *	nextDesc
	)

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, it is useful for the case:

for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used for it.
DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,

bytes), srcStartAddr, dstStartAddr, NULL);

DMA_StartTransfer(handle)

*
for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc2);

DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, NULL);

DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,

bytes), srcStartAddr, dstStartAddr, nextDesc0);

DMA_StartTransfer(handle);

*

Parameters

handle	Pointer to DMA handle.
xferCfg	xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
srcStartAddr	source start address.
dstStartAddr	destination start address.
nextDesc	address of next descriptor.

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, it is useful for the case:

for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used for it.
DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,

bytes), srcStartAddr, dstStartAddr, NULL);

DMA_StartTransfer(handle)

*
for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
//define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc2);

DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, NULL);

DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,

bytes), srcStartAddr, dstStartAddr, nextDesc0);

DMA_StartTransfer(handle);

*

Parameters

handle	Pointer to DMA handle.
xferCfg	xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
srcStartAddr	source start address.
dstStartAddr	destination start address.
nextDesc	address of next descriptor.

void DMA_SubmitChannelDescriptor	(	dma_handle_t *	handle,
		dma_descriptor_t *	descriptor
	)

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, this functiono is typical for the ping pong case:

for the ping pong case, application should responsible for the descriptor, for example, application should prepare two descriptor table with macro.
define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc0);

DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelDescriptor(handle, nextDesc0);

DMA_StartTransfer(handle);

*

Parameters

handle	Pointer to DMA handle.
descriptor	descriptor to submit.

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, this functiono is typical for the ping pong case:

for the ping pong case, application should responsible for the descriptor, for example, application should prepare two descriptor table with macro.
//define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc0);

DMA_SetChannelConfig(base, channel, trigger, isPeriph);

DMA_CreateHandle(handle, base, channel)

DMA_SubmitChannelDescriptor(handle, nextDesc0);

DMA_StartTransfer(handle);

*

Parameters

handle	Pointer to DMA handle.
descriptor	descriptor to submit.

status_t DMA_SubmitChannelTransfer	(	dma_handle_t *	handle,
		dma_channel_config_t *	config
	)

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time. It is used for the case:

for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used for it.
DMA_CreateHandle(handle, base, channel)

DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL);

DMA_SubmitChannelTransfer(handle, config)

DMA_StartTransfer(handle)

*
for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc2);

DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, NULL);

DMA_CreateHandle(handle, base, channel)

DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);

DMA_SubmitChannelTransfer(handle, config)

DMA_StartTransfer(handle)

*

for the ping pong case, application should responsible for link descriptor, for example, application should prepare two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.

   define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc0);
   DMA_CreateHandle(handle, base, channel)
   DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);
   DMA_SubmitChannelTransfer(handle, config)
   DMA_StartTransfer(handle)
* 

Parameters

handle	DMA handle pointer.
config	Pointer to DMA transfer configuration structure.

Return values

kStatus_DMA_Success	It means submit transfer request succeed.
kStatus_DMA_QueueFull	It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy	It means the given channel is busy, need to submit request later.

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time. It is used for the case:

for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used for it.
DMA_CreateHandle(handle, base, channel)

DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL);

DMA_SubmitChannelTransfer(handle, config)

DMA_StartTransfer(handle)

*
for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
//define link descriptor table in application with macro

DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);

DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc1);

DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, nextDesc2);

DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

srcStartAddr, dstStartAddr, NULL);

DMA_CreateHandle(handle, base, channel)

DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);

DMA_SubmitChannelTransfer(handle, config)

DMA_StartTransfer(handle)

*

for the ping pong case, application should responsible for link descriptor, for example, application should prepare two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.

   //define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc0);
   DMA_CreateHandle(handle, base, channel)
   DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);
   DMA_SubmitChannelTransfer(handle, config)
   DMA_StartTransfer(handle)
* 

Parameters

handle	DMA handle pointer.
config	Pointer to DMA transfer configuration structure.

Return values

kStatus_DMA_Success	It means submit transfer request succeed.
kStatus_DMA_QueueFull	It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy	It means the given channel is busy, need to submit request later.

void DMA_StartTransfer ( dma_handle_t * handle )

This function enables the channel request. User can call this function after submitting the transfer request It will trigger transfer start with software trigger only when hardware trigger is not used.

Parameters

handle DMA handle pointer.

void DMA_IRQHandle ( DMA_Type * base )

This function clears the channel major interrupt flag and call the callback function if it is not NULL.

Parameters

base	DMA base address.

Overview

Typical use case

DMA Operation

Files

Data Structures

Macros

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Enumerations

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DMA initialization and De-initialization

DMA Channel Operation

DMA Transactional Operation

Driver version

Data Structure Documentation

Data Fields

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Field Documentation

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Data Fields

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Field Documentation

Macro Definition Documentation

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Function Documentation