Overview

This section describes the programming interface of the SPI DMA driver.

Files
file	fsl_spi.h

file	fsl_spi.h

Data Structures
struct	spi_delay_config_t
	SPI delay time configure structure. More...

struct	spi_master_config_t
	SPI master user configure structure. More...

struct	spi_slave_config_t
	SPI slave user configure structure. More...

struct	spi_transfer_t
	SPI transfer structure. More...

struct	spi_half_duplex_transfer_t
	SPI half-duplex(master only) transfer structure. More...

struct	spi_config_t
	Internal configuration structure used in 'spi' and 'spi_dma' driver. More...

struct	spi_master_handle_t
	SPI transfer handle structure. More...

Macros
#define	SPI_DUMMYDATA (0xFFU)
	SPI dummy transfer data, the data is sent while txBuff is NULL. More...

#define	SPI_DUMMYDATA (0xFFU)
	SPI dummy transfer data, the data is sent while txBuff is NULL. More...

Typedefs
typedef spi_master_handle_t	spi_slave_handle_t
	Slave handle type.

typedef void(*	spi_master_callback_t )(SPI_Type base, spi_master_handle_t handle, status_t status, void *userData)
	SPI master callback for finished transmit.

typedef void(*	spi_slave_callback_t )(SPI_Type base, spi_slave_handle_t handle, status_t status, void *userData)
	SPI slave callback for finished transmit.

typedef void(*	flexcomm_spi_master_irq_handler_t )(SPI_Type base, spi_master_handle_t handle)
	Typedef for master interrupt handler. More...

typedef void(*	flexcomm_spi_slave_irq_handler_t )(SPI_Type base, spi_slave_handle_t handle)
	Typedef for slave interrupt handler. More...

typedef spi_master_handle_t	spi_slave_handle_t
	Slave handle type.

typedef void(*	spi_master_callback_t )(SPI_Type base, spi_master_handle_t handle, status_t status, void *userData)
	SPI master callback for finished transmit.

typedef void(*	spi_slave_callback_t )(SPI_Type base, spi_slave_handle_t handle, status_t status, void *userData)
	SPI slave callback for finished transmit.

Enumerations
enum	spi_xfer_option_t { kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK) }
	SPI transfer option. More...

enum	spi_shift_direction_t { kSPI_MsbFirst = 0U, kSPI_LsbFirst = 1U, kSPI_MsbFirst = 0U, kSPI_LsbFirst = 1U }
	SPI data shifter direction options. More...

enum	spi_clock_polarity_t { kSPI_ClockPolarityActiveHigh = 0x0U, kSPI_ClockPolarityActiveLow, kSPI_ClockPolarityActiveHigh = 0x0U, kSPI_ClockPolarityActiveLow }
	SPI clock polarity configuration. More...

enum	spi_clock_phase_t { kSPI_ClockPhaseFirstEdge = 0x0U, kSPI_ClockPhaseSecondEdge, kSPI_ClockPhaseFirstEdge = 0x0U, kSPI_ClockPhaseSecondEdge }
	SPI clock phase configuration. More...

enum	spi_txfifo_watermark_t { kSPI_TxFifo0 = 0, kSPI_TxFifo1 = 1, kSPI_TxFifo2 = 2, kSPI_TxFifo3 = 3, kSPI_TxFifo4 = 4, kSPI_TxFifo5 = 5, kSPI_TxFifo6 = 6, kSPI_TxFifo7 = 7, kSPI_TxFifo0 = 0, kSPI_TxFifo1 = 1, kSPI_TxFifo2 = 2, kSPI_TxFifo3 = 3, kSPI_TxFifo4 = 4, kSPI_TxFifo5 = 5, kSPI_TxFifo6 = 6, kSPI_TxFifo7 = 7 }
	txFIFO watermark values More...

enum	spi_rxfifo_watermark_t { kSPI_RxFifo1 = 0, kSPI_RxFifo2 = 1, kSPI_RxFifo3 = 2, kSPI_RxFifo4 = 3, kSPI_RxFifo5 = 4, kSPI_RxFifo6 = 5, kSPI_RxFifo7 = 6, kSPI_RxFifo8 = 7, kSPI_RxFifo1 = 0, kSPI_RxFifo2 = 1, kSPI_RxFifo3 = 2, kSPI_RxFifo4 = 3, kSPI_RxFifo5 = 4, kSPI_RxFifo6 = 5, kSPI_RxFifo7 = 6, kSPI_RxFifo8 = 7 }
	rxFIFO watermark values More...

enum	spi_data_width_t { kSPI_Data4Bits = 3, kSPI_Data5Bits = 4, kSPI_Data6Bits = 5, kSPI_Data7Bits = 6, kSPI_Data8Bits = 7, kSPI_Data9Bits = 8, kSPI_Data10Bits = 9, kSPI_Data11Bits = 10, kSPI_Data12Bits = 11, kSPI_Data13Bits = 12, kSPI_Data14Bits = 13, kSPI_Data15Bits = 14, kSPI_Data16Bits = 15, kSPI_Data4Bits = 3, kSPI_Data5Bits = 4, kSPI_Data6Bits = 5, kSPI_Data7Bits = 6, kSPI_Data8Bits = 7, kSPI_Data9Bits = 8, kSPI_Data10Bits = 9, kSPI_Data11Bits = 10, kSPI_Data12Bits = 11, kSPI_Data13Bits = 12, kSPI_Data14Bits = 13, kSPI_Data15Bits = 14, kSPI_Data16Bits = 15 }
	Transfer data width. More...

enum	spi_ssel_t { kSPI_Ssel0 = 0, kSPI_Ssel1 = 1, kSPI_Ssel2 = 2, kSPI_Ssel3 = 3, kSPI_Ssel0 = 0, kSPI_Ssel1 = 1, kSPI_Ssel2 = 2, kSPI_Ssel3 = 3 }
	Slave select. More...

enum	spi_spol_t
	ssel polarity

enum	{ kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), kStatus_SPI_BaudrateNotSupport }
	SPI transfer status. More...

enum	_spi_interrupt_enable { kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK }
	SPI interrupt sources. More...

enum	_spi_statusflags { kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK }
	SPI status flags. More...

enum	spi_xfer_option_t { kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK) }
	SPI transfer option. More...

enum	spi_shift_direction_t { kSPI_MsbFirst = 0U, kSPI_LsbFirst = 1U, kSPI_MsbFirst = 0U, kSPI_LsbFirst = 1U }
	SPI data shifter direction options. More...

enum	spi_clock_polarity_t { kSPI_ClockPolarityActiveHigh = 0x0U, kSPI_ClockPolarityActiveLow, kSPI_ClockPolarityActiveHigh = 0x0U, kSPI_ClockPolarityActiveLow }
	SPI clock polarity configuration. More...

enum	spi_clock_phase_t { kSPI_ClockPhaseFirstEdge = 0x0U, kSPI_ClockPhaseSecondEdge, kSPI_ClockPhaseFirstEdge = 0x0U, kSPI_ClockPhaseSecondEdge }
	SPI clock phase configuration. More...

enum	spi_txfifo_watermark_t { kSPI_TxFifo0 = 0, kSPI_TxFifo1 = 1, kSPI_TxFifo2 = 2, kSPI_TxFifo3 = 3, kSPI_TxFifo4 = 4, kSPI_TxFifo5 = 5, kSPI_TxFifo6 = 6, kSPI_TxFifo7 = 7, kSPI_TxFifo0 = 0, kSPI_TxFifo1 = 1, kSPI_TxFifo2 = 2, kSPI_TxFifo3 = 3, kSPI_TxFifo4 = 4, kSPI_TxFifo5 = 5, kSPI_TxFifo6 = 6, kSPI_TxFifo7 = 7 }
	txFIFO watermark values More...

enum	spi_rxfifo_watermark_t { kSPI_RxFifo1 = 0, kSPI_RxFifo2 = 1, kSPI_RxFifo3 = 2, kSPI_RxFifo4 = 3, kSPI_RxFifo5 = 4, kSPI_RxFifo6 = 5, kSPI_RxFifo7 = 6, kSPI_RxFifo8 = 7, kSPI_RxFifo1 = 0, kSPI_RxFifo2 = 1, kSPI_RxFifo3 = 2, kSPI_RxFifo4 = 3, kSPI_RxFifo5 = 4, kSPI_RxFifo6 = 5, kSPI_RxFifo7 = 6, kSPI_RxFifo8 = 7 }
	rxFIFO watermark values More...

enum	spi_data_width_t { kSPI_Data4Bits = 3, kSPI_Data5Bits = 4, kSPI_Data6Bits = 5, kSPI_Data7Bits = 6, kSPI_Data8Bits = 7, kSPI_Data9Bits = 8, kSPI_Data10Bits = 9, kSPI_Data11Bits = 10, kSPI_Data12Bits = 11, kSPI_Data13Bits = 12, kSPI_Data14Bits = 13, kSPI_Data15Bits = 14, kSPI_Data16Bits = 15, kSPI_Data4Bits = 3, kSPI_Data5Bits = 4, kSPI_Data6Bits = 5, kSPI_Data7Bits = 6, kSPI_Data8Bits = 7, kSPI_Data9Bits = 8, kSPI_Data10Bits = 9, kSPI_Data11Bits = 10, kSPI_Data12Bits = 11, kSPI_Data13Bits = 12, kSPI_Data14Bits = 13, kSPI_Data15Bits = 14, kSPI_Data16Bits = 15 }
	Transfer data width. More...

enum	spi_ssel_t { kSPI_Ssel0 = 0, kSPI_Ssel1 = 1, kSPI_Ssel2 = 2, kSPI_Ssel3 = 3, kSPI_Ssel0 = 0, kSPI_Ssel1 = 1, kSPI_Ssel2 = 2, kSPI_Ssel3 = 3 }
	Slave select. More...

enum	spi_spol_t
	ssel polarity

enum	_spi_status { kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), kStatus_SPI_BaudrateNotSupport }
	SPI transfer status. More...

enum	_spi_interrupt_enable { kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK }
	SPI interrupt sources. More...

enum	_spi_statusflags { kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK }
	SPI status flags. More...

Functions
uint32_t	SPI_GetInstance (SPI_Type *base)
	Returns instance number for SPI peripheral base address. More...

Variables
volatile uint8_t	s_dummyData []
	Global variable for dummy data value setting. More...

volatile uint8_t	s_dummyData []
	Global variable for dummy data value setting. More...

Driver version
#define	FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
	SPI driver version 2.1.0. More...

Driver version
#define	FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
	SPI driver version 2.0.5. More...

Initialization and deinitialization
void	SPI_MasterGetDefaultConfig (spi_master_config_t *config)
	Sets the SPI master configuration structure to default values. More...

status_t	SPI_MasterInit (SPI_Type base, const spi_master_config_t config, uint32_t srcClock_Hz)
	Initializes the SPI with master configuration. More...

void	SPI_SlaveGetDefaultConfig (spi_slave_config_t *config)
	Sets the SPI slave configuration structure to default values. More...

status_t	SPI_SlaveInit (SPI_Type base, const spi_slave_config_t config)
	Initializes the SPI with slave configuration. More...

void	SPI_Deinit (SPI_Type *base)
	De-initializes the SPI. More...

static void	SPI_Enable (SPI_Type *base, bool enable)
	Enable or disable the SPI Master or Slave. More...

Status
static uint32_t	SPI_GetStatusFlags (SPI_Type *base)
	Gets the status flag. More...

Interrupts
static void	SPI_EnableInterrupts (SPI_Type *base, uint32_t irqs)
	Enables the interrupt for the SPI. More...

static void	SPI_DisableInterrupts (SPI_Type *base, uint32_t irqs)
	Disables the interrupt for the SPI. More...

DMA Control
void	SPI_EnableTxDMA (SPI_Type *base, bool enable)
	Enables the DMA request from SPI txFIFO. More...

void	SPI_EnableRxDMA (SPI_Type *base, bool enable)
	Enables the DMA request from SPI rxFIFO. More...

Bus Operations
void *	SPI_GetConfig (SPI_Type *base)
	Returns the configurations. More...

status_t	SPI_MasterSetBaud (SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
	Sets the baud rate for SPI transfer. More...

void	SPI_WriteData (SPI_Type *base, uint16_t data, uint32_t configFlags)
	Writes a data into the SPI data register. More...

static uint32_t	SPI_ReadData (SPI_Type *base)
	Gets a data from the SPI data register. More...

static void	SPI_SetTransferDelay (SPI_Type base, const spi_delay_config_t config)
	Set delay time for transfer. More...

void	SPI_SetDummyData (SPI_Type *base, uint8_t dummyData)
	Set up the dummy data. More...

Transactional
status_t	SPI_MasterTransferCreateHandle (SPI_Type base, spi_master_handle_t handle, spi_master_callback_t callback, void *userData)
	Initializes the SPI master handle. More...

status_t	SPI_MasterTransferBlocking (SPI_Type base, spi_transfer_t xfer)
	Transfers a block of data using a polling method. More...

status_t	SPI_MasterTransferNonBlocking (SPI_Type base, spi_master_handle_t handle, spi_transfer_t *xfer)
	Performs a non-blocking SPI interrupt transfer. More...

status_t	SPI_MasterHalfDuplexTransferBlocking (SPI_Type base, spi_half_duplex_transfer_t xfer)
	Transfers a block of data using a polling method. More...

status_t	SPI_MasterHalfDuplexTransferNonBlocking (SPI_Type base, spi_master_handle_t handle, spi_half_duplex_transfer_t *xfer)
	Performs a non-blocking SPI interrupt transfer. More...

status_t	SPI_MasterTransferGetCount (SPI_Type base, spi_master_handle_t handle, size_t *count)
	Gets the master transfer count. More...

void	SPI_MasterTransferAbort (SPI_Type base, spi_master_handle_t handle)
	SPI master aborts a transfer using an interrupt. More...

void	SPI_MasterTransferHandleIRQ (SPI_Type base, spi_master_handle_t handle)
	Interrupts the handler for the SPI. More...

static status_t	SPI_SlaveTransferCreateHandle (SPI_Type base, spi_slave_handle_t handle, spi_slave_callback_t callback, void *userData)
	Initializes the SPI slave handle. More...

static status_t	SPI_SlaveTransferNonBlocking (SPI_Type base, spi_slave_handle_t handle, spi_transfer_t *xfer)
	Performs a non-blocking SPI slave interrupt transfer. More...

static status_t	SPI_SlaveTransferGetCount (SPI_Type base, spi_slave_handle_t handle, size_t *count)
	Gets the slave transfer count. More...

static void	SPI_SlaveTransferAbort (SPI_Type base, spi_slave_handle_t handle)
	SPI slave aborts a transfer using an interrupt. More...

static void	SPI_SlaveTransferHandleIRQ (SPI_Type base, spi_slave_handle_t handle)
	Interrupts a handler for the SPI slave. More...

Data Structure Documentation

struct spi_delay_config_t

Note: The DLY register controls several programmable delays related to SPI signalling, it stands for how many SPI clock time will be inserted. The maxinun value of these delay time is 15.

Data Fields
uint8_t	preDelay
	Delay between SSEL assertion and the beginning of transfer. More...

uint8_t	postDelay
	Delay between the end of transfer and SSEL deassertion. More...

uint8_t	frameDelay
	Delay between frame to frame. More...

uint8_t	transferDelay
	Delay between transfer to transfer. More...

Field Documentation

uint8_t spi_delay_config_t::preDelay

uint8_t spi_delay_config_t::postDelay

uint8_t spi_delay_config_t::frameDelay

uint8_t spi_delay_config_t::transferDelay

struct spi_master_config_t

Data Fields
bool	enableLoopback
	Enable loopback for test purpose.

bool	enableMaster
	Enable SPI at initialization time.

spi_clock_polarity_t	polarity
	Clock polarity.

spi_clock_phase_t	phase
	Clock phase.

spi_shift_direction_t	direction
	MSB or LSB.

uint32_t	baudRate_Bps
	Baud Rate for SPI in Hz.

spi_data_width_t	dataWidth
	Width of the data.

spi_ssel_t	sselNum
	Slave select number.

spi_spol_t	sselPol
	Configure active CS polarity.

uint8_t	txWatermark
	txFIFO watermark

uint8_t	rxWatermark
	rxFIFO watermark

spi_delay_config_t	delayConfig
	Delay configuration. More...

spi_txfifo_watermark_t	txWatermark
	txFIFO watermark

spi_rxfifo_watermark_t	rxWatermark
	rxFIFO watermark

Field Documentation

spi_delay_config_t spi_master_config_t::delayConfig

struct spi_slave_config_t

Data Fields
bool	enableSlave
	Enable SPI at initialization time.

spi_clock_polarity_t	polarity
	Clock polarity.

spi_clock_phase_t	phase
	Clock phase.

spi_shift_direction_t	direction
	MSB or LSB.

spi_data_width_t	dataWidth
	Width of the data.

spi_spol_t	sselPol
	Configure active CS polarity.

uint8_t	txWatermark
	txFIFO watermark

uint8_t	rxWatermark
	rxFIFO watermark

spi_txfifo_watermark_t	txWatermark
	txFIFO watermark

spi_rxfifo_watermark_t	rxWatermark
	rxFIFO watermark

struct spi_transfer_t

Data Fields
uint8_t *	txData
	Send buffer.

uint8_t *	rxData
	Receive buffer.

uint32_t	configFlags
	Additional option to control transfer, spi_xfer_option_t. More...

size_t	dataSize
	Transfer bytes.

Field Documentation

uint32_t spi_transfer_t::configFlags

struct spi_half_duplex_transfer_t

Data Fields
uint8_t *	txData
	Send buffer.

uint8_t *	rxData
	Receive buffer.

size_t	txDataSize
	Transfer bytes for transmit.

size_t	rxDataSize
	Transfer bytes.

uint32_t	configFlags
	Transfer configuration flags, spi_xfer_option_t. More...

bool	isPcsAssertInTransfer
	If PCS pin keep assert between transmit and receive. More...

bool	isTransmitFirst
	True for transmit first and false for receive first. More...

Field Documentation

uint32_t spi_half_duplex_transfer_t::configFlags

bool spi_half_duplex_transfer_t::isPcsAssertInTransfer

true for assert and false for deassert.

bool spi_half_duplex_transfer_t::isTransmitFirst

struct spi_config_t

struct _spi_master_handle

Master handle type.

Data Fields
uint8_t *volatile	txData
	Transfer buffer.

uint8_t *volatile	rxData
	Receive buffer.

volatile size_t	txRemainingBytes
	Number of data to be transmitted [in bytes].

volatile size_t	rxRemainingBytes
	Number of data to be received [in bytes].

volatile size_t	toReceiveCount
	Receive data remaining in bytes.

size_t	totalByteCount
	A number of transfer bytes.

volatile uint32_t	state
	SPI internal state.

spi_master_callback_t	callback
	SPI callback.

void *	userData
	Callback parameter.

uint8_t	dataWidth
	Width of the data [Valid values: 1 to 16].

uint8_t	sselNum
	Slave select number to be asserted when transferring data [Valid values: 0 to 3].

uint32_t	configFlags
	Additional option to control transfer.

uint8_t	txWatermark
	txFIFO watermark

uint8_t	rxWatermark
	rxFIFO watermark

spi_txfifo_watermark_t	txWatermark
	txFIFO watermark

spi_rxfifo_watermark_t	rxWatermark
	rxFIFO watermark

Macro Definition Documentation

#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))

#define SPI_DUMMYDATA (0xFFU)

#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))

#define SPI_DUMMYDATA (0xFFU)

Typedef Documentation

typedef void(* flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle)

typedef void(* flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle)

Enumeration Type Documentation

enum spi_xfer_option_t

Enumerator
kSPI_FrameDelay	A delay may be inserted, defined in the DLY register.
kSPI_FrameAssert	SSEL will be deasserted at the end of a transfer.
kSPI_FrameDelay	A delay may be inserted, defined in the DLY register.
kSPI_FrameAssert	SSEL will be deasserted at the end of a transfer.

enum spi_shift_direction_t

Enumerator
kSPI_MsbFirst	Data transfers start with most significant bit.
kSPI_LsbFirst	Data transfers start with least significant bit.
kSPI_MsbFirst	Data transfers start with most significant bit.
kSPI_LsbFirst	Data transfers start with least significant bit.

enum spi_clock_polarity_t

Enumerator
kSPI_ClockPolarityActiveHigh	Active-high SPI clock (idles low).
kSPI_ClockPolarityActiveLow	Active-low SPI clock (idles high).
kSPI_ClockPolarityActiveHigh	Active-high SPI clock (idles low).
kSPI_ClockPolarityActiveLow	Active-low SPI clock (idles high).

enum spi_clock_phase_t

Enumerator
kSPI_ClockPhaseFirstEdge	First edge on SCK occurs at the middle of the first cycle of a data transfer.
kSPI_ClockPhaseSecondEdge	First edge on SCK occurs at the start of the first cycle of a data transfer.
kSPI_ClockPhaseFirstEdge	First edge on SCK occurs at the middle of the first cycle of a data transfer.
kSPI_ClockPhaseSecondEdge	First edge on SCK occurs at the start of the first cycle of a data transfer.

enum spi_txfifo_watermark_t

Enumerator
kSPI_TxFifo0	SPI tx watermark is empty.
kSPI_TxFifo1	SPI tx watermark at 1 item.
kSPI_TxFifo2	SPI tx watermark at 2 items.
kSPI_TxFifo3	SPI tx watermark at 3 items.
kSPI_TxFifo4	SPI tx watermark at 4 items.
kSPI_TxFifo5	SPI tx watermark at 5 items.
kSPI_TxFifo6	SPI tx watermark at 6 items.
kSPI_TxFifo7	SPI tx watermark at 7 items.
kSPI_TxFifo0	SPI tx watermark is empty.
kSPI_TxFifo1	SPI tx watermark at 1 item.
kSPI_TxFifo2	SPI tx watermark at 2 items.
kSPI_TxFifo3	SPI tx watermark at 3 items.
kSPI_TxFifo4	SPI tx watermark at 4 items.
kSPI_TxFifo5	SPI tx watermark at 5 items.
kSPI_TxFifo6	SPI tx watermark at 6 items.
kSPI_TxFifo7	SPI tx watermark at 7 items.

enum spi_rxfifo_watermark_t

Enumerator
kSPI_RxFifo1	SPI rx watermark at 1 item.
kSPI_RxFifo2	SPI rx watermark at 2 items.
kSPI_RxFifo3	SPI rx watermark at 3 items.
kSPI_RxFifo4	SPI rx watermark at 4 items.
kSPI_RxFifo5	SPI rx watermark at 5 items.
kSPI_RxFifo6	SPI rx watermark at 6 items.
kSPI_RxFifo7	SPI rx watermark at 7 items.
kSPI_RxFifo8	SPI rx watermark at 8 items.
kSPI_RxFifo1	SPI rx watermark at 1 item.
kSPI_RxFifo2	SPI rx watermark at 2 items.
kSPI_RxFifo3	SPI rx watermark at 3 items.
kSPI_RxFifo4	SPI rx watermark at 4 items.
kSPI_RxFifo5	SPI rx watermark at 5 items.
kSPI_RxFifo6	SPI rx watermark at 6 items.
kSPI_RxFifo7	SPI rx watermark at 7 items.
kSPI_RxFifo8	SPI rx watermark at 8 items.

enum spi_data_width_t

Enumerator
kSPI_Data4Bits	4 bits data width
kSPI_Data5Bits	5 bits data width
kSPI_Data6Bits	6 bits data width
kSPI_Data7Bits	7 bits data width
kSPI_Data8Bits	8 bits data width
kSPI_Data9Bits	9 bits data width
kSPI_Data10Bits	10 bits data width
kSPI_Data11Bits	11 bits data width
kSPI_Data12Bits	12 bits data width
kSPI_Data13Bits	13 bits data width
kSPI_Data14Bits	14 bits data width
kSPI_Data15Bits	15 bits data width
kSPI_Data16Bits	16 bits data width
kSPI_Data4Bits	4 bits data width
kSPI_Data5Bits	5 bits data width
kSPI_Data6Bits	6 bits data width
kSPI_Data7Bits	7 bits data width
kSPI_Data8Bits	8 bits data width
kSPI_Data9Bits	9 bits data width
kSPI_Data10Bits	10 bits data width
kSPI_Data11Bits	11 bits data width
kSPI_Data12Bits	12 bits data width
kSPI_Data13Bits	13 bits data width
kSPI_Data14Bits	14 bits data width
kSPI_Data15Bits	15 bits data width
kSPI_Data16Bits	16 bits data width

enum spi_ssel_t

Enumerator
kSPI_Ssel0	Slave select 0.
kSPI_Ssel1	Slave select 1.
kSPI_Ssel2	Slave select 2.
kSPI_Ssel3	Slave select 3.
kSPI_Ssel0	Slave select 0.
kSPI_Ssel1	Slave select 1.
kSPI_Ssel2	Slave select 2.
kSPI_Ssel3	Slave select 3.

anonymous enum

Enumerator
kStatus_SPI_Busy	SPI bus is busy.
kStatus_SPI_Idle	SPI is idle.
kStatus_SPI_Error	SPI error.
kStatus_SPI_BaudrateNotSupport	Baudrate is not support in current clock source.

enum _spi_interrupt_enable

Enumerator
kSPI_RxLvlIrq	Rx level interrupt.
kSPI_TxLvlIrq	Tx level interrupt.
kSPI_RxLvlIrq	Rx level interrupt.
kSPI_TxLvlIrq	Tx level interrupt.

enum _spi_statusflags

Enumerator
kSPI_TxEmptyFlag	txFifo is empty
kSPI_TxNotFullFlag	txFifo is not full
kSPI_RxNotEmptyFlag	rxFIFO is not empty
kSPI_RxFullFlag	rxFIFO is full
kSPI_TxEmptyFlag	txFifo is empty
kSPI_TxNotFullFlag	txFifo is not full
kSPI_RxNotEmptyFlag	rxFIFO is not empty
kSPI_RxFullFlag	rxFIFO is full

enum spi_xfer_option_t

Enumerator
kSPI_FrameDelay	A delay may be inserted, defined in the DLY register.
kSPI_FrameAssert	SSEL will be deasserted at the end of a transfer.
kSPI_FrameDelay	A delay may be inserted, defined in the DLY register.
kSPI_FrameAssert	SSEL will be deasserted at the end of a transfer.

enum spi_shift_direction_t

Enumerator
kSPI_MsbFirst	Data transfers start with most significant bit.
kSPI_LsbFirst	Data transfers start with least significant bit.
kSPI_MsbFirst	Data transfers start with most significant bit.
kSPI_LsbFirst	Data transfers start with least significant bit.

enum spi_clock_polarity_t

Enumerator
kSPI_ClockPolarityActiveHigh	Active-high SPI clock (idles low).
kSPI_ClockPolarityActiveLow	Active-low SPI clock (idles high).
kSPI_ClockPolarityActiveHigh	Active-high SPI clock (idles low).
kSPI_ClockPolarityActiveLow	Active-low SPI clock (idles high).

enum spi_clock_phase_t

Enumerator
kSPI_ClockPhaseFirstEdge	First edge on SCK occurs at the middle of the first cycle of a data transfer.
kSPI_ClockPhaseSecondEdge	First edge on SCK occurs at the start of the first cycle of a data transfer.
kSPI_ClockPhaseFirstEdge	First edge on SCK occurs at the middle of the first cycle of a data transfer.
kSPI_ClockPhaseSecondEdge	First edge on SCK occurs at the start of the first cycle of a data transfer.

enum spi_txfifo_watermark_t

Enumerator
kSPI_TxFifo0	SPI tx watermark is empty.
kSPI_TxFifo1	SPI tx watermark at 1 item.
kSPI_TxFifo2	SPI tx watermark at 2 items.
kSPI_TxFifo3	SPI tx watermark at 3 items.
kSPI_TxFifo4	SPI tx watermark at 4 items.
kSPI_TxFifo5	SPI tx watermark at 5 items.
kSPI_TxFifo6	SPI tx watermark at 6 items.
kSPI_TxFifo7	SPI tx watermark at 7 items.
kSPI_TxFifo0	SPI tx watermark is empty.
kSPI_TxFifo1	SPI tx watermark at 1 item.
kSPI_TxFifo2	SPI tx watermark at 2 items.
kSPI_TxFifo3	SPI tx watermark at 3 items.
kSPI_TxFifo4	SPI tx watermark at 4 items.
kSPI_TxFifo5	SPI tx watermark at 5 items.
kSPI_TxFifo6	SPI tx watermark at 6 items.
kSPI_TxFifo7	SPI tx watermark at 7 items.

enum spi_rxfifo_watermark_t

Enumerator
kSPI_RxFifo1	SPI rx watermark at 1 item.
kSPI_RxFifo2	SPI rx watermark at 2 items.
kSPI_RxFifo3	SPI rx watermark at 3 items.
kSPI_RxFifo4	SPI rx watermark at 4 items.
kSPI_RxFifo5	SPI rx watermark at 5 items.
kSPI_RxFifo6	SPI rx watermark at 6 items.
kSPI_RxFifo7	SPI rx watermark at 7 items.
kSPI_RxFifo8	SPI rx watermark at 8 items.
kSPI_RxFifo1	SPI rx watermark at 1 item.
kSPI_RxFifo2	SPI rx watermark at 2 items.
kSPI_RxFifo3	SPI rx watermark at 3 items.
kSPI_RxFifo4	SPI rx watermark at 4 items.
kSPI_RxFifo5	SPI rx watermark at 5 items.
kSPI_RxFifo6	SPI rx watermark at 6 items.
kSPI_RxFifo7	SPI rx watermark at 7 items.
kSPI_RxFifo8	SPI rx watermark at 8 items.

enum spi_data_width_t

Enumerator
kSPI_Data4Bits	4 bits data width
kSPI_Data5Bits	5 bits data width
kSPI_Data6Bits	6 bits data width
kSPI_Data7Bits	7 bits data width
kSPI_Data8Bits	8 bits data width
kSPI_Data9Bits	9 bits data width
kSPI_Data10Bits	10 bits data width
kSPI_Data11Bits	11 bits data width
kSPI_Data12Bits	12 bits data width
kSPI_Data13Bits	13 bits data width
kSPI_Data14Bits	14 bits data width
kSPI_Data15Bits	15 bits data width
kSPI_Data16Bits	16 bits data width
kSPI_Data4Bits	4 bits data width
kSPI_Data5Bits	5 bits data width
kSPI_Data6Bits	6 bits data width
kSPI_Data7Bits	7 bits data width
kSPI_Data8Bits	8 bits data width
kSPI_Data9Bits	9 bits data width
kSPI_Data10Bits	10 bits data width
kSPI_Data11Bits	11 bits data width
kSPI_Data12Bits	12 bits data width
kSPI_Data13Bits	13 bits data width
kSPI_Data14Bits	14 bits data width
kSPI_Data15Bits	15 bits data width
kSPI_Data16Bits	16 bits data width

enum spi_ssel_t

Enumerator
kSPI_Ssel0	Slave select 0.
kSPI_Ssel1	Slave select 1.
kSPI_Ssel2	Slave select 2.
kSPI_Ssel3	Slave select 3.
kSPI_Ssel0	Slave select 0.
kSPI_Ssel1	Slave select 1.
kSPI_Ssel2	Slave select 2.
kSPI_Ssel3	Slave select 3.

enum _spi_status

Enumerator
kStatus_SPI_Busy	SPI bus is busy.
kStatus_SPI_Idle	SPI is idle.
kStatus_SPI_Error	SPI error.
kStatus_SPI_BaudrateNotSupport	Baudrate is not support in current clock source.

enum _spi_interrupt_enable

Enumerator
kSPI_RxLvlIrq	Rx level interrupt.
kSPI_TxLvlIrq	Tx level interrupt.
kSPI_RxLvlIrq	Rx level interrupt.
kSPI_TxLvlIrq	Tx level interrupt.

enum _spi_statusflags

Enumerator
kSPI_TxEmptyFlag	txFifo is empty
kSPI_TxNotFullFlag	txFifo is not full
kSPI_RxNotEmptyFlag	rxFIFO is not empty
kSPI_RxFullFlag	rxFIFO is full
kSPI_TxEmptyFlag	txFifo is empty
kSPI_TxNotFullFlag	txFifo is not full
kSPI_RxNotEmptyFlag	rxFIFO is not empty
kSPI_RxFullFlag	rxFIFO is full

Function Documentation

uint32_t SPI_GetInstance ( SPI_Type * base )

void SPI_MasterGetDefaultConfig ( spi_master_config_t * config )

The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). User may use the initialized structure unchanged in SPI_MasterInit(), or modify some fields of the structure before calling SPI_MasterInit(). After calling this API, the master is ready to transfer. Example:

spi_master_config_t config;

SPI_MasterGetDefaultConfig(&config);

Parameters

config pointer to master config structure

status_t SPI_MasterInit	(	SPI_Type *	base,
		const spi_master_config_t *	config,
		uint32_t	srcClock_Hz
	)

The configuration structure can be filled by user from scratch, or be set with default values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

spi_master_config_t config = {
.baudRate_Bps = 400000,
...
};
SPI_MasterInit(SPI0, &config);

Parameters

base	SPI base pointer
config	pointer to master configuration structure
srcClock_Hz	Source clock frequency.

void SPI_SlaveGetDefaultConfig ( spi_slave_config_t * config )

The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). Modify some fields of the structure before calling SPI_SlaveInit(). Example:

spi_slave_config_t config;

SPI_SlaveGetDefaultConfig(&config);

Parameters

config pointer to slave configuration structure

status_t SPI_SlaveInit	(	SPI_Type *	base,
		const spi_slave_config_t *	config
	)

The configuration structure can be filled by user from scratch or be set with default values by SPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

spi_slave_config_t config = {
.polarity = flexSPIClockPolarity_ActiveHigh;
.phase = flexSPIClockPhase_FirstEdge;
.direction = flexSPIMsbFirst;
...
};
SPI_SlaveInit(SPI0, &config);

Parameters

base	SPI base pointer
config	pointer to slave configuration structure

void SPI_Deinit ( SPI_Type * base )

Calling this API resets the SPI module, gates the SPI clock. The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.

Parameters

base	SPI base pointer

static void SPI_Enable	(	SPI_Type *	base,
		bool	enable
	)

inlinestatic

Parameters

base	SPI base pointer
enable	or disable ( true = enable, false = disable)

static uint32_t SPI_GetStatusFlags ( SPI_Type * base )

inlinestatic

Parameters

base	SPI base pointer

Returns: SPI Status, use status flag to AND _spi_statusflags could get the related status.

static void SPI_EnableInterrupts	(	SPI_Type *	base,
		uint32_t	irqs
	)

inlinestatic

Parameters

base	SPI base pointer
irqs	SPI interrupt source. The parameter can be any combination of the following values: kSPI_RxLvlIrq kSPI_TxLvlIrq

static void SPI_DisableInterrupts	(	SPI_Type *	base,
		uint32_t	irqs
	)

inlinestatic

Parameters

base	SPI base pointer
irqs	SPI interrupt source. The parameter can be any combination of the following values: kSPI_RxLvlIrq kSPI_TxLvlIrq

void SPI_EnableTxDMA	(	SPI_Type *	base,
		bool	enable
	)

Parameters

base	SPI base pointer
enable	True means enable DMA, false means disable DMA

void SPI_EnableRxDMA	(	SPI_Type *	base,
		bool	enable
	)

Parameters

base	SPI base pointer
enable	True means enable DMA, false means disable DMA

void* SPI_GetConfig ( SPI_Type * base )

Parameters

base	SPI peripheral address.

Returns: return configurations which contain datawidth and SSEL numbers. return data type is a pointer of spi_config_t.

status_t SPI_MasterSetBaud	(	SPI_Type *	base,
		uint32_t	baudrate_Bps,
		uint32_t	srcClock_Hz
	)

This is only used in master.

Parameters

base	SPI base pointer
baudrate_Bps	baud rate needed in Hz.
srcClock_Hz	SPI source clock frequency in Hz.

void SPI_WriteData	(	SPI_Type *	base,
		uint16_t	data,
		uint32_t	configFlags
	)

Parameters

base	SPI base pointer
data	needs to be write.
configFlags	transfer configuration options spi_xfer_option_t

static uint32_t SPI_ReadData ( SPI_Type * base )

inlinestatic

Parameters

base	SPI base pointer

Returns: Data in the register.

static void SPI_SetTransferDelay	(	SPI_Type *	base,
		const spi_delay_config_t *	config
	)

inlinestatic

   the delay uint is SPI clock time, maximum value is 0xF.

Parameters

base	SPI base pointer
config	configuration for delay option spi_delay_config_t.

void SPI_SetDummyData	(	SPI_Type *	base,
		uint8_t	dummyData
	)

Parameters

base	SPI peripheral address.
dummyData	Data to be transferred when tx buffer is NULL.

status_t SPI_MasterTransferCreateHandle	(	SPI_Type *	base,
		spi_master_handle_t *	handle,
		spi_master_callback_t	callback,
		void *	userData
	)

This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, for a specified SPI instance, call this API once to get the initialized handle.

Parameters

base	SPI peripheral base address.
handle	SPI handle pointer.
callback	Callback function.
userData	User data.

status_t SPI_MasterTransferBlocking	(	SPI_Type *	base,
		spi_transfer_t *	xfer
	)

Parameters

base	SPI base pointer
xfer	pointer to spi_xfer_config_t structure

Return values

kStatus_Success	Successfully start a transfer.
kStatus_InvalidArgument	Input argument is invalid.

status_t SPI_MasterTransferNonBlocking	(	SPI_Type *	base,
		spi_master_handle_t *	handle,
		spi_transfer_t *	xfer
	)

Parameters

base	SPI peripheral base address.
handle	pointer to spi_master_handle_t structure which stores the transfer state
xfer	pointer to spi_xfer_config_t structure

Return values

kStatus_Success	Successfully start a transfer.
kStatus_InvalidArgument	Input argument is invalid.
kStatus_SPI_Busy	SPI is not idle, is running another transfer.

status_t SPI_MasterHalfDuplexTransferBlocking	(	SPI_Type *	base,
		spi_half_duplex_transfer_t *	xfer
	)

This function will do a half-duplex transfer for SPI master, This is a blocking function, which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, users can set transmit first or receive first.

Parameters

base	SPI base pointer
xfer	pointer to spi_half_duplex_transfer_t structure

Returns: status of status_t.

status_t SPI_MasterHalfDuplexTransferNonBlocking	(	SPI_Type *	base,
		spi_master_handle_t *	handle,
		spi_half_duplex_transfer_t *	xfer
	)

This function using polling way to do the first half transimission and using interrupts to do the second half transimission, the transfer mechanism is half-duplex. When do the second half transimission, code will return right away. When all data is transferred, the callback function is called.

Parameters

base	SPI peripheral base address.
handle	pointer to spi_master_handle_t structure which stores the transfer state
xfer	pointer to spi_half_duplex_transfer_t structure

Returns: status of status_t.

status_t SPI_MasterTransferGetCount	(	SPI_Type *	base,
		spi_master_handle_t *	handle,
		size_t *	count
	)

This function gets the master transfer count.

Parameters

base	SPI peripheral base address.
handle	Pointer to the spi_master_handle_t structure which stores the transfer state.
count	The number of bytes transferred by using the non-blocking transaction.

Returns: status of status_t.

void SPI_MasterTransferAbort	(	SPI_Type *	base,
		spi_master_handle_t *	handle
	)

This function aborts a transfer using an interrupt.

Parameters

base	SPI peripheral base address.
handle	Pointer to the spi_master_handle_t structure which stores the transfer state.

void SPI_MasterTransferHandleIRQ	(	SPI_Type *	base,
		spi_master_handle_t *	handle
	)

Parameters

base	SPI peripheral base address.
handle	pointer to spi_master_handle_t structure which stores the transfer state.

static status_t SPI_SlaveTransferCreateHandle	(	SPI_Type *	base,
		spi_slave_handle_t *	handle,
		spi_slave_callback_t	callback,
		void *	userData
	)

inlinestatic

This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, for a specified SPI instance, call this API once to get the initialized handle.

Parameters

base	SPI peripheral base address.
handle	SPI handle pointer.
callback	Callback function.
userData	User data.

static status_t SPI_SlaveTransferNonBlocking	(	SPI_Type *	base,
		spi_slave_handle_t *	handle,
		spi_transfer_t *	xfer
	)

inlinestatic

Note: The API returns immediately after the transfer initialization is finished.

Parameters

base	SPI peripheral base address.
handle	pointer to spi_master_handle_t structure which stores the transfer state
xfer	pointer to spi_xfer_config_t structure

Return values

kStatus_Success	Successfully start a transfer.
kStatus_InvalidArgument	Input argument is invalid.
kStatus_SPI_Busy	SPI is not idle, is running another transfer.

static status_t SPI_SlaveTransferGetCount	(	SPI_Type *	base,
		spi_slave_handle_t *	handle,
		size_t *	count
	)

inlinestatic

This function gets the slave transfer count.

Parameters

base	SPI peripheral base address.
handle	Pointer to the spi_master_handle_t structure which stores the transfer state.
count	The number of bytes transferred by using the non-blocking transaction.

Returns: status of status_t.

static void SPI_SlaveTransferAbort	(	SPI_Type *	base,
		spi_slave_handle_t *	handle
	)

inlinestatic

This function aborts a transfer using an interrupt.

Parameters

base	SPI peripheral base address.
handle	Pointer to the spi_slave_handle_t structure which stores the transfer state.

static void SPI_SlaveTransferHandleIRQ	(	SPI_Type *	base,
		spi_slave_handle_t *	handle
	)

inlinestatic

Parameters

base	SPI peripheral base address.
handle	pointer to spi_slave_handle_t structure which stores the transfer state

Variable Documentation

volatile uint8_t s_dummyData[]

Overview

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Macros

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Initialization and deinitialization

Status

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DMA Control

Bus Operations

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Data Structure Documentation

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Field Documentation

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Field Documentation

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Field Documentation

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Data Fields

Macro Definition Documentation

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Variable Documentation