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MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
Files | |
file | fsl_clock.h |
Data Structures | |
struct | clock_arm_pll_config_t |
PLL configuration for ARM. More... | |
struct | clock_usb_pll_config_t |
PLL configuration for USB. More... | |
struct | clock_sys_pll_config_t |
PLL configuration for System. More... | |
struct | clock_sys_pll1_config_t |
PLL configure for Sys Pll1. More... | |
struct | clock_video_pll_config_t |
PLL configuration for AUDIO and VIDEO. More... | |
struct | clock_enet_pll_config_t |
PLL configuration for ENET. More... | |
Macros | |
#define | FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
Configure whether driver controls clock. More... | |
#define | CCSR_OFFSET 0x0C |
CCM registers offset. | |
#define | PLL_ARM_OFFSET 0x00 |
CCM Analog registers offset. | |
#define | CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) |
CCM ANALOG tuple macros to map corresponding registers and bit fields. | |
#define | SYS_PLL2_FREQ (528000000U) |
SYS_PLL_FREQ frequency in Hz. | |
#define | CLKPN_FREQ 0U |
clock1PN frequency. | |
#define | LPADC_CLOCKS |
Clock gate name array for ADC. More... | |
#define | ADC_ETC_CLOCKS |
Clock gate name array for ADC. More... | |
#define | AOI_CLOCKS |
Clock gate name array for AOI. More... | |
#define | DCDC_CLOCKS |
Clock gate name array for DCDC. More... | |
#define | DCDC_CLOCKS |
Clock gate name array for DCDC. More... | |
#define | SRC_CLOCKS |
Clock gate name array for SRC. More... | |
#define | GPC_CLOCKS |
Clock gate name array for GPC. More... | |
#define | SSARC_CLOCKS |
Clock gate name array for SSARC. More... | |
#define | WDOG_CLOCKS |
Clock gate name array for WDOG. More... | |
#define | EWM_CLOCKS |
Clock gate name array for EWM. More... | |
#define | SEMA_CLOCKS |
Clock gate name array for Sema. More... | |
#define | MU_CLOCKS |
Clock gate name array for MU. More... | |
#define | EDMA_CLOCKS |
Clock gate name array for EDMA. More... | |
#define | FLEXRAM_CLOCKS |
Clock gate name array for FLEXRAM. More... | |
#define | LMEM_CLOCKS |
Clock gate name array for LMEM. More... | |
#define | FLEXSPI_CLOCKS |
Clock gate name array for FLEXSPI. More... | |
#define | RDC_CLOCKS |
Clock gate name array for RDC. More... | |
#define | SEMC_CLOCKS |
Clock ip name array for SEMC. More... | |
#define | XECC_CLOCKS |
Clock ip name array for XECC. More... | |
#define | IEE_CLOCKS |
Clock ip name array for IEE. More... | |
#define | KEYMANAGER_CLOCKS |
Clock ip name array for KEY_MANAGER. More... | |
#define | OCOTP_CLOCKS |
Clock ip name array for OCOTP. More... | |
#define | CAAM_CLOCKS |
Clock ip name array for CAAM. More... | |
#define | XBAR_CLOCKS |
Clock ip name array for XBAR. More... | |
#define | IOMUXC_CLOCKS |
Clock ip name array for IOMUXC. More... | |
#define | GPIO_CLOCKS |
Clock ip name array for GPIO. More... | |
#define | KPP_CLOCKS |
Clock ip name array for KPP. More... | |
#define | FLEXIO_CLOCKS |
Clock ip name array for FLEXIO. More... | |
#define | DAC_CLOCKS |
Clock ip name array for DAC. More... | |
#define | CMP_CLOCKS |
Clock ip name array for CMP. More... | |
#define | PIT_CLOCKS |
Clock ip name array for PIT. More... | |
#define | GPT_CLOCKS |
Clock ip name array for GPT. More... | |
#define | TMR_CLOCKS |
Clock ip name array for QTIMER. More... | |
#define | ENC_CLOCKS |
Clock ip name array for ENC. More... | |
#define | PWM_CLOCKS |
Clock ip name array for PWM. More... | |
#define | FLEXCAN_CLOCKS |
Clock ip name array for FLEXCAN. More... | |
#define | LPUART_CLOCKS |
Clock ip name array for LPUART. More... | |
#define | LPI2C_CLOCKS |
Clock ip name array for LPI2C. More... | |
#define | LPSPI_CLOCKS |
Clock ip name array for LPSPI. More... | |
#define | ENET_CLOCKS |
Clock ip name array for ENET. More... | |
#define | ENET1G_CLOCKS |
Clock ip name array for ENET_1G. More... | |
#define | ENETQOS_CLOCKS |
Clock ip name array for ENET_QOS. More... | |
#define | USB_CLOCKS |
Clock ip name array for USB. More... | |
#define | SDIO_CLOCKS |
Clock ip name array for SDIO. More... | |
#define | USDHC_CLOCKS |
Clock ip name array for USDHC. More... | |
#define | ASRC_CLOCKS |
Clock ip name array for ASRC. More... | |
#define | MQS_CLOCKS |
Clock ip name array for MQS. More... | |
#define | PDM_CLOCKS |
Clock ip name array for PDM. More... | |
#define | SPDIF_CLOCKS |
Clock ip name array for SPDIF. More... | |
#define | SAI_CLOCKS |
Clock ip name array for SAI. More... | |
#define | PXP_CLOCKS |
Clock ip name array for PXP. More... | |
#define | GPU2D_CLOCKS |
Clock ip name array for GPU2d. More... | |
#define | LCDIF_CLOCKS |
Clock ip name array for LCDIF. More... | |
#define | LCDIFV2_CLOCKS |
Clock ip name array for LCDIFV2. More... | |
#define | MIPI_DSI_HOST_CLOCKS |
Clock ip name array for MIPI_DSI. More... | |
#define | MIPI_CSI2RX_CLOCKS |
Clock ip name array for MIPI_CSI. More... | |
#define | CSI_CLOCKS |
Clock ip name array for CSI. More... | |
#define | DCIC_MIPI_CLOCKS |
Clock ip name array for DCIC_MIPI. More... | |
#define | DCIC_LCD_CLOCKS |
Clock ip name array for DCIC_LCD. More... | |
#define | DMAMUX_CLOCKS |
Clock ip name array for DMAMUX_CLOCKS. More... | |
#define | XBARA_CLOCKS |
Clock ip name array for XBARA. More... | |
#define | XBARB_CLOCKS |
Clock ip name array for XBARB. More... | |
#define | kCLOCK_CoreSysClk kCLOCK_CpuClk |
For compatible with other platforms without CCM. More... | |
#define | CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq |
For compatible with other platforms without CCM. More... | |
Enumerations | |
enum | clock_osc_t { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U } |
OSC 24M sorce select. More... | |
enum | clock_gate_value_t { kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK } |
Clock gate value. More... | |
enum | clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U } |
System clock mode. More... | |
enum | clock_usb_src_t { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU } |
USB clock source definition. More... | |
enum | clock_usb_phy_src_t { kCLOCK_Usbphy480M = 0 } |
Source of the USB HS PHY. More... | |
enum | _clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U } |
PLL clock source, bypass cloco source also. More... | |
enum | clock_pll_post_div_t { kCLOCK_PllPostDiv2 = 0U, kCLOCK_PllPostDiv4 = 1U, kCLOCK_PllPostDiv8 = 2U, kCLOCK_PllPostDiv1 = 3U } |
enum | clock_pll_t |
PLL name. | |
enum | clock_pfd_t { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U } |
PLL PFD name. More... | |
Functions | |
static void | CLOCK_SetRootClockMux (clock_root_t root, uint8_t src) |
Set CCM Root Clock MUX node to certain value. More... | |
static uint32_t | CLOCK_GetRootClockMux (clock_root_t root) |
Get CCM Root Clock MUX value. More... | |
static clock_name_t | CLOCK_GetRootClockSource (clock_root_t root, uint32_t src) |
Get CCM Root Clock Source. More... | |
static void | CLOCK_SetRootClockDiv (clock_root_t root, uint8_t div) |
Set CCM Root Clock DIV certain value. More... | |
static uint32_t | CLOCK_GetRootClockDiv (clock_root_t root) |
Get CCM DIV node value. More... | |
static void | CLOCK_PowerOffRootClock (clock_root_t root) |
Power Off Root Clock. More... | |
static void | CLOCK_PowerOnRootClock (clock_root_t root) |
Power On Root Clock. More... | |
static void | CLOCK_SetRootClockMFx (clock_root_t root, uint32_t mfn, uint32_t mfd) |
Set MFN and MFD Root Clock. More... | |
static void | CLOCK_SetRootClock (clock_root_t root, const clock_root_config_t *config) |
Configure Root Clock. More... | |
static void | CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value) |
Control the clock gate for specific IP. More... | |
static void | CLOCK_EnableClock (clock_ip_name_t name) |
Enable the clock for specific IP. More... | |
static void | CLOCK_DisableClock (clock_ip_name_t name) |
Disable the clock for specific IP. More... | |
void | CLOCK_SetGroupConfig (clock_group_t group, const clock_group_config_t *config) |
Set the clock group configuration. More... | |
static void | CLOCK_SetMode (clock_mode_t mode) |
Setting the low power mode that system will enter on next assertion of dsm_request signal. More... | |
static uint32_t | CLOCK_GetOscFreq (void) |
Gets the OSC clock frequency. More... | |
uint32_t | CLOCK_GetAhbFreq (void) |
Gets the AHB clock frequency. More... | |
uint32_t | CLOCK_GetSemcFreq (void) |
Gets the SEMC clock frequency. More... | |
uint32_t | CLOCK_GetIpgFreq (void) |
Gets the IPG clock frequency. More... | |
uint32_t | CLOCK_GetPerClkFreq (void) |
Gets the PER clock frequency. More... | |
uint32_t | CLOCK_GetFreq (clock_name_t name) |
Gets the clock frequency for a specific clock name. More... | |
static uint32_t | CLOCK_GetRootClockFreq (clock_root_t root) |
Gets the clock frequency for a specific root clock name. More... | |
static uint32_t | CLOCK_GetM7Freq (void) |
Get the CCM CPU/core/system frequency. More... | |
static uint32_t | CLOCK_GetM4Freq (void) |
Get the CCM CPU/core/system frequency. More... | |
bool | CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq) |
Enable USB HS clock. More... | |
bool | CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq) |
Enable USB HS clock. More... | |
void | CLOCK_DisableUsbhs1PhyPllClock (void) |
Disable USB HS PHY PLL clock. More... | |
Variables | |
volatile uint32_t | g_xtalFreq |
External XTAL (24M OSC/SYSOSC) clock frequency. More... | |
volatile uint32_t | g_rtcXtalFreq |
External RTC XTAL (32K OSC) clock frequency. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) |
CLOCK driver version 2.1.1. More... | |
#define | SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (1000000000UL) |
#define | CCM_ANALOG_PLL_BYPASS_SHIFT (16U) |
#define | CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) |
#define | CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) |
OSC operations | |
void | CLOCK_InitExternalClk (bool bypassXtalOsc) |
Initialize the external 24MHz clock. More... | |
void | CLOCK_DeinitExternalClk (void) |
Deinitialize the external 24MHz clock. More... | |
void | CLOCK_SwitchOsc (clock_osc_t osc) |
Switch the OSC. More... | |
static uint32_t | CLOCK_GetRtcFreq (void) |
Gets the RTC clock frequency. More... | |
static void | CLOCK_SetXtalFreq (uint32_t freq) |
Set the XTAL (24M OSC) frequency based on board setting. More... | |
static void | CLOCK_SetRtcXtalFreq (uint32_t freq) |
Set the RTC XTAL (32K OSC) frequency based on board setting. More... | |
void | CLOCK_InitRcOsc24M (void) |
Initialize the RC oscillator 24MHz clock. | |
void | CLOCK_DeinitRcOsc24M (void) |
Power down the RCOSC 24M clock. | |
struct clock_arm_pll_config_t |
The output clock frequency is:
Fout=Fin*loopDivider /(2 * postDivider).
Fin is always 24MHz.
Data Fields | |
clock_pll_post_div_t | postDivider |
Post divider. More... | |
uint32_t | loopDivider |
PLL loop divider. More... | |
clock_pll_post_div_t clock_arm_pll_config_t::postDivider |
uint32_t clock_arm_pll_config_t::loopDivider |
Valid range: 104-208.
struct clock_usb_pll_config_t |
Data Fields | |
uint8_t | loopDivider |
PLL loop divider. More... | |
uint8_t | src |
Pll clock source, reference _clock_pll_clk_src. | |
uint8_t clock_usb_pll_config_t::loopDivider |
0 - Fout=Fref*20; 1 - Fout=Fref*22
struct clock_sys_pll_config_t |
Data Fields | |
uint8_t | loopDivider |
PLL loop divider. More... | |
uint32_t | mfn |
30 bit mfn of fractional loop divider. More... | |
uint32_t | mfi |
30 bit of fractional loop divider | |
uint16_t | ss_stop |
Stop value to get frequency change. More... | |
uint8_t | ss_enable |
Enable spread spectrum modulation. | |
uint16_t | ss_step |
Step value to get frequency change step. More... | |
uint8_t clock_sys_pll_config_t::loopDivider |
Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22
uint32_t clock_sys_pll_config_t::mfn |
uint16_t clock_sys_pll_config_t::ss_stop |
uint16_t clock_sys_pll_config_t::ss_step |
struct clock_sys_pll1_config_t |
struct clock_video_pll_config_t |
Data Fields | |
uint8_t | loopDivider |
PLL loop divider. More... | |
uint8_t | postDivider |
Divider after the PLL, should only be 1, 2, 4, 8, 16, 32. More... | |
uint32_t | numerator |
30 bit numerator of fractional loop divider. More... | |
uint32_t | denominator |
30 bit denominator of fractional loop divider | |
uint8_t clock_video_pll_config_t::loopDivider |
Valid range for DIV_SELECT divider value: 27~54.
uint8_t clock_video_pll_config_t::postDivider |
uint32_t clock_video_pll_config_t::numerator |
struct clock_enet_pll_config_t |
Data Fields | |
bool | enableClkOutput |
Power on and enable PLL clock output for ENET0 (ref_enetpll0). More... | |
bool | enableClkOutput25M |
Power on and enable PLL clock output for ENET2 (ref_enetpll2). More... | |
uint8_t | loopDivider |
Controls the frequency of the ENET0 reference clock. More... | |
uint8_t | src |
Pll clock source, reference _clock_pll_clk_src. | |
bool | enableClkOutput1 |
Power on and enable PLL clock output for ENET1 (ref_enetpll1). More... | |
uint8_t | loopDivider1 |
Controls the frequency of the ENET1 reference clock. More... | |
bool clock_enet_pll_config_t::enableClkOutput |
bool clock_enet_pll_config_t::enableClkOutput25M |
uint8_t clock_enet_pll_config_t::loopDivider |
b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz
bool clock_enet_pll_config_t::enableClkOutput1 |
uint8_t clock_enet_pll_config_t::loopDivider1 |
b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) |
#define LPADC_CLOCKS |
#define ADC_ETC_CLOCKS |
#define AOI_CLOCKS |
#define DCDC_CLOCKS |
Clock ip name array for DCDC.
#define DCDC_CLOCKS |
Clock ip name array for DCDC.
#define SRC_CLOCKS |
#define GPC_CLOCKS |
#define SSARC_CLOCKS |
#define WDOG_CLOCKS |
#define EWM_CLOCKS |
#define SEMA_CLOCKS |
#define MU_CLOCKS |
#define EDMA_CLOCKS |
#define FLEXRAM_CLOCKS |
#define LMEM_CLOCKS |
#define FLEXSPI_CLOCKS |
#define RDC_CLOCKS |
#define SEMC_CLOCKS |
#define XECC_CLOCKS |
#define IEE_CLOCKS |
#define KEYMANAGER_CLOCKS |
#define OCOTP_CLOCKS |
#define CAAM_CLOCKS |
#define XBAR_CLOCKS |
#define IOMUXC_CLOCKS |
#define GPIO_CLOCKS |
#define KPP_CLOCKS |
#define FLEXIO_CLOCKS |
#define DAC_CLOCKS |
#define CMP_CLOCKS |
#define PIT_CLOCKS |
#define GPT_CLOCKS |
#define TMR_CLOCKS |
#define ENC_CLOCKS |
#define PWM_CLOCKS |
#define FLEXCAN_CLOCKS |
#define LPUART_CLOCKS |
#define LPI2C_CLOCKS |
#define LPSPI_CLOCKS |
#define ENET_CLOCKS |
#define ENET1G_CLOCKS |
#define ENETQOS_CLOCKS |
#define USB_CLOCKS |
#define SDIO_CLOCKS |
#define USDHC_CLOCKS |
#define ASRC_CLOCKS |
#define MQS_CLOCKS |
#define PDM_CLOCKS |
#define SPDIF_CLOCKS |
#define SAI_CLOCKS |
#define PXP_CLOCKS |
#define GPU2D_CLOCKS |
#define LCDIF_CLOCKS |
#define LCDIFV2_CLOCKS |
#define MIPI_DSI_HOST_CLOCKS |
#define MIPI_CSI2RX_CLOCKS |
#define CSI_CLOCKS |
#define DCIC_MIPI_CLOCKS |
#define DCIC_LCD_CLOCKS |
#define DMAMUX_CLOCKS |
#define XBARA_CLOCKS |
#define XBARB_CLOCKS |
#define kCLOCK_CoreSysClk kCLOCK_CpuClk |
#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq |
enum clock_osc_t |
enum clock_gate_value_t |
enum clock_mode_t |
enum clock_usb_src_t |
enum clock_usb_phy_src_t |
enum _clock_pll_clk_src |
enum clock_pll_post_div_t |
enum clock_pfd_t |
|
inlinestatic |
root | Which root clock node to set, see clock_root_t. |
src | Clock mux value to set, different mux has different value range. |
|
inlinestatic |
mux | Which mux node to get, see clock_mux_t. |
|
inlinestatic |
root | Which root clock node to get, see clock_root_t. |
src | Clock mux value to get |
|
inlinestatic |
root | Which root clock to set, see clock_root_t. |
div | Clock div value to set, different divider has different value range. |
|
inlinestatic |
root | Which root clock node to get, see clock_root_t. |
|
inlinestatic |
root | Which root clock node to set, see clock_root_t. |
|
inlinestatic |
root | Which root clock node to set, see clock_root_t. |
|
inlinestatic |
root | Which root clock node to set, see clock_root_t. |
mfn | MFN value |
mfd | MFD value |
|
inlinestatic |
root | Which root clock node to set, see clock_root_t. |
config | root clock config, see clock_root_config_t |
|
inlinestatic |
name | Which clock to enable, see clock_ip_name_t. |
value | Clock gate value to set, see clock_gate_value_t. |
|
inlinestatic |
name | Which clock to enable, see clock_ip_name_t. |
|
inlinestatic |
name | Which clock to disable, see clock_ip_name_t. |
void CLOCK_SetGroupConfig | ( | clock_group_t | group, |
const clock_group_config_t * | config | ||
) |
group | Which group to configure, see clock_group_t. |
config | Configuration to set. |
|
inlinestatic |
mode | Which mode to enter, see clock_mode_t. |
|
inlinestatic |
This function will return the external XTAL OSC frequency if it is selected as the source of OSC, otherwise internal 24MHz RC OSC frequency will be returned.
osc | OSC type to get frequency. |
uint32_t CLOCK_GetAhbFreq | ( | void | ) |
uint32_t CLOCK_GetSemcFreq | ( | void | ) |
uint32_t CLOCK_GetIpgFreq | ( | void | ) |
uint32_t CLOCK_GetPerClkFreq | ( | void | ) |
uint32_t CLOCK_GetFreq | ( | clock_name_t | name | ) |
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.
clockName | Clock names defined in clock_name_t |
|
inlinestatic |
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.
clockName | Clock names defined in clock_root_t |
|
inlinestatic |
|
inlinestatic |
void CLOCK_InitExternalClk | ( | bool | bypassXtalOsc | ) |
This function supports two modes:
After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.
bypassXtalOsc | Pass in true to bypass the external crystal oscillator. |
void CLOCK_DeinitExternalClk | ( | void | ) |
This function disables the external 24MHz clock.
After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.
void CLOCK_SwitchOsc | ( | clock_osc_t | osc | ) |
This function switches the OSC source for SoC.
osc | OSC source to switch to. |
|
inlinestatic |
|
inlinestatic |
freq | The XTAL input clock frequency in Hz. |
|
inlinestatic |
freq | The RTC XTAL input clock frequency in Hz. |
bool CLOCK_EnableUsbhs0Clock | ( | clock_usb_src_t | src, |
uint32_t | freq | ||
) |
This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.
src | USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused. |
freq | USB HS does not care about the clock source, so this parameter is ignored. |
true | The clock is set successfully. |
false | The clock source is invalid to get proper USB HS clock. |
bool CLOCK_EnableUsbhs1Clock | ( | clock_usb_src_t | src, |
uint32_t | freq | ||
) |
This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.
src | USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused. |
freq | USB HS does not care about the clock source, so this parameter is ignored. |
true | The clock is set successfully. |
false | The clock source is invalid to get proper USB HS clock. |
void CLOCK_DisableUsbhs1PhyPllClock | ( | void | ) |
This function disables USB HS PHY PLL clock.
volatile uint32_t g_xtalFreq |
The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 24MHz,
volatile uint32_t g_rtcXtalFreq |
The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetRtcXtalFreq to set the value in to clock driver.