The MCUXpresso SDK provides a peripheral clock driver for the SYSCON module of MCUXpresso SDK devices.
Function description
Clock driver provides these functions:
- Functions to initialize the Core clock to given frequency
- Functions to configure the clock selection muxes.
- Functions to setup peripheral clock dividers
- Functions to set the flash wait states for the input freuqency
- Functions to get the frequency of the selected clock
- Functions to set PLL frequency
SYSCON Clock frequency functions
SYSCON clock module provides clocks, such as MCLKCLK, ADCCLK, DMICCLK, MCGFLLCLK, FXCOMCLK, WDTOSC, RTCOSC, USBCLK, and SYSPLL. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. CLOCK_SetupFROClocking() initializes the FRO to 12 MHz, 48 MHz, or 96 MHz frequency. CLOCK_SetupPLLData(), CLOCK_SetupSystemPLLPrec(), and CLOCK_SetPLLFreq() functions are used to setup the PLL. The SYSCON clock driver provides functions to get the frequency of these clocks, such as CLOCK_GetFreq(), CLOCK_GetFro12MFreq(), CLOCK_GetExtClkFreq(), CLOCK_GetWdtOscFreq(), CLOCK_GetFroHfFreq(), CLOCK_GetPllOutFreq(), CLOCK_GetOsc32KFreq(), CLOCK_GetCoreSysClkFreq(), CLOCK_GetI2SMClkFreq(), CLOCK_GetFlexCommClkFreq, and CLOCK_GetAsyncApbClkFreq.
SYSCON clock Selection Muxes
The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC, and PLL.
SYSCON clock dividers
The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, I2S, SYSTICK, AHB, ADC, and also CLKOUT and TRACE functions.
SYSCON flash wait states
The SYSCON clock driver provides the function CLOCK_SetFLASHAccessCyclesForFreq() that configures FLASHCFG register with a selected FLASHTIM value.
Typical use case
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on so that we can switch to its 12MHz mode temporarily
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| enum | clock_ip_name_t |
| | Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
|
| |
| enum | clock_name_t {
kCLOCK_CoreSysClk,
kCLOCK_MainClk,
kCLOCK_Fro,
kCLOCK_FroDiv,
kCLOCK_ExtClk,
kCLOCK_LPOsc,
kCLOCK_Frg
} |
| | Clock name used to get clock frequency. More...
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| |
| enum | clock_select_t |
| | Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value. More...
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| |
| enum | clock_divider_t |
| | Clock divider.
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| |
| enum | clock_fro_src_t { kCLOCK_FroSrcLpwrBootValue = 0U
} |
| | fro output frequency source definition More...
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| |
| enum | clock_fro_osc_freq_t {
kCLOCK_FroOscOut18M = 18000U,
kCLOCK_FroOscOut24M = 24000U,
kCLOCK_FroOscOut30M = 30000U
} |
| | fro oscillator output frequency value definition More...
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| |
| enum | clock_main_clk_src_t {
kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U),
kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U),
kCLOCK_MainClkSrcLPOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U),
kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U)
} |
| |
| #define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F001CD3U) |
Value:{ \
kCLOCK_Dac0, kCLOCK_Dac1, \
}
Value:{ \
kCLOCK_Uart0, kCLOCK_Uart1, \
}
| #define CLK_GATE_DEFINE |
( |
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reg, |
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|
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bit |
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) |
| ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU)) |
| Enumerator |
|---|
| kCLOCK_CoreSysClk |
Cpu/AHB/AHB matrix/Memories,etc.
|
| kCLOCK_MainClk |
Main clock.
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| kCLOCK_Fro |
FRO18/24/30.
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| kCLOCK_FroDiv |
FRO div clock.
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| kCLOCK_ExtClk |
External Clock.
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| kCLOCK_LPOsc |
Low power Oscillator.
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| kCLOCK_Frg |
fractional rate0
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| Enumerator |
|---|
| kCLOCK_FroSrcLpwrBootValue |
fro source from the fro oscillator divided by low power boot value
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| Enumerator |
|---|
| kCLOCK_FroOscOut18M |
FRO oscillator output 18M.
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| kCLOCK_FroOscOut24M |
FRO oscillator output 24M.
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| kCLOCK_FroOscOut30M |
FRO oscillator output 30M.
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| Enumerator |
|---|
| kCLOCK_MainClkSrcFro |
main clock source from FRO
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| kCLOCK_MainClkSrcExtClk |
main clock source from Ext clock
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| kCLOCK_MainClkSrcLPOsc |
main clock source from watchdog oscillator
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| kCLOCK_MainClkSrcFroDiv |
main clock source from FRO Div
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- Parameters
-
| src,reference | clock_main_clk_src_t to set the main clock source. |
| uint32_t CLOCK_GetFRGClkFreq |
( |
void |
| ) |
|
- Returns
- Frequency of FRG0 Clock.
| uint32_t CLOCK_GetMainClkFreq |
( |
void |
| ) |
|
- Returns
- Frequency of Main Clock.
| uint32_t CLOCK_GetFroFreq |
( |
void |
| ) |
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| static uint32_t CLOCK_GetCoreSysClkFreq |
( |
void |
| ) |
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inlinestatic |
- Returns
- Frequency of core.
| uint32_t CLOCK_GetClockOutClkFreq |
( |
void |
| ) |
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- Returns
- Frequency of ClockOut
| uint32_t CLOCK_GetUart0ClkFreq |
( |
void |
| ) |
|
| uint32_t CLOCK_GetUart1ClkFreq |
( |
void |
| ) |
|
- Returns
- Frequency of selected clock
| static uint32_t CLOCK_GetLPOscFreq |
( |
void |
| ) |
|
|
inlinestatic |
- Return values
-
| watch | dog OSC frequency value. |
| static uint32_t CLOCK_GetExtClkFreq |
( |
void |
| ) |
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|
inlinestatic |
- Return values
-
| external | clock frequency value. |
| volatile uint32_t g_Wdt_Osc_Freq |
This variable is used to store the watchdog oscillator frequency which is set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
| volatile uint32_t g_Ext_Clk_Freq |
This variable is used to store the external clock frequency which is include external oscillator clock and external clk in clock frequency value, it is set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc when external oscillator is used as external clock ,and it is returned by CLOCK_GetExtClkFreq.
