Clock Driver

Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

Data Structures
struct	ccm_analog_frac_pll_config_t
	Fractional-N PLL configuration. More...
struct	ccm_analog_integer_pll_config_t
	Integer PLL configuration. More...

Macros
#define	OSC24M_CLK_FREQ   24000000U
	XTAL 24M clock frequency.
#define	CLKPAD_FREQ   0U
	pad clock frequency.
#define	ECSPI_CLOCKS
	Clock ip name array for ECSPI. More...
#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...
#define	GPT_CLOCKS
	Clock ip name array for GPT. More...
#define	I2C_CLOCKS
	Clock ip name array for I2C. More...
#define	IOMUX_CLOCKS
	Clock ip name array for IOMUX. More...
#define	PWM_CLOCKS
	Clock ip name array for PWM. More...
#define	RDC_CLOCKS
	Clock ip name array for RDC. More...
#define	SAI_CLOCKS
	Clock ip name array for SAI. More...
#define	RDC_SEMA42_CLOCKS
	Clock ip name array for RDC SEMA42. More...
#define	UART_CLOCKS
	Clock ip name array for UART. More...
#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...
#define	WDOG_CLOCKS
	Clock ip name array for WDOG. More...
#define	TMU_CLOCKS
	Clock ip name array for TEMPSENSOR. More...
#define	SDMA_CLOCKS
	Clock ip name array for SDMA. More...
#define	MU_CLOCKS
	Clock ip name array for MU. More...
#define	QSPI_CLOCKS
	Clock ip name array for QSPI. More...
#define	PDM_CLOCKS
	Clock ip name array for PDM. More...
#define	CCM_BIT_FIELD_EXTRACTION(val, mask, shift)   (((val) & (mask)) >> (shift))
	CCM reg macros to extract corresponding registers bit field.
#define	CCM_REG_OFF(root, off)   (*((volatile uint32_t *)((uint32_t)(root) + (off))))
	CCM reg macros to map corresponding registers.
#define	AUDIO_PLL1_GEN_CTRL_OFFSET   0x00
	CCM Analog registers offset.
#define	CCM_ANALOG_TUPLE(reg, shift)   ((((reg)&0xFFFFU) << 16U) | ((shift)))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.
#define	CCM_TUPLE(ccgr, root)   ((ccgr) << 16U | (root))
	CCM CCGR and root tuple.
#define	kCLOCK_CoreSysClk   kCLOCK_CoreM4Clk
	For compatible with other platforms without CCM. More...
#define	CLOCK_GetCoreSysClkFreq   CLOCK_GetCoreM4Freq
	For compatible with other platforms without CCM. More...

Enumerations
enum	clock_name_t {   kCLOCK_CoreM4Clk,   kCLOCK_AxiClk,   kCLOCK_AhbClk,   kCLOCK_IpgClk }
	Clock name used to get clock frequency. More...
enum	clock_ip_name_t { ,   kCLOCK_Debug = CCM_TUPLE(4U, 32U),   kCLOCK_Dram = CCM_TUPLE(5U, 64U),   kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U),   kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U),   kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U),   kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U),   kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U),   kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U),   kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U),   kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U),   kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U),   kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U),   kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U),   kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U),   kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U),   kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U),   kCLOCK_I2c1 = CCM_TUPLE(23U, 90U),   kCLOCK_I2c2 = CCM_TUPLE(24U, 91U),   kCLOCK_I2c3 = CCM_TUPLE(25U, 92U),   kCLOCK_I2c4 = CCM_TUPLE(26U, 93U),   kCLOCK_Iomux0 = CCM_TUPLE(27U, 33U),   kCLOCK_Iomux1 = CCM_TUPLE(28U, 33U),   kCLOCK_Iomux2 = CCM_TUPLE(29U, 33U),   kCLOCK_Iomux3 = CCM_TUPLE(30U, 33U),   kCLOCK_Iomux4 = CCM_TUPLE(31U, 33U),   kCLOCK_Mu = CCM_TUPLE(33U, 33U),   kCLOCK_Ocram = CCM_TUPLE(35U, 16U),   kCLOCK_OcramS = CCM_TUPLE(36U, 32U),   kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U),   kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U),   kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U),   kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U),   kCLOCK_Qspi = CCM_TUPLE(47U, 87U),   kCLOCK_Rdc = CCM_TUPLE(49U, 33U),   kCLOCK_Sai1 = CCM_TUPLE(51U, 75U),   kCLOCK_Sai2 = CCM_TUPLE(52U, 76U),   kCLOCK_Sai3 = CCM_TUPLE(53U, 77U),   kCLOCK_Sai4 = CCM_TUPLE(54U, 78U),   kCLOCK_Sai5 = CCM_TUPLE(55U, 79U),   kCLOCK_Sai6 = CCM_TUPLE(56U, 80U),   kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U),   kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U),   kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U),   kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U),   kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U),   kCLOCK_Sim_display = CCM_TUPLE(63U, 16U),   kCLOCK_Sim_m = CCM_TUPLE(65U, 32U),   kCLOCK_Sim_main = CCM_TUPLE(66U, 16U),   kCLOCK_Sim_s = CCM_TUPLE(67U, 32U),   kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U),   kCLOCK_Uart1 = CCM_TUPLE(73U, 94U),   kCLOCK_Uart2 = CCM_TUPLE(74U, 95U),   kCLOCK_Uart3 = CCM_TUPLE(75U, 96U),   kCLOCK_Uart4 = CCM_TUPLE(76U, 97U),   kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U),   kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U),   kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U),   kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U),   kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U),   kCLOCK_Pdm = CCM_TUPLE(91U, 132U),   kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U),   kCLOCK_Sdma3 = CCM_TUPLE(95U, 35U),   kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF) }
	CCM CCGR gate control. More...
enum	clock_root_control_t {   kCLOCK_RootM4 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT),   kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT),   kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT),   kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT),   kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT),   kCLOCK_RootAudioAhb = (uint32_t)(&(CCM)->ROOT[34].TARGET_ROOT),   kCLOCK_RootAudioIpg = (uint32_t)(&(CCM)->ROOT[35].TARGET_ROOT),   kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT),   kCLOCK_RootSai1 = (uint32_t)(&(CCM)->ROOT[75].TARGET_ROOT),   kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT),   kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT),   kCLOCK_RootSai4 = (uint32_t)(&(CCM)->ROOT[78].TARGET_ROOT),   kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT),   kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT),   kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT),   kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT),   kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT),   kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT),   kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT),   kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT),   kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT),   kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT),   kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT),   kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT),   kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT),   kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT),   kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT),   kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT),   kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT),   kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT),   kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT),   kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT),   kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT),   kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT),   kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT),   kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT),   kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT),   kCLOCK_RootPdm = (uint32_t)(&(CCM)->ROOT[132].TARGET_ROOT) }
	ccm root name used to get clock frequency. More...
enum	clock_rootmux_m4_clk_sel_t {   kCLOCK_M4RootmuxOsc24M = 0U,   kCLOCK_M4RootmuxSysPll2Div5 = 1U,   kCLOCK_M4RootmuxSysPll2Div4 = 2U,   kCLOCK_M4RootmuxSysPll1Div3 = 3U,   kCLOCK_M4RootmuxSysPll1 = 4U,   kCLOCK_M4RootmuxAudioPll1 = 5U,   kCLOCK_M4RootmuxVideoPll1 = 6U,   kCLOCK_M4RootmuxSysPll3 = 7U }
	Root clock select enumeration for ARM Cortex-M4 core. More...
enum	clock_rootmux_axi_clk_sel_t {   kCLOCK_AxiRootmuxOsc24M = 0U,   kCLOCK_AxiRootmuxSysPll2Div3 = 1U,   kCLOCK_AxiRootmuxSysPll1 = 2U,   kCLOCK_AxiRootmuxSysPll2Div4 = 3U,   kCLOCK_AxiRootmuxSysPll2 = 4U,   kCLOCK_AxiRootmuxAudioPll1 = 5U,   kCLOCK_AxiRootmuxVideoPll1 = 6U,   kCLOCK_AxiRootmuxSysPll1Div8 = 7U }
	Root clock select enumeration for AXI bus. More...
enum	clock_rootmux_ahb_clk_sel_t {   kCLOCK_AhbRootmuxOsc24M = 0U,   kCLOCK_AhbRootmuxSysPll1Div6 = 1U,   kCLOCK_AhbRootmuxSysPll1 = 2U,   kCLOCK_AhbRootmuxSysPll1Div2 = 3U,   kCLOCK_AhbRootmuxSysPll2Div8 = 4U,   kCLOCK_AhbRootmuxSysPll3 = 5U,   kCLOCK_AhbRootmuxAudioPll1 = 6U,   kCLOCK_AhbRootmuxVideoPll1 = 7U }
	Root clock select enumeration for AHB bus. More...
enum	clock_rootmux_audio_ahb_clk_sel_t {   kCLOCK_AudioAhbRootmuxOsc24M = 0U,   kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U,   kCLOCK_AudioAhbRootmuxSysPll1 = 2U,   kCLOCK_AudioAhbRootmuxSysPll2 = 3U,   kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U,   kCLOCK_AudioAhbRootmuxSysPll3 = 5U,   kCLOCK_AudioAhbRootmuxAudioPll1 = 6U,   kCLOCK_AudioAhbRootmuxVideoPll1 = 7U }
	Root clock select enumeration for Audio AHB bus. More...
enum	clock_rootmux_qspi_clk_sel_t {   kCLOCK_QspiRootmuxOsc24M = 0U,   kCLOCK_QspiRootmuxSysPll1Div2 = 1U,   kCLOCK_QspiRootmuxSysPll2Div3 = 2U,   kCLOCK_QspiRootmuxSysPll2Div2 = 3U,   kCLOCK_QspiRootmuxAudioPll2 = 4U,   kCLOCK_QspiRootmuxSysPll1Div3 = 5U,   kCLOCK_QspiRootmuxSysPll3 = 6,   kCLOCK_QspiRootmuxSysPll1Div8 = 7U }
	Root clock select enumeration for QSPI peripheral. More...
enum	clock_rootmux_ecspi_clk_sel_t {   kCLOCK_EcspiRootmuxOsc24M = 0U,   kCLOCK_EcspiRootmuxSysPll2Div5 = 1U,   kCLOCK_EcspiRootmuxSysPll1Div20 = 2U,   kCLOCK_EcspiRootmuxSysPll1Div5 = 3U,   kCLOCK_EcspiRootmuxSysPll1 = 4U,   kCLOCK_EcspiRootmuxSysPll3 = 5U,   kCLOCK_EcspiRootmuxSysPll2Div4 = 6U,   kCLOCK_EcspiRootmuxAudioPll2 = 7U }
	Root clock select enumeration for ECSPI peripheral. More...
enum	clock_rootmux_i2c_clk_sel_t {   kCLOCK_I2cRootmuxOsc24M = 0U,   kCLOCK_I2cRootmuxSysPll1Div5 = 1U,   kCLOCK_I2cRootmuxSysPll2Div20 = 2U,   kCLOCK_I2cRootmuxSysPll3 = 3U,   kCLOCK_I2cRootmuxAudioPll1 = 4U,   kCLOCK_I2cRootmuxVideoPll1 = 5U,   kCLOCK_I2cRootmuxAudioPll2 = 6U,   kCLOCK_I2cRootmuxSysPll1Div6 = 7U }
	Root clock select enumeration for I2C peripheral. More...
enum	clock_rootmux_uart_clk_sel_t {   kCLOCK_UartRootmuxOsc24M = 0U,   kCLOCK_UartRootmuxSysPll1Div10 = 1U,   kCLOCK_UartRootmuxSysPll2Div5 = 2U,   kCLOCK_UartRootmuxSysPll2Div10 = 3U,   kCLOCK_UartRootmuxSysPll3 = 4U,   kCLOCK_UartRootmuxExtClk2 = 5U,   kCLOCK_UartRootmuxExtClk34 = 6U,   kCLOCK_UartRootmuxAudioPll2 = 7U }
	Root clock select enumeration for UART peripheral. More...
enum	clock_rootmux_gpt_t {   kCLOCK_GptRootmuxOsc24M = 0U,   kCLOCK_GptRootmuxSystemPll2Div10 = 1U,   kCLOCK_GptRootmuxSysPll1Div2 = 2U,   kCLOCK_GptRootmuxSysPll1Div20 = 3U,   kCLOCK_GptRootmuxVideoPll1 = 4U,   kCLOCK_GptRootmuxSystemPll1Div10 = 5U,   kCLOCK_GptRootmuxAudioPll1 = 6U,   kCLOCK_GptRootmuxExtClk123 = 7U }
	Root clock select enumeration for GPT peripheral. More...
enum	clock_rootmux_wdog_clk_sel_t {   kCLOCK_WdogRootmuxOsc24M = 0U,   kCLOCK_WdogRootmuxSysPll1Div6 = 1U,   kCLOCK_WdogRootmuxSysPll1Div5 = 2U,   kCLOCK_WdogRootmuxVpuPll = 3U,   kCLOCK_WdogRootmuxSystemPll2Div8 = 4U,   kCLOCK_WdogRootmuxSystemPll3 = 5U,   kCLOCK_WdogRootmuxSystemPll1Div10 = 6U,   kCLOCK_WdogRootmuxSystemPll2Div6 = 7U }
	Root clock select enumeration for WDOG peripheral. More...
enum	clock_rootmux_Pwm_clk_sel_t {   kCLOCK_PwmRootmuxOsc24M = 0U,   kCLOCK_PwmRootmuxSysPll2Div10 = 1U,   kCLOCK_PwmRootmuxSysPll1Div5 = 2U,   kCLOCK_PwmRootmuxSysPll1Div20 = 3U,   kCLOCK_PwmRootmuxSystemPll3 = 4U,   kCLOCK_PwmRootmuxExtClk12 = 5U,   kCLOCK_PwmRootmuxSystemPll1Div10 = 6U,   kCLOCK_PwmRootmuxVideoPll1 = 7U }
	Root clock select enumeration for PWM peripheral. More...
enum	clock_rootmux_sai_clk_sel_t {   kCLOCK_SaiRootmuxOsc24M = 0U,   kCLOCK_SaiRootmuxAudioPll1 = 1U,   kCLOCK_SaiRootmuxAudioPll2 = 2U,   kCLOCK_SaiRootmuxVideoPll1 = 3U,   kCLOCK_SaiRootmuxSysPll1Div6 = 4U,   kCLOCK_SaiRootmuxOsc26m = 5U,   kCLOCK_SaiRootmuxExtClk1 = 6U,   kCLOCK_SaiRootmuxExtClk2 = 7U }
	Root clock select enumeration for SAI peripheral. More...
enum	clock_rootmux_pdm_clk_sel_t {   kCLOCK_PdmRootmuxOsc24M = 0U,   kCLOCK_PdmRootmuxSystemPll2 = 1U,   kCLOCK_PdmRootmuxAudioPll1 = 2U,   kCLOCK_PdmRootmuxSysPll1 = 3U,   kCLOCK_PdmRootmuxSysPll2 = 4U,   kCLOCK_PdmRootmuxSysPll3 = 5U,   kCLOCK_PdmRootmuxExtClk3 = 6U,   kCLOCK_PdmRootmuxAudioPll2 = 7U }
	Root clock select enumeration for PDM peripheral. More...
enum	clock_rootmux_noc_clk_sel_t {   kCLOCK_NocRootmuxOsc24M = 0U,   kCLOCK_NocRootmuxSysPll1 = 1U,   kCLOCK_NocRootmuxSysPll3 = 2U,   kCLOCK_NocRootmuxSysPll2 = 3U,   kCLOCK_NocRootmuxSysPll2Div2 = 4U,   kCLOCK_NocRootmuxAudioPll1 = 5U,   kCLOCK_NocRootmuxVideoPll1 = 6U,   kCLOCK_NocRootmuxAudioPll2 = 7U }
	Root clock select enumeration for NOC CLK. More...
enum	clock_pll_gate_t {   kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL),   kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL),   kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL),   kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL),   kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL),   kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL),   kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL),   kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL),   kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL),   kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL),   kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL),   kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL),   kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL),   kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL),   kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL),   kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL),   kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL),   kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL),   kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL),   kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL),   kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL),   kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL),   kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL),   kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL),   kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL),   kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL),   kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL) }
	CCM PLL gate control. More...
enum	clock_gate_value_t {   kCLOCK_ClockNotNeeded = 0x0U,   kCLOCK_ClockNeededRun = 0x1111U,   kCLOCK_ClockNeededRunWait = 0x2222U,   kCLOCK_ClockNeededAll = 0x3333U }
	CCM gate control value. More...
enum	clock_pll_bypass_ctrl_t {   kCLOCK_AudioPll1BypassCtrl,   kCLOCK_AudioPll2BypassCtrl,   kCLOCK_VideoPll1BypassCtrl,   kCLOCK_DramPllInternalPll1BypassCtrl,   kCLOCK_GpuPLLPwrBypassCtrl,   kCLOCK_VpuPllPwrBypassCtrl,   kCLOCK_ArmPllPwrBypassCtrl,   kCLOCK_SysPll1InternalPll1BypassCtrl,   kCLOCK_SysPll2InternalPll1BypassCtrl,   kCLOCK_SysPll3InternalPll1BypassCtrl }
	PLL control names for PLL bypass. More...
enum	clock_pll_clke_t {   kCLOCK_AudioPll1Clke,   kCLOCK_AudioPll2Clke,   kCLOCK_VideoPll1Clke,   kCLOCK_DramPllClke,   kCLOCK_GpuPllClke,   kCLOCK_VpuPllClke,   kCLOCK_ArmPllClke,   kCLOCK_SystemPll1Clke,   kCLOCK_SystemPll1Div2Clke,   kCLOCK_SystemPll1Div3Clke,   kCLOCK_SystemPll1Div4Clke,   kCLOCK_SystemPll1Div5Clke,   kCLOCK_SystemPll1Div6Clke,   kCLOCK_SystemPll1Div8Clke,   kCLOCK_SystemPll1Div10Clke,   kCLOCK_SystemPll1Div20Clke,   kCLOCK_SystemPll2Clke,   kCLOCK_SystemPll2Div2Clke,   kCLOCK_SystemPll2Div3Clke,   kCLOCK_SystemPll2Div4Clke,   kCLOCK_SystemPll2Div5Clke,   kCLOCK_SystemPll2Div6Clke,   kCLOCK_SystemPll2Div8Clke,   kCLOCK_SystemPll2Div10Clke,   kCLOCK_SystemPll2Div20Clke,   kCLOCK_SystemPll3Clke }
	PLL clock names for clock enable/disable settings. More...
enum	clock_pll_ctrl_t
	ANALOG Power down override control.
enum	{   kANALOG_PllRefOsc24M = 0U,   kANALOG_PllPadClk = 1U }
	PLL reference clock select. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 2, 1))
	CLOCK driver version 2.2.1. More...

CCM Root Clock Setting
static void	CLOCK_SetRootMux (clock_root_control_t rootClk, uint32_t mux)
	Set clock root mux. More...
static uint32_t	CLOCK_GetRootMux (clock_root_control_t rootClk)
	Get clock root mux. More...
static void	CLOCK_EnableRoot (clock_root_control_t rootClk)
	Enable clock root. More...
static void	CLOCK_DisableRoot (clock_root_control_t rootClk)
	Disable clock root. More...
static bool	CLOCK_IsRootEnabled (clock_root_control_t rootClk)
	Check whether clock root is enabled. More...
void	CLOCK_UpdateRoot (clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)
	Update clock root in one step, for dynamical clock switching Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value. More...
void	CLOCK_SetRootDivider (clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)
	Set root clock divider Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value. More...
static uint32_t	CLOCK_GetRootPreDivider (clock_root_control_t rootClk)
	Get clock root PRE_PODF. More...
static uint32_t	CLOCK_GetRootPostDivider (clock_root_control_t rootClk)
	Get clock root POST_PODF. More...

CCM Gate Control
static void	CLOCK_ControlGate (uint32_t ccmGate, clock_gate_value_t control)
	lockrief Set PLL or CCGR gate control More...
void	CLOCK_EnableClock (clock_ip_name_t ccmGate)
	Enable CCGR clock gate and root clock gate for each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. More...
void	CLOCK_DisableClock (clock_ip_name_t ccmGate)
	Disable CCGR clock gate for the each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. More...

CCM Analog PLL Operatoin Functions
static void	CLOCK_PowerUpPll (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
	Power up PLL. More...
static void	CLOCK_PowerDownPll (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
	Power down PLL. More...
static void	CLOCK_SetPllBypass (CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
	PLL bypass setting. More...
static bool	CLOCK_IsPllBypassed (CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
	Check if PLL is bypassed. More...
static bool	CLOCK_IsPllLocked (CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
	Check if PLL clock is locked. More...
static void	CLOCK_EnableAnalogClock (CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
	Enable PLL clock. More...
static void	CLOCK_DisableAnalogClock (CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
	Disable PLL clock. More...
static void	CLOCK_OverridePllClke (CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
	Override PLL clock output enable. More...
static void	CLOCK_OverridePllPd (CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
	Override PLL power down. More...
void	CLOCK_InitArmPll (const ccm_analog_integer_pll_config_t *config)
	Initializes the ANALOG ARM PLL. More...
void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL.
void	CLOCK_InitSysPll1 (const ccm_analog_integer_pll_config_t *config)
	Initializes the ANALOG SYS PLL1. More...
void	CLOCK_DeinitSysPll1 (void)
	De-initialize the System PLL1.
void	CLOCK_InitSysPll2 (const ccm_analog_integer_pll_config_t *config)
	Initializes the ANALOG SYS PLL2. More...
void	CLOCK_DeinitSysPll2 (void)
	De-initialize the System PLL2.
void	CLOCK_InitSysPll3 (const ccm_analog_integer_pll_config_t *config)
	Initializes the ANALOG SYS PLL3. More...
void	CLOCK_DeinitSysPll3 (void)
	De-initialize the System PLL3.
void	CLOCK_InitAudioPll1 (const ccm_analog_frac_pll_config_t *config)
	Initializes the ANALOG AUDIO PLL1. More...
void	CLOCK_DeinitAudioPll1 (void)
	De-initialize the Audio PLL1.
void	CLOCK_InitAudioPll2 (const ccm_analog_frac_pll_config_t *config)
	Initializes the ANALOG AUDIO PLL2. More...
void	CLOCK_DeinitAudioPll2 (void)
	De-initialize the Audio PLL2.
void	CLOCK_InitVideoPll1 (const ccm_analog_frac_pll_config_t *config)
	Initializes the ANALOG VIDEO PLL1. More...
void	CLOCK_DeinitVideoPll1 (void)
	De-initialize the Video PLL1.
void	CLOCK_InitIntegerPll (CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type)
	Initializes the ANALOG Integer PLL. More...
uint32_t	CLOCK_GetIntegerPllFreq (CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)
	Get the ANALOG Integer PLL clock frequency. More...
void	CLOCK_InitFracPll (CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)
	Initializes the ANALOG Fractional PLL. More...
uint32_t	CLOCK_GetFracPllFreq (CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)
	Gets the ANALOG Fractional PLL clock frequency. More...
uint32_t	CLOCK_GetPllFreq (clock_pll_ctrl_t pll)
	Gets PLL clock frequency. More...
uint32_t	CLOCK_GetPllRefClkFreq (clock_pll_ctrl_t ctrl)
	Gets PLL reference clock frequency. More...

CCM Get frequency
uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...
uint32_t	CLOCK_GetCoreM4Freq (void)
	Get the CCM Cortex M4 core frequency. More...
uint32_t	CLOCK_GetAxiFreq (void)
	Get the CCM Axi bus frequency. More...
uint32_t	CLOCK_GetAhbFreq (void)
	Get the CCM Ahb bus frequency. More...

---

Data Structure Documentation

struct ccm_analog_frac_pll_config_t

Note: all the dividers in this configuration structure are the actually divider, software will map it to register value

Data Fields
uint8_t	refSel
	pll reference clock sel
uint32_t	mainDiv
	Value of the 10-bit programmable main-divider, range must be 64~1023.
uint32_t	dsm
	Value of 16-bit DSM.
uint8_t	preDiv
	Value of the 6-bit programmable pre-divider, range must be 1~63.
uint8_t	postDiv
	Value of the 3-bit programmable Scaler, range must be 0~6.

struct ccm_analog_integer_pll_config_t

Note: all the dividers in this configuration structure are the actually divider, software will map it to register value

Data Fields
uint8_t	refSel
	pll reference clock sel
uint32_t	mainDiv
	Value of the 10-bit programmable main-divider, range must be 64~1023.
uint8_t	preDiv
	Value of the 6-bit programmable pre-divider, range must be 1~63.
uint8_t	postDiv
	Value of the 3-bit programmable Scaler, range must be 0~6.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 2, 1))

#define ECSPI_CLOCKS

Value:

{                                                                  \
        kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
    }

#define GPIO_CLOCKS

Value:

{                                                                                           \
        kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
    }

#define GPT_CLOCKS

Value:

{                                                                                                   \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
    }

#define I2C_CLOCKS

Value:

{                                                                         \
        kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
    }

#define IOMUX_CLOCKS

Value:

{                                                                                   \
        kCLOCK_Iomuxc0, kCLOCK_Iomuxc1, kCLOCK_Iomuxc2, kCLOCK_Iomuxc3, kCLOCK_Iomuxc4, \
    }

#define PWM_CLOCKS

Value:

{                                                                         \
        kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
    }

#define RDC_CLOCKS

Value:

{               \
        kCLOCK_Rdc, \
    }

#define SAI_CLOCKS

Value:

{                                                                                                   \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
    }

#define RDC_SEMA42_CLOCKS

Value:

{                                                      \
        kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
    }

#define UART_CLOCKS

Value:

{                                                                             \
        kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
    }

#define USDHC_CLOCKS

Value:

{                                                                 \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
    }

#define WDOG_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
    }

#define TMU_CLOCKS

Value:

{                      \
        kCLOCK_TempSensor, \
    }

#define SDMA_CLOCKS

Value:

{                                            \
        kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3 \
    }

#define MU_CLOCKS

Value:

{             \
        kCLOCK_Mu \
    }

#define QSPI_CLOCKS

Value:

{               \
        kCLOCK_Qspi \
    }

#define PDM_CLOCKS

Value:

{              \
        kCLOCK_Pdm \
    }

#define kCLOCK_CoreSysClk   kCLOCK_CoreM4Clk

#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCoreM4Freq

Enumeration Type Documentation

enum clock_name_t

Enumerator
kCLOCK_CoreM4Clk	ARM M4 Core clock.
kCLOCK_AxiClk	Main AXI bus clock.
kCLOCK_AhbClk	AHB bus clock.
kCLOCK_IpgClk	IPG bus clock.

enum clock_ip_name_t

Enumerator
kCLOCK_Debug	DEBUG Clock Gate.
kCLOCK_Dram	DRAM Clock Gate.
kCLOCK_Ecspi1	ECSPI1 Clock Gate.
kCLOCK_Ecspi2	ECSPI2 Clock Gate.
kCLOCK_Ecspi3	ECSPI3 Clock Gate.
kCLOCK_Gpio1	GPIO1 Clock Gate.
kCLOCK_Gpio2	GPIO2 Clock Gate.
kCLOCK_Gpio3	GPIO3 Clock Gate.
kCLOCK_Gpio4	GPIO4 Clock Gate.
kCLOCK_Gpio5	GPIO5 Clock Gate.
kCLOCK_Gpt1	GPT1 Clock Gate.
kCLOCK_Gpt2	GPT2 Clock Gate.
kCLOCK_Gpt3	GPT3 Clock Gate.
kCLOCK_Gpt4	GPT4 Clock Gate.
kCLOCK_Gpt5	GPT5 Clock Gate.
kCLOCK_Gpt6	GPT6 Clock Gate.
kCLOCK_I2c1	I2C1 Clock Gate.
kCLOCK_I2c2	I2C2 Clock Gate.
kCLOCK_I2c3	I2C3 Clock Gate.
kCLOCK_I2c4	I2C4 Clock Gate.
kCLOCK_Iomux0	IOMUX Clock Gate.
kCLOCK_Iomux1	IOMUX Clock Gate.
kCLOCK_Iomux2	IOMUX Clock Gate.
kCLOCK_Iomux3	IOMUX Clock Gate.
kCLOCK_Iomux4	IOMUX Clock Gate.
kCLOCK_Mu	MU Clock Gate.
kCLOCK_Ocram	OCRAM Clock Gate.
kCLOCK_OcramS	OCRAM S Clock Gate.
kCLOCK_Pwm1	PWM1 Clock Gate.
kCLOCK_Pwm2	PWM2 Clock Gate.
kCLOCK_Pwm3	PWM3 Clock Gate.
kCLOCK_Pwm4	PWM4 Clock Gate.
kCLOCK_Qspi	QSPI Clock Gate.
kCLOCK_Rdc	RDC Clock Gate.
kCLOCK_Sai1	SAI1 Clock Gate.
kCLOCK_Sai2	SAI2 Clock Gate.
kCLOCK_Sai3	SAI3 Clock Gate.
kCLOCK_Sai4	SAI4 Clock Gate.
kCLOCK_Sai5	SAI5 Clock Gate.
kCLOCK_Sai6	SAI6 Clock Gate.
kCLOCK_Sdma1	SDMA1 Clock Gate.
kCLOCK_Sdma2	SDMA2 Clock Gate.
kCLOCK_Sec_Debug	SEC_DEBUG Clock Gate.
kCLOCK_Sema42_1	RDC SEMA42 Clock Gate.
kCLOCK_Sema42_2	RDC SEMA42 Clock Gate.
kCLOCK_Sim_display	SIM_Display Clock Gate.
kCLOCK_Sim_m	SIM_M Clock Gate.
kCLOCK_Sim_main	SIM_MAIN Clock Gate.
kCLOCK_Sim_s	SIM_S Clock Gate.
kCLOCK_Sim_wakeup	SIM_WAKEUP Clock Gate.
kCLOCK_Uart1	UART1 Clock Gate.
kCLOCK_Uart2	UART2 Clock Gate.
kCLOCK_Uart3	UART3 Clock Gate.
kCLOCK_Uart4	UART4 Clock Gate.
kCLOCK_Usdhc1	USDHC1 Clock Gate.
kCLOCK_Usdhc2	USDHC2 Clock Gate.
kCLOCK_Wdog1	WDOG1 Clock Gate.
kCLOCK_Wdog2	WDOG2 Clock Gate.
kCLOCK_Wdog3	WDOG3 Clock Gate.
kCLOCK_Pdm	PDM Clock Gate.
kCLOCK_Usdhc3	USDHC3 Clock Gate.
kCLOCK_Sdma3	SDMA3 Clock Gate.
kCLOCK_TempSensor	TempSensor Clock Gate.

enum clock_root_control_t

Enumerator
kCLOCK_RootM4	ARM Cortex-M4 Clock control name.
kCLOCK_RootAxi	AXI Clock control name.
kCLOCK_RootNoc	NOC Clock control name.
kCLOCK_RootAhb	AHB Clock control name.
kCLOCK_RootIpg	IPG Clock control name.
kCLOCK_RootAudioAhb	Audio AHB Clock control name.
kCLOCK_RootAudioIpg	Audio IPG Clock control name.
kCLOCK_RootDramAlt	DRAM ALT Clock control name.
kCLOCK_RootSai1	SAI1 Clock control name.
kCLOCK_RootSai2	SAI2 Clock control name.
kCLOCK_RootSai3	SAI3 Clock control name.
kCLOCK_RootSai4	SAI4 Clock control name.
kCLOCK_RootSai5	SAI5 Clock control name.
kCLOCK_RootSai6	SAI6 Clock control name.
kCLOCK_RootQspi	QSPI Clock control name.
kCLOCK_RootI2c1	I2C1 Clock control name.
kCLOCK_RootI2c2	I2C2 Clock control name.
kCLOCK_RootI2c3	I2C3 Clock control name.
kCLOCK_RootI2c4	I2C4 Clock control name.
kCLOCK_RootUart1	UART1 Clock control name.
kCLOCK_RootUart2	UART2 Clock control name.
kCLOCK_RootUart3	UART3 Clock control name.
kCLOCK_RootUart4	UART4 Clock control name.
kCLOCK_RootEcspi1	ECSPI1 Clock control name.
kCLOCK_RootEcspi2	ECSPI2 Clock control name.
kCLOCK_RootEcspi3	ECSPI3 Clock control name.
kCLOCK_RootPwm1	PWM1 Clock control name.
kCLOCK_RootPwm2	PWM2 Clock control name.
kCLOCK_RootPwm3	PWM3 Clock control name.
kCLOCK_RootPwm4	PWM4 Clock control name.
kCLOCK_RootGpt1	GPT1 Clock control name.
kCLOCK_RootGpt2	GPT2 Clock control name.
kCLOCK_RootGpt3	GPT3 Clock control name.
kCLOCK_RootGpt4	GPT4 Clock control name.
kCLOCK_RootGpt5	GPT5 Clock control name.
kCLOCK_RootGpt6	GPT6 Clock control name.
kCLOCK_RootWdog	WDOG Clock control name.
kCLOCK_RootPdm	PDM Clock control name.

enum clock_rootmux_m4_clk_sel_t

Enumerator
kCLOCK_M4RootmuxOsc24M	ARM Cortex-M4 Clock from OSC 24M.
kCLOCK_M4RootmuxSysPll2Div5	ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.
kCLOCK_M4RootmuxSysPll2Div4	ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.
kCLOCK_M4RootmuxSysPll1Div3	ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.
kCLOCK_M4RootmuxSysPll1	ARM Cortex-M4 Clock from SYSTEM PLL1.
kCLOCK_M4RootmuxAudioPll1	ARM Cortex-M4 Clock from AUDIO PLL1.
kCLOCK_M4RootmuxVideoPll1	ARM Cortex-M4 Clock from VIDEO PLL1.
kCLOCK_M4RootmuxSysPll3	ARM Cortex-M4 Clock from SYSTEM PLL3.

enum clock_rootmux_axi_clk_sel_t

Enumerator
kCLOCK_AxiRootmuxOsc24M	ARM AXI Clock from OSC 24M.
kCLOCK_AxiRootmuxSysPll2Div3	ARM AXI Clock from SYSTEM PLL2 divided by 3.
kCLOCK_AxiRootmuxSysPll1	ARM AXI Clock from SYSTEM PLL1.
kCLOCK_AxiRootmuxSysPll2Div4	ARM AXI Clock from SYSTEM PLL2 divided by 4.
kCLOCK_AxiRootmuxSysPll2	ARM AXI Clock from SYSTEM PLL2.
kCLOCK_AxiRootmuxAudioPll1	ARM AXI Clock from AUDIO PLL1.
kCLOCK_AxiRootmuxVideoPll1	ARM AXI Clock from VIDEO PLL1.
kCLOCK_AxiRootmuxSysPll1Div8	ARM AXI Clock from SYSTEM PLL1 divided by 8.

enum clock_rootmux_ahb_clk_sel_t

Enumerator
kCLOCK_AhbRootmuxOsc24M	ARM AHB Clock from OSC 24M.
kCLOCK_AhbRootmuxSysPll1Div6	ARM AHB Clock from SYSTEM PLL1 divided by 6.
kCLOCK_AhbRootmuxSysPll1	ARM AHB Clock from SYSTEM PLL1.
kCLOCK_AhbRootmuxSysPll1Div2	ARM AHB Clock from SYSTEM PLL1 divided by 2.
kCLOCK_AhbRootmuxSysPll2Div8	ARM AHB Clock from SYSTEM PLL2 divided by 8.
kCLOCK_AhbRootmuxSysPll3	ARM AHB Clock from SYSTEM PLL3.
kCLOCK_AhbRootmuxAudioPll1	ARM AHB Clock from AUDIO PLL1.
kCLOCK_AhbRootmuxVideoPll1	ARM AHB Clock from VIDEO PLL1.

enum clock_rootmux_audio_ahb_clk_sel_t

Enumerator
kCLOCK_AudioAhbRootmuxOsc24M	ARM Audio AHB Clock from OSC 24M.
kCLOCK_AudioAhbRootmuxSysPll2Div2	ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.
kCLOCK_AudioAhbRootmuxSysPll1	ARM Audio AHB Clock from SYSTEM PLL1.
kCLOCK_AudioAhbRootmuxSysPll2	ARM Audio AHB Clock from SYSTEM PLL2.
kCLOCK_AudioAhbRootmuxSysPll2Div6	ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.
kCLOCK_AudioAhbRootmuxSysPll3	ARM Audio AHB Clock from SYSTEM PLL3.
kCLOCK_AudioAhbRootmuxAudioPll1	ARM Audio AHB Clock from AUDIO PLL1.
kCLOCK_AudioAhbRootmuxVideoPll1	ARM Audio AHB Clock from VIDEO PLL1.

enum clock_rootmux_qspi_clk_sel_t

Enumerator
kCLOCK_QspiRootmuxOsc24M	ARM QSPI Clock from OSC 24M.
kCLOCK_QspiRootmuxSysPll1Div2	ARM QSPI Clock from SYSTEM PLL1 divided by 2.
kCLOCK_QspiRootmuxSysPll2Div3	ARM QSPI Clock from SYSTEM PLL2 divided by 3.
kCLOCK_QspiRootmuxSysPll2Div2	ARM QSPI Clock from SYSTEM PLL2 divided by 2.
kCLOCK_QspiRootmuxAudioPll2	ARM QSPI Clock from AUDIO PLL2.
kCLOCK_QspiRootmuxSysPll1Div3	ARM QSPI Clock from SYSTEM PLL1 divided by 3.
kCLOCK_QspiRootmuxSysPll3	ARM QSPI Clock from SYSTEM PLL3.
kCLOCK_QspiRootmuxSysPll1Div8	ARM QSPI Clock from SYSTEM PLL1 divided by 8.

enum clock_rootmux_ecspi_clk_sel_t

Enumerator
kCLOCK_EcspiRootmuxOsc24M	ECSPI Clock from OSC 24M.
kCLOCK_EcspiRootmuxSysPll2Div5	ECSPI Clock from SYSTEM PLL2 divided by 5.
kCLOCK_EcspiRootmuxSysPll1Div20	ECSPI Clock from SYSTEM PLL1 divided by 20.
kCLOCK_EcspiRootmuxSysPll1Div5	ECSPI Clock from SYSTEM PLL1 divided by 5.
kCLOCK_EcspiRootmuxSysPll1	ECSPI Clock from SYSTEM PLL1.
kCLOCK_EcspiRootmuxSysPll3	ECSPI Clock from SYSTEM PLL3.
kCLOCK_EcspiRootmuxSysPll2Div4	ECSPI Clock from SYSTEM PLL2 divided by 4.
kCLOCK_EcspiRootmuxAudioPll2	ECSPI Clock from AUDIO PLL2.

enum clock_rootmux_i2c_clk_sel_t

Enumerator
kCLOCK_I2cRootmuxOsc24M	I2C Clock from OSC 24M.
kCLOCK_I2cRootmuxSysPll1Div5	I2C Clock from SYSTEM PLL1 divided by 5.
kCLOCK_I2cRootmuxSysPll2Div20	I2C Clock from SYSTEM PLL2 divided by 20.
kCLOCK_I2cRootmuxSysPll3	I2C Clock from SYSTEM PLL3 .
kCLOCK_I2cRootmuxAudioPll1	I2C Clock from AUDIO PLL1.
kCLOCK_I2cRootmuxVideoPll1	I2C Clock from VIDEO PLL1.
kCLOCK_I2cRootmuxAudioPll2	I2C Clock from AUDIO PLL2.
kCLOCK_I2cRootmuxSysPll1Div6	I2C Clock from SYSTEM PLL1 divided by 6.

enum clock_rootmux_uart_clk_sel_t

Enumerator
kCLOCK_UartRootmuxOsc24M	UART Clock from OSC 24M.
kCLOCK_UartRootmuxSysPll1Div10	UART Clock from SYSTEM PLL1 divided by 10.
kCLOCK_UartRootmuxSysPll2Div5	UART Clock from SYSTEM PLL2 divided by 5.
kCLOCK_UartRootmuxSysPll2Div10	UART Clock from SYSTEM PLL2 divided by 10.
kCLOCK_UartRootmuxSysPll3	UART Clock from SYSTEM PLL3.
kCLOCK_UartRootmuxExtClk2	UART Clock from External Clock 2.
kCLOCK_UartRootmuxExtClk34	UART Clock from External Clock 3, External Clock 4.
kCLOCK_UartRootmuxAudioPll2	UART Clock from Audio PLL2.

enum clock_rootmux_gpt_t

Enumerator
kCLOCK_GptRootmuxOsc24M	GPT Clock from OSC 24M.
kCLOCK_GptRootmuxSystemPll2Div10	GPT Clock from SYSTEM PLL2 divided by 10.
kCLOCK_GptRootmuxSysPll1Div2	GPT Clock from SYSTEM PLL1 divided by 2.
kCLOCK_GptRootmuxSysPll1Div20	GPT Clock from SYSTEM PLL1 divided by 20.
kCLOCK_GptRootmuxVideoPll1	GPT Clock from VIDEO PLL1.
kCLOCK_GptRootmuxSystemPll1Div10	GPT Clock from SYSTEM PLL1 divided by 10.
kCLOCK_GptRootmuxAudioPll1	GPT Clock from AUDIO PLL1.
kCLOCK_GptRootmuxExtClk123	GPT Clock from External Clock1, External Clock2, External Clock3.

enum clock_rootmux_wdog_clk_sel_t

Enumerator
kCLOCK_WdogRootmuxOsc24M	WDOG Clock from OSC 24M.
kCLOCK_WdogRootmuxSysPll1Div6	WDOG Clock from SYSTEM PLL1 divided by 6.
kCLOCK_WdogRootmuxSysPll1Div5	WDOG Clock from SYSTEM PLL1 divided by 5.
kCLOCK_WdogRootmuxVpuPll	WDOG Clock from VPU DLL.
kCLOCK_WdogRootmuxSystemPll2Div8	WDOG Clock from SYSTEM PLL2 divided by 8.
kCLOCK_WdogRootmuxSystemPll3	WDOG Clock from SYSTEM PLL3.
kCLOCK_WdogRootmuxSystemPll1Div10	WDOG Clock from SYSTEM PLL1 divided by 10.
kCLOCK_WdogRootmuxSystemPll2Div6	WDOG Clock from SYSTEM PLL2 divided by 6.

enum clock_rootmux_Pwm_clk_sel_t

Enumerator
kCLOCK_PwmRootmuxOsc24M	PWM Clock from OSC 24M.
kCLOCK_PwmRootmuxSysPll2Div10	PWM Clock from SYSTEM PLL2 divided by 10.
kCLOCK_PwmRootmuxSysPll1Div5	PWM Clock from SYSTEM PLL1 divided by 5.
kCLOCK_PwmRootmuxSysPll1Div20	PWM Clock from SYSTEM PLL1 divided by 20.
kCLOCK_PwmRootmuxSystemPll3	PWM Clock from SYSTEM PLL3.
kCLOCK_PwmRootmuxExtClk12	PWM Clock from External Clock1, External Clock2.
kCLOCK_PwmRootmuxSystemPll1Div10	PWM Clock from SYSTEM PLL1 divided by 10.
kCLOCK_PwmRootmuxVideoPll1	PWM Clock from VIDEO PLL1.

enum clock_rootmux_sai_clk_sel_t

Enumerator
kCLOCK_SaiRootmuxOsc24M	SAI Clock from OSC 24M.
kCLOCK_SaiRootmuxAudioPll1	SAI Clock from AUDIO PLL1.
kCLOCK_SaiRootmuxAudioPll2	SAI Clock from AUDIO PLL2.
kCLOCK_SaiRootmuxVideoPll1	SAI Clock from VIDEO PLL1.
kCLOCK_SaiRootmuxSysPll1Div6	SAI Clock from SYSTEM PLL1 divided by 6.
kCLOCK_SaiRootmuxOsc26m	SAI Clock from OSC HDMI 26M.
kCLOCK_SaiRootmuxExtClk1	SAI Clock from External Clock1, External Clock2, External Clock3.
kCLOCK_SaiRootmuxExtClk2	SAI Clock from External Clock2, External Clock3, External Clock4.

enum clock_rootmux_pdm_clk_sel_t

Enumerator
kCLOCK_PdmRootmuxOsc24M	GPT Clock from OSC 24M.
kCLOCK_PdmRootmuxSystemPll2	GPT Clock from SYSTEM PLL2 divided by 10.
kCLOCK_PdmRootmuxAudioPll1	GPT Clock from SYSTEM PLL1 divided by 2.
kCLOCK_PdmRootmuxSysPll1	GPT Clock from SYSTEM PLL1 divided by 20.
kCLOCK_PdmRootmuxSysPll2	GPT Clock from VIDEO PLL1.
kCLOCK_PdmRootmuxSysPll3	GPT Clock from SYSTEM PLL1 divided by 10.
kCLOCK_PdmRootmuxExtClk3	GPT Clock from AUDIO PLL1.
kCLOCK_PdmRootmuxAudioPll2	GPT Clock from External Clock1, External Clock2, External Clock3.

enum clock_rootmux_noc_clk_sel_t

Enumerator
kCLOCK_NocRootmuxOsc24M	NOC Clock from OSC 24M.
kCLOCK_NocRootmuxSysPll1	NOC Clock from SYSTEM PLL1.
kCLOCK_NocRootmuxSysPll3	NOC Clock from SYSTEM PLL3.
kCLOCK_NocRootmuxSysPll2	NOC Clock from SYSTEM PLL2.
kCLOCK_NocRootmuxSysPll2Div2	NOC Clock from SYSTEM PLL2 divided by 2.
kCLOCK_NocRootmuxAudioPll1	NOC Clock from AUDIO PLL1.
kCLOCK_NocRootmuxVideoPll1	NOC Clock from VIDEO PLL1.
kCLOCK_NocRootmuxAudioPll2	NOC Clock from AUDIO PLL2.

enum clock_pll_gate_t

Enumerator
kCLOCK_ArmPllGate	ARM PLL Gate.
kCLOCK_GpuPllGate	GPU PLL Gate.
kCLOCK_VpuPllGate	VPU PLL Gate.
kCLOCK_DramPllGate	DRAM PLL1 Gate.
kCLOCK_SysPll1Gate	SYSTEM PLL1 Gate.
kCLOCK_SysPll1Div2Gate	SYSTEM PLL1 Div2 Gate.
kCLOCK_SysPll1Div3Gate	SYSTEM PLL1 Div3 Gate.
kCLOCK_SysPll1Div4Gate	SYSTEM PLL1 Div4 Gate.
kCLOCK_SysPll1Div5Gate	SYSTEM PLL1 Div5 Gate.
kCLOCK_SysPll1Div6Gate	SYSTEM PLL1 Div6 Gate.
kCLOCK_SysPll1Div8Gate	SYSTEM PLL1 Div8 Gate.
kCLOCK_SysPll1Div10Gate	SYSTEM PLL1 Div10 Gate.
kCLOCK_SysPll1Div20Gate	SYSTEM PLL1 Div20 Gate.
kCLOCK_SysPll2Gate	SYSTEM PLL2 Gate.
kCLOCK_SysPll2Div2Gate	SYSTEM PLL2 Div2 Gate.
kCLOCK_SysPll2Div3Gate	SYSTEM PLL2 Div3 Gate.
kCLOCK_SysPll2Div4Gate	SYSTEM PLL2 Div4 Gate.
kCLOCK_SysPll2Div5Gate	SYSTEM PLL2 Div5 Gate.
kCLOCK_SysPll2Div6Gate	SYSTEM PLL2 Div6 Gate.
kCLOCK_SysPll2Div8Gate	SYSTEM PLL2 Div8 Gate.
kCLOCK_SysPll2Div10Gate	SYSTEM PLL2 Div10 Gate.
kCLOCK_SysPll2Div20Gate	SYSTEM PLL2 Div20 Gate.
kCLOCK_SysPll3Gate	SYSTEM PLL3 Gate.
kCLOCK_AudioPll1Gate	AUDIO PLL1 Gate.
kCLOCK_AudioPll2Gate	AUDIO PLL2 Gate.
kCLOCK_VideoPll1Gate	VIDEO PLL1 Gate.
kCLOCK_VideoPll2Gate	VIDEO PLL2 Gate.

enum clock_gate_value_t

Enumerator
kCLOCK_ClockNotNeeded	Clock always disabled.
kCLOCK_ClockNeededRun	Clock enabled when CPU is running.
kCLOCK_ClockNeededRunWait	Clock enabled when CPU is running or in WAIT mode.
kCLOCK_ClockNeededAll	Clock always enabled.

enum clock_pll_bypass_ctrl_t

These constants define the PLL control names for PLL bypass.

• 0:15: REG offset to CCM_ANALOG_BASE in bytes.
• 16:20: bypass bit shift.

Enumerator
kCLOCK_AudioPll1BypassCtrl	CCM Audio PLL1 bypass Control.
kCLOCK_AudioPll2BypassCtrl	CCM Audio PLL2 bypass Control.
kCLOCK_VideoPll1BypassCtrl	CCM Video Pll1 bypass Control.
kCLOCK_DramPllInternalPll1BypassCtrl	CCM DRAM PLL bypass Control.
kCLOCK_GpuPLLPwrBypassCtrl	CCM Gpu PLL bypass Control.
kCLOCK_VpuPllPwrBypassCtrl	CCM Vpu PLL bypass Control.
kCLOCK_ArmPllPwrBypassCtrl	CCM Arm PLL bypass Control.
kCLOCK_SysPll1InternalPll1BypassCtrl	CCM System PLL1 bypass Control.
kCLOCK_SysPll2InternalPll1BypassCtrl	CCM System PLL2 bypass Control.
kCLOCK_SysPll3InternalPll1BypassCtrl	CCM System PLL3 bypass Control.

enum clock_pll_clke_t

These constants define the PLL clock names for PLL clock enable/disable operations.

• 0:15: REG offset to CCM_ANALOG_BASE in bytes.
• 16:20: Clock enable bit shift.

Enumerator
kCLOCK_AudioPll1Clke	Audio pll1 clke.
kCLOCK_AudioPll2Clke	Audio pll2 clke.
kCLOCK_VideoPll1Clke	Video pll1 clke.
kCLOCK_DramPllClke	Dram pll clke.
kCLOCK_GpuPllClke	Gpu pll clke.
kCLOCK_VpuPllClke	Vpu pll clke.
kCLOCK_ArmPllClke	Arm pll clke.
kCLOCK_SystemPll1Clke	System pll1 clke.
kCLOCK_SystemPll1Div2Clke	System pll1 Div2 clke.
kCLOCK_SystemPll1Div3Clke	System pll1 Div3 clke.
kCLOCK_SystemPll1Div4Clke	System pll1 Div4 clke.
kCLOCK_SystemPll1Div5Clke	System pll1 Div5 clke.
kCLOCK_SystemPll1Div6Clke	System pll1 Div6 clke.
kCLOCK_SystemPll1Div8Clke	System pll1 Div8 clke.
kCLOCK_SystemPll1Div10Clke	System pll1 Div10 clke.
kCLOCK_SystemPll1Div20Clke	System pll1 Div20 clke.
kCLOCK_SystemPll2Clke	System pll2 clke.
kCLOCK_SystemPll2Div2Clke	System pll2 Div2 clke.
kCLOCK_SystemPll2Div3Clke	System pll2 Div3 clke.
kCLOCK_SystemPll2Div4Clke	System pll2 Div4 clke.
kCLOCK_SystemPll2Div5Clke	System pll2 Div5 clke.
kCLOCK_SystemPll2Div6Clke	System pll2 Div6 clke.
kCLOCK_SystemPll2Div8Clke	System pll2 Div8 clke.
kCLOCK_SystemPll2Div10Clke	System pll2 Div10 clke.
kCLOCK_SystemPll2Div20Clke	System pll2 Div20 clke.
kCLOCK_SystemPll3Clke	System pll3 clke.

anonymous enum

Enumerator
kANALOG_PllRefOsc24M	reference OSC 24M
kANALOG_PllPadClk	reference PAD CLK

Function Documentation

static void CLOCK_SetRootMux ( clock_root_control_t  rootClk, uint32_t  mux  )

inlinestatic

User maybe need to set more than one mux ROOT according to the clock tree description in the reference manual.

Parameters

rootClk	Root clock control (see clock_root_control_t enumeration).
mux	Root mux value (see _ccm_rootmux_xxx enumeration).

static uint32_t CLOCK_GetRootMux ( clock_root_control_t  rootClk )

inlinestatic

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

Parameters

rootClk

Root clock control (see clock_root_control_t enumeration).

Returns

Root mux value (see _ccm_rootmux_xxx enumeration).

static void CLOCK_EnableRoot ( clock_root_control_t  rootClk )

inlinestatic

Parameters

base	CCM base pointer.
rootClk	Root clock control (see clock_root_control_t enumeration)

static void CLOCK_DisableRoot ( clock_root_control_t  rootClk )

inlinestatic

Parameters

base	CCM base pointer.
rootClk	Root control (see clock_root_control_t enumeration)

static bool CLOCK_IsRootEnabled ( clock_root_control_t  rootClk )

inlinestatic

Parameters

base	CCM base pointer.
rootClk	Root control (see clock_root_control_t enumeration)

Returns

CCM root enabled or not.

• true: Clock root is enabled.
• false: Clock root is disabled.

void CLOCK_UpdateRoot	(	clock_root_control_t	ccmRootClk,
		uint32_t	mux,
		uint32_t	pre,
		uint32_t	post
	)

Parameters

ccmRootClk	Root control (see clock_root_control_t enumeration)
root	mux value (see _ccm_rootmux_xxx enumeration)
pre	Pre divider value (0-7, divider=n+1)
post	Post divider value (0-63, divider=n+1)

void CLOCK_SetRootDivider	(	clock_root_control_t	ccmRootClk,
		uint32_t	pre,
		uint32_t	post
	)

Parameters

ccmRootClk	Root control (see clock_root_control_t enumeration)
pre	Pre divider value (1-8)
post	Post divider value (1-64)

static uint32_t CLOCK_GetRootPreDivider ( clock_root_control_t  rootClk )

inlinestatic

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

Parameters

rootClk

Root clock name (see clock_root_control_t enumeration).

Returns

Root Pre divider value.

static uint32_t CLOCK_GetRootPostDivider ( clock_root_control_t  rootClk )

inlinestatic

In order to get the clock source of root, user maybe need to get more than one ROOT's mux value to obtain the final clock source of root.

Parameters

rootClk

Root clock name (see clock_root_control_t enumeration).

Returns

Root Post divider value.

static void CLOCK_ControlGate ( uint32_t  ccmGate, clock_gate_value_t  control  )

inlinestatic

base CCM base pointer.

Parameters

ccmGate	Gate control (see clock_pll_gate_t and clock_ip_name_t enumeration)
control	Gate control value (see clock_gate_value_t)

void CLOCK_EnableClock

(

clock_ip_name_t

ccmGate

)

Take care of that one module may need to set more than one clock gate.

Parameters

ccmGate

Gate control for each module (see clock_ip_name_t enumeration).

void CLOCK_DisableClock

(

clock_ip_name_t

ccmGate

)

Take care of that one module may need to set more than one clock gate.

Parameters

ccmGate

Gate control for each module (see clock_ip_name_t enumeration).

static void CLOCK_PowerUpPll ( CCM_ANALOG_Type *  base, clock_pll_ctrl_t  pllControl  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllControl	PLL control name (see clock_pll_ctrl_t enumeration)

static void CLOCK_PowerDownPll ( CCM_ANALOG_Type *  base, clock_pll_ctrl_t  pllControl  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllControl	PLL control name (see clock_pll_ctrl_t enumeration)

static void CLOCK_SetPllBypass ( CCM_ANALOG_Type *  base, clock_pll_bypass_ctrl_t  pllControl, bool  bypass  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllControl	PLL control name (see ccm_analog_pll_control_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false: Do not bypass the PLL.

static bool CLOCK_IsPllBypassed ( CCM_ANALOG_Type *  base, clock_pll_bypass_ctrl_t  pllControl  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllControl	PLL control name (see ccm_analog_pll_control_t enumeration)

Returns

PLL bypass status.

• true: The PLL is bypassed.
• false: The PLL is not bypassed.

static bool CLOCK_IsPllLocked ( CCM_ANALOG_Type *  base, clock_pll_ctrl_t  pllControl  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllControl	PLL control name (see clock_pll_ctrl_t enumeration)

Returns

PLL lock status.

• true: The PLL clock is locked.
• false: The PLL clock is not locked.

static void CLOCK_EnableAnalogClock ( CCM_ANALOG_Type *  base, clock_pll_clke_t  pllClock  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllClock	PLL clock name (see ccm_analog_pll_clock_t enumeration)

static void CLOCK_DisableAnalogClock ( CCM_ANALOG_Type *  base, clock_pll_clke_t  pllClock  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pllClock	PLL clock name (see ccm_analog_pll_clock_t enumeration)

static void CLOCK_OverridePllClke ( CCM_ANALOG_Type *  base, clock_pll_clke_t  ovClock, bool  override  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
ovClock	PLL clock name (see clock_pll_clke_t enumeration)
override	Override the PLL. true: Override the PLL clke, CCM will handle it. false: Do not override the PLL clke.

static void CLOCK_OverridePllPd ( CCM_ANALOG_Type *  base, clock_pll_ctrl_t  pdClock, bool  override  )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pdClock	PLL clock name (see clock_pll_ctrl_t enumeration)
override	Override the PLL. true: Override the PLL clke, CCM will handle it. false: Do not override the PLL clke.

void CLOCK_InitArmPll

(

const ccm_analog_integer_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_integer_pll_config_t enumeration).

Note

This function can't detect whether the Arm PLL has been enabled and used by some IPs.

void CLOCK_InitSysPll1

(

const ccm_analog_integer_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_integer_pll_config_t enumeration).

Note

This function can't detect whether the SYS PLL has been enabled and used by some IPs.

void CLOCK_InitSysPll2

(

const ccm_analog_integer_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_integer_pll_config_t enumeration).

Note

This function can't detect whether the SYS PLL has been enabled and used by some IPs.

void CLOCK_InitSysPll3

(

const ccm_analog_integer_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_integer_pll_config_t enumeration).

Note

This function can't detect whether the SYS PLL has been enabled and used by some IPs.

void CLOCK_InitAudioPll1

(

const ccm_analog_frac_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

Note

This function can't detect whether the AUDIO PLL has been enabled and used by some IPs.

void CLOCK_InitAudioPll2

(

const ccm_analog_frac_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

Note

This function can't detect whether the AUDIO PLL has been enabled and used by some IPs.

void CLOCK_InitVideoPll1

(

const ccm_analog_frac_pll_config_t *

config

)

Parameters

config

Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

void CLOCK_InitIntegerPll	(	CCM_ANALOG_Type *	base,
		const ccm_analog_integer_pll_config_t *	config,
		clock_pll_ctrl_t	type
	)

Parameters

base	CCM ANALOG base address
config	Pointer to the configuration structure(see ccm_analog_integer_pll_config_t enumeration).
type	integer pll type

uint32_t CLOCK_GetIntegerPllFreq	(	CCM_ANALOG_Type *	base,
		clock_pll_ctrl_t	type,
		uint32_t	refClkFreq,
		bool	pll1Bypass
	)

Parameters

base	CCM ANALOG base address.
type	integer pll type
pll1Bypass	pll1 bypass flag

Returns

Clock frequency

void CLOCK_InitFracPll	(	CCM_ANALOG_Type *	base,
		const ccm_analog_frac_pll_config_t *	config,
		clock_pll_ctrl_t	type
	)

Parameters

base	CCM ANALOG base address.
config	Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
type	fractional pll type.

uint32_t CLOCK_GetFracPllFreq	(	CCM_ANALOG_Type *	base,
		clock_pll_ctrl_t	type,
		uint32_t	refClkFreq
	)

Parameters

base	CCM_ANALOG base pointer.
type	fractional pll type.
fractional	pll reference clock frequency

Returns

Clock frequency

uint32_t CLOCK_GetPllFreq

(

clock_pll_ctrl_t

pll

)

Parameters

type	fractional pll type.

Returns

Clock frequency

uint32_t CLOCK_GetPllRefClkFreq

(

clock_pll_ctrl_t

ctrl

)

Parameters

type	fractional pll type.

Returns

Clock frequency

uint32_t CLOCK_GetFreq

(

clock_name_t

clockName

)

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName

Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

uint32_t CLOCK_GetCoreM4Freq

(

void

)

Returns

Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAxiFreq

(

void

)

Returns

Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAhbFreq

(

void

)

Returns

Clock frequency; If the clock is invalid, returns 0.