Clock Driver

Overview

The MCUXpresso SDK provides a peripheral clock driver for the SYSCON module of MCUXpresso SDK devices.

Function description

Clock driver provides these functions:

• Functions to initialize the Core clock to given frequency
• Functions to configure the clock selection muxes.
• Functions to setup peripheral clock dividers
• Functions to set the flash wait states for the input freuqency
• Functions to get the frequency of the selected clock
• Functions to set PLL frequency

SYSCON Clock frequency functions

SYSCON clock module provides clocks, such as MCLKCLK, ADCCLK, DMICCLK, MCGFLLCLK, FXCOMCLK, WDTOSC, RTCOSC, USBCLK, and SYSPLL. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. CLOCK_SetupFROClocking() initializes the FRO to 12 MHz, 48 MHz, or 96 MHz frequency. CLOCK_SetupPLLData(), CLOCK_SetupSystemPLLPrec(), and CLOCK_SetPLLFreq() functions are used to setup the PLL. The SYSCON clock driver provides functions to get the frequency of these clocks, such as CLOCK_GetFreq(), CLOCK_GetFro12MFreq(), CLOCK_GetExtClkFreq(), CLOCK_GetWdtOscFreq(), CLOCK_GetFroHfFreq(), CLOCK_GetPllOutFreq(), CLOCK_GetOsc32KFreq(), CLOCK_GetCoreSysClkFreq(), CLOCK_GetI2SMClkFreq(), CLOCK_GetFlexCommClkFreq, and CLOCK_GetAsyncApbClkFreq.

SYSCON clock Selection Muxes

The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC, and PLL.

SYSCON clock dividers

The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, I2S, SYSTICK, AHB, ADC, and also CLKOUT and TRACE functions.

SYSCON flash wait states

The SYSCON clock driver provides the function CLOCK_SetFLASHAccessCyclesForFreq() that configures FLASHCFG register with a selected FLASHTIM value.

Typical use case

POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on so that we can switch to its 12MHz mode temporarily 

Files
file	fsl_clock.h

Data Structures
struct	pll_config_t
	PLL configuration structure. More...
struct	pll_setup_t
	PLL setup structure This structure can be used to pre-build a PLL setup configuration at run-time and quickly set the PLL to the configuration. More...

Macros
#define	CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT   2U
	User-defined the size of cache for CLOCK_PllGetConfig() function. More...
#define	FLEXCOMM_CLOCKS
	Clock ip name array for FLEXCOMM. More...
#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...
#define	BI2C_CLOCKS
	Clock ip name array for BI2C. More...
#define	LPSI_CLOCKS
	Clock ip name array for LSPI. More...
#define	FLEXI2S_CLOCKS
	Clock ip name array for FLEXI2S. More...
#define	UTICK_CLOCKS
	Clock ip name array for UTICK. More...
#define	DMIC_CLOCKS
	Clock ip name array for DMIC. More...
#define	DMA_CLOCKS
	Clock ip name array for DMA. More...
#define	CTIMER_CLOCKS
	Clock ip name array for CT32B. More...
#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...
#define	ADC_CLOCKS
	Clock ip name array for ADC. More...
#define	MRT_CLOCKS
	Clock ip name array for MRT. More...
#define	SCT_CLOCKS
	Clock ip name array for MRT. More...
#define	RTC_CLOCKS
	Clock ip name array for RTC. More...
#define	WWDT_CLOCKS
	Clock ip name array for WWDT. More...
#define	CRC_CLOCKS
	Clock ip name array for CRC. More...
#define	USBD_CLOCKS
	Clock ip name array for USBD. More...
#define	GINT_CLOCKS
	Clock ip name array for GINT. More...
#define	CLK_GATE_REG_OFFSET_SHIFT   8U
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
#define	CLK_ATTACH_ID(mux, sel, pos)   ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1UL) & 0xFU) << 8U) << ((pos)*12U))
	Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards. More...
#define	PLL_CONFIGFLAG_USEINRATE   (1U << 0U)
	PLL configuration structure flags for 'flags' field These flags control how the PLL configuration function sets up the PLL setup structure. More...
#define	PLL_CONFIGFLAG_FORCENOFRACT   (1U << 2U)
	Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \ SS hardware.
#define	PLL_SETUPFLAG_POWERUP   (1U << 0U)
	PLL setup structure flags for 'flags' field These flags control how the PLL setup function sets up the PLL. More...
#define	PLL_SETUPFLAG_WAITLOCK   (1U << 1U)
	Setup will wait for PLL to lock, implying the PLL will be pwoered on.
#define	PLL_SETUPFLAG_ADGVOLT   (1U << 2U)
	Optimize system voltage for the new PLL rate.
#define	PLL_SETUPFLAG_USEFEEDBACKDIV2   (1U << 3U)
	Use feedback divider by 2 in divider path.

Enumerations
enum	clock_ip_name_t
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
enum	clock_name_t {   kCLOCK_CoreSysClk,   kCLOCK_BusClk,   kCLOCK_FroHf,   kCLOCK_Fro12M,   kCLOCK_ExtClk,   kCLOCK_PllOut,   kCLOCK_UsbClk,   kCLOCK_WdtOsc,   kCLOCK_Frg,   kCLOCK_AsyncApbClk,   kCLOCK_FlexI2S }
	Clock name used to get clock frequency. More...
enum	async_clock_src_t {   kCLOCK_AsyncMainClk = 0,   kCLOCK_AsyncFro12Mhz }
enum	clock_flashtim_t {   kCLOCK_Flash1Cycle = 0,   kCLOCK_Flash2Cycle,   kCLOCK_Flash3Cycle,   kCLOCK_Flash4Cycle,   kCLOCK_Flash5Cycle,   kCLOCK_Flash6Cycle,   kCLOCK_Flash7Cycle }
	FLASH Access time definitions. More...
enum	ss_progmodfm_t {   kSS_MF_512 = (0 << 20),   kSS_MF_384 = (1 << 20),   kSS_MF_256 = (2 << 20),   kSS_MF_128 = (3 << 20),   kSS_MF_64 = (4 << 20),   kSS_MF_32 = (5 << 20),   kSS_MF_24 = (6 << 20),   kSS_MF_16 = (7 << 20) }
	PLL Spread Spectrum (SS) Programmable modulation frequency See (MF) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	ss_progmoddp_t {   kSS_MR_K0 = (0 << 23),   kSS_MR_K1 = (1 << 23),   kSS_MR_K1_5 = (2 << 23),   kSS_MR_K2 = (3 << 23),   kSS_MR_K3 = (4 << 23),   kSS_MR_K4 = (5 << 23),   kSS_MR_K6 = (6 << 23),   kSS_MR_K8 = (7 << 23) }
	PLL Spread Spectrum (SS) Programmable frequency modulation depth See (MR) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	ss_modwvctrl_t {   kSS_MC_NOC = (0 << 26),   kSS_MC_RECC = (2 << 26),   kSS_MC_MAXC = (3 << 26) }
	PLL Spread Spectrum (SS) Modulation waveform control See (MC) field in the SYSPLLSSCTRL1 register in the UM. More...
enum	pll_error_t {   kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),   kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),   kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),   kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),   kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),   kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) }
	PLL status definitions. More...
enum	clock_usb_src_t {   kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,   kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,   kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk,   kCLOCK_UsbSrcNone }
	USB clock source definition. More...

Functions
static void	CLOCK_SetFLASHAccessCycles (clock_flashtim_t clks)
	Set FLASH memory access time in clocks. More...
status_t	CLOCK_SetupFROClocking (uint32_t iFreq)
	Initialize the Core clock to given frequency (12, 48 or 96 MHz). Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is enabled. More...
void	CLOCK_AttachClk (clock_attach_id_t connection)
	Configure the clock selection muxes. More...
clock_attach_id_t	CLOCK_GetClockAttachId (clock_attach_id_t attachId)
	Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id. More...
void	CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
	Setup peripheral clock dividers. More...
void	CLOCK_SetFLASHAccessCyclesForFreq (uint32_t iFreq)
	Set the flash wait states for the input freuqency. More...
uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Return Frequency of selected clock. More...
uint32_t	CLOCK_GetFRGInputClock (void)
	Return Input frequency for the Fractional baud rate generator. More...
uint32_t	CLOCK_GetDmicClkFreq (void)
	Return Input frequency for the DMIC. More...
uint32_t	CLOCK_GetFrgClkFreq (void)
	Return Input frequency for the FRG. More...
uint32_t	CLOCK_SetFRGClock (uint32_t freq)
	Set output of the Fractional baud rate generator. More...
uint32_t	CLOCK_GetFro12MFreq (void)
	Return Frequency of FRO 12MHz. More...
uint32_t	CLOCK_GetExtClkFreq (void)
	Return Frequency of External Clock. More...
uint32_t	CLOCK_GetWdtOscFreq (void)
	Return Frequency of Watchdog Oscillator. More...
uint32_t	CLOCK_GetFroHfFreq (void)
	Return Frequency of High-Freq output of FRO. More...
uint32_t	CLOCK_GetUsbClkFreq (void)
	Return Frequency of USB. More...
uint32_t	CLOCK_GetPllOutFreq (void)
	Return Frequency of PLL. More...
uint32_t	CLOCK_GetOsc32KFreq (void)
	Return Frequency of 32kHz osc. More...
uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Return Frequency of Core System. More...
uint32_t	CLOCK_GetI2SMClkFreq (void)
	Return Frequency of I2S MCLK Clock. More...
uint32_t	CLOCK_GetFlexCommClkFreq (uint32_t id)
	Return Frequency of Flexcomm functional Clock. More...
uint32_t	CLOCK_GetAdcClkFreq (void)
	Return Frequency of Adc Clock. More...
__STATIC_INLINE async_clock_src_t	CLOCK_GetAsyncApbClkSrc (void)
	Return Asynchronous APB Clock source. More...
uint32_t	CLOCK_GetAsyncApbClkFreq (void)
	Return Frequency of Asynchronous APB Clock. More...
uint32_t	CLOCK_GetSystemPLLInClockRate (void)
	Return System PLL input clock rate. More...
uint32_t	CLOCK_GetSystemPLLOutClockRate (bool recompute)
	Return System PLL output clock rate. More...
__STATIC_INLINE void	CLOCK_SetBypassPLL (bool bypass)
	Enables and disables PLL bypass mode. More...
__STATIC_INLINE bool	CLOCK_IsSystemPLLLocked (void)
	Check if PLL is locked or not. More...
void	CLOCK_SetStoredPLLClockRate (uint32_t rate)
	Store the current PLL rate. More...
uint32_t	CLOCK_GetSystemPLLOutFromSetup (pll_setup_t *pSetup)
	Return System PLL output clock rate from setup structure. More...
pll_error_t	CLOCK_SetupPLLData (pll_config_t *pControl, pll_setup_t *pSetup)
	Set PLL output based on the passed PLL setup data. More...
pll_error_t	CLOCK_SetupSystemPLLPrec (pll_setup_t *pSetup, uint32_t flagcfg)
	Set PLL output from PLL setup structure (precise frequency) More...
pll_error_t	CLOCK_SetPLLFreq (const pll_setup_t *pSetup)
	Set PLL output from PLL setup structure (precise frequency) More...
void	CLOCK_SetupSystemPLLMult (uint32_t multiply_by, uint32_t input_freq)
	Set PLL output based on the multiplier and input frequency. More...
static void	CLOCK_DisableUsbfs0Clock (void)
	Disable USB FS clock. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 1))
	CLOCK driver version 2.5.1. More...

---

Data Structure Documentation

struct pll_config_t

This structure can be used to configure the settings for a PLL setup structure. Fill in the desired configuration for the PLL and call the PLL setup function to fill in a PLL setup structure.

Data Fields
uint32_t	desiredRate
	Desired PLL rate in Hz.
uint32_t	inputRate
	PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set.
uint32_t	flags
	PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions.
ss_progmodfm_t	ss_mf
	SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
ss_progmoddp_t	ss_mr
	SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
ss_modwvctrl_t	ss_mc
	SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag.
bool	mfDither
	false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag

struct pll_setup_t

It can be populated with the PLL setup function. If powering up or waiting for PLL lock, the PLL input clock source should be configured prior to PLL setup.

Data Fields
uint32_t	syspllctrl
	PLL control register SYSPLLCTRL.
uint32_t	syspllndec
	PLL NDEC register SYSPLLNDEC.
uint32_t	syspllpdec
	PLL PDEC register SYSPLLPDEC.
uint32_t	syspllssctrl [2]
	PLL SSCTL registers SYSPLLSSCTRL.
uint32_t	pllRate
	Acutal PLL rate.
uint32_t	flags
	PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions.

Macro Definition Documentation

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 5, 1))

#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT   2U

Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function would cache the recent calulation and accelerate the execution to get the right settings.

#define FLEXCOMM_CLOCKS

Value:

{                                                                                                               \
        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
            kCLOCK_FlexComm6, kCLOCK_FlexComm7                                                                      \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
            kCLOCK_MinUart6, kCLOCK_MinUart7                                                                  \
    }

#define BI2C_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
    }

#define LPSI_CLOCKS

Value:

{                                                                                                                  \
        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
    }

#define FLEXI2S_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7                                                                  \
    }

#define UTICK_CLOCKS

Value:

{                \
        kCLOCK_Utick \
    }

#define DMIC_CLOCKS

Value:

{               \
        kCLOCK_DMic \
    }

#define DMA_CLOCKS

Value:

{              \
        kCLOCK_Dma \
    }

#define CTIMER_CLOCKS

Value:

{                                                                             \
        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
    }

#define GPIO_CLOCKS

Value:

{                              \
        kCLOCK_Gpio0, kCLOCK_Gpio1 \
    }

#define ADC_CLOCKS

Value:

{               \
        kCLOCK_Adc0 \
    }

#define MRT_CLOCKS

Value:

{              \
        kCLOCK_Mrt \
    }

#define SCT_CLOCKS

Value:

{               \
        kCLOCK_Sct0 \
    }

#define RTC_CLOCKS

Value:

{              \
        kCLOCK_Rtc \
    }

#define WWDT_CLOCKS

Value:

{               \
        kCLOCK_Wwdt \
    }

#define CRC_CLOCKS

Value:

{              \
        kCLOCK_Crc \
    }

#define USBD_CLOCKS

Value:

{                \
        kCLOCK_Usbd0 \
    }

#define GINT_CLOCKS

Value:

{                            \
        kCLOCK_Gint, kCLOCK_Gint \
    }

GINT0 & GINT1 share same slot

#define CLK_GATE_REG_OFFSET_SHIFT   8U

#define CLK_ATTACH_ID	(		mux,
			sel,
			pos
	)		((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1UL) & 0xFU) << 8U) << ((pos)*12U))

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

#define PLL_CONFIGFLAG_USEINRATE   (1U << 0U)

When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the configuration structure must be assigned with the expected PLL frequency. If the PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration function and the driver will determine the PLL rate from the currently selected PLL source. This flag might be used to configure the PLL input clock more accurately when using the WDT oscillator or a more dyanmic CLKIN source.

When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider are not used.
Flag to use InputRate in PLL configuration structure for setup

#define PLL_SETUPFLAG_POWERUP   (1U << 0U)

Setup will power on the PLL after setup

Enumeration Type Documentation

enum clock_ip_name_t

enum clock_name_t

Enumerator
kCLOCK_CoreSysClk	Core/system clock (aka MAIN_CLK)
kCLOCK_BusClk	Bus clock (AHB clock)
kCLOCK_FroHf	FRO48/96.
kCLOCK_Fro12M	FRO12M.
kCLOCK_ExtClk	External Clock.
kCLOCK_PllOut	PLL Output.
kCLOCK_UsbClk	USB input.
kCLOCK_WdtOsc	Watchdog Oscillator.
kCLOCK_Frg	Frg Clock.
kCLOCK_AsyncApbClk	Async APB clock.
kCLOCK_FlexI2S	FlexI2S clock.

enum async_clock_src_t

Clock source selections for the asynchronous APB clock

Enumerator
kCLOCK_AsyncMainClk	Main System clock.
kCLOCK_AsyncFro12Mhz	12MHz FRO

enum clock_flashtim_t

Enumerator
kCLOCK_Flash1Cycle	Flash accesses use 1 CPU clock.
kCLOCK_Flash2Cycle	Flash accesses use 2 CPU clocks.
kCLOCK_Flash3Cycle	Flash accesses use 3 CPU clocks.
kCLOCK_Flash4Cycle	Flash accesses use 4 CPU clocks.
kCLOCK_Flash5Cycle	Flash accesses use 5 CPU clocks.
kCLOCK_Flash6Cycle	Flash accesses use 6 CPU clocks.
kCLOCK_Flash7Cycle	Flash accesses use 7 CPU clocks.

enum ss_progmodfm_t

Enumerator
kSS_MF_512	Nss = 512 (fm ? 3.9 - 7.8 kHz)
kSS_MF_384	Nss ?= 384 (fm ? 5.2 - 10.4 kHz)
kSS_MF_256	Nss = 256 (fm ? 7.8 - 15.6 kHz)
kSS_MF_128	Nss = 128 (fm ? 15.6 - 31.3 kHz)
kSS_MF_64	Nss = 64 (fm ? 32.3 - 64.5 kHz)
kSS_MF_32	Nss = 32 (fm ? 62.5- 125 kHz)
kSS_MF_24	Nss ?= 24 (fm ? 83.3- 166.6 kHz)
kSS_MF_16	Nss = 16 (fm ? 125- 250 kHz)

enum ss_progmoddp_t

Enumerator
kSS_MR_K0	k = 0 (no spread spectrum)
kSS_MR_K1	k = 1
kSS_MR_K1_5	k = 1.5
kSS_MR_K2	k = 2
kSS_MR_K3	k = 3
kSS_MR_K4	k = 4
kSS_MR_K6	k = 6
kSS_MR_K8	k = 8

enum ss_modwvctrl_t

Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

Enumerator
kSS_MC_NOC	no compensation
kSS_MC_RECC	recommended setting
kSS_MC_MAXC	max. compensation

enum pll_error_t

Enumerator
kStatus_PLL_Success	PLL operation was successful.
kStatus_PLL_OutputTooLow	PLL output rate request was too low.
kStatus_PLL_OutputTooHigh	PLL output rate request was too high.
kStatus_PLL_InputTooLow	PLL input rate is too low.
kStatus_PLL_InputTooHigh	PLL input rate is too high.
kStatus_PLL_OutsideIntLimit	Requested output rate isn't possible.

enum clock_usb_src_t

Enumerator
kCLOCK_UsbSrcFro	Use FRO 96 or 48 MHz.
kCLOCK_UsbSrcSystemPll	Use System PLL output.
kCLOCK_UsbSrcMainClock	Use Main clock.
kCLOCK_UsbSrcNone	Use None, this may be selected in order to reduce power when no output is needed.

Function Documentation

static void CLOCK_SetFLASHAccessCycles ( clock_flashtim_t  clks )

inlinestatic

Parameters

clks	: Clock cycles for FLASH access

Returns

Nothing

status_t CLOCK_SetupFROClocking

(

uint32_t

iFreq

)

Parameters

iFreq

: Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)

Returns

returns success or fail status.

void CLOCK_AttachClk

(

clock_attach_id_t

connection

)

Parameters

connection

: Clock to be configured.

Returns

Nothing

clock_attach_id_t CLOCK_GetClockAttachId

(

clock_attach_id_t

attachId

)

Parameters

attachId

: Clock attach id to get.

Returns

Clock source value.

void CLOCK_SetClkDiv	(	clock_div_name_t	div_name,
		uint32_t	divided_by_value,
		bool	reset
	)

Parameters

div_name	: Clock divider name
divided_by_value,:	Value to be divided
reset	: Whether to reset the divider counter.

Returns

Nothing

void CLOCK_SetFLASHAccessCyclesForFreq

(

uint32_t

iFreq

)

Parameters

iFreq

: Input frequency

Returns

Nothing

uint32_t CLOCK_GetFreq

(

clock_name_t

clockName

)

Returns

Frequency of selected clock

uint32_t CLOCK_GetFRGInputClock

(

void

)

Returns

Input Frequency for FRG

uint32_t CLOCK_GetDmicClkFreq

(

void

)

Returns

Input Frequency for DMIC

uint32_t CLOCK_GetFrgClkFreq

(

void

)

Returns

Input Frequency for FRG

uint32_t CLOCK_SetFRGClock

(

uint32_t

freq

)

Parameters

freq	: Desired output frequency

Returns

Error Code 0 - fail 1 - success

uint32_t CLOCK_GetFro12MFreq

(

void

)

Returns

Frequency of FRO 12MHz

uint32_t CLOCK_GetExtClkFreq

(

void

)

Returns

Frequency of External Clock. If no external clock is used returns 0.

uint32_t CLOCK_GetWdtOscFreq

(

void

)

Returns

Frequency of Watchdog Oscillator

uint32_t CLOCK_GetFroHfFreq

(

void

)

Returns

Frequency of High-Freq output of FRO

uint32_t CLOCK_GetUsbClkFreq

(

void

)

Returns

Frequency of USB

uint32_t CLOCK_GetPllOutFreq

(

void

)

Returns

Frequency of PLL

uint32_t CLOCK_GetOsc32KFreq

(

void

)

Returns

Frequency of 32kHz osc

uint32_t CLOCK_GetCoreSysClkFreq

(

void

)

Returns

Frequency of Core System

uint32_t CLOCK_GetI2SMClkFreq

(

void

)

Returns

Frequency of I2S MCLK Clock

uint32_t CLOCK_GetFlexCommClkFreq

(

uint32_t

id

)

Returns

Frequency of Flexcomm functional Clock

uint32_t CLOCK_GetAdcClkFreq

(

void

)

Returns

Frequency of Adc Clock.

__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc

(

void

)

Returns

Asynchronous APB CLock source

uint32_t CLOCK_GetAsyncApbClkFreq

(

void

)

Returns

Frequency of Asynchronous APB Clock Clock

uint32_t CLOCK_GetSystemPLLInClockRate

(

void

)

Returns

System PLL input clock rate

uint32_t CLOCK_GetSystemPLLOutClockRate

(

bool

recompute

)

Parameters

recompute

: Forces a PLL rate recomputation if true

Returns

System PLL output clock rate

Note

The PLL rate is cached in the driver in a variable as the rate computation function can take some time to perform. It is recommended to use 'false' with the 'recompute' parameter.

__STATIC_INLINE void CLOCK_SetBypassPLL

(

bool

bypass

)

bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass

Returns

System PLL output clock rate

__STATIC_INLINE bool CLOCK_IsSystemPLLLocked

(

void

)

Returns

true if the PLL is locked, false if not locked

void CLOCK_SetStoredPLLClockRate

(

uint32_t

rate

)

Parameters

rate,:

Current rate of the PLL

Returns

Nothing

uint32_t CLOCK_GetSystemPLLOutFromSetup

(

pll_setup_t *

pSetup

)

Parameters

pSetup

: Pointer to a PLL setup structure

Returns

System PLL output clock rate calculated from the setup structure

pll_error_t CLOCK_SetupPLLData	(	pll_config_t *	pControl,
		pll_setup_t *	pSetup
	)

Parameters

pControl	: Pointer to populated PLL control structure to generate setup with
pSetup	: Pointer to PLL setup structure to be filled

Returns

PLL_ERROR_SUCCESS on success, or PLL setup error code

Note

Actual frequency for setup may vary from the desired frequency based on the accuracy of input clocks, rounding, non-fractional PLL mode, etc.

pll_error_t CLOCK_SetupSystemPLLPrec	(	pll_setup_t *	pSetup,
		uint32_t	flagcfg
	)

Parameters

pSetup	: Pointer to populated PLL setup structure
flagcfg	: Flag configuration for PLL config structure

Returns

PLL_ERROR_SUCCESS on success, or PLL setup error code

Note

This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

pll_error_t CLOCK_SetPLLFreq

(

const pll_setup_t *

pSetup

)

Parameters

pSetup

: Pointer to populated PLL setup structure

Returns

kStatus_PLL_Success on success, or PLL setup error code

Note

This function will power off the PLL, setup the PLL with the new setup data, and then optionally powerup the PLL, wait for PLL lock, and adjust system voltages to the new PLL rate. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

void CLOCK_SetupSystemPLLMult	(	uint32_t	multiply_by,
		uint32_t	input_freq
	)

Parameters

multiply_by	: multiplier
input_freq	: Clock input frequency of the PLL

Returns

Nothing

Note

Unlike the Chip_Clock_SetupSystemPLLPrec() function, this function does not disable or enable PLL power, wait for PLL lock, or adjust system voltages. These must be done in the application. The function will not alter any source clocks (ie, main systen clock) that may use the PLL, so these should be setup prior to and after exiting the function.

static void CLOCK_DisableUsbfs0Clock ( void  )

inlinestatic

Disable USB FS clock.