Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

Modules
	System Clock Generator (SCG)

Files
file	fsl_clock.h

Data Structures
struct	scg_sys_clk_config_t
	SCG system clock configuration. More...

struct	scg_sosc_config_t
	SCG system OSC configuration. More...

struct	scg_sirc_config_t
	SCG slow IRC clock configuration. More...

struct	scg_firc_trim_config_t
	SCG fast IRC clock trim configuration. More...

struct	scg_firc_config_t
	SCG fast IRC clock configuration. More...

struct	scg_spll_config_t
	SCG system PLL configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX. More...

#define	RTC_CLOCKS
	Clock ip name array for RTC. More...

#define	RTCOSC_CLOCKS
	Clock ip name array for RTCOSC. More...

#define	PORT_CLOCKS
	Clock ip name array for PORT. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	LPTMR_CLOCKS
	Clock ip name array for LPTMR. More...

#define	ADC12_CLOCKS
	Clock ip name array for ADC16. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	FLASH_CLOCKS
	Clock ip name array for FLASH. More...

#define	SYSMPU_CLOCKS
	Clock ip name array for MPU. More...

#define	EWM_CLOCKS
	Clock ip name array for EWM. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	FTM_CLOCKS
	Clock ip name array for FLEXTMR. More...

#define	PDB_CLOCKS
	Clock ip name array for PDB. More...

#define	PWT_CLOCKS
	Clock ip name array for PWT. More...

#define	LPO_CLK_FREQ 128000U
	LPO clock frequency.

#define	CLOCK_GetOsc0ErClkFreq CLOCK_GetErClkFreq
	For compatible with other MCG platforms. More...

#define	CLOCK_GetEr32kClkFreq CLOCK_GetOsc32kClkFreq
	For compatible with other MCG platforms. More...

Enumerations
enum	clock_name_t { kCLOCK_CoreSysClk, kCLOCK_BusClk, kCLOCK_FlexBusClk, kCLOCK_FlashClk, kCLOCK_ScgSysOscClk, kCLOCK_ScgSircClk, kCLOCK_ScgFircClk, kCLOCK_ScgSysPllClk, kCLOCK_ScgSysOscAsyncDiv1Clk, kCLOCK_ScgSysOscAsyncDiv2Clk, kCLOCK_ScgSircAsyncDiv1Clk, kCLOCK_ScgSircAsyncDiv2Clk, kCLOCK_ScgFircAsyncDiv1Clk, kCLOCK_ScgFircAsyncDiv2Clk, kCLOCK_ScgSysPllAsyncDiv1Clk, kCLOCK_ScgSysPllAsyncDiv2Clk, kCLOCK_LpoClk, kCLOCK_Osc32kClk, kCLOCK_ErClk }
	Clock name used to get clock frequency. More...

enum	clock_ip_src_t { kCLOCK_IpSrcNoneOrExt = 0U, kCLOCK_IpSrcSysOscAsync = 1U, kCLOCK_IpSrcSircAsync = 2U, kCLOCK_IpSrcFircAsync = 3U, kCLOCK_IpSrcSysPllAsync = 6U }
	Clock source for peripherals that support various clock selections. More...

enum	clock_ip_name_t
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. More...

enum	osc32_mode_t { kOSC32_Bypass = OSC32_CR_ROSCEN_MASK, kOSC32_Crystal = OSC32_CR_ROSCEN_MASK \| OSC32_CR_ROSCEREFS_MASK, kOSC32_CrystalEnableInStop }
	OSC32 work mode. More...

enum	{ kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) }
	SCG status return codes. More...

enum	scg_sys_clk_t { kSCG_SysClkSlow, kSCG_SysClkBus, kSCG_SysClkCore }
	SCG system clock type. More...

enum	scg_sys_clk_src_t { kSCG_SysClkSrcSysOsc = 1U, kSCG_SysClkSrcSirc = 2U, kSCG_SysClkSrcFirc = 3U, kSCG_SysClkSrcSysPll = 6U }
	SCG system clock source. More...

enum	scg_sys_clk_div_t { kSCG_SysClkDivBy1 = 0U, kSCG_SysClkDivBy2 = 1U, kSCG_SysClkDivBy3 = 2U, kSCG_SysClkDivBy4 = 3U, kSCG_SysClkDivBy5 = 4U, kSCG_SysClkDivBy6 = 5U, kSCG_SysClkDivBy7 = 6U, kSCG_SysClkDivBy8 = 7U, kSCG_SysClkDivBy9 = 8U, kSCG_SysClkDivBy10 = 9U, kSCG_SysClkDivBy11 = 10U, kSCG_SysClkDivBy12 = 11U, kSCG_SysClkDivBy13 = 12U, kSCG_SysClkDivBy14 = 13U, kSCG_SysClkDivBy15 = 14U, kSCG_SysClkDivBy16 = 15U }
	SCG system clock divider value. More...

enum	clock_clkout_src_t { kClockClkoutSelScgSlow = 0U, kClockClkoutSelSysOsc = 1U, kClockClkoutSelSirc = 2U, kClockClkoutSelFirc = 3U, kClockClkoutSelSysPll = 6U }
	SCG clock out configuration (CLKOUTSEL). More...

enum	scg_async_clk_t { kSCG_AsyncDiv1Clk, kSCG_AsyncDiv2Clk }
	SCG asynchronous clock type. More...

enum	scg_async_clk_div_t { kSCG_AsyncClkDisable = 0U, kSCG_AsyncClkDivBy1 = 1U, kSCG_AsyncClkDivBy2 = 2U, kSCG_AsyncClkDivBy4 = 3U, kSCG_AsyncClkDivBy8 = 4U, kSCG_AsyncClkDivBy16 = 5U, kSCG_AsyncClkDivBy32 = 6U, kSCG_AsyncClkDivBy64 = 7U }
	SCG asynchronous clock divider value. More...

enum	scg_sosc_monitor_mode_t { kSCG_SysOscMonitorDisable = 0U, kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, kSCG_SysOscMonitorReset }
	SCG system OSC monitor mode. More...

enum	scg_sosc_mode_t { kSCG_SysOscModeExt = 0U, kSCG_SysOscModeOscLowPower = SCG_SOSCCFG_EREFS_MASK, kSCG_SysOscModeOscHighGain = SCG_SOSCCFG_EREFS_MASK \| SCG_SOSCCFG_HGO_MASK }
	OSC work mode. More...

enum	{ kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK, kSCG_SysOscEnableInStop = SCG_SOSCCSR_SOSCSTEN_MASK, kSCG_SysOscEnableInLowPower = SCG_SOSCCSR_SOSCLPEN_MASK, kSCG_SysOscEnableErClk = SCG_SOSCCSR_SOSCERCLKEN_MASK }
	OSC enable mode. More...

enum	scg_sirc_range_t { kSCG_SircRangeLow, kSCG_SircRangeHigh }
	SCG slow IRC clock frequency range. More...

enum	{ kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK, kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK, kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK }
	SIRC enable mode. More...

enum	scg_firc_trim_mode_t { kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK \| SCG_FIRCCSR_FIRCTRUP_MASK }
	SCG fast IRC trim mode. More...

enum	scg_firc_trim_div_t { kSCG_FircTrimDivBy1, kSCG_FircTrimDivBy128, kSCG_FircTrimDivBy256, kSCG_FircTrimDivBy512, kSCG_FircTrimDivBy1024, kSCG_FircTrimDivBy2048 }
	SCG fast IRC trim predivided value for system OSC. More...

enum	scg_firc_trim_src_t { kSCG_FircTrimSrcSysOsc = 2U }
	SCG fast IRC trim source. More...

enum	scg_firc_range_t { kSCG_FircRange48M, kSCG_FircRange52M, kSCG_FircRange56M, kSCG_FircRange60M }
	SCG fast IRC clock frequency range. More...

enum	{ kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK, kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK, kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK, kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK }
	FIRC enable mode. More...

enum	scg_spll_src_t { kSCG_SysPllSrcSysOsc, kSCG_SysPllSrcFirc }
	SCG system PLL clock source. More...

enum	scg_spll_monitor_mode_t { kSCG_SysPllMonitorDisable = 0U, kSCG_SysPllMonitorInt = SCG_SPLLCSR_SPLLCM_MASK, kSCG_SysPllMonitorReset }
	SCG system PLL monitor mode. More...

enum	{ kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK, kSCG_SysPllEnableInStop = SCG_SPLLCSR_SPLLSTEN_MASK }
	SPLL enable mode. More...

Functions
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static bool	CLOCK_IsEnabledByOtherCore (clock_ip_name_t name)
	Check whether the clock is already enabled and configured by any other core. More...

static void	CLOCK_SetIpSrc (clock_ip_name_t name, clock_ip_src_t src)
	Set the clock source for specific IP module. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Get the core clock or system clock frequency. More...

uint32_t	CLOCK_GetBusClkFreq (void)
	Get the bus clock frequency. More...

uint32_t	CLOCK_GetFlashClkFreq (void)
	Get the flash clock frequency. More...

uint32_t	CLOCK_GetOsc32kClkFreq (void)
	Get the OSC 32K clock frequency (OSC32KCLK). More...

uint32_t	CLOCK_GetErClkFreq (void)
	Get the external reference clock frequency (ERCLK). More...

uint32_t	CLOCK_GetIpFreq (clock_ip_name_t name)
	Gets the clock frequency for a specific IP module. More...

Variables
volatile uint32_t	g_xtal0Freq
	External XTAL0 (OSC0/SYSOSC) clock frequency. More...

volatile uint32_t	g_xtal32Freq
	External XTAL32/EXTAL32 clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
	CLOCK driver version 2.3.1. More...

MCU System Clock.
uint32_t	CLOCK_GetSysClkFreq (scg_sys_clk_t type)
	Gets the SCG system clock frequency. More...

static void	CLOCK_SetVlprModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for VLPR mode. More...

static void	CLOCK_SetRunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for RUN mode. More...

static void	CLOCK_SetHsrunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for HSRUN mode. More...

static void	CLOCK_GetCurSysClkConfig (scg_sys_clk_config_t *config)
	Gets the system clock configuration in the current power mode. More...

static void	CLOCK_SetClkOutSel (clock_clkout_src_t setting)
	Sets the clock out selection. More...

SCG System OSC Clock.
status_t	CLOCK_InitSysOsc (const scg_sosc_config_t *config)
	Initializes the SCG system OSC. More...

status_t	CLOCK_DeinitSysOsc (void)
	De-initializes the SCG system OSC. More...

static void	CLOCK_SetSysOscAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetSysOscFreq (void)
	Gets the SCG system OSC clock frequency (SYSOSC). More...

uint32_t	CLOCK_GetSysOscAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the system OSC. More...

static bool	CLOCK_IsSysOscErr (void)
	Checks whether the system OSC clock error occurs. More...

static void	CLOCK_ClearSysOscErr (void)
	Clears the system OSC clock error.

static void	CLOCK_SetSysOscMonitorMode (scg_sosc_monitor_mode_t mode)
	Sets the system OSC monitor mode. More...

static bool	CLOCK_IsSysOscValid (void)
	Checks whether the system OSC clock is valid. More...

SCG Slow IRC Clock.
status_t	CLOCK_InitSirc (const scg_sirc_config_t *config)
	Initializes the SCG slow IRC clock. More...

status_t	CLOCK_DeinitSirc (void)
	De-initializes the SCG slow IRC. More...

static void	CLOCK_SetSircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetSircFreq (void)
	Gets the SCG SIRC clock frequency. More...

uint32_t	CLOCK_GetSircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the SIRC. More...

static bool	CLOCK_IsSircValid (void)
	Checks whether the SIRC clock is valid. More...

SCG Fast IRC Clock.
status_t	CLOCK_InitFirc (const scg_firc_config_t *config)
	Initializes the SCG fast IRC clock. More...

status_t	CLOCK_DeinitFirc (void)
	De-initializes the SCG fast IRC. More...

static void	CLOCK_SetFircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetFircFreq (void)
	Gets the SCG FIRC clock frequency. More...

uint32_t	CLOCK_GetFircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the FIRC. More...

static bool	CLOCK_IsFircErr (void)
	Checks whether the FIRC clock error occurs. More...

static void	CLOCK_ClearFircErr (void)
	Clears the FIRC clock error.

static bool	CLOCK_IsFircValid (void)
	Checks whether the FIRC clock is valid. More...

SCG System PLL Clock.
uint32_t	CLOCK_GetSysPllMultDiv (uint32_t refFreq, uint32_t desireFreq, uint8_t mult, uint8_t prediv)
	Calculates the MULT and PREDIV for the PLL. More...

status_t	CLOCK_InitSysPll (const scg_spll_config_t *config)
	Initializes the SCG system PLL. More...

status_t	CLOCK_DeinitSysPll (void)
	De-initializes the SCG system PLL. More...

static void	CLOCK_SetSysPllAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetSysPllFreq (void)
	Gets the SCG system PLL clock frequency. More...

uint32_t	CLOCK_GetSysPllAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the system PLL. More...

static bool	CLOCK_IsSysPllErr (void)
	Checks whether the system PLL clock error occurs. More...

static void	CLOCK_ClearSysPllErr (void)
	Clears the system PLL clock error.

static void	CLOCK_SetSysPllMonitorMode (scg_spll_monitor_mode_t mode)
	Sets the system PLL monitor mode. More...

static bool	CLOCK_IsSysPllValid (void)
	Checks whether the system PLL clock is valid. More...

OSC32 operations
void	OSC32_Init (OSC32_Type *base, osc32_mode_t mode)
	Initializes OSC32. More...

void	OSC32_Deinit (OSC32_Type *base)
	Deinitializes OSC32. More...

External clock frequency
static void	CLOCK_SetXtal0Freq (uint32_t freq)
	Sets the XTAL0 frequency based on board settings. More...

static void	CLOCK_SetXtal32Freq (uint32_t freq)
	Sets the XTAL32 frequency based on board settings. More...

Data Structure Documentation

struct scg_sys_clk_config_t

Data Fields
uint32_t	divSlow: 4
	Slow clock divider, see scg_sys_clk_div_t. More...

uint32_t	divBus: 4
	Bus clock divider, see scg_sys_clk_div_t. More...

uint32_t	__pad0__: 4
	Reserved. More...

uint32_t	__pad1__: 4
	Reserved. More...

uint32_t	divCore: 4
	Core clock divider, see scg_sys_clk_div_t. More...

uint32_t	__pad2__: 4
	Reserved. More...

uint32_t	src: 4
	System clock source, see scg_sys_clk_src_t. More...

uint32_t	__pad3__: 4
	reserved. More...

Field Documentation

uint32_t scg_sys_clk_config_t::divSlow

uint32_t scg_sys_clk_config_t::divBus

uint32_t scg_sys_clk_config_t::__pad0__

uint32_t scg_sys_clk_config_t::__pad1__

uint32_t scg_sys_clk_config_t::divCore

uint32_t scg_sys_clk_config_t::__pad2__

uint32_t scg_sys_clk_config_t::src

uint32_t scg_sys_clk_config_t::__pad3__

struct scg_sosc_config_t

Data Fields
uint32_t	freq
	System OSC frequency. More...

scg_sosc_monitor_mode_t	monitorMode
	Clock monitor mode selected. More...

uint8_t	enableMode
	Enable mode, OR'ed value of _scg_sosc_enable_mode. More...

scg_async_clk_div_t	div1
	SOSCDIV1 value. More...

scg_async_clk_div_t	div2
	SOSCDIV2 value. More...

scg_sosc_mode_t	workMode
	OSC work mode. More...

Field Documentation

uint32_t scg_sosc_config_t::freq

scg_sosc_monitor_mode_t scg_sosc_config_t::monitorMode

uint8_t scg_sosc_config_t::enableMode

scg_async_clk_div_t scg_sosc_config_t::div1

scg_async_clk_div_t scg_sosc_config_t::div2

scg_sosc_mode_t scg_sosc_config_t::workMode

struct scg_sirc_config_t

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _scg_sirc_enable_mode. More...

scg_async_clk_div_t	div1
	SIRCDIV1 value. More...

scg_async_clk_div_t	div2
	SIRCDIV2 value. More...

scg_sirc_range_t	range
	Slow IRC frequency range. More...

Field Documentation

uint32_t scg_sirc_config_t::enableMode

scg_async_clk_div_t scg_sirc_config_t::div1

scg_async_clk_div_t scg_sirc_config_t::div2

scg_sirc_range_t scg_sirc_config_t::range

struct scg_firc_trim_config_t

Data Fields
scg_firc_trim_mode_t	trimMode
	FIRC trim mode. More...

scg_firc_trim_src_t	trimSrc
	Trim source. More...

scg_firc_trim_div_t	trimDiv
	Trim predivided value for the system OSC. More...

uint8_t	trimCoar
	Trim coarse value; Irrelevant if trimMode is kSCG_FircTrimUpdate. More...

uint8_t	trimFine
	Trim fine value; Irrelevant if trimMode is kSCG_FircTrimUpdate. More...

Field Documentation

scg_firc_trim_mode_t scg_firc_trim_config_t::trimMode

scg_firc_trim_src_t scg_firc_trim_config_t::trimSrc

scg_firc_trim_div_t scg_firc_trim_config_t::trimDiv

uint8_t scg_firc_trim_config_t::trimCoar

uint8_t scg_firc_trim_config_t::trimFine

struct scg_firc_config_t

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _scg_firc_enable_mode. More...

scg_async_clk_div_t	div1
	FIRCDIV1 value. More...

scg_async_clk_div_t	div2
	FIRCDIV2 value. More...

scg_firc_range_t	range
	Fast IRC frequency range. More...

const scg_firc_trim_config_t *	trimConfig
	Pointer to the FIRC trim configuration; set NULL to disable trim. More...

Field Documentation

uint32_t scg_firc_config_t::enableMode

scg_async_clk_div_t scg_firc_config_t::div1

scg_async_clk_div_t scg_firc_config_t::div2

scg_firc_range_t scg_firc_config_t::range

const scg_firc_trim_config_t* scg_firc_config_t::trimConfig

struct scg_spll_config_t

Data Fields
uint8_t	enableMode
	Enable mode, OR'ed value of _scg_spll_enable_mode.

scg_spll_monitor_mode_t	monitorMode
	Clock monitor mode selected. More...

scg_async_clk_div_t	div1
	SPLLDIV1 value. More...

scg_async_clk_div_t	div2
	SPLLDIV2 value. More...

scg_spll_src_t	src
	Clock source. More...

uint8_t	prediv
	PLL reference clock divider. More...

uint8_t	mult
	System PLL multiplier. More...

Field Documentation

scg_spll_monitor_mode_t scg_spll_config_t::monitorMode

scg_async_clk_div_t scg_spll_config_t::div1

scg_async_clk_div_t scg_spll_config_t::div2

scg_spll_src_t scg_spll_config_t::src

uint8_t scg_spll_config_t::prediv

uint8_t scg_spll_config_t::mult

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))

#define DMAMUX_CLOCKS

Value:

{                  \
        kCLOCK_Dmamux0 \
    }

#define RTC_CLOCKS

Value:

{               \
        kCLOCK_Rtc0 \
    }

#define RTCOSC_CLOCKS

Value:

{                  \
        kCLOCK_RtcOsc0 \
    }

#define PORT_CLOCKS

Value:

{                                                                        \
        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
    }

#define LPI2C_CLOCKS

Value:

{                                \
        kCLOCK_Lpi2c0, kCLOCK_Lpi2c1 \
    }

#define FLEXIO_CLOCKS

Value:

{                  \
        kCLOCK_Flexio0 \
    }

#define EDMA_CLOCKS

Value:

{               \
        kCLOCK_Dma0 \
    }

#define LPUART_CLOCKS

Value:

{                                                  \
        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2 \
    }

#define DAC_CLOCKS

Value:

{               \
        kCLOCK_Dac0 \
    }

#define LPTMR_CLOCKS

Value:

{                 \
        kCLOCK_Lptmr0 \
    }

#define ADC12_CLOCKS

Value:

{                                         \
        kCLOCK_Adc0, kCLOCK_Adc1, kCLOCK_Adc2 \
    }

#define LPSPI_CLOCKS

Value:

{                                \
        kCLOCK_Lpspi0, kCLOCK_Lpspi1 \
    }

#define LPIT_CLOCKS

Value:

{                \
        kCLOCK_Lpit0 \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define CMP_CLOCKS

Value:

{                                         \
        kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
    }

#define FLASH_CLOCKS

Value:

{                 \
        kCLOCK_Flash0 \
    }

#define SYSMPU_CLOCKS

Value:

{                  \
        kCLOCK_Sysmpu0 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define FLEXCAN_CLOCKS

Value:

{                                    \
        kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
    }

#define FTM_CLOCKS

Value:

{                                                      \
        kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
    }

#define PDB_CLOCKS

Value:

{                                         \
        kCLOCK_Pdb0, kCLOCK_Pdb1, kCLOCK_Pdb2 \
    }

#define PWT_CLOCKS

Value:

{               \
        kCLOCK_Pwt0 \
    }

#define CLOCK_GetOsc0ErClkFreq CLOCK_GetErClkFreq

#define CLOCK_GetEr32kClkFreq CLOCK_GetOsc32kClkFreq

Enumeration Type Documentation

enum clock_name_t

Enumerator
kCLOCK_CoreSysClk	Core/system clock.
kCLOCK_BusClk	Bus clock.
kCLOCK_FlexBusClk	FlexBus clock.
kCLOCK_FlashClk	Flash clock.
kCLOCK_ScgSysOscClk	SCG system OSC clock. (SYSOSC)
kCLOCK_ScgSircClk	SCG SIRC clock.
kCLOCK_ScgFircClk	SCG FIRC clock.
kCLOCK_ScgSysPllClk	SCG system PLL clock. (SYSPLL)
kCLOCK_ScgSysOscAsyncDiv1Clk	SOSCDIV1_CLK.
kCLOCK_ScgSysOscAsyncDiv2Clk	SOSCDIV2_CLK.
kCLOCK_ScgSircAsyncDiv1Clk	SIRCDIV1_CLK.
kCLOCK_ScgSircAsyncDiv2Clk	SIRCDIV2_CLK.
kCLOCK_ScgFircAsyncDiv1Clk	FIRCDIV1_CLK.
kCLOCK_ScgFircAsyncDiv2Clk	FIRCDIV2_CLK.
kCLOCK_ScgSysPllAsyncDiv1Clk	SPLLDIV1_CLK.
kCLOCK_ScgSysPllAsyncDiv2Clk	SPLLDIV2_CLK.
kCLOCK_LpoClk	LPO clock.
kCLOCK_Osc32kClk	External OSC 32K clock (OSC32KCLK)
kCLOCK_ErClk	ERCLK. The external reference clock from SCG.

enum clock_ip_src_t

Enumerator
kCLOCK_IpSrcNoneOrExt	Clock is off or external clock is used.
kCLOCK_IpSrcSysOscAsync	System Oscillator async clock.
kCLOCK_IpSrcSircAsync	Slow IRC async clock.
kCLOCK_IpSrcFircAsync	Fast IRC async clock.
kCLOCK_IpSrcSysPllAsync	System PLL async clock.

enum clock_ip_name_t

It is defined as the corresponding register address.

enum osc32_mode_t

Enumerator
kOSC32_Bypass	Bypass mode, use external input clock directly.
kOSC32_Crystal	Crystal mode, does not work in stop mode.
kOSC32_CrystalEnableInStop	Crystal mode, still work in stop mode.

anonymous enum

Enumerator
kStatus_SCG_Busy	Clock is busy.
kStatus_SCG_InvalidSrc	Invalid source.

enum scg_sys_clk_t

Enumerator
kSCG_SysClkSlow	System slow clock.
kSCG_SysClkBus	Bus clock.
kSCG_SysClkCore	Core clock.

enum scg_sys_clk_src_t

Enumerator
kSCG_SysClkSrcSysOsc	System OSC.
kSCG_SysClkSrcSirc	Slow IRC.
kSCG_SysClkSrcFirc	Fast IRC.
kSCG_SysClkSrcSysPll	System PLL.

enum scg_sys_clk_div_t

Enumerator
kSCG_SysClkDivBy1	Divided by 1.
kSCG_SysClkDivBy2	Divided by 2.
kSCG_SysClkDivBy3	Divided by 3.
kSCG_SysClkDivBy4	Divided by 4.
kSCG_SysClkDivBy5	Divided by 5.
kSCG_SysClkDivBy6	Divided by 6.
kSCG_SysClkDivBy7	Divided by 7.
kSCG_SysClkDivBy8	Divided by 8.
kSCG_SysClkDivBy9	Divided by 9.
kSCG_SysClkDivBy10	Divided by 10.
kSCG_SysClkDivBy11	Divided by 11.
kSCG_SysClkDivBy12	Divided by 12.
kSCG_SysClkDivBy13	Divided by 13.
kSCG_SysClkDivBy14	Divided by 14.
kSCG_SysClkDivBy15	Divided by 15.
kSCG_SysClkDivBy16	Divided by 16.

enum clock_clkout_src_t

Enumerator
kClockClkoutSelScgSlow	SCG slow clock.
kClockClkoutSelSysOsc	System OSC.
kClockClkoutSelSirc	Slow IRC.
kClockClkoutSelFirc	Fast IRC.
kClockClkoutSelSysPll	System PLL.

enum scg_async_clk_t

Enumerator

kSCG_AsyncDiv1Clk

The async clock by DIV1, e.g.

SOSCDIV1_CLK, SIRCDIV1_CLK.

kSCG_AsyncDiv2Clk

The async clock by DIV2, e.g.

SOSCDIV2_CLK, SIRCDIV2_CLK.

enum scg_async_clk_div_t

Enumerator
kSCG_AsyncClkDisable	Clock output is disabled.
kSCG_AsyncClkDivBy1	Divided by 1.
kSCG_AsyncClkDivBy2	Divided by 2.
kSCG_AsyncClkDivBy4	Divided by 4.
kSCG_AsyncClkDivBy8	Divided by 8.
kSCG_AsyncClkDivBy16	Divided by 16.
kSCG_AsyncClkDivBy32	Divided by 32.
kSCG_AsyncClkDivBy64	Divided by 64.

enum scg_sosc_monitor_mode_t

Enumerator
kSCG_SysOscMonitorDisable	Monitor disabled.
kSCG_SysOscMonitorInt	Interrupt when the system OSC error is detected.
kSCG_SysOscMonitorReset	Reset when the system OSC error is detected.

enum scg_sosc_mode_t

Enumerator
kSCG_SysOscModeExt	Use external clock.
kSCG_SysOscModeOscLowPower	Oscillator low power.
kSCG_SysOscModeOscHighGain	Oscillator high gain.

anonymous enum

Enumerator
kSCG_SysOscEnable	Enable OSC clock.
kSCG_SysOscEnableInStop	Enable OSC in stop mode.
kSCG_SysOscEnableInLowPower	Enable OSC in low power mode.
kSCG_SysOscEnableErClk	Enable OSCERCLK.

enum scg_sirc_range_t

Enumerator
kSCG_SircRangeLow	Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP).
kSCG_SircRangeHigh	Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP).

anonymous enum

Enumerator
kSCG_SircEnable	Enable SIRC clock.
kSCG_SircEnableInStop	Enable SIRC in stop mode.
kSCG_SircEnableInLowPower	Enable SIRC in low power mode.

enum scg_firc_trim_mode_t

Enumerator

kSCG_FircTrimNonUpdate

FIRC trim enable but not enable trim value update.

In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure scg_firc_trim_config_t.

kSCG_FircTrimUpdate

FIRC trim enable and trim value update enable.

In this mode, the trim value is auto update.

enum scg_firc_trim_div_t

Enumerator
kSCG_FircTrimDivBy1	Divided by 1.
kSCG_FircTrimDivBy128	Divided by 128.
kSCG_FircTrimDivBy256	Divided by 256.
kSCG_FircTrimDivBy512	Divided by 512.
kSCG_FircTrimDivBy1024	Divided by 1024.
kSCG_FircTrimDivBy2048	Divided by 2048.

enum scg_firc_trim_src_t

Enumerator
kSCG_FircTrimSrcSysOsc	System OSC.

enum scg_firc_range_t

Enumerator
kSCG_FircRange48M	Fast IRC is trimmed to 48 MHz.
kSCG_FircRange52M	Fast IRC is trimmed to 52 MHz.
kSCG_FircRange56M	Fast IRC is trimmed to 56 MHz.
kSCG_FircRange60M	Fast IRC is trimmed to 60 MHz.

anonymous enum

Enumerator
kSCG_FircEnable	Enable FIRC clock.
kSCG_FircEnableInStop	Enable FIRC in stop mode.
kSCG_FircEnableInLowPower	Enable FIRC in low power mode.
kSCG_FircDisableRegulator	Disable regulator.

enum scg_spll_src_t

Enumerator
kSCG_SysPllSrcSysOsc	System PLL clock source is system OSC.
kSCG_SysPllSrcFirc	System PLL clock source is fast IRC.

enum scg_spll_monitor_mode_t

Enumerator
kSCG_SysPllMonitorDisable	Monitor disabled.
kSCG_SysPllMonitorInt	Interrupt when the system PLL error is detected.
kSCG_SysPllMonitorReset	Reset when the system PLL error is detected.

anonymous enum

Enumerator
kSCG_SysPllEnable	Enable SPLL clock.
kSCG_SysPllEnableInStop	Enable SPLL in stop mode.

Function Documentation

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

static bool CLOCK_IsEnabledByOtherCore ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which peripheral to check, see clock_ip_name_t.

Returns: True if clock is already enabled, otherwise false.

static void CLOCK_SetIpSrc	(	clock_ip_name_t	name,
		clock_ip_src_t	src
	)

inlinestatic

Set the clock source for specific IP, not all modules need to set the clock source, should only use this function for the modules need source setting.

Parameters

name	Which peripheral to check, see clock_ip_name_t.
src	Clock source to set.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetBusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFlashClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetOsc32kClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetErClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetIpFreq ( clock_ip_name_t name )

This function gets the IP module clock frequency based on PCC registers. It is only used for the IP modules which could select clock source by PCC[PCS].

Parameters

name	Which peripheral to get, see clock_ip_name_t.

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetSysClkFreq ( scg_sys_clk_t type )

This function gets the SCG system clock frequency. These clocks are used for core, platform, external, and bus clock domains.

Parameters

type	Which type of clock to get, core clock or slow clock.

Returns: Clock frequency.

static void CLOCK_SetVlprModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for VLPR mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetRunModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for RUN mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetHsrunModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for HSRUN mode.

Parameters

config Pointer to the configuration.

static void CLOCK_GetCurSysClkConfig ( scg_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration in the current power mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetClkOutSel ( clock_clkout_src_t setting )

inlinestatic

This function sets the clock out selection (CLKOUTSEL).

Parameters

setting The selection to set.

Returns: The current clock out selection.

status_t CLOCK_InitSysOsc ( const scg_sosc_config_t * config )

This function enables the SCG system OSC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	System OSC is initialized.
kStatus_SCG_Busy	System OSC has been enabled and is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note: This function can't detect whether the system OSC has been enabled and used by an IP.

status_t CLOCK_DeinitSysOsc ( void )

This function disables the SCG system OSC clock.

Return values

kStatus_Success	System OSC is deinitialized.
kStatus_SCG_Busy	System OSC is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note: This function can't detect whether the system OSC is used by an IP.

static void CLOCK_SetSysOscAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetSysOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSysOscAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsSysOscErr ( void )

inlinestatic

Returns: True if the error occurs, false if not.

static void CLOCK_SetSysOscMonitorMode ( scg_sosc_monitor_mode_t mode )

inlinestatic

This function sets the system OSC monitor mode. The mode can be disabled, it can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

static bool CLOCK_IsSysOscValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

status_t CLOCK_InitSirc ( const scg_sirc_config_t * config )

This function enables the SCG slow IRC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	SIRC is initialized.
kStatus_SCG_Busy	SIRC has been enabled and is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note: This function can't detect whether the system OSC has been enabled and used by an IP.

status_t CLOCK_DeinitSirc ( void )

This function disables the SCG slow IRC.

Return values

kStatus_Success	SIRC is deinitialized.
kStatus_SCG_Busy	SIRC is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note: This function can't detect whether the SIRC is used by an IP.

static void CLOCK_SetSircAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetSircFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSircAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsSircValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

status_t CLOCK_InitFirc ( const scg_firc_config_t * config )

This function enables the SCG fast IRC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	FIRC is initialized.
kStatus_SCG_Busy	FIRC has been enabled and is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note: This function can't detect whether the FIRC has been enabled and used by an IP.

status_t CLOCK_DeinitFirc ( void )

This function disables the SCG fast IRC.

Return values

kStatus_Success	FIRC is deinitialized.
kStatus_SCG_Busy	FIRC is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note: This function can't detect whether the FIRC is used by an IP.

static void CLOCK_SetFircAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetFircFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFircAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsFircErr ( void )

inlinestatic

Returns: True if the error occurs, false if not.

static bool CLOCK_IsFircValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

uint32_t CLOCK_GetSysPllMultDiv	(	uint32_t	refFreq,
		uint32_t	desireFreq,
		uint8_t *	mult,
		uint8_t *	prediv
	)

This function calculates the proper MULT and PREDIV to generate the desired PLL output frequency with the input reference clock frequency. It returns the closest frequency match that the PLL can generate. The corresponding MULT/PREDIV are returned with parameters. If the desired frequency is not valid, this function returns 0.

Parameters

refFreq	The input reference clock frequency.
desireFreq	The desired output clock frequency.
mult	The value of MULT.
prediv	The value of PREDIV.

Returns: The PLL output frequency with the MULT and PREDIV; If the desired frequency can't be generated, this function returns 0U.

status_t CLOCK_InitSysPll ( const scg_spll_config_t * config )

This function enables the SCG system PLL clock according to the configuration. The system PLL can use the system OSC or FIRC as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing SPLL clock output:

* const scg_spll_config_t g_scgSysPllConfig = {.enableMode = kSCG_SysPllEnable,
*                                            .monitorMode = kSCG_SysPllMonitorDisable,
*                                            .div1 = kSCG_AsyncClkDivBy1,
*                                            .div2 = kSCG_AsyncClkDisable,
*                                            .div3 = kSCG_AsyncClkDivBy2,
*                                            .src = kSCG_SysPllSrcFirc,
*                                            .isBypassSelected = false,
*                                            .isPfdSelected = false,
*                                            .prediv = 5U,
*                                            .pfdClkout = kSCG_AuxPllPfd0Clk,
*                                            .mult = 20U,
*                                            .pllPostdiv1 = kSCG_SysClkDivBy3,
*                                            .pllPostdiv2 = kSCG_SysClkDivBy4};
* CLOCK_InitSysPll(&g_scgSysPllConfig);
* 

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	System PLL is initialized.
kStatus_SCG_Busy	System PLL has been enabled and is used by the system clock.
kStatus_ReadOnly	System PLL control register is locked.

Note: This function can't detect whether the system PLL has been enabled and used by an IP.

status_t CLOCK_DeinitSysPll ( void )

This function disables the SCG system PLL.

Return values

kStatus_Success	system PLL is deinitialized.
kStatus_SCG_Busy	system PLL is used by the system clock.
kStatus_ReadOnly	System PLL control register is locked.

Note: This function can't detect whether the system PLL is used by an IP.

static void CLOCK_SetSysPllAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetSysPllFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSysPllAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsSysPllErr ( void )

inlinestatic

Returns: True if an error occurs, false if not.

static void CLOCK_SetSysPllMonitorMode ( scg_spll_monitor_mode_t mode )

inlinestatic

This function sets the system PLL monitor mode. The mode can be disabled. It can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

static bool CLOCK_IsSysPllValid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

void OSC32_Init	(	OSC32_Type *	base,
		osc32_mode_t	mode
	)

Parameters

base	OSC32 peripheral base address.
mode	OSC32 work mode, see osc32_mode_t

void OSC32_Deinit ( OSC32_Type * base )

Parameters

base	OSC32 peripheral base address.

static void CLOCK_SetXtal0Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL0/EXTAL0 input clock frequency in Hz.

static void CLOCK_SetXtal32Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL32/EXTAL32 input clock frequency in Hz.

Variable Documentation

volatile uint32_t g_xtal0Freq

The XTAL0/EXTAL0 (OSC0/SYSOSC) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:

* CLOCK_InitSysOsc(...);
* CLOCK_SetXtal0Freq(80000000);
* 

This is important for the multicore platforms where only one core needs to set up the OSC0/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.

volatile uint32_t g_xtal32Freq

The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.

Overview

Modules

Files

Data Structures

Macros

Enumerations

Functions

Variables

Driver version

MCU System Clock.

SCG System OSC Clock.

SCG Slow IRC Clock.

SCG Fast IRC Clock.

SCG System PLL Clock.

OSC32 operations

External clock frequency

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation