This section describes the programming interface of the SPI Cortex Microcontroller Software Interface Standard (CMSIS) driver. And this driver defines generic peripheral driver interfaces for middleware making it reusable across a wide range of supported microcontroller devices. The API connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces. More information and usage methord see http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
Function groups
SPI CMSIS GetVersion Operation
This function group will return the SPI CMSIS Driver version to user.
SPI CMSIS GetCapabilities Operation
This function group will return the capabilities of this driver.
SPI CMSIS Initialize and Uninitialize Operation
This function will initialize and uninitialize the instance in master mode or slave mode. And this API must be called before you configure an instance or after you Deinit an instance.The right steps to start an instance is that you must initialize the instance which been slected firstly,then you can power on the instance.After these all have been done,you can configure the instance by using control operation.If you want to Uninitialize the instance, you must power off the instance first.
SPI CMSIS Transfer Operation
This function group controls the transfer, master send/receive data, and slave send/receive data.
SPI CMSIS Status Operation
This function group gets the SPI transfer status.
SPI CMSIS Control Operation
This function can configure instance as master mode or slave mode, set baudrate for master mode transfer, get current baudrate of master mode transfer,set transfer data bits and other control command.
Typical use case
Master Operation
uint8_t masterRxData[TRANSFER_SIZE] = {0U};
uint8_t masterTxData[TRANSFER_SIZE] = {0U};
DRIVER_MASTER_SPI.Initialize(SPI_MasterSignalEvent_t);
DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL);
DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE);
DRIVER_MASTER_SPI.Transfer(masterTxData, masterRxData, TRANSFER_SIZE);
DRIVER_MASTER_SPI.PowerControl(ARM_POWER_OFF);
DRIVER_MASTER_SPI.Uninitialize();
Slave Operation
uint8_t slaveRxData[TRANSFER_SIZE] = {0U};
uint8_t slaveTxData[TRANSFER_SIZE] = {0U};
DRIVER_SLAVE_SPI.Initialize(SPI_SlaveSignalEvent_t);
DRIVER_SLAVE_SPI.PowerControl(ARM_POWER_FULL);
DRIVER_SLAVE_SPI.Control(ARM_SPI_MODE_SLAVE, false);
DRIVER_SLAVE_SPI.Transfer(slaveTxData, slaveRxData, TRANSFER_SIZE);
DRIVER_SLAVE_SPI.PowerControl(ARM_POWER_OFF);
DRIVER_SLAVE_SPI.Uninitialize();
This section describes the programming interface of the SPI DMA driver.
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#define | SPI_DUMMYDATA (0xFFU) |
| SPI dummy transfer data, the data is sent while txBuff is NULL. More...
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enum | spi_xfer_option_t {
kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK),
kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK)
} |
| SPI transfer option. More...
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enum | spi_shift_direction_t {
kSPI_MsbFirst = 0U,
kSPI_LsbFirst = 1U
} |
| SPI data shifter direction options. More...
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enum | spi_clock_polarity_t {
kSPI_ClockPolarityActiveHigh = 0x0U,
kSPI_ClockPolarityActiveLow
} |
| SPI clock polarity configuration. More...
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enum | spi_clock_phase_t {
kSPI_ClockPhaseFirstEdge = 0x0U,
kSPI_ClockPhaseSecondEdge
} |
| SPI clock phase configuration. More...
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enum | spi_txfifo_watermark_t {
kSPI_TxFifo0 = 0,
kSPI_TxFifo1 = 1,
kSPI_TxFifo2 = 2,
kSPI_TxFifo3 = 3,
kSPI_TxFifo4 = 4,
kSPI_TxFifo5 = 5,
kSPI_TxFifo6 = 6,
kSPI_TxFifo7 = 7
} |
| txFIFO watermark values More...
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enum | spi_rxfifo_watermark_t {
kSPI_RxFifo1 = 0,
kSPI_RxFifo2 = 1,
kSPI_RxFifo3 = 2,
kSPI_RxFifo4 = 3,
kSPI_RxFifo5 = 4,
kSPI_RxFifo6 = 5,
kSPI_RxFifo7 = 6,
kSPI_RxFifo8 = 7
} |
| rxFIFO watermark values More...
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enum | spi_data_width_t {
kSPI_Data4Bits = 3,
kSPI_Data5Bits = 4,
kSPI_Data6Bits = 5,
kSPI_Data7Bits = 6,
kSPI_Data8Bits = 7,
kSPI_Data9Bits = 8,
kSPI_Data10Bits = 9,
kSPI_Data11Bits = 10,
kSPI_Data12Bits = 11,
kSPI_Data13Bits = 12,
kSPI_Data14Bits = 13,
kSPI_Data15Bits = 14,
kSPI_Data16Bits = 15
} |
| Transfer data width. More...
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enum | spi_ssel_t {
kSPI_Ssel0 = 0,
kSPI_Ssel1 = 1,
kSPI_Ssel2 = 2,
kSPI_Ssel3 = 3
} |
| Slave select. More...
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enum | spi_spol_t |
| ssel polarity
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enum | {
kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0),
kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1),
kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2),
kStatus_SPI_BaudrateNotSupport
} |
| SPI transfer status. More...
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enum | _spi_interrupt_enable {
kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK,
kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK
} |
| SPI interrupt sources. More...
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enum | _spi_statusflags {
kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK,
kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK,
kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK,
kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK
} |
| SPI status flags. More...
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struct spi_delay_config_t |
Note: The DLY register controls several programmable delays related to SPI signalling, it stands for how many SPI clock time will be inserted. The maxinun value of these delay time is 15.
uint8_t spi_delay_config_t::preDelay |
uint8_t spi_delay_config_t::postDelay |
uint8_t spi_delay_config_t::frameDelay |
uint8_t spi_delay_config_t::transferDelay |
struct spi_master_config_t |
struct spi_slave_config_t |
uint32_t spi_transfer_t::configFlags |
struct spi_half_duplex_transfer_t |
uint32_t spi_half_duplex_transfer_t::configFlags |
bool spi_half_duplex_transfer_t::isPcsAssertInTransfer |
true for assert and false for deassert.
bool spi_half_duplex_transfer_t::isTransmitFirst |
struct _spi_master_handle |
#define SPI_DUMMYDATA (0xFFU) |
typedef void(* flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle) |
typedef void(* flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle) |
Enumerator |
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kSPI_FrameDelay |
A delay may be inserted, defined in the DLY register.
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kSPI_FrameAssert |
SSEL will be deasserted at the end of a transfer.
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Enumerator |
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kSPI_MsbFirst |
Data transfers start with most significant bit.
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kSPI_LsbFirst |
Data transfers start with least significant bit.
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Enumerator |
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kSPI_ClockPolarityActiveHigh |
Active-high SPI clock (idles low).
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kSPI_ClockPolarityActiveLow |
Active-low SPI clock (idles high).
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Enumerator |
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kSPI_ClockPhaseFirstEdge |
First edge on SCK occurs at the middle of the first cycle of a data transfer.
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kSPI_ClockPhaseSecondEdge |
First edge on SCK occurs at the start of the first cycle of a data transfer.
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Enumerator |
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kSPI_TxFifo0 |
SPI tx watermark is empty.
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kSPI_TxFifo1 |
SPI tx watermark at 1 item.
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kSPI_TxFifo2 |
SPI tx watermark at 2 items.
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kSPI_TxFifo3 |
SPI tx watermark at 3 items.
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kSPI_TxFifo4 |
SPI tx watermark at 4 items.
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kSPI_TxFifo5 |
SPI tx watermark at 5 items.
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kSPI_TxFifo6 |
SPI tx watermark at 6 items.
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kSPI_TxFifo7 |
SPI tx watermark at 7 items.
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Enumerator |
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kSPI_RxFifo1 |
SPI rx watermark at 1 item.
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kSPI_RxFifo2 |
SPI rx watermark at 2 items.
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kSPI_RxFifo3 |
SPI rx watermark at 3 items.
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kSPI_RxFifo4 |
SPI rx watermark at 4 items.
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kSPI_RxFifo5 |
SPI rx watermark at 5 items.
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kSPI_RxFifo6 |
SPI rx watermark at 6 items.
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kSPI_RxFifo7 |
SPI rx watermark at 7 items.
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kSPI_RxFifo8 |
SPI rx watermark at 8 items.
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Enumerator |
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kSPI_Data4Bits |
4 bits data width
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kSPI_Data5Bits |
5 bits data width
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kSPI_Data6Bits |
6 bits data width
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kSPI_Data7Bits |
7 bits data width
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kSPI_Data8Bits |
8 bits data width
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kSPI_Data9Bits |
9 bits data width
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kSPI_Data10Bits |
10 bits data width
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kSPI_Data11Bits |
11 bits data width
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kSPI_Data12Bits |
12 bits data width
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kSPI_Data13Bits |
13 bits data width
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kSPI_Data14Bits |
14 bits data width
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kSPI_Data15Bits |
15 bits data width
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kSPI_Data16Bits |
16 bits data width
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Enumerator |
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kSPI_Ssel0 |
Slave select 0.
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kSPI_Ssel1 |
Slave select 1.
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kSPI_Ssel2 |
Slave select 2.
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kSPI_Ssel3 |
Slave select 3.
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Enumerator |
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kStatus_SPI_Busy |
SPI bus is busy.
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kStatus_SPI_Idle |
SPI is idle.
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kStatus_SPI_Error |
SPI error.
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kStatus_SPI_BaudrateNotSupport |
Baudrate is not support in current clock source.
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Enumerator |
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kSPI_RxLvlIrq |
Rx level interrupt.
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kSPI_TxLvlIrq |
Tx level interrupt.
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Enumerator |
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kSPI_TxEmptyFlag |
txFifo is empty
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kSPI_TxNotFullFlag |
txFifo is not full
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kSPI_RxNotEmptyFlag |
rxFIFO is not empty
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kSPI_RxFullFlag |
rxFIFO is full
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volatile uint8_t s_dummyData[] |