Power driver

Overview

The MCUXpresso SDK provides a power driver for the MCUXpresso SDK devices.

Function description

Power driver and library provides these functions:

• Functions to enable and disable power to different peripherals
• Functions to enable and disable deep sleep in the ARM Core.
• Functions to enter deep sleep mode and deep power down mode
• Functions to set the voltages for different frequency for both normal regulation and low power regulation modes

Power enable and disable

Power driver provides two API's POWER_EnablePD() and POWER_DisablePD() to enable or disable the PDRUNCFG bits in SYSCON The PDRUNCFG has an inverted logic, for example, the peripheral is powered on when the bit is cleared and powered off when bit is set. The API POWER_DisablePD() is used to power on a peripheral and POWER_EnablePD() is used to power off a peripheral. The API takes a parameter type pd_bit_t, which organizes the PDRUNCFG bits. The driver also provides two separate API's to power down and power up Flash, POWER_PowerDownFlash(), and POWER_PowerUpFlash()

Enable and Disable Deep Sleep in Core

The power driver provides two API's POWER_EnableDeepSleep() and POWER_DisableDeepSleep() to enable or disable the deep sleep bit in the ARM Core. POWER_EnableDeepSleep() is used to enable deep sleep, and POWER_DisableDeepSleep() is used to disable deep sleep.

Entering Power Modes

The Power library provides two API's to enter low power modes, for example, Deep Sleep and Deep Power Down. Deep Sleep is a sleep mode in which the ARM Core, Flash, and many other peripheral are turned off to save power. The processor can be woken by an IO activity and resumes executing from next instruction after sleep. If a peripheral or RAM needs to On for wakeup or to retain memory then those peripheral need to be kept on during deep sleep. Deep power down is a power down mode where the processor resets upon wake up and during power down the entire part is powered down except for the RTC. For Deep Power Down only the Reset and RTC Alarm or WakeUp can be wakeup sources. The power library provides an API POWER_EnterDeepSleep() to enter deep sleep mode. This function takes a parameter which is a bit mask of the PDRUNCFG register. Any bit that is set is powered on during deep sleep. This mask would usually has the RAM memory that needs to retain power and also any wakeup source. The API POWER_EnterDeepPowerDown() is used to enter deep power down mode. This API also has a parameter but since the voltage is cut off for the peripheral this parameter has no effect

Set Voltages for Frequency

The power library provides API's to set the voltage for the desired operating frequency of the processor. The voltage regulation system can be in normal regulation mode or in low power regulation mode. The API POWER_SetVoltageForFreq() is used to set the voltage for normal regulation mode. Based on the frequency parameter the optimum voltage level is set. The API POWER_SetLowPowerVoltageForFreq() is used to set the low-power voltage regulation mode and set the voltages for the desired frequency. For POWER_SetLowPowerVoltageForFreq() only two FRO frequencies are supported, 12MHz and 48 MHz.

Typical use case

Power Enable and Set Voltage example

POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on so that we can switch to its 12MHz mode temporarily 

Data Structures
struct	LPC_LOWPOWER_T
	Low Power main structure. More...
struct	lowpower_driver_interface_t
	Interface for lowpower functions. More...

Macros
#define	LOWPOWER_CFG_LPMODE_ACTIVE   0
	ACTIVE mode.
#define	LOWPOWER_CFG_LPMODE_DEEPSLEEP   1
	DEEP SLEEP mode.
#define	LOWPOWER_CFG_LPMODE_POWERDOWN   2
	POWER DOWN mode.
#define	LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN   3
	DEEP POWER DOWN mode.
#define	LOWPOWER_CFG_LPMODE_SLEEP   4
	SLEEP mode.
#define	LOWPOWER_CFG_SELCLOCK_1MHZ   0
	The 1 MHz clock is used during the configuration of the PMC.
#define	LOWPOWER_CFG_SELCLOCK_12MHZ   1
	The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)
#define	LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM   0
	In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM.
#define	LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP   1
	In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC)
#define	LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING   0
	All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible – 1.1V typical – during low power mode)
#define	LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING   1
	All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible – down to 0.7V – during low power mode)
#define	LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER   0
	LDO DEEP SLEEP uses Flash Buffer as reference.
#define	LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V   1
	LDO DEEP SLEEP uses Band Gap 0.8V as reference.
#define	LOWPOWER_CPURETCTRL_ENA_DISABLE   0
	In POWER DOWN mode, CPU Retention is disabled.
#define	LOWPOWER_CPURETCTRL_ENA_ENABLE   1
	In POWER DOWN mode, CPU Retention is enabled.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX0   (1UL << 0)
	SRAM instances retention control during low power modes. More...
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX1   (1UL << 1)
	Enable SRAMX_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX2   (1UL << 2)
	Enable SRAMX_2 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX3   (1UL << 3)
	Enable SRAMX_3 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM00   (1UL << 4)
	Enable SRAM0_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM01   (1UL << 5)
	Enable SRAM0_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM10   (1UL << 6)
	Enable SRAM1_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM20   (1UL << 7)
	Enable SRAM2_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM30   (1UL << 8)
	Enable SRAM3_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM31   (1UL << 9)
	Enable SRAM3_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM40   (1UL << 10)
	Enable SRAM4_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM41   (1UL << 11)
	Enable SRAM4_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM42   (1UL << 12)
	Enable SRAM4_2 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM43   (1UL << 13)
	Enable SRAM4_3 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS   (1UL << 14)
	Enable SRAM USB HS retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF   (1UL << 15)
	Enable SRAM PUFF retention when entering in Low power modes.
#define	LOWPOWER_SRAM_LPMODE_MASK   (0xFUL)
	SRAM Low Power Modes.
#define	LOWPOWER_SRAM_LPMODE_ACTIVE   (0x6UL)
	SRAM functional mode.
#define	LOWPOWER_SRAM_LPMODE_SLEEP   (0xFUL)
	SRAM Sleep mode (Data retention, fast wake up)
#define	LOWPOWER_SRAM_LPMODE_DEEPSLEEP   (0x8UL)
	SRAM Deep Sleep mode (Data retention, slow wake up)
#define	LOWPOWER_SRAM_LPMODE_SHUTDOWN   (0x9UL)
	SRAM Shut Down mode (no data retention)
#define	LOWPOWER_SRAM_LPMODE_POWERUP   (0xAUL)
	SRAM is powering up.
#define	LOWPOWER_VOLTAGE_LDO_PMU_INDEX   0
	LDO Voltage control in Low Power Modes.
#define	WAKEUP_SYS   (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
	Low Power Modes Wake up sources.
#define	WAKEUP_SDMA0   (1ULL << 1)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_GLOBALINT0   (1ULL << 2)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_GLOBALINT1   (1ULL << 3)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_INT0_0   (1ULL << 4)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_1   (1ULL << 5)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_2   (1ULL << 6)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_3   (1ULL << 7)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_UTICK   (1ULL << 8)
	[SLEEP, ]
#define	WAKEUP_MRT   (1ULL << 9)
	[SLEEP, ]
#define	WAKEUP_CTIMER0   (1ULL << 10)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER1   (1ULL << 11)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SCT   (1ULL << 12)
	[SLEEP, ]
#define	WAKEUP_CTIMER3   (1ULL << 13)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM0   (1ULL << 14)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM1   (1ULL << 15)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM2   (1ULL << 16)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM3   (1ULL << 17)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_FLEXCOMM4   (1ULL << 18)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM5   (1ULL << 19)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM6   (1ULL << 20)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM7   (1ULL << 21)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_ADC   (1ULL << 22)
	[SLEEP, ]
#define	WAKEUP_ACMP_CAPT   (1ULL << 24)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_USB0_NEEDCLK   (1ULL << 27)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_USB0   (1ULL << 28)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_RTC_LITE_ALARM_WAKEUP   (1ULL << 29)
	[SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN]
#define	WAKEUP_EZH_ARCH_B   (1ULL << 30)
	[SLEEP, ]
#define	WAKEUP_WAKEUP_MAILBOX   (1ULL << 31)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_INT0_4   (1ULL << 32)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_5   (1ULL << 33)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_6   (1ULL << 34)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_7   (1ULL << 35)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER2   (1ULL << 36)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER4   (1ULL << 37)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_OS_EVENT_TIMER   (1ULL << 38)
	[SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN]
#define	WAKEUP_SDIO   (1ULL << 42)
	[SLEEP, ]
#define	WAKEUP_USB1   (1ULL << 47)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_USB1_NEEDCLK   (1ULL << 48)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SEC_HYPERVISOR_CALL   (1ULL << 49)
	[SLEEP, ]
#define	WAKEUP_SEC_GPIO_INT0_0   (1ULL << 50)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SEC_GPIO_INT0_1   (1ULL << 51)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_PLU   (1ULL << 52)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SHA   (1ULL << 54)
	[SLEEP, ]
#define	WAKEUP_CASPER   (1ULL << 55)
	[SLEEP, ]
#define	WAKEUP_PUFF   (1ULL << 56)
	[SLEEP, ]
#define	WAKEUP_PQ   (1ULL << 57)
	[SLEEP, ]
#define	WAKEUP_SDMA1   (1ULL << 58)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_LSPI_HS   (1ULL << 59)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_ALLWAKEUPIOS   (1ULL << 63)
	[ , DEEP POWER DOWN]
#define	LOWPOWER_HWWAKE_FORCED   (1UL << 0)
	Sleep Postpone. More...
#define	LOWPOWER_HWWAKE_PERIPHERALS   (1UL << 1)
	Wake for Flexcomms. More...
#define	LOWPOWER_HWWAKE_SDMA0   (1UL << 3)
	Wake for DMA0. More...
#define	LOWPOWER_HWWAKE_SDMA1   (1UL << 5)
	Wake for DMA1. More...
#define	LOWPOWER_HWWAKE_ENABLE_FRO192M   (1UL << 31)
	Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set.
#define	LOWPOWER_WAKEUPIOSRC_PIO0_INDEX   0
	Wake up I/O sources. More...
#define	LOWPOWER_WAKEUPIOSRC_PIO1_INDEX   2
	Pin P0(28)
#define	LOWPOWER_WAKEUPIOSRC_PIO2_INDEX   4
	Pin P1(18)
#define	LOWPOWER_WAKEUPIOSRC_PIO3_INDEX   6
	Pin P1(30)
#define	LOWPOWER_WAKEUPIOSRC_DISABLE   0
	Wake up is disable.
#define	LOWPOWER_WAKEUPIOSRC_RISING   1
	Wake up on rising edge.
#define	LOWPOWER_WAKEUPIOSRC_FALLING   2
	Wake up on falling edge.
#define	LOWPOWER_WAKEUPIOSRC_RISING_FALLING   3
	Wake up on both rising or falling edges.
#define	LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX   8
	Wake-up I/O 0 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX   9
	Wake-up I/O 1 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX   10
	Wake-up I/O 2 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX   11
	Wake-up I/O 3 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX)
	Wake-up I/O 0 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX)
	Wake-up I/O 1 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX)
	Wake-up I/O 2 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX)
	Wake-up I/O 3 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PULLDOWN   0
	Select pull-down.
#define	LOWPOWER_WAKEUPIO_PULLUP   1
	Select pull-up.
#define	LOWPOWER_TIMERCFG_CTRL_INDEX   0
	Wake up timers configuration in Low Power Modes.
#define	LOWPOWER_TIMERCFG_CTRL_DISABLE   0
	Wake Timer Disable.
#define	LOWPOWER_TIMERCFG_CTRL_ENABLE   1
	Wake Timer Enable.
#define	LOWPOWER_TIMERCFG_TIMER_RTC1KHZ   0
	Primary Wake up timers configuration in Low Power Modes. More...
#define	LOWPOWER_TIMERCFG_TIMER_RTC1HZ   1
	1 Hz Real Time Counter (RTC) used as wake up source
#define	LOWPOWER_TIMERCFG_TIMER_OSTIMER   2
	OS Event Timer used as wake up source.
#define	LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ   0
	Wake up Timers uses FRO 32 KHz as clock source.
#define	LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ   1
	Wake up Timers uses Chrystal 32 KHz as clock source.

Enumerations
enum	LPC_POWER_DOMAIN_T {   VD_AON = 0x0,   VD_MEM = 0x1,   VD_DCDC = 0x2,   VD_DEEPSLEEP = 0x3 }
	Low Power main structure. More...
enum	pd_bit_t
	Analog components power modes control during low power modes.
enum	power_bod_vbat_level_t {   kPOWER_BodVbatLevel1000mv = 0,   kPOWER_BodVbatLevel1100mv = 1,   kPOWER_BodVbatLevel1200mv = 2,   kPOWER_BodVbatLevel1300mv = 3,   kPOWER_BodVbatLevel1400mv = 4,   kPOWER_BodVbatLevel1500mv = 5,   kPOWER_BodVbatLevel1600mv = 6,   kPOWER_BodVbatLevel1650mv = 7,   kPOWER_BodVbatLevel1700mv = 8,   kPOWER_BodVbatLevel1750mv = 9,   kPOWER_BodVbatLevel1800mv = 10,   kPOWER_BodVbatLevel1900mv = 11,   kPOWER_BodVbatLevel2000mv = 12,   kPOWER_BodVbatLevel2100mv = 13,   kPOWER_BodVbatLevel2200mv = 14,   kPOWER_BodVbatLevel2300mv = 15,   kPOWER_BodVbatLevel2400mv = 16,   kPOWER_BodVbatLevel2500mv = 17,   kPOWER_BodVbatLevel2600mv = 18,   kPOWER_BodVbatLevel2700mv = 19,   kPOWER_BodVbatLevel2806mv = 20,   kPOWER_BodVbatLevel2900mv = 21,   kPOWER_BodVbatLevel3000mv = 22,   kPOWER_BodVbatLevel3100mv = 23,   kPOWER_BodVbatLevel3200mv = 24,   kPOWER_BodVbatLevel3300mv = 25 }
enum	power_bod_core_level_t {   kPOWER_BodCoreLevel600mv = 0,   kPOWER_BodCoreLevel650mv = 1,   kPOWER_BodCoreLevel700mv = 2,   kPOWER_BodCoreLevel750mv = 3,   kPOWER_BodCoreLevel800mv = 4,   kPOWER_BodCoreLevel850mv = 5,   kPOWER_BodCoreLevel900mv = 6,   kPOWER_BodCoreLevel950mv = 7 }
enum	power_bod_hyst_t {   kPOWER_BodHystLevel25mv = 0U,   kPOWER_BodHystLevel50mv = 1U,   kPOWER_BodHystLevel75mv = 2U,   kPOWER_BodHystLevel100mv = 3U }
enum	v_ao_t {   V_AO_0P700 = 1,   V_AO_0P725 = 2,   V_AO_0P750 = 3,   V_AO_0P775 = 4,   V_AO_0P800 = 5,   V_AO_0P825 = 6,   V_AO_0P850 = 7,   V_AO_0P875 = 8,   V_AO_0P900 = 9,   V_AO_0P960 = 10,   V_AO_0P970 = 11,   V_AO_0P980 = 12,   V_AO_0P990 = 13,   V_AO_1P000 = 14,   V_AO_1P010 = 15,   V_AO_1P020 = 16,   V_AO_1P030 = 17,   V_AO_1P040 = 18,   V_AO_1P050 = 19,   V_AO_1P060 = 20,   V_AO_1P070 = 21,   V_AO_1P080 = 22,   V_AO_1P090 = 23,   V_AO_1P100 = 24,   V_AO_1P110 = 25,   V_AO_1P120 = 26,   V_AO_1P130 = 27,   V_AO_1P140 = 28,   V_AO_1P150 = 29,   V_AO_1P160 = 30,   V_AO_1P220 = 31 }
	Always On and Memories LDO voltage settings. More...
enum	v_deepsleep_t {   V_DEEPSLEEP_0P900 = 0,   V_DEEPSLEEP_0P925 = 1,   V_DEEPSLEEP_0P950 = 2,   V_DEEPSLEEP_0P975 = 3,   V_DEEPSLEEP_1P000 = 4,   V_DEEPSLEEP_1P025 = 5,   V_DEEPSLEEP_1P050 = 6,   V_DEEPSLEEP_1P075 = 7 }
	Deep Sleep LDO voltage settings. More...
enum	v_dcdc_t {   V_DCDC_0P950 = 0,   V_DCDC_0P975 = 1,   V_DCDC_1P000 = 2,   V_DCDC_1P025 = 3,   V_DCDC_1P050 = 4,   V_DCDC_1P075 = 5,   V_DCDC_1P100 = 6,   V_DCDC_1P125 = 7,   V_DCDC_1P150 = 8,   V_DCDC_1P175 = 9,   V_DCDC_1P200 = 10 }
	DCDC voltage settings. More...
enum	v_flashnv_t {   V_LDOFLASHNV_1P650 = 0,   V_LDOFLASHNV_1P700 = 1,   V_LDOFLASHNV_1P750 = 2,   V_LDOFLASHNV_0P800 = 3,   V_LDOFLASHNV_1P850 = 4,   V_LDOFLASHNV_1P900 = 5,   V_LDOFLASHNV_1P950 = 6,   V_LDOFLASHNV_2P000 = 7 }
	LDO_FLASH_NV & LDO_USB voltage settings. More...

Functions
static void	POWER_EnablePD (pd_bit_t en)
	API to enable PDRUNCFG bit in the Syscon. More...
static void	POWER_DisablePD (pd_bit_t en)
	API to disable PDRUNCFG bit in the Syscon. More...
static void	POWER_SetBodVbatLevel (power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)
	set BOD VBAT level. More...
static void	POWER_SetBodCoreLevel (power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset)
	set BOD core level. More...
static void	POWER_EnableDeepSleep (void)
	API to enable deep sleep bit in the ARM Core. More...
static void	POWER_DisableDeepSleep (void)
	API to disable deep sleep bit in the ARM Core. More...
static void	POWER_PowerDownFlash (void)
	API to power down flash controller. More...
static void	POWER_PowerUpFlash (void)
	API to power up flash controller. More...
void	POWER_EnterLowPower (LPC_LOWPOWER_T *p_lowpower_cfg)
	Configures and enters in low power mode. More...
void	POWER_CycleCpuAndFlash (void)
	Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event This MUST BE EXECUTED outside the Flash: either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is preferable to have all functions defined in this file implemented in ROM. More...
void	POWER_EnterDeepSleep (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t hardware_wake_ctrl)
	Configures and enters in DEEP-SLEEP low power mode. More...
void	POWER_EnterPowerDown (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl)
	Configures and enters in POWERDOWN low power mode. More...
void	POWER_EnterDeepPowerDown (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl)
	Configures and enters in DEEPPOWERDOWN low power mode. More...
void	POWER_EnterSleep (void)
	Configures and enters in SLEEP low power mode. More...
void	POWER_SetVoltageForFreq (uint32_t system_freq_hz)
	Power Library API to choose normal regulation and set the voltage for the desired operating frequency. More...
uint32_t	POWER_GetLibVersion (void)
	Power Library API to return the library version. More...
void	POWER_Xtal16mhzCapabankTrim (int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100)
	Sets board-specific trim values for 16MHz XTAL. More...
void	POWER_Xtal32khzCapabankTrim (int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100)
	Sets board-specific trim values for 32kHz XTAL. More...
void	POWER_SetXtal16mhzLdo (void)
	Enables and sets LDO for 16MHz XTAL. More...
void	POWER_SetXtal16mhzTrim (uint32_t amp, uint32_t gm)
	Set up 16-MHz XTAL Trimmings. More...

Driver version
#define	FSL_POWER_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))
	power driver version 1.0.0. More...

---

Data Structure Documentation

struct LPC_LOWPOWER_T

Data Fields
__IO uint32_t	CFG
	Low Power Mode Configuration, and miscallenous options.
__IO uint32_t	PDCTRL0
	Power Down control : controls power of various modules in the different Low power modes, including ROM.
__IO uint32_t	SRAMRETCTRL
	Power Down control : controls power SRAM instances in the different Low power modes.
__IO uint32_t	CPURETCTRL
	CPU0 retention control : controls CPU retention parameters in POWER DOWN modes.
__IO uint64_t	VOLTAGE
	Voltage control in Low Power Modes.
__IO uint64_t	WAKEUPSRC
	Wake up sources control for sleepcon.
__IO uint64_t	WAKEUPINT
	Wake up sources control for ARM.
__IO uint32_t	HWWAKE
	Interrupt that can postpone power down modes in case an interrupt is pending when the processor request deepsleep.
__IO uint32_t	WAKEUPIOSRC
	Wake up I/O sources in DEEP POWER DOWN mode.
__IO uint32_t	TIMERCFG
	Wake up timers configuration.
__IO uint32_t	TIMERCOUNT
	Wake up Timer count.
__IO uint32_t	POWERCYCLE
	Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some interrupt handlers)

struct lowpower_driver_interface_t

Macro Definition Documentation

#define FSL_POWER_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))

#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0   (1UL << 0)

Enable SRAMX_0 retention when entering in Low power modes

#define LOWPOWER_HWWAKE_FORCED   (1UL << 0)

Force peripheral clocking to stay on during deep-sleep mode.

#define LOWPOWER_HWWAKE_PERIPHERALS   (1UL << 1)

Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted

#define LOWPOWER_HWWAKE_SDMA0   (1UL << 3)

DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS

#define LOWPOWER_HWWAKE_SDMA1   (1UL << 5)

DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS

#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX   0

Pin P1( 1)

#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ   0

1 KHz Real Time Counter (RTC) used as wake up source

Enumeration Type Documentation

enum LPC_POWER_DOMAIN_T

Enumerator
VD_AON	Digital Always On power domain.
VD_MEM	Memories (SRAM) power domain.
VD_DCDC	Core logic power domain.
VD_DEEPSLEEP	Core logic power domain.

enum power_bod_vbat_level_t

Enumerator
kPOWER_BodVbatLevel1000mv	Brown out detector VBAT level 1V.
kPOWER_BodVbatLevel1100mv	Brown out detector VBAT level 1.1V.
kPOWER_BodVbatLevel1200mv	Brown out detector VBAT level 1.2V.
kPOWER_BodVbatLevel1300mv	Brown out detector VBAT level 1.3V.
kPOWER_BodVbatLevel1400mv	Brown out detector VBAT level 1.4V.
kPOWER_BodVbatLevel1500mv	Brown out detector VBAT level 1.5V.
kPOWER_BodVbatLevel1600mv	Brown out detector VBAT level 1.6V.
kPOWER_BodVbatLevel1650mv	Brown out detector VBAT level 1.65V.
kPOWER_BodVbatLevel1700mv	Brown out detector VBAT level 1.7V.
kPOWER_BodVbatLevel1750mv	Brown out detector VBAT level 1.75V.
kPOWER_BodVbatLevel1800mv	Brown out detector VBAT level 1.8V.
kPOWER_BodVbatLevel1900mv	Brown out detector VBAT level 1.9V.
kPOWER_BodVbatLevel2000mv	Brown out detector VBAT level 2V.
kPOWER_BodVbatLevel2100mv	Brown out detector VBAT level 2.1V.
kPOWER_BodVbatLevel2200mv	Brown out detector VBAT level 2.2V.
kPOWER_BodVbatLevel2300mv	Brown out detector VBAT level 2.3V.
kPOWER_BodVbatLevel2400mv	Brown out detector VBAT level 2.4V.
kPOWER_BodVbatLevel2500mv	Brown out detector VBAT level 2.5V.
kPOWER_BodVbatLevel2600mv	Brown out detector VBAT level 2.6V.
kPOWER_BodVbatLevel2700mv	Brown out detector VBAT level 2.7V.
kPOWER_BodVbatLevel2806mv	Brown out detector VBAT level 2.806V.
kPOWER_BodVbatLevel2900mv	Brown out detector VBAT level 2.9V.
kPOWER_BodVbatLevel3000mv	Brown out detector VBAT level 3.0V.
kPOWER_BodVbatLevel3100mv	Brown out detector VBAT level 3.1V.
kPOWER_BodVbatLevel3200mv	Brown out detector VBAT level 3.2V.
kPOWER_BodVbatLevel3300mv	Brown out detector VBAT level 3.3V.

enum power_bod_core_level_t

Enumerator
kPOWER_BodCoreLevel600mv	Brown out detector core level 600mV.
kPOWER_BodCoreLevel650mv	Brown out detector core level 650mV.
kPOWER_BodCoreLevel700mv	Brown out detector core level 700mV.
kPOWER_BodCoreLevel750mv	Brown out detector core level 750mV.
kPOWER_BodCoreLevel800mv	Brown out detector core level 800mV.
kPOWER_BodCoreLevel850mv	Brown out detector core level 850mV.
kPOWER_BodCoreLevel900mv	Brown out detector core level 900mV.
kPOWER_BodCoreLevel950mv	Brown out detector core level 950mV.

enum power_bod_hyst_t

Enumerator
kPOWER_BodHystLevel25mv	BOD Hysteresis control level 25mv.
kPOWER_BodHystLevel50mv	BOD Hysteresis control level 50mv.
kPOWER_BodHystLevel75mv	BOD Hysteresis control level 75mv.
kPOWER_BodHystLevel100mv	BOD Hysteresis control level 100mv.

enum v_ao_t

Enumerator
V_AO_0P700	0.7 V
V_AO_0P725	0.725 V
V_AO_0P750	0.75 V
V_AO_0P775	0.775 V
V_AO_0P800	0.8 V
V_AO_0P825	0.825 V
V_AO_0P850	0.85 V
V_AO_0P875	0.875 V
V_AO_0P900	0.9 V
V_AO_0P960	0.96 V
V_AO_0P970	0.97 V
V_AO_0P980	0.98 V
V_AO_0P990	0.99 V
V_AO_1P000	1 V
V_AO_1P010	1.01 V
V_AO_1P020	1.02 V
V_AO_1P030	1.03 V
V_AO_1P040	1.04 V
V_AO_1P050	1.05 V
V_AO_1P060	1.06 V
V_AO_1P070	1.07 V
V_AO_1P080	1.08 V
V_AO_1P090	1.09 V
V_AO_1P100	1.1 V
V_AO_1P110	1.11 V
V_AO_1P120	1.12 V
V_AO_1P130	1.13 V
V_AO_1P140	1.14 V
V_AO_1P150	1.15 V
V_AO_1P160	1.16 V
V_AO_1P220	1.22 V

enum v_deepsleep_t

Enumerator
V_DEEPSLEEP_0P900	0.9 V
V_DEEPSLEEP_0P925	0.925 V
V_DEEPSLEEP_0P950	0.95 V
V_DEEPSLEEP_0P975	0.975 V
V_DEEPSLEEP_1P000	1.000 V
V_DEEPSLEEP_1P025	1.025 V
V_DEEPSLEEP_1P050	1.050 V
V_DEEPSLEEP_1P075	1.075 V

enum v_dcdc_t

Enumerator
V_DCDC_0P950	0.95 V
V_DCDC_0P975	0.975 V
V_DCDC_1P000	1 V
V_DCDC_1P025	1.025 V
V_DCDC_1P050	1.050 V
V_DCDC_1P075	1.075 V
V_DCDC_1P100	1.1 V
V_DCDC_1P125	1.125 V
V_DCDC_1P150	1.150 V
V_DCDC_1P175	1.175 V
V_DCDC_1P200	1.2 V

enum v_flashnv_t

Enumerator
V_LDOFLASHNV_1P650	0.95 V
V_LDOFLASHNV_1P700	0.975 V
V_LDOFLASHNV_1P750	1 V
V_LDOFLASHNV_0P800	1.025 V
V_LDOFLASHNV_1P850	1.050 V
V_LDOFLASHNV_1P900	1.075 V
V_LDOFLASHNV_1P950	1.1 V
V_LDOFLASHNV_2P000	1.125 V

Function Documentation

static void POWER_EnablePD ( pd_bit_t  en )

inlinestatic

Note that enabling the bit powers down the peripheral

Parameters

en	peripheral for which to enable the PDRUNCFG bit

Returns

none

static void POWER_DisablePD ( pd_bit_t  en )

inlinestatic

Note that disabling the bit powers up the peripheral

Parameters

en	peripheral for which to disable the PDRUNCFG bit

Returns

none

static void POWER_SetBodVbatLevel ( power_bod_vbat_level_t  level, power_bod_hyst_t  hyst, bool  enBodVbatReset  )

inlinestatic

Parameters

level	BOD detect level
hyst	BoD Hysteresis control
enBodVbatReset	VBAT brown out detect reset

static void POWER_SetBodCoreLevel ( power_bod_core_level_t  level, power_bod_hyst_t  hyst, bool  enBodCoreReset  )

inlinestatic

Parameters

level	BOD detect level
hyst	BoD Hysteresis control
enBodCoreReset	core brown out detect reset

static void POWER_EnableDeepSleep ( void  )

inlinestatic

Parameters

none

Returns

none

static void POWER_DisableDeepSleep ( void  )

inlinestatic

Parameters

none

Returns

none

static void POWER_PowerDownFlash ( void  )

inlinestatic

Parameters

none

Returns

none

static void POWER_PowerUpFlash ( void  )

inlinestatic

Parameters

none

Returns

none

void POWER_EnterLowPower

(

LPC_LOWPOWER_T *

p_lowpower_cfg

)

Parameters

p_lowpower_cfg,:

pointer to a structure that contains all low power mode parameters

Returns

Nothing

     !!! IMPORTANT NOTES :
      1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the

API. 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk of Dead Lock). 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)

void POWER_CycleCpuAndFlash

(

void

)

Parameters

None

Returns

Nothing

void POWER_EnterDeepSleep	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	hardware_wake_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
hardware_wake_ctrl,:

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) reset)

void POWER_EnterPowerDown	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	cpu_retention_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
cpu_retention_ctrl,:	0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are RESERVED.

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl") 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) reset)

void POWER_EnterDeepPowerDown	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	wakeup_io_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
wakeup_io_ctrl,:

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)

void POWER_EnterSleep

(

void

)

Parameters

:

Returns

Nothing

void POWER_SetVoltageForFreq

(

uint32_t

system_freq_hz

)

Parameters

system_freq_hz

- The desired frequency (in Hertz) at which the part would like to operate, note that the voltage and flash wait states should be set before changing frequency

Returns

none

uint32_t POWER_GetLibVersion

(

void

)

Parameters

none

Returns

version number of the power library

void POWER_Xtal16mhzCapabankTrim	(	int32_t	pi32_16MfXtalIecLoadpF_x100,
		int32_t	pi32_16MfXtalPPcbParCappF_x100,
		int32_t	pi32_16MfXtalNPcbParCappF_x100
	)

Parameters

pi32_32MfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32MfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32MfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns

none

Note

Following default Values can be used: pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void POWER_Xtal32khzCapabankTrim	(	int32_t	pi32_32kfXtalIecLoadpF_x100,
		int32_t	pi32_32kfXtalPPcbParCappF_x100,
		int32_t	pi32_32kfXtalNPcbParCappF_x100
	)

Parameters

pi32_32kfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns

none

Note

Following default Values can be used: pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void POWER_SetXtal16mhzLdo

(

void

)

Parameters

none

Returns

none

void POWER_SetXtal16mhzTrim	(	uint32_t	amp,
		uint32_t	gm
	)

Parameters

amp	Amplitude
gm	Transconductance

Returns

none