MCUXpresso SDK API Reference Manual  Rev. 0
NXP Semiconductors
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Clock

Overview

Files

file  fsl_clock.h
 

Data Structures

struct  clock_arm_pll_config_t
 PLL configuration for ARM. More...
 
struct  clock_usb_pll_config_t
 PLL configuration for USB. More...
 
struct  clock_sys_pll_config_t
 PLL configuration for System. More...
 
struct  clock_audio_pll_config_t
 PLL configuration for AUDIO and VIDEO. More...
 
struct  clock_video_pll_config_t
 PLL configuration for AUDIO and VIDEO. More...
 
struct  clock_enet_pll_config_t
 PLL configuration for ENET. More...
 

Macros

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
 Configure whether driver controls clock. More...
 
#define CCSR_OFFSET   0x0C
 CCM registers offset.
 
#define PLL_ARM_OFFSET   0x00
 CCM Analog registers offset.
 
#define CCM_ANALOG_TUPLE(reg, shift)   (((reg & 0xFFFU) << 16U) | (shift))
 CCM ANALOG tuple macros to map corresponding registers and bit fields.
 
#define CLKPN_FREQ   0U
 clock1PN frequency.
 
#define ADC_CLOCKS
 Clock ip name array for ADC. More...
 
#define AOI_CLOCKS
 Clock ip name array for AOI. More...
 
#define BEE_CLOCKS
 Clock ip name array for BEE. More...
 
#define CMP_CLOCKS
 Clock ip name array for CMP. More...
 
#define CSI_CLOCKS
 Clock ip name array for CSI. More...
 
#define DCDC_CLOCKS
 Clock ip name array for DCDC. More...
 
#define DCP_CLOCKS
 Clock ip name array for DCP. More...
 
#define DMAMUX_CLOCKS
 Clock ip name array for DMAMUX_CLOCKS. More...
 
#define EDMA_CLOCKS
 Clock ip name array for DMA. More...
 
#define ENC_CLOCKS
 Clock ip name array for ENC. More...
 
#define ENET_CLOCKS
 Clock ip name array for ENET. More...
 
#define EWM_CLOCKS
 Clock ip name array for EWM. More...
 
#define FLEXCAN_CLOCKS
 Clock ip name array for FLEXCAN. More...
 
#define FLEXCAN_PERIPH_CLOCKS
 Clock ip name array for FLEXCAN Peripheral clock. More...
 
#define FLEXIO_CLOCKS
 Clock ip name array for FLEXIO. More...
 
#define FLEXRAM_CLOCKS
 Clock ip name array for FLEXRAM. More...
 
#define FLEXSPI_CLOCKS
 Clock ip name array for FLEXSPI. More...
 
#define FLEXSPI_EXSC_CLOCKS
 Clock ip name array for FLEXSPI EXSC. More...
 
#define GPIO_CLOCKS
 Clock ip name array for GPIO. More...
 
#define GPT_CLOCKS
 Clock ip name array for GPT. More...
 
#define KPP_CLOCKS
 Clock ip name array for KPP. More...
 
#define LCDIF_CLOCKS
 Clock ip name array for LCDIF. More...
 
#define LCDIF_PERIPH_CLOCKS
 Clock ip name array for LCDIF PIXEL. More...
 
#define LPI2C_CLOCKS
 Clock ip name array for LPI2C. More...
 
#define LPSPI_CLOCKS
 Clock ip name array for LPSPI. More...
 
#define LPUART_CLOCKS
 Clock ip name array for LPUART. More...
 
#define MQS_CLOCKS
 Clock ip name array for MQS. More...
 
#define OCRAM_EXSC_CLOCKS
 Clock ip name array for OCRAM EXSC. More...
 
#define PIT_CLOCKS
 Clock ip name array for PIT. More...
 
#define PWM_CLOCKS
 Clock ip name array for PWM. More...
 
#define PXP_CLOCKS
 Clock ip name array for PXP. More...
 
#define RTWDOG_CLOCKS
 Clock ip name array for RTWDOG. More...
 
#define SAI_CLOCKS
 Clock ip name array for SAI. More...
 
#define SEMC_CLOCKS
 Clock ip name array for SEMC. More...
 
#define SEMC_EXSC_CLOCKS
 Clock ip name array for SEMC EXSC. More...
 
#define TMR_CLOCKS
 Clock ip name array for QTIMER. More...
 
#define TRNG_CLOCKS
 Clock ip name array for TRNG. More...
 
#define TSC_CLOCKS
 Clock ip name array for TSC. More...
 
#define WDOG_CLOCKS
 Clock ip name array for WDOG. More...
 
#define USDHC_CLOCKS
 Clock ip name array for USDHC. More...
 
#define SPDIF_CLOCKS
 Clock ip name array for SPDIF. More...
 
#define XBARA_CLOCKS
 Clock ip name array for XBARA. More...
 
#define XBARB_CLOCKS
 Clock ip name array for XBARB. More...
 
#define kCLOCK_CoreSysClk   kCLOCK_CpuClk
 For compatible with other platforms without CCM. More...
 
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
 For compatible with other platforms without CCM. More...
 

Enumerations

enum  clock_name_t {
  kCLOCK_CpuClk = 0x0U,
  kCLOCK_AhbClk = 0x1U,
  kCLOCK_SemcClk = 0x2U,
  kCLOCK_IpgClk = 0x3U,
  kCLOCK_PerClk = 0x4U,
  kCLOCK_OscClk = 0x5U,
  kCLOCK_RtcClk = 0x6U,
  kCLOCK_ArmPllClk = 0x7U,
  kCLOCK_Usb1PllClk = 0x8U,
  kCLOCK_Usb1PllPfd0Clk = 0x9U,
  kCLOCK_Usb1PllPfd1Clk = 0xAU,
  kCLOCK_Usb1PllPfd2Clk = 0xBU,
  kCLOCK_Usb1PllPfd3Clk = 0xCU,
  kCLOCK_Usb2PllClk = 0xDU,
  kCLOCK_SysPllClk = 0xEU,
  kCLOCK_SysPllPfd0Clk = 0xFU,
  kCLOCK_SysPllPfd1Clk = 0x10U,
  kCLOCK_SysPllPfd2Clk = 0x11U,
  kCLOCK_SysPllPfd3Clk = 0x12U,
  kCLOCK_EnetPll0Clk = 0x13U,
  kCLOCK_EnetPll1Clk = 0x14U,
  kCLOCK_EnetPll2Clk = 0x15U,
  kCLOCK_AudioPllClk = 0x16U,
  kCLOCK_VideoPllClk = 0x17U
}
 Clock name used to get clock frequency. More...
 
enum  clock_ip_name_t { ,
  kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,
  kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,
  kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,
  kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT,
  kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,
  kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,
  kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,
  kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT,
  kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT,
  kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT,
  kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT,
  kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT,
  kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT,
  kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT,
  kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT,
  kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT,
  kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,
  kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,
  kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,
  kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT,
  kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT,
  kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT,
  kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,
  kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT,
  kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,
  kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT,
  kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT,
  kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT,
  kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT,
  kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT,
  kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT,
  kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT,
  kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,
  kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT,
  kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,
  kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,
  kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,
  kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT,
  kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,
  kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT,
  kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT,
  kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT,
  kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT,
  kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT,
  kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT,
  kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT,
  kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT,
  kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT,
  kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT,
  kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT,
  kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,
  kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT,
  kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,
  kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT,
  kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,
  kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,
  kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,
  kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,
  kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT,
  kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT,
  kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT,
  kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT,
  kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT,
  kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT,
  kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,
  kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT,
  kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,
  kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,
  kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT,
  kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,
  kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,
  kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,
  kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT,
  kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT,
  kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT,
  kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT,
  kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT,
  kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT,
  kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT,
  kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,
  kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,
  kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,
  kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,
  kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,
  kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,
  kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT,
  kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,
  kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT,
  kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,
  kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT,
  kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT,
  kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT,
  kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT,
  kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT,
  kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT,
  kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,
  kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT,
  kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT,
  kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,
  kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT,
  kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,
  kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,
  kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,
  kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT,
  kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT,
  kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT,
  kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT,
  kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT,
  kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT,
  kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT,
  kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT,
  kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT,
  kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT,
  kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT,
  kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT,
  kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT,
  kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT,
  kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT
}
 CCM CCGR gate control for each module independently. More...
 
enum  clock_osc_t {
  kCLOCK_RcOsc = 0U,
  kCLOCK_XtalOsc = 1U
}
 OSC 24M sorce select. More...
 
enum  clock_gate_value_t {
  kCLOCK_ClockNotNeeded = 0U,
  kCLOCK_ClockNeededRun = 1U,
  kCLOCK_ClockNeededRunWait = 3U
}
 Clock gate value. More...
 
enum  clock_mode_t {
  kCLOCK_ModeRun = 0U,
  kCLOCK_ModeWait = 1U,
  kCLOCK_ModeStop = 2U
}
 System clock mode. More...
 
enum  clock_mux_t {
  kCLOCK_Pll3SwMux,
  kCLOCK_PeriphMux,
  kCLOCK_SemcAltMux,
  kCLOCK_SemcMux,
  kCLOCK_PrePeriphMux,
  kCLOCK_TraceMux,
  kCLOCK_PeriphClk2Mux,
  kCLOCK_Flexspi2Mux,
  kCLOCK_LpspiMux,
  kCLOCK_FlexspiMux,
  kCLOCK_Usdhc2Mux,
  kCLOCK_Usdhc1Mux,
  kCLOCK_Sai3Mux,
  kCLOCK_Sai2Mux,
  kCLOCK_Sai1Mux,
  kCLOCK_PerclkMux,
  kCLOCK_Flexio2Mux,
  kCLOCK_CanMux,
  kCLOCK_UartMux,
  kCLOCK_SpdifMux,
  kCLOCK_Flexio1Mux,
  kCLOCK_Lpi2cMux,
  kCLOCK_LcdifPreMux,
  kCLOCK_CsiMux
}
 MUX control names for clock mux setting. More...
 
enum  clock_div_t {
  kCLOCK_ArmDiv,
  kCLOCK_PeriphClk2Div,
  kCLOCK_SemcDiv,
  kCLOCK_AhbDiv,
  kCLOCK_IpgDiv,
  kCLOCK_Flexspi2Div,
  kCLOCK_LpspiDiv,
  kCLOCK_LcdifDiv,
  kCLOCK_FlexspiDiv,
  kCLOCK_PerclkDiv,
  kCLOCK_CanDiv,
  kCLOCK_TraceDiv,
  kCLOCK_Usdhc2Div,
  kCLOCK_Usdhc1Div,
  kCLOCK_UartDiv,
  kCLOCK_Flexio2Div,
  kCLOCK_Sai3PreDiv,
  kCLOCK_Sai3Div,
  kCLOCK_Flexio2PreDiv,
  kCLOCK_Sai1PreDiv,
  kCLOCK_Sai1Div,
  kCLOCK_Sai2PreDiv,
  kCLOCK_Sai2Div,
  kCLOCK_Spdif0PreDiv,
  kCLOCK_Spdif0Div,
  kCLOCK_Flexio1PreDiv,
  kCLOCK_Flexio1Div,
  kCLOCK_Lpi2cDiv,
  kCLOCK_LcdifPreDiv,
  kCLOCK_CsiDiv
}
 DIV control names for clock div setting. More...
 
enum  clock_usb_src_t {
  kCLOCK_Usb480M = 0,
  kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU
}
 USB clock source definition. More...
 
enum  clock_usb_phy_src_t { kCLOCK_Usbphy480M = 0 }
 Source of the USB HS PHY. More...
 
enum  _clock_pll_clk_src {
  kCLOCK_PllClkSrc24M = 0U,
  kCLOCK_PllSrcClkPN = 1U
}
 PLL clock source, bypass cloco source also. More...
 
enum  clock_pll_t {
  kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT),
  kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),
  kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),
  kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT),
  kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT),
  kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT),
  kCLOCK_PllEnet2 = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT),
  kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT),
  kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)
}
 PLL name. More...
 
enum  clock_pfd_t {
  kCLOCK_Pfd0 = 0U,
  kCLOCK_Pfd1 = 1U,
  kCLOCK_Pfd2 = 2U,
  kCLOCK_Pfd3 = 3U
}
 PLL PFD name. More...
 

Functions

static void CLOCK_SetMux (clock_mux_t mux, uint32_t value)
 Set CCM MUX node to certain value. More...
 
static uint32_t CLOCK_GetMux (clock_mux_t mux)
 Get CCM MUX value. More...
 
static void CLOCK_SetDiv (clock_div_t divider, uint32_t value)
 Set CCM DIV node to certain value. More...
 
static uint32_t CLOCK_GetDiv (clock_div_t divider)
 Get CCM DIV node value. More...
 
static void CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
 Control the clock gate for specific IP. More...
 
static void CLOCK_EnableClock (clock_ip_name_t name)
 Enable the clock for specific IP. More...
 
static void CLOCK_DisableClock (clock_ip_name_t name)
 Disable the clock for specific IP. More...
 
static void CLOCK_SetMode (clock_mode_t mode)
 Setting the low power mode that system will enter on next assertion of dsm_request signal. More...
 
static uint32_t CLOCK_GetOscFreq (void)
 Gets the OSC clock frequency. More...
 
uint32_t CLOCK_GetAhbFreq (void)
 Gets the AHB clock frequency. More...
 
uint32_t CLOCK_GetSemcFreq (void)
 Gets the SEMC clock frequency. More...
 
uint32_t CLOCK_GetIpgFreq (void)
 Gets the IPG clock frequency. More...
 
uint32_t CLOCK_GetPerClkFreq (void)
 Gets the PER clock frequency. More...
 
uint32_t CLOCK_GetFreq (clock_name_t name)
 Gets the clock frequency for a specific clock name. More...
 
static uint32_t CLOCK_GetCpuClkFreq (void)
 Get the CCM CPU/core/system frequency. More...
 
bool CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock. More...
 
bool CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock. More...
 

Variables

volatile uint32_t g_xtalFreq
 External XTAL (24M OSC/SYSOSC) clock frequency. More...
 
volatile uint32_t g_rtcXtalFreq
 External RTC XTAL (32K OSC) clock frequency. More...
 

Driver version

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 1, 7))
 CLOCK driver version 2.1.7. More...
 
#define CCM_ANALOG_PLL_BYPASS_SHIFT   (16U)
 
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK   (0xC000U)
 
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT   (14U)
 

OSC operations

void CLOCK_InitExternalClk (bool bypassXtalOsc)
 Initialize the external 24MHz clock. More...
 
void CLOCK_DeinitExternalClk (void)
 Deinitialize the external 24MHz clock. More...
 
void CLOCK_SwitchOsc (clock_osc_t osc)
 Switch the OSC. More...
 
static uint32_t CLOCK_GetRtcFreq (void)
 Gets the RTC clock frequency. More...
 
static void CLOCK_SetXtalFreq (uint32_t freq)
 Set the XTAL (24M OSC) frequency based on board setting. More...
 
static void CLOCK_SetRtcXtalFreq (uint32_t freq)
 Set the RTC XTAL (32K OSC) frequency based on board setting. More...
 
void CLOCK_InitRcOsc24M (void)
 Initialize the RC oscillator 24MHz clock.
 
void CLOCK_DeinitRcOsc24M (void)
 Power down the RCOSC 24M clock.
 

PLL/PFD operations

void CLOCK_DisableUsbhs1PhyPllClock (void)
 Disable USB HS PHY PLL clock. More...
 
static void CLOCK_SetPllBypass (CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
 PLL bypass setting. More...
 
static bool CLOCK_IsPllBypassed (CCM_ANALOG_Type *base, clock_pll_t pll)
 Check if PLL is bypassed. More...
 
static bool CLOCK_IsPllEnabled (CCM_ANALOG_Type *base, clock_pll_t pll)
 Check if PLL is enabled. More...
 
static void CLOCK_SetPllBypassRefClkSrc (CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
 PLL bypass clock source setting. More...
 
static uint32_t CLOCK_GetPllBypassRefClk (CCM_ANALOG_Type *base, clock_pll_t pll)
 Get PLL bypass clock value, it is PLL reference clock actually. More...
 
void CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
 Initialize the ARM PLL. More...
 
void CLOCK_DeinitArmPll (void)
 De-initialize the ARM PLL.
 
void CLOCK_InitSysPll (const clock_sys_pll_config_t *config)
 Initialize the System PLL. More...
 
void CLOCK_DeinitSysPll (void)
 De-initialize the System PLL.
 
void CLOCK_InitUsb1Pll (const clock_usb_pll_config_t *config)
 Initialize the USB1 PLL. More...
 
void CLOCK_DeinitUsb1Pll (void)
 Deinitialize the USB1 PLL.
 
void CLOCK_InitUsb2Pll (const clock_usb_pll_config_t *config)
 Initialize the USB2 PLL. More...
 
void CLOCK_DeinitUsb2Pll (void)
 Deinitialize the USB2 PLL.
 
void CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
 Initializes the Audio PLL. More...
 
void CLOCK_DeinitAudioPll (void)
 De-initialize the Audio PLL.
 
void CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
 Initialize the video PLL. More...
 
void CLOCK_DeinitVideoPll (void)
 De-initialize the Video PLL.
 
void CLOCK_InitEnetPll (const clock_enet_pll_config_t *config)
 Initialize the ENET PLL. More...
 
void CLOCK_DeinitEnetPll (void)
 Deinitialize the ENET PLL. More...
 
uint32_t CLOCK_GetPllFreq (clock_pll_t pll)
 Get current PLL output frequency. More...
 
void CLOCK_InitSysPfd (clock_pfd_t pfd, uint8_t pfdFrac)
 Initialize the System PLL PFD. More...
 
void CLOCK_DeinitSysPfd (clock_pfd_t pfd)
 De-initialize the System PLL PFD. More...
 
void CLOCK_InitUsb1Pfd (clock_pfd_t pfd, uint8_t pfdFrac)
 Initialize the USB1 PLL PFD. More...
 
void CLOCK_DeinitUsb1Pfd (clock_pfd_t pfd)
 De-initialize the USB1 PLL PFD. More...
 
uint32_t CLOCK_GetSysPfdFreq (clock_pfd_t pfd)
 Get current System PLL PFD output frequency. More...
 
uint32_t CLOCK_GetUsb1PfdFreq (clock_pfd_t pfd)
 Get current USB1 PLL PFD output frequency. More...
 
bool CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock. More...
 
void CLOCK_DisableUsbhs0PhyPllClock (void)
 Disable USB HS PHY PLL clock. More...
 
bool CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock. More...
 

Data Structure Documentation

struct clock_arm_pll_config_t

Data Fields

uint32_t loopDivider
 PLL loop divider. More...
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 

Field Documentation

uint32_t clock_arm_pll_config_t::loopDivider

Valid range for divider value: 54-108. Fout=Fin*loopDivider/2.

struct clock_usb_pll_config_t

Data Fields

uint8_t loopDivider
 PLL loop divider. More...
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 

Field Documentation

uint8_t clock_usb_pll_config_t::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct clock_sys_pll_config_t

Data Fields

uint8_t loopDivider
 PLL loop divider. More...
 
uint32_t numerator
 30 bit numerator of fractional loop divider. More...
 
uint32_t denominator
 30 bit denominator of fractional loop divider
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 
uint16_t ss_stop
 Stop value to get frequency change. More...
 
uint8_t ss_enable
 Enable spread spectrum modulation.
 
uint16_t ss_step
 Step value to get frequency change step. More...
 

Field Documentation

uint8_t clock_sys_pll_config_t::loopDivider

Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22

uint32_t clock_sys_pll_config_t::numerator
uint16_t clock_sys_pll_config_t::ss_stop
uint16_t clock_sys_pll_config_t::ss_step
struct clock_audio_pll_config_t

Data Fields

uint8_t loopDivider
 PLL loop divider. More...
 
uint8_t postDivider
 Divider after the PLL, should only be 1, 2, 4, 8, 16. More...
 
uint32_t numerator
 30 bit numerator of fractional loop divider. More...
 
uint32_t denominator
 30 bit denominator of fractional loop divider
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 

Field Documentation

uint8_t clock_audio_pll_config_t::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t clock_audio_pll_config_t::postDivider
uint32_t clock_audio_pll_config_t::numerator
struct clock_video_pll_config_t

Data Fields

uint8_t loopDivider
 PLL loop divider. More...
 
uint8_t postDivider
 Divider after the PLL, should only be 1, 2, 4, 8, 16. More...
 
uint32_t numerator
 30 bit numerator of fractional loop divider. More...
 
uint32_t denominator
 30 bit denominator of fractional loop divider
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 

Field Documentation

uint8_t clock_video_pll_config_t::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t clock_video_pll_config_t::postDivider
uint32_t clock_video_pll_config_t::numerator
struct clock_enet_pll_config_t

Data Fields

bool enableClkOutput
 Power on and enable PLL clock output for ENET0 (ref_enetpll0). More...
 
bool enableClkOutput25M
 Power on and enable PLL clock output for ENET2 (ref_enetpll2). More...
 
uint8_t loopDivider
 Controls the frequency of the ENET0 reference clock. More...
 
uint8_t src
 Pll clock source, reference _clock_pll_clk_src.
 
bool enableClkOutput1
 Power on and enable PLL clock output for ENET1 (ref_enetpll1). More...
 
uint8_t loopDivider1
 Controls the frequency of the ENET1 reference clock. More...
 

Field Documentation

bool clock_enet_pll_config_t::enableClkOutput
bool clock_enet_pll_config_t::enableClkOutput25M
uint8_t clock_enet_pll_config_t::loopDivider

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

bool clock_enet_pll_config_t::enableClkOutput1
uint8_t clock_enet_pll_config_t::loopDivider1

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note
All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 1, 7))
#define ADC_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
}
CCGR1, CG8.
Definition: fsl_clock.h:464
CCGR1, CG4.
Definition: fsl_clock.h:460
#define AOI_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
}
CCGR1, CG7.
Definition: fsl_clock.h:463
CCGR3, CG4.
Definition: fsl_clock.h:496
#define BEE_CLOCKS
Value:
{ \
}
CCGR4, CG3.
Definition: fsl_clock.h:512
#define CMP_CLOCKS
Value:
{ \
}
CCGR3, CG10.
Definition: fsl_clock.h:502
CCGR3, CG13.
Definition: fsl_clock.h:505
CCGR3, CG12.
Definition: fsl_clock.h:504
CCGR3, CG11.
Definition: fsl_clock.h:503
#define CSI_CLOCKS
Value:
{ \
}
CCGR2, CG1.
Definition: fsl_clock.h:475
#define DCDC_CLOCKS
Value:
{ \
}
CCGR6, CG3.
Definition: fsl_clock.h:548
#define DCP_CLOCKS
Value:
{ \
}
CCGR0, CG5.
Definition: fsl_clock.h:443
#define DMAMUX_CLOCKS
Value:
{ \
}
CCGR5, CG3.
Definition: fsl_clock.h:530
#define EDMA_CLOCKS
Value:
{ \
}
CCGR5, CG3.
Definition: fsl_clock.h:530
#define ENC_CLOCKS
Value:
{ \
}
CCGR4, CG15.
Definition: fsl_clock.h:524
CCGR4, CG13.
Definition: fsl_clock.h:522
CCGR4, CG12.
Definition: fsl_clock.h:521
CCGR4, CG14.
Definition: fsl_clock.h:523
#define ENET_CLOCKS
Value:
{ \
kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \
}
CCGR7, CG0.
Definition: fsl_clock.h:563
CCGR1, CG5.
Definition: fsl_clock.h:461
#define EWM_CLOCKS
Value:
{ \
}
CCGR3, CG7.
Definition: fsl_clock.h:499
#define FLEXCAN_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
}
CCGR0, CG7.
Definition: fsl_clock.h:445
CCGR0, CG9.
Definition: fsl_clock.h:447
CCGR7, CG3.
Definition: fsl_clock.h:566
#define FLEXCAN_PERIPH_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
}
CCGR0, CG8.
Definition: fsl_clock.h:446
CCGR0, CG10.
Definition: fsl_clock.h:448
CCGR7, CG4.
Definition: fsl_clock.h:567
#define FLEXIO_CLOCKS
Value:
{ \
}
CCGR3, CG0.
Definition: fsl_clock.h:492
CCGR5, CG1.
Definition: fsl_clock.h:528
CCGR7, CG6.
Definition: fsl_clock.h:569
#define FLEXRAM_CLOCKS
Value:
{ \
}
CCGR3, CG9.
Definition: fsl_clock.h:501
#define FLEXSPI_CLOCKS
Value:
{ \
kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
}
CCGR6, CG5.
Definition: fsl_clock.h:550
CCGR7, CG1.
Definition: fsl_clock.h:564
#define FLEXSPI_EXSC_CLOCKS
Value:
{ \
}
CCGR0, CG3.
Definition: fsl_clock.h:441
#define GPIO_CLOCKS
Value:
{ \
}
CCGR1, CG15.
Definition: fsl_clock.h:471
CCGR2, CG13.
Definition: fsl_clock.h:487
CCGR0, CG15.
Definition: fsl_clock.h:453
CCGR3, CG6.
Definition: fsl_clock.h:498
CCGR1, CG13.
Definition: fsl_clock.h:469
#define GPT_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
}
CCGR0, CG12.
Definition: fsl_clock.h:450
CCGR1, CG10.
Definition: fsl_clock.h:466
#define KPP_CLOCKS
Value:
{ \
}
CCGR5, CG4.
Definition: fsl_clock.h:531
#define LCDIF_CLOCKS
Value:
{ \
}
CCGR2, CG14.
Definition: fsl_clock.h:488
#define LCDIF_PERIPH_CLOCKS
Value:
{ \
}
CCGR3, CG5.
Definition: fsl_clock.h:497
#define LPI2C_CLOCKS
Value:
{ \
}
CCGR2, CG3.
Definition: fsl_clock.h:477
CCGR2, CG4.
Definition: fsl_clock.h:478
CCGR6, CG12.
Definition: fsl_clock.h:557
CCGR2, CG5.
Definition: fsl_clock.h:479
#define LPSPI_CLOCKS
Value:
{ \
}
CCGR1, CG0.
Definition: fsl_clock.h:456
CCGR1, CG1.
Definition: fsl_clock.h:457
CCGR1, CG3.
Definition: fsl_clock.h:459
CCGR1, CG2.
Definition: fsl_clock.h:458
#define LPUART_CLOCKS
Value:
{ \
}
CCGR0, CG14.
Definition: fsl_clock.h:452
CCGR6, CG7.
Definition: fsl_clock.h:552
CCGR3, CG3.
Definition: fsl_clock.h:495
CCGR1, CG12.
Definition: fsl_clock.h:468
CCGR0, CG6.
Definition: fsl_clock.h:444
CCGR3, CG1.
Definition: fsl_clock.h:493
CCGR5, CG12.
Definition: fsl_clock.h:539
CCGR5, CG13.
Definition: fsl_clock.h:540
#define MQS_CLOCKS
Value:
{ \
}
CCGR0, CG2.
Definition: fsl_clock.h:440
#define OCRAM_EXSC_CLOCKS
Value:
{ \
}
CCGR2, CG0.
Definition: fsl_clock.h:474
#define PIT_CLOCKS
Value:
{ \
}
CCGR1, CG6.
Definition: fsl_clock.h:462
#define PWM_CLOCKS
Value:
{ \
{ \
kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \
} \
, {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
{kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
{ \
} \
}
CCGR4, CG10.
Definition: fsl_clock.h:519
CCGR4, CG9.
Definition: fsl_clock.h:518
CCGR4, CG8.
Definition: fsl_clock.h:517
CCGR4, CG11.
Definition: fsl_clock.h:520
#define PXP_CLOCKS
Value:
{ \
}
CCGR2, CG15.
Definition: fsl_clock.h:489
#define RTWDOG_CLOCKS
Value:
{ \
}
CCGR5, CG2.
Definition: fsl_clock.h:529
#define SAI_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
}
CCGR5, CG10.
Definition: fsl_clock.h:537
CCGR5, CG9.
Definition: fsl_clock.h:536
CCGR5, CG11.
Definition: fsl_clock.h:538
#define SEMC_CLOCKS
Value:
{ \
}
CCGR3, CG2.
Definition: fsl_clock.h:494
#define SEMC_EXSC_CLOCKS
Value:
{ \
}
CCGR1, CG9.
Definition: fsl_clock.h:465
#define TMR_CLOCKS
Value:
{ \
}
CCGR6, CG15.
Definition: fsl_clock.h:560
CCGR6, CG8.
Definition: fsl_clock.h:553
CCGR6, CG13.
Definition: fsl_clock.h:558
CCGR6, CG14.
Definition: fsl_clock.h:559
#define TRNG_CLOCKS
Value:
{ \
}
CCGR6, CG6.
Definition: fsl_clock.h:551
#define TSC_CLOCKS
Value:
{ \
}
CCGR4, CG5.
Definition: fsl_clock.h:514
#define WDOG_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
}
CCGR5, CG5.
Definition: fsl_clock.h:532
CCGR3, CG8.
Definition: fsl_clock.h:500
#define USDHC_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
}
CCGR6, CG2.
Definition: fsl_clock.h:547
CCGR6, CG1.
Definition: fsl_clock.h:546
#define SPDIF_CLOCKS
Value:
{ \
}
CCGR5, CG7.
Definition: fsl_clock.h:534
#define XBARA_CLOCKS
Value:
{ \
}
CCGR2, CG11.
Definition: fsl_clock.h:485
#define XBARB_CLOCKS
Value:
{ \
kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
}
CCGR2, CG12.
Definition: fsl_clock.h:486
CCGR2, CG7.
Definition: fsl_clock.h:481
#define kCLOCK_CoreSysClk   kCLOCK_CpuClk
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq

Enumeration Type Documentation

Enumerator
kCLOCK_CpuClk 

CPU clock.

kCLOCK_AhbClk 

AHB clock.

kCLOCK_SemcClk 

SEMC clock.

kCLOCK_IpgClk 

IPG clock.

kCLOCK_PerClk 

PER clock.

kCLOCK_OscClk 

OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL].

kCLOCK_RtcClk 

RTC clock.

(RTCCLK)

kCLOCK_ArmPllClk 

ARMPLLCLK.

kCLOCK_Usb1PllClk 

USB1PLLCLK.

kCLOCK_Usb1PllPfd0Clk 

USB1PLLPDF0CLK.

kCLOCK_Usb1PllPfd1Clk 

USB1PLLPFD1CLK.

kCLOCK_Usb1PllPfd2Clk 

USB1PLLPFD2CLK.

kCLOCK_Usb1PllPfd3Clk 

USB1PLLPFD3CLK.

kCLOCK_Usb2PllClk 

USB2PLLCLK.

kCLOCK_SysPllClk 

SYSPLLCLK.

kCLOCK_SysPllPfd0Clk 

SYSPLLPDF0CLK.

kCLOCK_SysPllPfd1Clk 

SYSPLLPFD1CLK.

kCLOCK_SysPllPfd2Clk 

SYSPLLPFD2CLK.

kCLOCK_SysPllPfd3Clk 

SYSPLLPFD3CLK.

kCLOCK_EnetPll0Clk 

Enet PLLCLK ref_enetpll0.

kCLOCK_EnetPll1Clk 

Enet PLLCLK ref_enetpll1.

kCLOCK_EnetPll2Clk 

Enet PLLCLK ref_enetpll2.

kCLOCK_AudioPllClk 

Audio PLLCLK.

kCLOCK_VideoPllClk 

Video PLLCLK.

Enumerator
kCLOCK_Aips_tz1 

CCGR0, CG0.

kCLOCK_Aips_tz2 

CCGR0, CG1.

kCLOCK_Mqs 

CCGR0, CG2.

kCLOCK_FlexSpiExsc 

CCGR0, CG3.

kCLOCK_Sim_M_Main 

CCGR0, CG4.

kCLOCK_Dcp 

CCGR0, CG5.

kCLOCK_Lpuart3 

CCGR0, CG6.

kCLOCK_Can1 

CCGR0, CG7.

kCLOCK_Can1S 

CCGR0, CG8.

kCLOCK_Can2 

CCGR0, CG9.

kCLOCK_Can2S 

CCGR0, CG10.

kCLOCK_Trace 

CCGR0, CG11.

kCLOCK_Gpt2 

CCGR0, CG12.

kCLOCK_Gpt2S 

CCGR0, CG13.

kCLOCK_Lpuart2 

CCGR0, CG14.

kCLOCK_Gpio2 

CCGR0, CG15.

kCLOCK_Lpspi1 

CCGR1, CG0.

kCLOCK_Lpspi2 

CCGR1, CG1.

kCLOCK_Lpspi3 

CCGR1, CG2.

kCLOCK_Lpspi4 

CCGR1, CG3.

kCLOCK_Adc2 

CCGR1, CG4.

kCLOCK_Enet 

CCGR1, CG5.

kCLOCK_Pit 

CCGR1, CG6.

kCLOCK_Aoi2 

CCGR1, CG7.

kCLOCK_Adc1 

CCGR1, CG8.

kCLOCK_SemcExsc 

CCGR1, CG9.

kCLOCK_Gpt1 

CCGR1, CG10.

kCLOCK_Gpt1S 

CCGR1, CG11.

kCLOCK_Lpuart4 

CCGR1, CG12.

kCLOCK_Gpio1 

CCGR1, CG13.

kCLOCK_Csu 

CCGR1, CG14.

kCLOCK_Gpio5 

CCGR1, CG15.

kCLOCK_OcramExsc 

CCGR2, CG0.

kCLOCK_Csi 

CCGR2, CG1.

kCLOCK_IomuxcSnvs 

CCGR2, CG2.

kCLOCK_Lpi2c1 

CCGR2, CG3.

kCLOCK_Lpi2c2 

CCGR2, CG4.

kCLOCK_Lpi2c3 

CCGR2, CG5.

kCLOCK_Ocotp 

CCGR2, CG6.

kCLOCK_Xbar3 

CCGR2, CG7.

kCLOCK_Ipmux1 

CCGR2, CG8.

kCLOCK_Ipmux2 

CCGR2, CG9.

kCLOCK_Ipmux3 

CCGR2, CG10.

kCLOCK_Xbar1 

CCGR2, CG11.

kCLOCK_Xbar2 

CCGR2, CG12.

kCLOCK_Gpio3 

CCGR2, CG13.

kCLOCK_Lcd 

CCGR2, CG14.

kCLOCK_Pxp 

CCGR2, CG15.

kCLOCK_Flexio2 

CCGR3, CG0.

kCLOCK_Lpuart5 

CCGR3, CG1.

kCLOCK_Semc 

CCGR3, CG2.

kCLOCK_Lpuart6 

CCGR3, CG3.

kCLOCK_Aoi1 

CCGR3, CG4.

kCLOCK_LcdPixel 

CCGR3, CG5.

kCLOCK_Gpio4 

CCGR3, CG6.

kCLOCK_Ewm0 

CCGR3, CG7.

kCLOCK_Wdog1 

CCGR3, CG8.

kCLOCK_FlexRam 

CCGR3, CG9.

kCLOCK_Acmp1 

CCGR3, CG10.

kCLOCK_Acmp2 

CCGR3, CG11.

kCLOCK_Acmp3 

CCGR3, CG12.

kCLOCK_Acmp4 

CCGR3, CG13.

kCLOCK_Ocram 

CCGR3, CG14.

kCLOCK_IomuxcSnvsGpr 

CCGR3, CG15.

kCLOCK_Iomuxc 

CCGR4, CG1.

kCLOCK_IomuxcGpr 

CCGR4, CG2.

kCLOCK_Bee 

CCGR4, CG3.

kCLOCK_SimM7 

CCGR4, CG4.

kCLOCK_Tsc 

CCGR4, CG5.

kCLOCK_SimM 

CCGR4, CG6.

kCLOCK_SimEms 

CCGR4, CG7.

kCLOCK_Pwm1 

CCGR4, CG8.

kCLOCK_Pwm2 

CCGR4, CG9.

kCLOCK_Pwm3 

CCGR4, CG10.

kCLOCK_Pwm4 

CCGR4, CG11.

kCLOCK_Enc1 

CCGR4, CG12.

kCLOCK_Enc2 

CCGR4, CG13.

kCLOCK_Enc3 

CCGR4, CG14.

kCLOCK_Enc4 

CCGR4, CG15.

kCLOCK_Rom 

CCGR5, CG0.

kCLOCK_Flexio1 

CCGR5, CG1.

kCLOCK_Wdog3 

CCGR5, CG2.

kCLOCK_Dma 

CCGR5, CG3.

kCLOCK_Kpp 

CCGR5, CG4.

kCLOCK_Wdog2 

CCGR5, CG5.

kCLOCK_Aips_tz4 

CCGR5, CG6.

kCLOCK_Spdif 

CCGR5, CG7.

kCLOCK_SimMain 

CCGR5, CG8.

kCLOCK_Sai1 

CCGR5, CG9.

kCLOCK_Sai2 

CCGR5, CG10.

kCLOCK_Sai3 

CCGR5, CG11.

kCLOCK_Lpuart1 

CCGR5, CG12.

kCLOCK_Lpuart7 

CCGR5, CG13.

kCLOCK_SnvsHp 

CCGR5, CG14.

kCLOCK_SnvsLp 

CCGR5, CG15.

kCLOCK_UsbOh3 

CCGR6, CG0.

kCLOCK_Usdhc1 

CCGR6, CG1.

kCLOCK_Usdhc2 

CCGR6, CG2.

kCLOCK_Dcdc 

CCGR6, CG3.

kCLOCK_Ipmux4 

CCGR6, CG4.

kCLOCK_FlexSpi 

CCGR6, CG5.

kCLOCK_Trng 

CCGR6, CG6.

kCLOCK_Lpuart8 

CCGR6, CG7.

kCLOCK_Timer4 

CCGR6, CG8.

kCLOCK_Aips_tz3 

CCGR6, CG9.

kCLOCK_SimPer 

CCGR6, CG10.

kCLOCK_Anadig 

CCGR6, CG11.

kCLOCK_Lpi2c4 

CCGR6, CG12.

kCLOCK_Timer1 

CCGR6, CG13.

kCLOCK_Timer2 

CCGR6, CG14.

kCLOCK_Timer3 

CCGR6, CG15.

kCLOCK_Enet2 

CCGR7, CG0.

kCLOCK_FlexSpi2 

CCGR7, CG1.

kCLOCK_Axbs_l 

CCGR7, CG2.

kCLOCK_Can3 

CCGR7, CG3.

kCLOCK_Can3S 

CCGR7, CG4.

kCLOCK_Aips_lite 

CCGR7, CG5.

kCLOCK_Flexio3 

CCGR7, CG6.

Enumerator
kCLOCK_RcOsc 

On chip OSC.

kCLOCK_XtalOsc 

24M Xtal OSC

Enumerator
kCLOCK_ClockNotNeeded 

Clock is off during all modes.

kCLOCK_ClockNeededRun 

Clock is on in run mode, but off in WAIT and STOP modes.

kCLOCK_ClockNeededRunWait 

Clock is on during all modes, except STOP mode.

Enumerator
kCLOCK_ModeRun 

Remain in run mode.

kCLOCK_ModeWait 

Transfer to wait mode.

kCLOCK_ModeStop 

Transfer to stop mode.

These constants define the mux control names for clock mux setting.

  • 0:7: REG offset to CCM_BASE in bytes.
  • 8:15: Root clock setting bit field shift.
  • 16:31: Root clock setting bit field width.
Enumerator
kCLOCK_Pll3SwMux 

pll3_sw_clk mux name

kCLOCK_PeriphMux 

periph mux name

kCLOCK_SemcAltMux 

semc mux name

kCLOCK_SemcMux 

semc mux name

kCLOCK_PrePeriphMux 

pre-periph mux name

kCLOCK_TraceMux 

trace mux name

kCLOCK_PeriphClk2Mux 

periph clock2 mux name

kCLOCK_Flexspi2Mux 

flexspi2 mux name

kCLOCK_LpspiMux 

lpspi mux name

kCLOCK_FlexspiMux 

flexspi mux name

kCLOCK_Usdhc2Mux 

usdhc2 mux name

kCLOCK_Usdhc1Mux 

usdhc1 mux name

kCLOCK_Sai3Mux 

sai3 mux name

kCLOCK_Sai2Mux 

sai2 mux name

kCLOCK_Sai1Mux 

sai1 mux name

kCLOCK_PerclkMux 

perclk mux name

kCLOCK_Flexio2Mux 

flexio2 mux name

kCLOCK_CanMux 

can mux name

kCLOCK_UartMux 

uart mux name

kCLOCK_SpdifMux 

spdif mux name

kCLOCK_Flexio1Mux 

flexio1 mux name

kCLOCK_Lpi2cMux 

lpi2c mux name

kCLOCK_LcdifPreMux 

lcdif pre mux name

kCLOCK_CsiMux 

csi mux name

These constants define div control names for clock div setting.

  • 0:7: REG offset to CCM_BASE in bytes.
  • 8:15: Root clock setting bit field shift.
  • 16:31: Root clock setting bit field width.
Enumerator
kCLOCK_ArmDiv 

core div name

kCLOCK_PeriphClk2Div 

periph clock2 div name

kCLOCK_SemcDiv 

semc div name

kCLOCK_AhbDiv 

ahb div name

kCLOCK_IpgDiv 

ipg div name

kCLOCK_Flexspi2Div 

flexspi2 div name

kCLOCK_LpspiDiv 

lpspi div name

kCLOCK_LcdifDiv 

lcdif div name

kCLOCK_FlexspiDiv 

flexspi div name

kCLOCK_PerclkDiv 

perclk div name

kCLOCK_CanDiv 

can div name

kCLOCK_TraceDiv 

trace div name

kCLOCK_Usdhc2Div 

usdhc2 div name

kCLOCK_Usdhc1Div 

usdhc1 div name

kCLOCK_UartDiv 

uart div name

kCLOCK_Flexio2Div 

flexio2 pre div name

kCLOCK_Sai3PreDiv 

sai3 pre div name

kCLOCK_Sai3Div 

sai3 div name

kCLOCK_Flexio2PreDiv 

sai3 pre div name

kCLOCK_Sai1PreDiv 

sai1 pre div name

kCLOCK_Sai1Div 

sai1 div name

kCLOCK_Sai2PreDiv 

sai2 pre div name

kCLOCK_Sai2Div 

sai2 div name

kCLOCK_Spdif0PreDiv 

spdif pre div name

kCLOCK_Spdif0Div 

spdif div name

kCLOCK_Flexio1PreDiv 

flexio1 pre div name

kCLOCK_Flexio1Div 

flexio1 div name

kCLOCK_Lpi2cDiv 

lpi2c div name

kCLOCK_LcdifPreDiv 

lcdif pre div name

kCLOCK_CsiDiv 

csi div name

Enumerator
kCLOCK_Usb480M 

Use 480M.

kCLOCK_UsbSrcUnused 

Used when the function does not care the clock source.

Enumerator
kCLOCK_Usbphy480M 

Use 480M.

Enumerator
kCLOCK_PllClkSrc24M 

Pll clock source 24M.

kCLOCK_PllSrcClkPN 

Pll clock source CLK1_P and CLK1_N.

Enumerator
kCLOCK_PllArm 

PLL ARM.

kCLOCK_PllSys 

PLL SYS.

kCLOCK_PllUsb1 

PLL USB1.

kCLOCK_PllAudio 

PLL Audio.

kCLOCK_PllVideo 

PLL Video.

kCLOCK_PllEnet 

PLL Enet0.

kCLOCK_PllEnet2 

PLL Enet1.

kCLOCK_PllEnet25M 

PLL Enet2.

kCLOCK_PllUsb2 

PLL USB2.

Enumerator
kCLOCK_Pfd0 

PLL PFD0.

kCLOCK_Pfd1 

PLL PFD1.

kCLOCK_Pfd2 

PLL PFD2.

kCLOCK_Pfd3 

PLL PFD3.

Function Documentation

static void CLOCK_SetMux ( clock_mux_t  mux,
uint32_t  value 
)
inlinestatic
Parameters
muxWhich mux node to set, see clock_mux_t.
valueClock mux value to set, different mux has different value range.
static uint32_t CLOCK_GetMux ( clock_mux_t  mux)
inlinestatic
Parameters
muxWhich mux node to get, see clock_mux_t.
Returns
Clock mux value.
static void CLOCK_SetDiv ( clock_div_t  divider,
uint32_t  value 
)
inlinestatic
Parameters
dividerWhich div node to set, see clock_div_t.
valueClock div value to set, different divider has different value range.
static uint32_t CLOCK_GetDiv ( clock_div_t  divider)
inlinestatic
Parameters
dividerWhich div node to get, see clock_div_t.
static void CLOCK_ControlGate ( clock_ip_name_t  name,
clock_gate_value_t  value 
)
inlinestatic
Parameters
nameWhich clock to enable, see clock_ip_name_t.
valueClock gate value to set, see clock_gate_value_t.
static void CLOCK_EnableClock ( clock_ip_name_t  name)
inlinestatic
Parameters
nameWhich clock to enable, see clock_ip_name_t.
static void CLOCK_DisableClock ( clock_ip_name_t  name)
inlinestatic
Parameters
nameWhich clock to disable, see clock_ip_name_t.
static void CLOCK_SetMode ( clock_mode_t  mode)
inlinestatic
Parameters
modeWhich mode to enter, see clock_mode_t.
static uint32_t CLOCK_GetOscFreq ( void  )
inlinestatic

This function will return the external XTAL OSC frequency if it is selected as the source of OSC, otherwise internal 24MHz RC OSC frequency will be returned.

Parameters
oscOSC type to get frequency.
Returns
Clock frequency; If the clock is invalid, returns 0.
uint32_t CLOCK_GetAhbFreq ( void  )
Returns
The AHB clock frequency value in hertz.
uint32_t CLOCK_GetSemcFreq ( void  )
Returns
The SEMC clock frequency value in hertz.
uint32_t CLOCK_GetIpgFreq ( void  )
Returns
The IPG clock frequency value in hertz.
uint32_t CLOCK_GetPerClkFreq ( void  )
Returns
The PER clock frequency value in hertz.
uint32_t CLOCK_GetFreq ( clock_name_t  name)

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters
clockNameClock names defined in clock_name_t
Returns
Clock frequency value in hertz
static uint32_t CLOCK_GetCpuClkFreq ( void  )
inlinestatic
Returns
Clock frequency; If the clock is invalid, returns 0.
void CLOCK_InitExternalClk ( bool  bypassXtalOsc)

This function supports two modes:

  1. Use external crystal oscillator.
  2. Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters
bypassXtalOscPass in true to bypass the external crystal oscillator.
Note
This device does not support bypass external crystal oscillator, so the input parameter should always be false.
void CLOCK_DeinitExternalClk ( void  )

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

void CLOCK_SwitchOsc ( clock_osc_t  osc)

This function switches the OSC source for SoC.

Parameters
oscOSC source to switch to.
static uint32_t CLOCK_GetRtcFreq ( void  )
inlinestatic
Returns
Clock frequency; If the clock is invalid, returns 0.
static void CLOCK_SetXtalFreq ( uint32_t  freq)
inlinestatic
Parameters
freqThe XTAL input clock frequency in Hz.
static void CLOCK_SetRtcXtalFreq ( uint32_t  freq)
inlinestatic
Parameters
freqThe RTC XTAL input clock frequency in Hz.
bool CLOCK_EnableUsbhs0Clock ( clock_usb_src_t  src,
uint32_t  freq 
)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters
srcUSB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freqUSB HS does not care about the clock source, so this parameter is ignored.
Return values
trueThe clock is set successfully.
falseThe clock source is invalid to get proper USB HS clock.
bool CLOCK_EnableUsbhs1Clock ( clock_usb_src_t  src,
uint32_t  freq 
)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters
srcUSB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freqUSB HS does not care about the clock source, so this parameter is ignored.
Return values
trueThe clock is set successfully.
falseThe clock source is invalid to get proper USB HS clock.
void CLOCK_DisableUsbhs1PhyPllClock ( void  )

This function disables USB HS PHY PLL clock.

static void CLOCK_SetPllBypass ( CCM_ANALOG_Type *  base,
clock_pll_t  pll,
bool  bypass 
)
inlinestatic
Parameters
baseCCM_ANALOG base pointer.
pllPLL control name (see ccm_analog_pll_control_t enumeration)
bypassBypass the PLL.
  • true: Bypass the PLL.
  • false:Not bypass the PLL.
static bool CLOCK_IsPllBypassed ( CCM_ANALOG_Type *  base,
clock_pll_t  pll 
)
inlinestatic
Parameters
baseCCM_ANALOG base pointer.
pllPLL control name (see ccm_analog_pll_control_t enumeration)
Returns
PLL bypass status.
  • true: The PLL is bypassed.
  • false: The PLL is not bypassed.
static bool CLOCK_IsPllEnabled ( CCM_ANALOG_Type *  base,
clock_pll_t  pll 
)
inlinestatic
Parameters
baseCCM_ANALOG base pointer.
pllPLL control name (see ccm_analog_pll_control_t enumeration)
Returns
PLL bypass status.
  • true: The PLL is enabled.
  • false: The PLL is not enabled.
static void CLOCK_SetPllBypassRefClkSrc ( CCM_ANALOG_Type *  base,
clock_pll_t  pll,
uint32_t  src 
)
inlinestatic

Note: change the bypass clock source also change the pll reference clock source.

Parameters
baseCCM_ANALOG base pointer.
pllPLL control name (see ccm_analog_pll_control_t enumeration)
srcBypass clock source, reference _clock_pll_bypass_clk_src.
static uint32_t CLOCK_GetPllBypassRefClk ( CCM_ANALOG_Type *  base,
clock_pll_t  pll 
)
inlinestatic

If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned.

Parameters
baseCCM_ANALOG base pointer.
pllPLL control name (see ccm_analog_pll_control_t enumeration)
Return values
bypassreference clock frequency value.
void CLOCK_InitArmPll ( const clock_arm_pll_config_t config)

This function initialize the ARM PLL with specific settings

Parameters
configconfiguration to set to PLL.
void CLOCK_InitSysPll ( const clock_sys_pll_config_t config)

This function initializes the System PLL with specific settings

Parameters
configConfiguration to set to PLL.
void CLOCK_InitUsb1Pll ( const clock_usb_pll_config_t config)

This function initializes the USB1 PLL with specific settings

Parameters
configConfiguration to set to PLL.
void CLOCK_InitUsb2Pll ( const clock_usb_pll_config_t config)

This function initializes the USB2 PLL with specific settings

Parameters
configConfiguration to set to PLL.
void CLOCK_InitAudioPll ( const clock_audio_pll_config_t config)

This function initializes the Audio PLL with specific settings

Parameters
configConfiguration to set to PLL.
void CLOCK_InitVideoPll ( const clock_video_pll_config_t config)

This function configures the Video PLL with specific settings

Parameters
configconfiguration to set to PLL.
void CLOCK_InitEnetPll ( const clock_enet_pll_config_t config)

This function initializes the ENET PLL with specific settings.

Parameters
configConfiguration to set to PLL.
void CLOCK_DeinitEnetPll ( void  )

This function disables the ENET PLL.

uint32_t CLOCK_GetPllFreq ( clock_pll_t  pll)

This function get current output frequency of specific PLL

Parameters
pllpll name to get frequency.
Returns
The PLL output frequency in hertz.
void CLOCK_InitSysPfd ( clock_pfd_t  pfd,
uint8_t  pfdFrac 
)

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters
pfdWhich PFD clock to enable.
pfdFracThe PFD FRAC value.
Note
It is recommended that PFD settings are kept between 12-35.
void CLOCK_DeinitSysPfd ( clock_pfd_t  pfd)

This function disables the System PLL PFD.

Parameters
pfdWhich PFD clock to disable.
void CLOCK_InitUsb1Pfd ( clock_pfd_t  pfd,
uint8_t  pfdFrac 
)

This function initializes the USB1 PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters
pfdWhich PFD clock to enable.
pfdFracThe PFD FRAC value.
Note
It is recommended that PFD settings are kept between 12-35.
void CLOCK_DeinitUsb1Pfd ( clock_pfd_t  pfd)

This function disables the USB1 PLL PFD.

Parameters
pfdWhich PFD clock to disable.
uint32_t CLOCK_GetSysPfdFreq ( clock_pfd_t  pfd)

This function get current output frequency of specific System PLL PFD

Parameters
pfdpfd name to get frequency.
Returns
The PFD output frequency in hertz.
uint32_t CLOCK_GetUsb1PfdFreq ( clock_pfd_t  pfd)

This function get current output frequency of specific USB1 PLL PFD

Parameters
pfdpfd name to get frequency.
Returns
The PFD output frequency in hertz.
bool CLOCK_EnableUsbhs0PhyPllClock ( clock_usb_phy_src_t  src,
uint32_t  freq 
)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters
srcUSB HS PHY PLL clock source.
freqThe frequency specified by src.
Return values
trueThe clock is set successfully.
falseThe clock source is invalid to get proper USB HS clock.
void CLOCK_DisableUsbhs0PhyPllClock ( void  )

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1PhyPllClock ( clock_usb_phy_src_t  src,
uint32_t  freq 
)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters
srcUSB HS PHY PLL clock source.
freqThe frequency specified by src.
Return values
trueThe clock is set successfully.
falseThe clock source is invalid to get proper USB HS clock.

Variable Documentation

volatile uint32_t g_xtalFreq

The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetXtalFreq to set the value in to clock driver. For example, if XTAL is 24MHz,

* CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC
* CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver.
*
volatile uint32_t g_rtcXtalFreq

The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the function CLOCK_SetRtcXtalFreq to set the value in to clock driver.