MCUXpresso SDK API Reference Manual  Rev. 0
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SEMC: Smart External DRAM Controller Driver

Overview

The MCUXpresso SDK provides a peripheral driver for the Smart External DRAM Controller block of MCUXpresso SDK devices.

The SEMC Initialize is to initialize for common configure: gate the SEMC clock, configure IOMUX, and queue weight setting. The SEMC Deinitialize is to ungate the clock and disable SEMC module.

The interrupt and disable operation for SEMC.

This group is mainly provide NAND/NOR memory access API which is through IP bus/ IP command access. Since the AXI access is directly read/write is so easy, so the AXI read/write part is not provided in SEMC.

Typical use case

Data Structures

struct  semc_sdram_config_t
 SEMC SDRAM configuration structure. More...
 
struct  semc_nand_timing_config_t
 SEMC NAND device timing configuration structure. More...
 
struct  semc_nand_config_t
 SEMC NAND configuration structure. More...
 
struct  semc_nor_config_t
 SEMC NOR configuration structure. More...
 
struct  semc_sram_config_t
 SEMC SRAM configuration structure. More...
 
struct  semc_dbi_config_t
 SEMC DBI configuration structure. More...
 
struct  semc_queuea_weight_struct_t
 SEMC AXI queue a weight setting structure. More...
 
union  semc_queuea_weight_t
 SEMC AXI queue a weight setting union. More...
 
struct  semc_queueb_weight_struct_t
 SEMC AXI queue b weight setting structure. More...
 
union  semc_queueb_weight_t
 SEMC AXI queue b weight setting union. More...
 
struct  semc_axi_queueweight_t
 SEMC AXI queue weight setting. More...
 
struct  semc_config_t
 SEMC configuration structure. More...
 

Enumerations

enum  
 SEMC status. More...
 
enum  semc_mem_type_t {
  kSEMC_MemType_SDRAM = 0,
  kSEMC_MemType_SRAM,
  kSEMC_MemType_NOR,
  kSEMC_MemType_NAND,
  kSEMC_MemType_8080
}
 SEMC memory device type. More...
 
enum  semc_waitready_polarity_t {
  kSEMC_LowActive = 0,
  kSEMC_HighActive
}
 SEMC WAIT/RDY polarity. More...
 
enum  semc_sdram_cs_t {
  kSEMC_SDRAM_CS0 = 0,
  kSEMC_SDRAM_CS1,
  kSEMC_SDRAM_CS2,
  kSEMC_SDRAM_CS3
}
 SEMC SDRAM Chip selection . More...
 
enum  semc_nand_access_type_t
 SEMC NAND device type. More...
 
enum  semc_interrupt_enable_t {
  kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK,
  kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK,
  kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK,
  kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK
}
 SEMC interrupts . More...
 
enum  semc_ipcmd_datasize_t {
  kSEMC_IPcmdDataSize_1bytes = 1,
  kSEMC_IPcmdDataSize_2bytes,
  kSEMC_IPcmdDataSize_3bytes,
  kSEMC_IPcmdDataSize_4bytes
}
 SEMC IP command data size in bytes. More...
 
enum  semc_refresh_time_t {
  kSEMC_RefreshThreeClocks = 0x0U,
  kSEMC_RefreshSixClocks,
  kSEMC_RefreshNineClocks
}
 SEMC auto-refresh timing. More...
 
enum  semc_caslatency_t {
  kSEMC_LatencyOne = 1,
  kSEMC_LatencyTwo,
  kSEMC_LatencyThree
}
 CAS latency. More...
 
enum  semc_sdram_column_bit_num_t {
  kSEMC_SdramColunm_12bit = 0x0U,
  kSEMC_SdramColunm_11bit,
  kSEMC_SdramColunm_10bit,
  kSEMC_SdramColunm_9bit
}
 SEMC sdram column address bit number. More...
 
enum  sem_sdram_burst_len_t {
  kSEMC_Sdram_BurstLen1 = 0,
  kSEMC_Sdram_BurstLen2,
  kSEMC_Sdram_BurstLen4,
  kSEMC_Sdram_BurstLen8
}
 SEMC sdram burst length. More...
 
enum  semc_nand_column_bit_num_t {
  kSEMC_NandColum_16bit = 0x0U,
  kSEMC_NandColum_15bit,
  kSEMC_NandColum_14bit,
  kSEMC_NandColum_13bit,
  kSEMC_NandColum_12bit,
  kSEMC_NandColum_11bit,
  kSEMC_NandColum_10bit,
  kSEMC_NandColum_9bit
}
 SEMC nand column address bit number. More...
 
enum  sem_nand_burst_len_t {
  kSEMC_Nand_BurstLen1 = 0,
  kSEMC_Nand_BurstLen2,
  kSEMC_Nand_BurstLen4,
  kSEMC_Nand_BurstLen8,
  kSEMC_Nand_BurstLen16,
  kSEMC_Nand_BurstLen32,
  kSEMC_Nand_BurstLen64
}
 SEMC nand burst length. More...
 
enum  semc_norsram_column_bit_num_t {
  kSEMC_NorColum_12bit = 0x0U,
  kSEMC_NorColum_11bit,
  kSEMC_NorColum_10bit,
  kSEMC_NorColum_9bit,
  kSEMC_NorColum_8bit,
  kSEMC_NorColum_7bit,
  kSEMC_NorColum_6bit,
  kSEMC_NorColum_5bit,
  kSEMC_NorColum_4bit,
  kSEMC_NorColum_3bit,
  kSEMC_NorColum_2bit
}
 SEMC nor/sram column address bit number. More...
 
enum  sem_norsram_burst_len_t {
  kSEMC_Nor_BurstLen1 = 0,
  kSEMC_Nor_BurstLen2,
  kSEMC_Nor_BurstLen4,
  kSEMC_Nor_BurstLen8,
  kSEMC_Nor_BurstLen16,
  kSEMC_Nor_BurstLen32,
  kSEMC_Nor_BurstLen64
}
 SEMC nor/sram burst length. More...
 
enum  semc_dbi_column_bit_num_t {
  kSEMC_Dbi_Colum_12bit = 0x0U,
  kSEMC_Dbi_Colum_11bit,
  kSEMC_Dbi_Colum_10bit,
  kSEMC_Dbi_Colum_9bit,
  kSEMC_Dbi_Colum_8bit,
  kSEMC_Dbi_Colum_7bit,
  kSEMC_Dbi_Colum_6bit,
  kSEMC_Dbi_Colum_5bit,
  kSEMC_Dbi_Colum_4bit,
  kSEMC_Dbi_Colum_3bit,
  kSEMC_Dbi_Colum_2bit
}
 SEMC dbi column address bit number. More...
 
enum  sem_dbi_burst_len_t {
  kSEMC_Dbi_BurstLen1 = 0,
  kSEMC_Dbi_BurstLen2,
  kSEMC_Dbi_Dbi_BurstLen4,
  kSEMC_Dbi_BurstLen8,
  kSEMC_Dbi_BurstLen16,
  kSEMC_Dbi_BurstLen32,
  kSEMC_Dbi_BurstLen64
}
 SEMC dbi burst length. More...
 
enum  semc_iomux_pin {
  kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT,
  kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT,
  kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT,
  kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT,
  kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT,
  kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT
}
 SEMC IOMUXC. More...
 
enum  semc_iomux_nora27_pin {
  kSEMC_MORA27_NONE = 0,
  kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT,
  kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT
}
 SEMC NOR/PSRAM Address bit 27 A27. More...
 
enum  smec_port_size_t {
  kSEMC_PortSize8Bit = 0,
  kSEMC_PortSize16Bit
}
 SEMC port size. More...
 
enum  semc_addr_mode_t {
  kSEMC_AddrDataMux = 0,
  kSEMC_AdvAddrdataMux,
  kSEMC_AddrDataNonMux
}
 SEMC address mode. More...
 
enum  semc_dqs_mode_t {
  kSEMC_Loopbackinternal = 0,
  kSEMC_Loopbackdqspad
}
 SEMC DQS read strobe mode. More...
 
enum  semc_adv_polarity_t {
  kSEMC_AdvActiveLow = 0,
  kSEMC_AdvActivehigh
}
 SEMC ADV signal active polarity. More...
 
enum  semc_rdy_polarity_t {
  kSEMC_RdyActiveLow = 0,
  kSEMC_RdyActivehigh
}
 SEMC RDY signal active polarity. More...
 
enum  semc_ipcmd_nand_addrmode_t {
  kSEMC_NANDAM_ColumnRow = 0x0U,
  kSEMC_NANDAM_ColumnCA0,
  kSEMC_NANDAM_ColumnCA0CA1,
  kSEMC_NANDAM_RawRA0,
  kSEMC_NANDAM_RawRA0RA1,
  kSEMC_NANDAM_RawRA0RA1RA2
}
 SEMC IP command for NAND: address mode. More...
 
enum  semc_ipcmd_nand_cmdmode_t {
  kSEMC_NANDCM_Command = 0x2U,
  kSEMC_NANDCM_CommandHold,
  kSEMC_NANDCM_CommandAddress,
  kSEMC_NANDCM_CommandAddressHold,
  kSEMC_NANDCM_CommandAddressRead,
  kSEMC_NANDCM_CommandAddressWrite,
  kSEMC_NANDCM_CommandRead,
  kSEMC_NANDCM_CommandWrite,
  kSEMC_NANDCM_Read,
  kSEMC_NANDCM_Write
}
 SEMC IP command for NAND: command mode. More...
 
enum  semc_nand_address_option_t {
  kSEMC_NandAddrOption_5byte_CA2RA3 = 0U,
  kSEMC_NandAddrOption_4byte_CA2RA2 = 2U,
  kSEMC_NandAddrOption_3byte_CA2RA1 = 4U,
  kSEMC_NandAddrOption_4byte_CA1RA3 = 1U,
  kSEMC_NandAddrOption_3byte_CA1RA2 = 3U,
  kSEMC_NandAddrOption_2byte_CA1RA1 = 7U
}
 SEMC NAND address option. More...
 
enum  semc_ipcmd_nor_dbi_t {
  kSEMC_NORDBICM_Read = 0x2U,
  kSEMC_NORDBICM_Write
}
 SEMC IP command for NOR. More...
 
enum  semc_ipcmd_sram_t {
  kSEMC_SRAMCM_ArrayRead = 0x2U,
  kSEMC_SRAMCM_ArrayWrite,
  kSEMC_SRAMCM_RegRead,
  kSEMC_SRAMCM_RegWrite
}
 SEMC IP command for SRAM. More...
 
enum  semc_ipcmd_sdram_t {
  kSEMC_SDRAMCM_Read = 0x8U,
  kSEMC_SDRAMCM_Write,
  kSEMC_SDRAMCM_Modeset,
  kSEMC_SDRAMCM_Active,
  kSEMC_SDRAMCM_AutoRefresh,
  kSEMC_SDRAMCM_SelfRefresh,
  kSEMC_SDRAMCM_Precharge,
  kSEMC_SDRAMCM_Prechargeall
}
 SEMC IP command for SDARM. More...
 

Driver version

#define FSL_SEMC_DRIVER_VERSION   (MAKE_VERSION(2, 1, 0))
 SEMC driver version 2.1.0. More...
 

SEMC Initialization and De-initialization

void SEMC_GetDefaultConfig (semc_config_t *config)
 Gets the SEMC default basic configuration structure. More...
 
void SEMC_Init (SEMC_Type *base, semc_config_t *configure)
 Initializes SEMC. More...
 
void SEMC_Deinit (SEMC_Type *base)
 Deinitializes the SEMC module and gates the clock. More...
 

SEMC Configuration Operation For Each Memory Type

status_t SEMC_ConfigureSDRAM (SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)
 Configures SDRAM controller in SEMC. More...
 
status_t SEMC_ConfigureNAND (SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
 Configures NAND controller in SEMC. More...
 
status_t SEMC_ConfigureNOR (SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
 Configures NOR controller in SEMC. More...
 
status_t SEMC_ConfigureSRAM (SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)
 Configures SRAM controller in SEMC. More...
 
status_t SEMC_ConfigureDBI (SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)
 Configures DBI controller in SEMC. More...
 

SEMC Interrupt Operation

static void SEMC_EnableInterrupts (SEMC_Type *base, uint32_t mask)
 Enables the SEMC interrupt. More...
 
static void SEMC_DisableInterrupts (SEMC_Type *base, uint32_t mask)
 Disables the SEMC interrupt. More...
 
static bool SEMC_GetStatusFlag (SEMC_Type *base)
 Gets the SEMC status. More...
 
static void SEMC_ClearStatusFlags (SEMC_Type *base, uint32_t mask)
 Clears the SEMC status flag state. More...
 

SEMC Memory Access Operation

static bool SEMC_IsInIdle (SEMC_Type *base)
 Check if SEMC is in idle. More...
 
status_t SEMC_SendIPCommand (SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
 SEMC IP command access. More...
 
static uint16_t SEMC_BuildNandIPCommand (uint8_t userCommand, semc_ipcmd_nand_addrmode_t addrMode, semc_ipcmd_nand_cmdmode_t cmdMode)
 Build SEMC IP command for NAND. More...
 
static bool SEMC_IsNandReady (SEMC_Type *base)
 Check if the NAND device is ready. More...
 
status_t SEMC_IPCommandNandWrite (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 SEMC NAND device memory write through IP command. More...
 
status_t SEMC_IPCommandNandRead (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 SEMC NAND device memory read through IP command. More...
 
status_t SEMC_IPCommandNorWrite (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 SEMC NOR device memory write through IP command. More...
 
status_t SEMC_IPCommandNorRead (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 SEMC NOR device memory read through IP command. More...
 

Data Structure Documentation

struct semc_sdram_config_t
  1. The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
  2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

Data Fields

semc_iomux_pin csxPinMux
 CS pin mux. More...
 
uint32_t address
 The base address. More...
 
uint32_t memsize_kbytes
 The memory size in unit of kbytes. More...
 
smec_port_size_t portSize
 Port size. More...
 
sem_sdram_burst_len_t burstLen
 Burst length. More...
 
semc_sdram_column_bit_num_t columnAddrBitNum
 Column address bit number. More...
 
semc_caslatency_t casLatency
 CAS latency. More...
 
uint8_t tPrecharge2Act_Ns
 Precharge to active wait time in unit of nanosecond. More...
 
uint8_t tAct2ReadWrite_Ns
 Act to read/write wait time in unit of nanosecond. More...
 
uint8_t tRefreshRecovery_Ns
 Refresh recovery time in unit of nanosecond. More...
 
uint8_t tWriteRecovery_Ns
 write recovery time in unit of nanosecond. More...
 
uint8_t tCkeOff_Ns
 CKE off minimum time in unit of nanosecond. More...
 
uint8_t tAct2Prechage_Ns
 Active to precharge in unit of nanosecond. More...
 
uint8_t tSelfRefRecovery_Ns
 Self refresh recovery time in unit of nanosecond. More...
 
uint8_t tRefresh2Refresh_Ns
 Refresh to refresh wait time in unit of nanosecond. More...
 
uint8_t tAct2Act_Ns
 Active to active wait time in unit of nanosecond. More...
 
uint32_t tPrescalePeriod_Ns
 Prescaler timer period should not be larger than 256 * 16 * clock cycle. More...
 
uint32_t tIdleTimeout_Ns
 Idle timeout in unit of prescale time period. More...
 
uint32_t refreshPeriod_nsPerRow
 Refresh timer period like 64ms * 1000000/8192 . More...
 
uint32_t refreshUrgThreshold
 Refresh urgent threshold. More...
 
uint8_t refreshBurstLen
 Refresh burst length. More...
 

Field Documentation

semc_iomux_pin semc_sdram_config_t::csxPinMux

The kSEMC_MUXA8 is not valid in sdram pin mux setting.

uint32_t semc_sdram_config_t::address
uint32_t semc_sdram_config_t::memsize_kbytes
smec_port_size_t semc_sdram_config_t::portSize
sem_sdram_burst_len_t semc_sdram_config_t::burstLen
semc_sdram_column_bit_num_t semc_sdram_config_t::columnAddrBitNum
semc_caslatency_t semc_sdram_config_t::casLatency
uint8_t semc_sdram_config_t::tPrecharge2Act_Ns
uint8_t semc_sdram_config_t::tAct2ReadWrite_Ns
uint8_t semc_sdram_config_t::tRefreshRecovery_Ns
uint8_t semc_sdram_config_t::tWriteRecovery_Ns
uint8_t semc_sdram_config_t::tCkeOff_Ns
uint8_t semc_sdram_config_t::tAct2Prechage_Ns
uint8_t semc_sdram_config_t::tSelfRefRecovery_Ns
uint8_t semc_sdram_config_t::tRefresh2Refresh_Ns
uint8_t semc_sdram_config_t::tAct2Act_Ns
uint32_t semc_sdram_config_t::tPrescalePeriod_Ns
uint32_t semc_sdram_config_t::tIdleTimeout_Ns
uint32_t semc_sdram_config_t::refreshPeriod_nsPerRow
uint32_t semc_sdram_config_t::refreshUrgThreshold
uint8_t semc_sdram_config_t::refreshBurstLen
struct semc_nand_timing_config_t

Data Fields

uint8_t tCeSetup_Ns
 CE setup time: tCS. More...
 
uint8_t tCeHold_Ns
 CE hold time: tCH. More...
 
uint8_t tCeInterval_Ns
 CE interval time:tCEITV. More...
 
uint8_t tWeLow_Ns
 WE low time: tWP. More...
 
uint8_t tWeHigh_Ns
 WE high time: tWH. More...
 
uint8_t tReLow_Ns
 RE low time: tRP. More...
 
uint8_t tReHigh_Ns
 RE high time: tREH. More...
 
uint8_t tTurnAround_Ns
 Turnaround time for async mode: tTA. More...
 
uint8_t tWehigh2Relow_Ns
 WE# high to RE# wait time: tWHR. More...
 
uint8_t tRehigh2Welow_Ns
 RE# high to WE# low wait time: tRHW. More...
 
uint8_t tAle2WriteStart_Ns
 ALE to write start wait time: tADL. More...
 
uint8_t tReady2Relow_Ns
 Ready to RE# low min wait time: tRR. More...
 
uint8_t tWehigh2Busy_Ns
 WE# high to busy wait time: tWB. More...
 

Field Documentation

uint8_t semc_nand_timing_config_t::tCeSetup_Ns
uint8_t semc_nand_timing_config_t::tCeHold_Ns
uint8_t semc_nand_timing_config_t::tCeInterval_Ns
uint8_t semc_nand_timing_config_t::tWeLow_Ns
uint8_t semc_nand_timing_config_t::tWeHigh_Ns
uint8_t semc_nand_timing_config_t::tReLow_Ns
uint8_t semc_nand_timing_config_t::tReHigh_Ns
uint8_t semc_nand_timing_config_t::tTurnAround_Ns
uint8_t semc_nand_timing_config_t::tWehigh2Relow_Ns
uint8_t semc_nand_timing_config_t::tRehigh2Welow_Ns
uint8_t semc_nand_timing_config_t::tAle2WriteStart_Ns
uint8_t semc_nand_timing_config_t::tReady2Relow_Ns
uint8_t semc_nand_timing_config_t::tWehigh2Busy_Ns
struct semc_nand_config_t

Data Fields

semc_iomux_pin cePinMux
 The CE pin mux setting. More...
 
uint32_t axiAddress
 The base address for AXI nand. More...
 
uint32_t axiMemsize_kbytes
 The memory size in unit of kbytes for AXI nand. More...
 
uint32_t ipgAddress
 The base address for IPG nand . More...
 
uint32_t ipgMemsize_kbytes
 The memory size in unit of kbytes for IPG nand. More...
 
semc_rdy_polarity_t rdyactivePolarity
 Wait ready polarity. More...
 
bool edoModeEnabled
 EDO mode enabled. More...
 
semc_nand_column_bit_num_t columnAddrBitNum
 Column address bit number. More...
 
semc_nand_address_option_t arrayAddrOption
 Address option. More...
 
sem_nand_burst_len_t burstLen
 Burst length. More...
 
smec_port_size_t portSize
 Port size. More...
 
semc_nand_timing_config_ttimingConfig
 SEMC nand timing configuration. More...
 

Field Documentation

semc_iomux_pin semc_nand_config_t::cePinMux

The kSEMC_MUXRDY is not valid for CE pin setting.

uint32_t semc_nand_config_t::axiAddress
uint32_t semc_nand_config_t::axiMemsize_kbytes
uint32_t semc_nand_config_t::ipgAddress
uint32_t semc_nand_config_t::ipgMemsize_kbytes
semc_rdy_polarity_t semc_nand_config_t::rdyactivePolarity
bool semc_nand_config_t::edoModeEnabled
semc_nand_column_bit_num_t semc_nand_config_t::columnAddrBitNum
semc_nand_address_option_t semc_nand_config_t::arrayAddrOption
sem_nand_burst_len_t semc_nand_config_t::burstLen
smec_port_size_t semc_nand_config_t::portSize
semc_nand_timing_config_t* semc_nand_config_t::timingConfig
struct semc_nor_config_t

Data Fields

semc_iomux_pin cePinMux
 The CE# pin mux setting. More...
 
semc_iomux_nora27_pin addr27
 The Addr bit 27 pin mux setting. More...
 
uint32_t address
 The base address. More...
 
uint32_t memsize_kbytes
 The memory size in unit of kbytes. More...
 
uint8_t addrPortWidth
 The address port width. More...
 
semc_rdy_polarity_t rdyactivePolarity
 Wait ready polarity. More...
 
semc_adv_polarity_t advActivePolarity
 ADV# polarity. More...
 
semc_norsram_column_bit_num_t columnAddrBitNum
 Column address bit number. More...
 
semc_addr_mode_t addrMode
 Address mode. More...
 
sem_norsram_burst_len_t burstLen
 Burst length. More...
 
smec_port_size_t portSize
 Port size. More...
 
uint8_t tCeSetup_Ns
 The CE setup time. More...
 
uint8_t tCeHold_Ns
 The CE hold time. More...
 
uint8_t tCeInterval_Ns
 CE interval minimum time. More...
 
uint8_t tAddrSetup_Ns
 The address setup time. More...
 
uint8_t tAddrHold_Ns
 The address hold time. More...
 
uint8_t tWeLow_Ns
 WE low time for async mode. More...
 
uint8_t tWeHigh_Ns
 WE high time for async mode. More...
 
uint8_t tReLow_Ns
 RE low time for async mode. More...
 
uint8_t tReHigh_Ns
 RE high time for async mode. More...
 
uint8_t tTurnAround_Ns
 Turnaround time for async mode. More...
 
uint8_t tAddr2WriteHold_Ns
 Address to write data hold time for async mode. More...
 
uint8_t latencyCount
 Latency count for sync mode. More...
 
uint8_t readCycle
 Read cycle time for sync mode. More...
 

Field Documentation

semc_iomux_pin semc_nor_config_t::cePinMux
semc_iomux_nora27_pin semc_nor_config_t::addr27
uint32_t semc_nor_config_t::address
uint32_t semc_nor_config_t::memsize_kbytes
uint8_t semc_nor_config_t::addrPortWidth
semc_rdy_polarity_t semc_nor_config_t::rdyactivePolarity
semc_adv_polarity_t semc_nor_config_t::advActivePolarity
semc_norsram_column_bit_num_t semc_nor_config_t::columnAddrBitNum
semc_addr_mode_t semc_nor_config_t::addrMode
sem_norsram_burst_len_t semc_nor_config_t::burstLen
smec_port_size_t semc_nor_config_t::portSize
uint8_t semc_nor_config_t::tCeSetup_Ns
uint8_t semc_nor_config_t::tCeHold_Ns
uint8_t semc_nor_config_t::tCeInterval_Ns
uint8_t semc_nor_config_t::tAddrSetup_Ns
uint8_t semc_nor_config_t::tAddrHold_Ns
uint8_t semc_nor_config_t::tWeLow_Ns
uint8_t semc_nor_config_t::tWeHigh_Ns
uint8_t semc_nor_config_t::tReLow_Ns
uint8_t semc_nor_config_t::tReHigh_Ns
uint8_t semc_nor_config_t::tTurnAround_Ns
uint8_t semc_nor_config_t::tAddr2WriteHold_Ns
uint8_t semc_nor_config_t::latencyCount
uint8_t semc_nor_config_t::readCycle
struct semc_sram_config_t

Data Fields

semc_iomux_pin cePinMux
 The CE# pin mux setting. More...
 
semc_iomux_nora27_pin addr27
 The Addr bit 27 pin mux setting. More...
 
uint32_t address
 The base address. More...
 
uint32_t memsize_kbytes
 The memory size in unit of kbytes. More...
 
uint8_t addrPortWidth
 The address port width. More...
 
semc_adv_polarity_t advActivePolarity
 ADV# polarity 1: active high, 0: active low. More...
 
semc_addr_mode_t addrMode
 Address mode. More...
 
sem_norsram_burst_len_t burstLen
 Burst length. More...
 
smec_port_size_t portSize
 Port size. More...
 
uint8_t tCeSetup_Ns
 The CE setup time. More...
 
uint8_t tCeHold_Ns
 The CE hold time. More...
 
uint8_t tCeInterval_Ns
 CE interval minimum time. More...
 
uint8_t tAddrSetup_Ns
 The address setup time. More...
 
uint8_t tAddrHold_Ns
 The address hold time. More...
 
uint8_t tWeLow_Ns
 WE low time for async mode. More...
 
uint8_t tWeHigh_Ns
 WE high time for async mode. More...
 
uint8_t tReLow_Ns
 RE low time for async mode. More...
 
uint8_t tReHigh_Ns
 RE high time for async mode. More...
 
uint8_t tTurnAround_Ns
 Turnaround time for async mode. More...
 
uint8_t tAddr2WriteHold_Ns
 Address to write data hold time for async mode. More...
 
uint8_t tWriteSetup_Ns
 Write data setup time for sync mode. More...
 
uint8_t tWriteHold_Ns
 Write hold time for sync mode. More...
 
uint8_t latencyCount
 Latency count for sync mode. More...
 
uint8_t readCycle
 Read cycle time for sync mode. More...
 

Field Documentation

semc_iomux_pin semc_sram_config_t::cePinMux
semc_iomux_nora27_pin semc_sram_config_t::addr27
uint32_t semc_sram_config_t::address
uint32_t semc_sram_config_t::memsize_kbytes
uint8_t semc_sram_config_t::addrPortWidth
semc_adv_polarity_t semc_sram_config_t::advActivePolarity
semc_addr_mode_t semc_sram_config_t::addrMode
sem_norsram_burst_len_t semc_sram_config_t::burstLen
smec_port_size_t semc_sram_config_t::portSize
uint8_t semc_sram_config_t::tCeSetup_Ns
uint8_t semc_sram_config_t::tCeHold_Ns
uint8_t semc_sram_config_t::tCeInterval_Ns
uint8_t semc_sram_config_t::tAddrSetup_Ns
uint8_t semc_sram_config_t::tAddrHold_Ns
uint8_t semc_sram_config_t::tWeLow_Ns
uint8_t semc_sram_config_t::tWeHigh_Ns
uint8_t semc_sram_config_t::tReLow_Ns
uint8_t semc_sram_config_t::tReHigh_Ns
uint8_t semc_sram_config_t::tTurnAround_Ns
uint8_t semc_sram_config_t::tAddr2WriteHold_Ns
uint8_t semc_sram_config_t::tWriteSetup_Ns
uint8_t semc_sram_config_t::tWriteHold_Ns
uint8_t semc_sram_config_t::latencyCount
uint8_t semc_sram_config_t::readCycle
struct semc_dbi_config_t

Data Fields

semc_iomux_pin csxPinMux
 The CE# pin mux. More...
 
uint32_t address
 The base address. More...
 
uint32_t memsize_kbytes
 The memory size in unit of 4kbytes. More...
 
semc_dbi_column_bit_num_t columnAddrBitNum
 Column address bit number. More...
 
sem_dbi_burst_len_t burstLen
 Burst length. More...
 
smec_port_size_t portSize
 Port size. More...
 
uint8_t tCsxSetup_Ns
 The CSX setup time. More...
 
uint8_t tCsxHold_Ns
 The CSX hold time. More...
 
uint8_t tWexLow_Ns
 WEX low time. More...
 
uint8_t tWexHigh_Ns
 WEX high time. More...
 
uint8_t tRdxLow_Ns
 RDX low time. More...
 
uint8_t tRdxHigh_Ns
 RDX high time. More...
 
uint8_t tCsxInterval_Ns
 Write data setup time. More...
 

Field Documentation

semc_iomux_pin semc_dbi_config_t::csxPinMux
uint32_t semc_dbi_config_t::address
uint32_t semc_dbi_config_t::memsize_kbytes
semc_dbi_column_bit_num_t semc_dbi_config_t::columnAddrBitNum
sem_dbi_burst_len_t semc_dbi_config_t::burstLen
smec_port_size_t semc_dbi_config_t::portSize
uint8_t semc_dbi_config_t::tCsxSetup_Ns
uint8_t semc_dbi_config_t::tCsxHold_Ns
uint8_t semc_dbi_config_t::tWexLow_Ns
uint8_t semc_dbi_config_t::tWexHigh_Ns
uint8_t semc_dbi_config_t::tRdxLow_Ns
uint8_t semc_dbi_config_t::tRdxHigh_Ns
uint8_t semc_dbi_config_t::tCsxInterval_Ns
struct semc_queuea_weight_struct_t

Data Fields

uint32_t qos: 4
 weight of qos for queue 0 . More...
 
uint32_t aging: 4
 weight of aging for queue 0. More...
 
uint32_t slaveHitSwith: 8
 weight of read/write switch for queue 0. More...
 
uint32_t slaveHitNoswitch: 8
 weight of read/write no switch for queue 0 . More...
 

Field Documentation

uint32_t semc_queuea_weight_struct_t::qos
uint32_t semc_queuea_weight_struct_t::aging
uint32_t semc_queuea_weight_struct_t::slaveHitSwith
uint32_t semc_queuea_weight_struct_t::slaveHitNoswitch
union semc_queuea_weight_t

Data Fields

semc_queuea_weight_struct_t queueaConfig
 Structure configuration for queueA. More...
 
uint32_t queueaValue
 Configuration value for queueA which could directly write to the reg. More...
 

Field Documentation

semc_queuea_weight_struct_t semc_queuea_weight_t::queueaConfig
uint32_t semc_queuea_weight_t::queueaValue
struct semc_queueb_weight_struct_t

Data Fields

uint32_t qos: 4
 weight of qos for queue 1. More...
 
uint32_t aging: 4
 weight of aging for queue 1. More...
 
uint32_t slaveHitSwith: 8
 weight of read/write switch for queue 1. More...
 
uint32_t weightPagehit: 8
 weight of page hit for queue 1 only . More...
 
uint32_t bankRotation: 8
 weight of bank rotation for queue 1 only . More...
 

Field Documentation

uint32_t semc_queueb_weight_struct_t::qos
uint32_t semc_queueb_weight_struct_t::aging
uint32_t semc_queueb_weight_struct_t::slaveHitSwith
uint32_t semc_queueb_weight_struct_t::weightPagehit
uint32_t semc_queueb_weight_struct_t::bankRotation
union semc_queueb_weight_t

Data Fields

semc_queueb_weight_struct_t queuebConfig
 Structure configuration for queueB. More...
 
uint32_t queuebValue
 Configuration value for queueB which could directly write to the reg. More...
 

Field Documentation

semc_queueb_weight_struct_t semc_queueb_weight_t::queuebConfig
uint32_t semc_queueb_weight_t::queuebValue
struct semc_axi_queueweight_t

Data Fields

semc_queuea_weight_t queueaWeight
 Weight settings for queue a. More...
 
semc_queueb_weight_t queuebWeight
 Weight settings for queue b. More...
 

Field Documentation

semc_queuea_weight_t semc_axi_queueweight_t::queueaWeight
semc_queueb_weight_t semc_axi_queueweight_t::queuebWeight
struct semc_config_t

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it's similar to the busTimeoutCycles.

Data Fields

semc_dqs_mode_t dqsMode
 Dummy read strobe mode: use enum in "semc_dqs_mode_t". More...
 
uint8_t cmdTimeoutCycles
 Command execution timeout cycles. More...
 
uint8_t busTimeoutCycles
 Bus timeout cycles. More...
 
semc_axi_queueweight_t queueWeight
 AXI queue weight. More...
 

Field Documentation

semc_dqs_mode_t semc_config_t::dqsMode
uint8_t semc_config_t::cmdTimeoutCycles
uint8_t semc_config_t::busTimeoutCycles
semc_axi_queueweight_t semc_config_t::queueWeight

Macro Definition Documentation

#define FSL_SEMC_DRIVER_VERSION   (MAKE_VERSION(2, 1, 0))

Enumeration Type Documentation

anonymous enum
Enumerator
kSEMC_MemType_SDRAM 

SDRAM.

kSEMC_MemType_SRAM 

SRAM.

kSEMC_MemType_NOR 

NOR.

kSEMC_MemType_NAND 

NAND.

kSEMC_MemType_8080 
Enumerator
kSEMC_LowActive 

Low active.

kSEMC_HighActive 

High active.

Enumerator
kSEMC_SDRAM_CS0 

SEMC SDRAM CS0.

kSEMC_SDRAM_CS1 

SEMC SDRAM CS1.

kSEMC_SDRAM_CS2 

SEMC SDRAM CS2.

kSEMC_SDRAM_CS3 

SEMC SDRAM CS3.

Enumerator
kSEMC_IPCmdDoneInterrupt 

Ip command done interrupt.

kSEMC_IPCmdErrInterrupt 

Ip command error interrupt.

kSEMC_AXICmdErrInterrupt 

AXI command error interrupt.

kSEMC_AXIBusErrInterrupt 

AXI bus error interrupt.

Enumerator
kSEMC_IPcmdDataSize_1bytes 

The IP command data size 1 byte.

kSEMC_IPcmdDataSize_2bytes 

The IP command data size 2 byte.

kSEMC_IPcmdDataSize_3bytes 

The IP command data size 3 byte.

kSEMC_IPcmdDataSize_4bytes 

The IP command data size 4 byte.

Enumerator
kSEMC_RefreshThreeClocks 

The refresh timing with three bus clocks.

kSEMC_RefreshSixClocks 

The refresh timing with six bus clocks.

kSEMC_RefreshNineClocks 

The refresh timing with nine bus clocks.

Enumerator
kSEMC_LatencyOne 

Latency 1.

kSEMC_LatencyTwo 

Latency 2.

kSEMC_LatencyThree 

Latency 3.

Enumerator
kSEMC_SdramColunm_12bit 

12 bit.

kSEMC_SdramColunm_11bit 

11 bit.

kSEMC_SdramColunm_10bit 

10 bit.

kSEMC_SdramColunm_9bit 

9 bit.

Enumerator
kSEMC_Sdram_BurstLen1 

Burst length 1.

kSEMC_Sdram_BurstLen2 

Burst length 2.

kSEMC_Sdram_BurstLen4 

Burst length 4.

kSEMC_Sdram_BurstLen8 

Burst length 8.

Enumerator
kSEMC_NandColum_16bit 

16 bit.

kSEMC_NandColum_15bit 

15 bit.

kSEMC_NandColum_14bit 

14 bit.

kSEMC_NandColum_13bit 

13 bit.

kSEMC_NandColum_12bit 

12 bit.

kSEMC_NandColum_11bit 

11 bit.

kSEMC_NandColum_10bit 

10 bit.

kSEMC_NandColum_9bit 

9 bit.

Enumerator
kSEMC_Nand_BurstLen1 

Burst length 1.

kSEMC_Nand_BurstLen2 

Burst length 2.

kSEMC_Nand_BurstLen4 

Burst length 4.

kSEMC_Nand_BurstLen8 

Burst length 8.

kSEMC_Nand_BurstLen16 

Burst length 16.

kSEMC_Nand_BurstLen32 

Burst length 32.

kSEMC_Nand_BurstLen64 

Burst length 64.

Enumerator
kSEMC_NorColum_12bit 

12 bit.

kSEMC_NorColum_11bit 

11 bit.

kSEMC_NorColum_10bit 

10 bit.

kSEMC_NorColum_9bit 

9 bit.

kSEMC_NorColum_8bit 

8 bit.

kSEMC_NorColum_7bit 

7 bit.

kSEMC_NorColum_6bit 

6 bit.

kSEMC_NorColum_5bit 

5 bit.

kSEMC_NorColum_4bit 

4 bit.

kSEMC_NorColum_3bit 

3 bit.

kSEMC_NorColum_2bit 

2 bit.

Enumerator
kSEMC_Nor_BurstLen1 

Burst length 1.

kSEMC_Nor_BurstLen2 

Burst length 2.

kSEMC_Nor_BurstLen4 

Burst length 4.

kSEMC_Nor_BurstLen8 

Burst length 8.

kSEMC_Nor_BurstLen16 

Burst length 16.

kSEMC_Nor_BurstLen32 

Burst length 32.

kSEMC_Nor_BurstLen64 

Burst length 64.

Enumerator
kSEMC_Dbi_Colum_12bit 

12 bit.

kSEMC_Dbi_Colum_11bit 

11 bit.

kSEMC_Dbi_Colum_10bit 

10 bit.

kSEMC_Dbi_Colum_9bit 

9 bit.

kSEMC_Dbi_Colum_8bit 

8 bit.

kSEMC_Dbi_Colum_7bit 

7 bit.

kSEMC_Dbi_Colum_6bit 

6 bit.

kSEMC_Dbi_Colum_5bit 

5 bit.

kSEMC_Dbi_Colum_4bit 

4 bit.

kSEMC_Dbi_Colum_3bit 

3 bit.

kSEMC_Dbi_Colum_2bit 

2 bit.

Enumerator
kSEMC_Dbi_BurstLen1 

Burst length 1.

kSEMC_Dbi_BurstLen2 

Burst length 2.

kSEMC_Dbi_Dbi_BurstLen4 

Burst length 4.

kSEMC_Dbi_BurstLen8 

Burst length 8.

kSEMC_Dbi_BurstLen16 

Burst length 16.

kSEMC_Dbi_BurstLen32 

Burst length 32.

kSEMC_Dbi_BurstLen64 

Burst length 64.

Enumerator
kSEMC_MUXA8 

MUX A8 pin.

kSEMC_MUXCSX0 

MUX CSX0 pin.

kSEMC_MUXCSX1 

MUX CSX1 Pin.

kSEMC_MUXCSX2 

MUX CSX2 Pin.

kSEMC_MUXCSX3 

MUX CSX3 Pin.

kSEMC_MUXRDY 

MUX RDY pin.

Enumerator
kSEMC_MORA27_NONE 

No NOR/SRAM A27 pin.

kSEMC_NORA27_MUXCSX3 

MUX CSX3 Pin.

kSEMC_NORA27_MUXRDY 

MUX RDY pin.

Enumerator
kSEMC_PortSize8Bit 

8-Bit port size.

kSEMC_PortSize16Bit 

16-Bit port size.

Enumerator
kSEMC_AddrDataMux 

SEMC address/data mux mode.

kSEMC_AdvAddrdataMux 

Advanced address/data mux mode.

kSEMC_AddrDataNonMux 

Address/data non-mux mode.

Enumerator
kSEMC_Loopbackinternal 

Dummy read strobe loopbacked internally.

kSEMC_Loopbackdqspad 

Dummy read strobe loopbacked from DQS pad.

Enumerator
kSEMC_AdvActiveLow 

Adv active low.

kSEMC_AdvActivehigh 

Adv active low.

Enumerator
kSEMC_RdyActiveLow 

Adv active low.

kSEMC_RdyActivehigh 

Adv active low.

Enumerator
kSEMC_NANDAM_ColumnRow 

Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2).

kSEMC_NANDAM_ColumnCA0 

Address mode: column address only(1 Byte-CA0).

kSEMC_NANDAM_ColumnCA0CA1 

Address mode: column address only(2 Byte-CA0/CA1).

kSEMC_NANDAM_RawRA0 

Address mode: row address only(1 Byte-RA0).

kSEMC_NANDAM_RawRA0RA1 

Address mode: row address only(2 Byte-RA0/RA1).

kSEMC_NANDAM_RawRA0RA1RA2 

Address mode: row address only(3 Byte-RA0).

Enumerator
kSEMC_NANDCM_Command 

command.

kSEMC_NANDCM_CommandHold 

Command hold.

kSEMC_NANDCM_CommandAddress 

Command address.

kSEMC_NANDCM_CommandAddressHold 

Command address hold.

kSEMC_NANDCM_CommandAddressRead 

Command address read.

kSEMC_NANDCM_CommandAddressWrite 

Command address write.

kSEMC_NANDCM_CommandRead 

Command read.

kSEMC_NANDCM_CommandWrite 

Command write.

kSEMC_NANDCM_Read 

Read.

kSEMC_NANDCM_Write 

Write.

Enumerator
kSEMC_NandAddrOption_5byte_CA2RA3 

CA0+CA1+RA0+RA1+RA2.

kSEMC_NandAddrOption_4byte_CA2RA2 

CA0+CA1+RA0+RA1.

kSEMC_NandAddrOption_3byte_CA2RA1 

CA0+CA1+RA0.

kSEMC_NandAddrOption_4byte_CA1RA3 

CA0+RA0+RA1+RA2.

kSEMC_NandAddrOption_3byte_CA1RA2 

CA0+RA0+RA1.

kSEMC_NandAddrOption_2byte_CA1RA1 

CA0+RA0.

Enumerator
kSEMC_NORDBICM_Read 

NOR read.

kSEMC_NORDBICM_Write 

NOR write.

Enumerator
kSEMC_SRAMCM_ArrayRead 

SRAM memory array read.

kSEMC_SRAMCM_ArrayWrite 

SRAM memory array write.

kSEMC_SRAMCM_RegRead 

SRAM memory register read.

kSEMC_SRAMCM_RegWrite 

SRAM memory register write.

Enumerator
kSEMC_SDRAMCM_Read 

SDRAM memory read.

kSEMC_SDRAMCM_Write 

SDRAM memory write.

kSEMC_SDRAMCM_Modeset 

SDRAM MODE SET.

kSEMC_SDRAMCM_Active 

SDRAM active.

kSEMC_SDRAMCM_AutoRefresh 

SDRAM auto-refresh.

kSEMC_SDRAMCM_SelfRefresh 

SDRAM self-refresh.

kSEMC_SDRAMCM_Precharge 

SDRAM precharge.

kSEMC_SDRAMCM_Prechargeall 

SDRAM precharge all.

Function Documentation

void SEMC_GetDefaultConfig ( semc_config_t config)

The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example:

Parameters
configThe SEMC configuration structure pointer.
void SEMC_Init ( SEMC_Type *  base,
semc_config_t configure 
)

This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.

Parameters
baseSEMC peripheral base address.
configureThe SEMC configuration structure pointer.
void SEMC_Deinit ( SEMC_Type *  base)

This function gates the SEMC clock. As a result, the SEMC module doesn't work after calling this function, for some IDE, calling this API may cause the next downloading operation failed. so, please call this API cautiously. Additional, users can using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control operation in drivers.

Parameters
baseSEMC peripheral base address.
status_t SEMC_ConfigureSDRAM ( SEMC_Type *  base,
semc_sdram_cs_t  cs,
semc_sdram_config_t config,
uint32_t  clkSrc_Hz 
)
Parameters
baseSEMC peripheral base address.
csThe chip selection.
configThe sdram configuration.
clkSrc_HzThe SEMC clock frequency.
status_t SEMC_ConfigureNAND ( SEMC_Type *  base,
semc_nand_config_t config,
uint32_t  clkSrc_Hz 
)
Parameters
baseSEMC peripheral base address.
configThe nand configuration.
clkSrc_HzThe SEMC clock frequency.
status_t SEMC_ConfigureNOR ( SEMC_Type *  base,
semc_nor_config_t config,
uint32_t  clkSrc_Hz 
)
Parameters
baseSEMC peripheral base address.
configThe nor configuration.
clkSrc_HzThe SEMC clock frequency.
status_t SEMC_ConfigureSRAM ( SEMC_Type *  base,
semc_sram_config_t config,
uint32_t  clkSrc_Hz 
)
Parameters
baseSEMC peripheral base address.
configThe sram configuration.
clkSrc_HzThe SEMC clock frequency.
status_t SEMC_ConfigureDBI ( SEMC_Type *  base,
semc_dbi_config_t config,
uint32_t  clkSrc_Hz 
)
Parameters
baseSEMC peripheral base address.
configThe dbi configuration.
clkSrc_HzThe SEMC clock frequency.
static void SEMC_EnableInterrupts ( SEMC_Type *  base,
uint32_t  mask 
)
inlinestatic

This function enables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to enable the IP command done and error interrupt, do the following.

Parameters
baseSEMC peripheral base address.
maskSEMC interrupts to enable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.
static void SEMC_DisableInterrupts ( SEMC_Type *  base,
uint32_t  mask 
)
inlinestatic

This function disables the SEMC interrupts according to the provided mask. The mask is a logical OR of enumeration members. See semc_interrupt_enable_t. For example, to disable the IP command done and error interrupt, do the following.

Parameters
baseSEMC peripheral base address.
maskSEMC interrupts to disable. This is a logical OR of the enumeration :: semc_interrupt_enable_t.
static bool SEMC_GetStatusFlag ( SEMC_Type *  base)
inlinestatic

This function gets the SEMC interrupts event status. User can use the a logical OR of enumeration member as a mask. See semc_interrupt_enable_t.

Parameters
baseSEMC peripheral base address.
Returns
status flag, use status flag in semc_interrupt_enable_t to get the related status.
static void SEMC_ClearStatusFlags ( SEMC_Type *  base,
uint32_t  mask 
)
inlinestatic

The following status register flags can be cleared SEMC interrupt status.

Parameters
baseSEMC base pointer
maskThe status flag mask, a logical OR of enumeration member semc_interrupt_enable_t.
static bool SEMC_IsInIdle ( SEMC_Type *  base)
inlinestatic
Parameters
baseSEMC peripheral base address.
Returns
True SEMC is in idle, false is not in idle.
status_t SEMC_SendIPCommand ( SEMC_Type *  base,
semc_mem_type_t  type,
uint32_t  address,
uint32_t  command,
uint32_t  write,
uint32_t *  read 
)
Parameters
baseSEMC peripheral base address.
typeSEMC memory type. refer to "semc_mem_type_t"
addressSEMC device address.
commandSEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". For SRAM device, take refer to "semc_ipcmd_sram_t". For SDRAM device, take refer to "semc_ipcmd_sdram_t".
writeData for write access.
readData pointer for read data out.
static uint16_t SEMC_BuildNandIPCommand ( uint8_t  userCommand,
semc_ipcmd_nand_addrmode_t  addrMode,
semc_ipcmd_nand_cmdmode_t  cmdMode 
)
inlinestatic

This function build SEMC NAND IP command. The command is build of user command code, SEMC address mode and SEMC command mode.

Parameters
userCommandNAND device normal command.
addrModeNAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
cmdModeNAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
static bool SEMC_IsNandReady ( SEMC_Type *  base)
inlinestatic
Parameters
baseSEMC peripheral base address.
Returns
True NAND is ready, false NAND is not ready.
status_t SEMC_IPCommandNandWrite ( SEMC_Type *  base,
uint32_t  address,
uint8_t *  data,
uint32_t  size_bytes 
)
Parameters
baseSEMC peripheral base address.
addressSEMC NAND device address.
dataData for write access.
size_bytesData length.
status_t SEMC_IPCommandNandRead ( SEMC_Type *  base,
uint32_t  address,
uint8_t *  data,
uint32_t  size_bytes 
)
Parameters
baseSEMC peripheral base address.
addressSEMC NAND device address.
dataData pointer for data read out.
size_bytesData length.
status_t SEMC_IPCommandNorWrite ( SEMC_Type *  base,
uint32_t  address,
uint8_t *  data,
uint32_t  size_bytes 
)
Parameters
baseSEMC peripheral base address.
addressSEMC NOR device address.
dataData for write access.
size_bytesData length.
status_t SEMC_IPCommandNorRead ( SEMC_Type *  base,
uint32_t  address,
uint8_t *  data,
uint32_t  size_bytes 
)
Parameters
baseSEMC peripheral base address.
addressSEMC NOR device address.
dataData pointer for data read out.
size_bytesData length.