MCUXpresso SDK API Reference Manual  Rev. 0
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SRC: System Reset Controller Driver

Overview

The MCUXpresso SDK provides a peripheral driver for the System Reset Controller (SRC) module.

The System Reset Controller (SRC) controls the reset and boot operation of the SoC. It is responsible for the generation of all reset signals and boot decoding. The reset controller determines the source and the type of reset, such as POR, WARM, COLD, and performs the necessary reset qualification and stretching sequences. Based on the type of reset, the reset logic generates the reset sequence for the entire IC.

Enumerations

enum  _src_reset_status_flags {
  kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK,
  kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK,
  kSRC_JTAGSystemResetFlag,
  kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK,
  kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK,
  kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK,
  kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK,
  kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK,
  kSRC_LockupSysResetFlag,
  kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK
}
 SRC reset status flags. More...
 
enum  src_warm_reset_bypass_count_t {
  kSRC_WarmResetWaitAlways = 0U,
  kSRC_WarmResetWaitClk16 = 1U,
  kSRC_WarmResetWaitClk32 = 2U,
  kSRC_WarmResetWaitClk64 = 3U
}
 Selection of WARM reset bypass count. More...
 

Functions

static void SRC_EnableWDOG3Reset (SRC_Type *base, bool enable)
 Enable the WDOG3 reset. More...
 
static void SRC_EnableCoreDebugResetAfterPowerGate (SRC_Type *base, bool enable)
 Debug reset would be asserted after power gating event. More...
 
static void SRC_DoSoftwareResetARMCore0 (SRC_Type *base)
 Do software reset the ARM core0 only. More...
 
static bool SRC_GetSoftwareResetARMCore0Done (SRC_Type *base)
 Check if the software for ARM core0 is done. More...
 
static void SRC_EnableWDOGReset (SRC_Type *base, bool enable)
 Enable the WDOG Reset in SRC. More...
 
static uint32_t SRC_GetBootModeWord1 (SRC_Type *base)
 Get the boot mode register 1 value. More...
 
static uint32_t SRC_GetBootModeWord2 (SRC_Type *base)
 Get the boot mode register 2 value. More...
 
static uint32_t SRC_GetResetStatusFlags (SRC_Type *base)
 Get the status flags of SRC. More...
 
void SRC_ClearResetStatusFlags (SRC_Type *base, uint32_t flags)
 Clear the status flags of SRC. More...
 
static void SRC_SetGeneralPurposeRegister (SRC_Type *base, uint32_t index, uint32_t value)
 Set value to general purpose registers. More...
 
static uint32_t SRC_GetGeneralPurposeRegister (SRC_Type *base, uint32_t index)
 Get the value from general purpose registers. More...
 

Driver version

#define FSL_SRC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
 SRC driver version 2.0.1. More...
 

Macro Definition Documentation

#define FSL_SRC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))

Enumeration Type Documentation

Enumerator
kSRC_TemperatureSensorResetFlag 

Indicates whether the reset was the result of software reset from on-chip Temperature Sensor.

Temperature Sensor Interrupt needs to be served before this bit can be cleaned.

kSRC_Wdog3ResetFlag 

IC Watchdog3 Time-out reset.

Indicates whether the reset was the result of the watchdog3 time-out event.

kSRC_JTAGSystemResetFlag 

Indicates whether the reset was the result of software reset form JTAG.

kSRC_JTAGSoftwareResetFlag 

Indicates whether the reset was the result of setting SJC_GPCCR bit 31.

kSRC_JTAGGeneratedResetFlag 

Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST or HIGHZ.

kSRC_WatchdogResetFlag 

Indicates a reset has been caused by the watchdog timer timing out.

This reset source can be blocked by disabling the watchdog.

kSRC_IppUserResetFlag 

Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.

kSRC_CsuResetFlag 

Indicates whether the reset was the result of the csu_reset_b input.

kSRC_LockupSysResetFlag 

Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core.

kSRC_IppResetPinFlag 

Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence).

This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated.

Enumerator
kSRC_WarmResetWaitAlways 

System will wait until MMDC acknowledge is asserted.

kSRC_WarmResetWaitClk16 

Wait 16 32KHz clock cycles before switching the reset.

kSRC_WarmResetWaitClk32 

Wait 32 32KHz clock cycles before switching the reset.

kSRC_WarmResetWaitClk64 

Wait 64 32KHz clock cycles before switching the reset.

Function Documentation

static void SRC_EnableWDOG3Reset ( SRC_Type *  base,
bool  enable 
)
inlinestatic

The WDOG3 reset is enabled by default.

Parameters
baseSRC peripheral base address.
enableEnable the reset or not.
static void SRC_EnableCoreDebugResetAfterPowerGate ( SRC_Type *  base,
bool  enable 
)
inlinestatic
Parameters
baseSRC peripheral base address.
enableEnable the reset or not.
static void SRC_DoSoftwareResetARMCore0 ( SRC_Type *  base)
inlinestatic
Parameters
baseSRC peripheral base address.
static bool SRC_GetSoftwareResetARMCore0Done ( SRC_Type *  base)
inlinestatic
Parameters
baseSRC peripheral base address.
Returns
If the reset is done.
static void SRC_EnableWDOGReset ( SRC_Type *  base,
bool  enable 
)
inlinestatic

WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear that bit is the hardware reset.

Parameters
baseSRC peripheral base address.
enableEnable the reset or not.
static uint32_t SRC_GetBootModeWord1 ( SRC_Type *  base)
inlinestatic

The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. See to chip-specific document for detail information about value.

Parameters
baseSRC peripheral base address.
Returns
status of BOOT_CFGx pins of the chip.
static uint32_t SRC_GetBootModeWord2 ( SRC_Type *  base)
inlinestatic

The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values that controls boot of the chip. See to chip-specific document for detail information about value.

Parameters
baseSRC peripheral base address.
Returns
status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
static uint32_t SRC_GetResetStatusFlags ( SRC_Type *  base)
inlinestatic
Parameters
baseSRC peripheral base address.
Returns
Mask value of status flags, see to _src_reset_status_flags.
void SRC_ClearResetStatusFlags ( SRC_Type *  base,
uint32_t  flags 
)
Parameters
baseSRC peripheral base address.
Maskvalue of status flags to be cleared, see to _src_reset_status_flags.
static void SRC_SetGeneralPurposeRegister ( SRC_Type *  base,
uint32_t  index,
uint32_t  value 
)
inlinestatic

General purpose registers (GPRx) would hold the value during reset process. Wakeup function could be kept in these register. For example, the GPR1 holds the entry function for waking-up from Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the arbitray values.

Parameters
baseSRC peripheral base address.
indexThe index of GPRx register array. Note index 0 reponses the GPR1 register.
valueSetting value for GPRx register.
static uint32_t SRC_GetGeneralPurposeRegister ( SRC_Type *  base,
uint32_t  index 
)
inlinestatic
Parameters
baseSRC peripheral base address.
indexThe index of GPRx register array. Note index 0 reponses the GPR1 register.
Returns
The setting value for GPRx register.