MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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Macros | |
#define | FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
PHY driver version. More... | |
#define | PHY_BASICCONTROL_REG 0x00U |
Defines the PHY registers. More... | |
#define | PHY_BASICSTATUS_REG 0x01U |
The PHY basic status register. More... | |
#define | PHY_ID1_REG 0x02U |
The PHY ID one register. More... | |
#define | PHY_ID2_REG 0x03U |
The PHY ID two register. More... | |
#define | PHY_AUTONEG_ADVERTISE_REG 0x04U |
The PHY auto-negotiate advertise register. More... | |
#define | PHY_STATUS_REG 0x10 |
The PHY Status register. More... | |
#define | PHY_CONTROL_ID1 0x2000U |
The PHY ID1 register value. More... | |
#define | PHY_BCTL_DUPLEX_MASK 0x0100U |
Defines the mask flag in basic control register. More... | |
#define | PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U |
The PHY restart auto negotiation mask. More... | |
#define | PHY_BCTL_AUTONEG_MASK 0x1000U |
The PHY auto negotiation bit mask. More... | |
#define | PHY_BCTL_SPEED_MASK 0x2000U |
The PHY speed bit mask. More... | |
#define | PHY_BCTL_LOOP_MASK 0x4000U |
The PHY loop bit mask. More... | |
#define | PHY_BCTL_RESET_MASK 0x8000U |
The PHY reset bit mask. More... | |
#define | PHY_BCTL_SPEED_100M_MASK 0x2000U |
The PHY 100M speed mask. More... | |
#define | PHY_LINK_READY_MASK 0x0001U |
The PHY link up. More... | |
#define | PHY_STATUS_SPEED_MASK 0x0002U |
The PHY speed mask. More... | |
#define | PHY_STATUS_DUPLEX_MASK 0x0004U |
The PHY duplex mask. More... | |
#define | PHY_STATUS_FULL_DUPLEX_MASK 0x0004U |
The PHY duplex mask. More... | |
#define | PHY_BSTATUS_LINKSTATUS_MASK 0x0004U |
Defines the mask flag in basic status register. More... | |
#define | PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U |
The PHY auto-negotiation ability mask. More... | |
#define | PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U |
The PHY auto-negotiation complete mask. More... | |
#define | PHY_100BaseT4_ABILITY_MASK 0x200U |
Defines the mask flag in PHY auto-negotiation advertise register. More... | |
#define | PHY_100BASETX_FULLDUPLEX_MASK 0x100U |
The PHY has the 100M full duplex ability. More... | |
#define | PHY_100BASETX_HALFDUPLEX_MASK 0x080U |
The PHY has the 100M full duplex ability. More... | |
#define | PHY_10BASETX_FULLDUPLEX_MASK 0x040U |
The PHY has the 10M full duplex ability. More... | |
#define | PHY_10BASETX_HALFDUPLEX_MASK 0x020U |
The PHY has the 10M full duplex ability. More... | |
#define | FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
PHY driver version. More... | |
Enumerations | |
enum | _phy_status { kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2), kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) } |
Defines the PHY status. More... | |
enum | phy_speed_t { kPHY_Speed10M = 0U, kPHY_Speed100M, kPHY_Speed10M = 0U, kPHY_Speed100M } |
Defines the PHY link speed. More... | |
enum | phy_duplex_t { kPHY_HalfDuplex = 0U, kPHY_FullDuplex, kPHY_HalfDuplex = 0U, kPHY_FullDuplex } |
Defines the PHY link duplex. More... | |
enum | phy_loop_t { kPHY_LocalLoop = 0U, kPHY_RemoteLoop, kPHY_LocalLoop = 0U, kPHY_RemoteLoop } |
Defines the PHY loopback mode. More... | |
enum | _phy_status { kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2), kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) } |
Defines the PHY status. More... | |
enum | phy_speed_t { kPHY_Speed10M = 0U, kPHY_Speed100M, kPHY_Speed10M = 0U, kPHY_Speed100M } |
Defines the PHY link speed. More... | |
enum | phy_duplex_t { kPHY_HalfDuplex = 0U, kPHY_FullDuplex, kPHY_HalfDuplex = 0U, kPHY_FullDuplex } |
Defines the PHY link duplex. More... | |
enum | phy_loop_t { kPHY_LocalLoop = 0U, kPHY_RemoteLoop, kPHY_LocalLoop = 0U, kPHY_RemoteLoop } |
Defines the PHY loopback mode. More... | |
PHY Driver | |
status_t | PHY_Init (ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) |
Initializes PHY. More... | |
status_t | PHY_Write (ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) |
PHY Write function. More... | |
status_t | PHY_Read (ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) |
PHY Read function. More... | |
status_t | PHY_EnableLoopback (ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) |
Enables/disables PHY loopback. More... | |
status_t | PHY_GetLinkStatus (ENET_Type *base, uint32_t phyAddr, bool *status) |
Gets the PHY link status. More... | |
status_t | PHY_GetLinkSpeedDuplex (ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) |
Gets the PHY link speed and duplex. More... | |
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
Version 2.0.0.
#define PHY_BASICCONTROL_REG 0x00U |
The PHY basic control register.
#define PHY_BASICSTATUS_REG 0x01U |
#define PHY_ID1_REG 0x02U |
#define PHY_ID2_REG 0x03U |
#define PHY_AUTONEG_ADVERTISE_REG 0x04U |
#define PHY_STATUS_REG 0x10 |
#define PHY_CONTROL_ID1 0x2000U |
#define PHY_BCTL_DUPLEX_MASK 0x0100U |
The PHY duplex bit mask.
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U |
#define PHY_BCTL_AUTONEG_MASK 0x1000U |
#define PHY_BCTL_SPEED_MASK 0x2000U |
#define PHY_BCTL_LOOP_MASK 0x4000U |
#define PHY_BCTL_RESET_MASK 0x8000U |
#define PHY_BCTL_SPEED_100M_MASK 0x2000U |
#define PHY_LINK_READY_MASK 0x0001U |
#define PHY_STATUS_SPEED_MASK 0x0002U |
#define PHY_STATUS_DUPLEX_MASK 0x0004U |
#define PHY_STATUS_FULL_DUPLEX_MASK 0x0004U |
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U |
The PHY link status mask.
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U |
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U |
#define PHY_100BaseT4_ABILITY_MASK 0x200U |
The PHY have the T4 ability.
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U |
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U |
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U |
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U |
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
Version 2.0.0.
enum _phy_status |
enum phy_speed_t |
enum phy_duplex_t |
enum phy_loop_t |
enum _phy_status |
enum phy_speed_t |
enum phy_duplex_t |
enum phy_loop_t |
status_t PHY_Init | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
uint32_t | srcClock_Hz | ||
) |
This function initialize the SMI interface and initialize PHY. The SMI is the MII management interface between PHY and MAC, which should be firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
base | ENET peripheral base address. |
phyAddr | The PHY address. |
srcClock_Hz | The module clock frequency - system clock for MII management interface - SMI. |
kStatus_Success | PHY initialize success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |
kStatus_PHY_AutoNegotiateFail | PHY auto negotiate fail |
status_t PHY_Write | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
uint32_t | phyReg, | ||
uint32_t | data | ||
) |
This function write data over the SMI to the specified PHY register. This function is called by all PHY interfaces.
base | ENET peripheral base address. |
phyAddr | The PHY address. |
phyReg | The PHY register. |
data | The data written to the PHY register. |
kStatus_Success | PHY write success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |
status_t PHY_Read | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
uint32_t | phyReg, | ||
uint32_t * | dataPtr | ||
) |
This interface read data over the SMI from the specified PHY register. This function is called by all PHY interfaces.
base | ENET peripheral base address. |
phyAddr | The PHY address. |
phyReg | The PHY register. |
dataPtr | The address to store the data read from the PHY register. |
kStatus_Success | PHY read success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |
status_t PHY_EnableLoopback | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
phy_loop_t | mode, | ||
phy_speed_t | speed, | ||
bool | enable | ||
) |
base | ENET peripheral base address. |
phyAddr | The PHY address. |
mode | The loopback mode to be enabled, please see "phy_loop_t". the two loopback mode should not be both set. when one loopback mode is set the other one should be disabled. |
speed | PHY speed for loopback mode. |
enable | True to enable, false to disable. |
kStatus_Success | PHY loopback success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |
status_t PHY_GetLinkStatus | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
bool * | status | ||
) |
base | ENET peripheral base address. |
phyAddr | The PHY address. |
status | The link up or down status of the PHY.
|
kStatus_Success | PHY get link status success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |
status_t PHY_GetLinkSpeedDuplex | ( | ENET_Type * | base, |
uint32_t | phyAddr, | ||
phy_speed_t * | speed, | ||
phy_duplex_t * | duplex | ||
) |
base | ENET peripheral base address. |
phyAddr | The PHY address. |
speed | The address of PHY link speed. |
duplex | The link duplex of PHY. |
kStatus_Success | PHY get link speed and duplex success |
kStatus_PHY_SMIVisitTimeout | PHY SMI visit time out |