Overview

The MCUXpresso SDK provides a peripheral driver for the CACHE Controller of MCUXpresso SDK devices.

The CACHE driver is created to help the user more easily operate the cache memory. The APIs for basic operations are including the following three levels:

1L. The L1 cache driver API. This level provides the level 1 caches controller drivers. The L1 caches are mainly integrated in the Core memory system, Cortex-M7 L1 caches, etc. For our Cortex-M4 series platforms, the L1 cache is the local memory controller (LMEM) which is not integrated in the Cortex-M4 processer memory system.

2L. The L2 cache driver API. This level provides the level 2 cache controller drivers. The L2 cache could be integrated in the CORE memory system or an external L2 cache memory, PL310, etc.

3L. The combined cache driver API. This level provides many APIs for combined L1 and L2 cache maintain operations. This is provided for MCUXpresso SDK drivers (DMA, ENET, USDHC, etc) which should do the cache maintenance in their transactional APIs.

Function groups

L1 CACHE Operation

The L1 CACHE has both code cache and data cache. This function group provides independent two groups API for both code cache and data cache. There are Enable/Disable APIs for code cache and data cache control and cache maintenance operations as Invalidate/Clean/CleanInvalidate by all and by address range.

L2 CACHE Operation

The L2 CACHE does not divide the cache to data and code. Instead, this function group provides one group cache maintenance operations as Enable/Disable/Invalidate/Clean/CleanInvalidate by all and by address range. Except the maintenance operation APIs, the L2 CACHE has it's initialization/configure API. The user can use the default configure parameter by calling L2CACHE_GetDefaultConfig() or changing the parameters as they wish. Then, call L2CACHE_Init to do the L2 CACHE initialization. After initialization, the L2 cache can then be enabled.

Note: For the core external l2 Cache, the SoC usually has the control bit to select the SRAM to use as L2 Cache or normal SRAM. Make sure this selection is right when you use the L2 CACHE feature.

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
	cache driver version 2.0.3. More...

Control for cortex-m7 L1 cache
static void	L1CACHE_EnableICache (void)
	Enables cortex-m7 L1 instruction cache.

static void	L1CACHE_DisableICache (void)
	Disables cortex-m7 L1 instruction cache.

static void	L1CACHE_InvalidateICache (void)
	Invalidate cortex-m7 L1 instruction cache.

void	L1CACHE_InvalidateICacheByRange (uint32_t address, uint32_t size_byte)
	Invalidate cortex-m7 L1 instruction cache by range. More...

static void	L1CACHE_EnableDCache (void)
	Enables cortex-m7 L1 data cache.

static void	L1CACHE_DisableDCache (void)
	Disables cortex-m7 L1 data cache.

static void	L1CACHE_InvalidateDCache (void)
	Invalidates cortex-m7 L1 data cache.

static void	L1CACHE_CleanDCache (void)
	Cleans cortex-m7 L1 data cache.

static void	L1CACHE_CleanInvalidateDCache (void)
	Cleans and Invalidates cortex-m7 L1 data cache.

static void	L1CACHE_InvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates cortex-m7 L1 data cache by range. More...

static void	L1CACHE_CleanDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans cortex-m7 L1 data cache by range. More...

static void	L1CACHE_CleanInvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates cortex-m7 L1 data cache by range. More...

Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
Mainly used for many drivers for easy cache operation.
void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates all instruction caches by range. More...

void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates all data caches by range. More...

void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Cleans all data caches by range. More...

void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates all data caches by range. More...

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))

Function Documentation

void L1CACHE_InvalidateICacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void L1CACHE_InvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void L1CACHE_CleanDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be cleaned.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void L1CACHE_CleanInvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be clean and invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void ICACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void DCACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void DCACHE_CleanByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void DCACHE_CleanInvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned and invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Overview

Function groups

L1 CACHE Operation

L2 CACHE Operation

Driver version

Control for cortex-m7 L1 cache

Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)

Macro Definition Documentation

Function Documentation