The MCUXpresso SDK provides a peripheral driver for the System Reset Controller (SRC) module.
The System Reset Controller (SRC) controls the reset and boot operation of the SoC. It is responsible for the generation of all reset signals and boot decoding. The reset controller determines the source and the type of reset, such as POR, WARM, COLD, and performs the necessary reset qualification and stretching sequences. Based on the type of reset, the reset logic generates the reset sequence for the entire IC.
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| enum | _src_reset_status_flags {
kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK,
kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK,
kSRC_JTAGSystemResetFlag,
kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK,
kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK,
kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK,
kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK,
kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK,
kSRC_LockupSysResetFlag,
kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK
} |
| | SRC reset status flags. More...
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| enum | src_warm_reset_bypass_count_t {
kSRC_WarmResetWaitAlways = 0U,
kSRC_WarmResetWaitClk16 = 1U,
kSRC_WarmResetWaitClk32 = 2U,
kSRC_WarmResetWaitClk64 = 3U
} |
| | Selection of WARM reset bypass count. More...
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| Enumerator |
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| kSRC_TemperatureSensorResetFlag |
Indicates whether the reset was the result of software reset from on-chip Temperature Sensor.
Temperature Sensor Interrupt needs to be served before this bit can be cleaned.
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| kSRC_Wdog3ResetFlag |
IC Watchdog3 Time-out reset.
Indicates whether the reset was the result of the watchdog3 time-out event.
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| kSRC_JTAGSystemResetFlag |
Indicates whether the reset was the result of software reset form JTAG.
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| kSRC_JTAGSoftwareResetFlag |
Indicates whether the reset was the result of setting SJC_GPCCR bit 31.
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| kSRC_JTAGGeneratedResetFlag |
Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST or HIGHZ.
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| kSRC_WatchdogResetFlag |
Indicates a reset has been caused by the watchdog timer timing out.
This reset source can be blocked by disabling the watchdog.
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| kSRC_IppUserResetFlag |
Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.
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| kSRC_CsuResetFlag |
Indicates whether the reset was the result of the csu_reset_b input.
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| kSRC_LockupSysResetFlag |
Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core.
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| kSRC_IppResetPinFlag |
Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence).
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This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated.
| Enumerator |
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| kSRC_WarmResetWaitAlways |
System will wait until MMDC acknowledge is asserted.
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| kSRC_WarmResetWaitClk16 |
Wait 16 32KHz clock cycles before switching the reset.
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| kSRC_WarmResetWaitClk32 |
Wait 32 32KHz clock cycles before switching the reset.
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| kSRC_WarmResetWaitClk64 |
Wait 64 32KHz clock cycles before switching the reset.
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| static void SRC_EnableWDOG3Reset |
( |
SRC_Type * |
base, |
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bool |
enable |
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) |
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inlinestatic |
The WDOG3 reset is enabled by default.
- Parameters
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| base | SRC peripheral base address. |
| enable | Enable the reset or not. |
| static void SRC_EnableCoreDebugResetAfterPowerGate |
( |
SRC_Type * |
base, |
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bool |
enable |
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) |
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inlinestatic |
- Parameters
-
| base | SRC peripheral base address. |
| enable | Enable the reset or not. |
| static void SRC_DoSoftwareResetARMCore0 |
( |
SRC_Type * |
base | ) |
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inlinestatic |
- Parameters
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| base | SRC peripheral base address. |
| static bool SRC_GetSoftwareResetARMCore0Done |
( |
SRC_Type * |
base | ) |
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inlinestatic |
- Parameters
-
| base | SRC peripheral base address. |
- Returns
- If the reset is done.
| static void SRC_EnableWDOGReset |
( |
SRC_Type * |
base, |
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bool |
enable |
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) |
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inlinestatic |
WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear that bit is the hardware reset.
- Parameters
-
| base | SRC peripheral base address. |
| enable | Enable the reset or not. |
| static uint32_t SRC_GetBootModeWord1 |
( |
SRC_Type * |
base | ) |
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inlinestatic |
The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. See to chip-specific document for detail information about value.
- Parameters
-
| base | SRC peripheral base address. |
- Returns
- status of BOOT_CFGx pins of the chip.
| static uint32_t SRC_GetBootModeWord2 |
( |
SRC_Type * |
base | ) |
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inlinestatic |
The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values that controls boot of the chip. See to chip-specific document for detail information about value.
- Parameters
-
| base | SRC peripheral base address. |
- Returns
- status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
| static uint32_t SRC_GetResetStatusFlags |
( |
SRC_Type * |
base | ) |
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inlinestatic |
| void SRC_ClearResetStatusFlags |
( |
SRC_Type * |
base, |
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uint32_t |
flags |
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) |
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| static void SRC_SetGeneralPurposeRegister |
( |
SRC_Type * |
base, |
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uint32_t |
index, |
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uint32_t |
value |
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) |
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inlinestatic |
General purpose registers (GPRx) would hold the value during reset process. Wakeup function could be kept in these register. For example, the GPR1 holds the entry function for waking-up from Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the arbitray values.
- Parameters
-
| base | SRC peripheral base address. |
| index | The index of GPRx register array. Note index 0 reponses the GPR1 register. |
| value | Setting value for GPRx register. |
| static uint32_t SRC_GetGeneralPurposeRegister |
( |
SRC_Type * |
base, |
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|
uint32_t |
index |
|
) |
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inlinestatic |
- Parameters
-
| base | SRC peripheral base address. |
| index | The index of GPRx register array. Note index 0 reponses the GPR1 register. |
- Returns
- The setting value for GPRx register.
