The MCUXpresso SDK provides a power driver for the MCUXpresso SDK devices.
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#define | PM_CFG_SRAM_BANK_BIT_BASE 0 |
| SRAM banks definition list for retention in power down modes !
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#define | POWER_WAKEUPSRC_SYSTEM LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ |
| BOD, Watchdog Timer, Flash controller, [DEEP SLEEP] BODVBAT [POWER_DOWN].
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#define | POWER_WAKEUPSRC_DMA LOWPOWER_WAKEUPSRCINT0_DMA_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_GINT LOWPOWER_WAKEUPSRCINT0_GINT_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_IRBLASTER LOWPOWER_WAKEUPSRCINT0_IRBLASTER_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PINT0 LOWPOWER_WAKEUPSRCINT0_PINT0_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PINT1 LOWPOWER_WAKEUPSRCINT0_PINT1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PINT2 LOWPOWER_WAKEUPSRCINT0_PINT2_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PINT3 LOWPOWER_WAKEUPSRCINT0_PINT3_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_SPIFI LOWPOWER_WAKEUPSRCINT0_SPIFI_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_TIMER0 LOWPOWER_WAKEUPSRCINT0_TIMER0_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_TIMER1 LOWPOWER_WAKEUPSRCINT0_TIMER1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_USART0 LOWPOWER_WAKEUPSRCINT0_USART0_IRQ |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_USART1 LOWPOWER_WAKEUPSRCINT0_USART1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_I2C0 LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_I2C1 LOWPOWER_WAKEUPSRCINT0_I2C1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_SPI0 LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_SPI1 LOWPOWER_WAKEUPSRCINT0_SPI1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM0 LOWPOWER_WAKEUPSRCINT0_PWM0_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM1 LOWPOWER_WAKEUPSRCINT0_PWM1_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM2 LOWPOWER_WAKEUPSRCINT0_PWM2_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM3 LOWPOWER_WAKEUPSRCINT0_PWM3_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM4 LOWPOWER_WAKEUPSRCINT0_PWM4_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM5 LOWPOWER_WAKEUPSRCINT0_PWM5_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM6 LOWPOWER_WAKEUPSRCINT0_PWM6_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM7 LOWPOWER_WAKEUPSRCINT0_PWM7_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM8 LOWPOWER_WAKEUPSRCINT0_PWM8_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM9 LOWPOWER_WAKEUPSRCINT0_PWM9_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_PWM10 LOWPOWER_WAKEUPSRCINT0_PWM10_IR |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_I2C2 LOWPOWER_WAKEUPSRCINT0_I2C2_IRQ |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_RTC LOWPOWER_WAKEUPSRCINT0_RTC_IRQ |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_NFCTAG LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ |
| [DEEP SLEEP, POWER DOWN (ES2 Only), DEEP DOWN (ES2 only)]
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#define | POWER_WAKEUPSRC_MAILBOX LOWPOWER_WAKEUPSRCINT0_MAILBOX_IRQ |
| Mailbox, Wake-up from DEEP SLEEP and POWER DOWN low power mode [DEEP SLEEP, POWER DOWN].
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#define | POWER_WAKEUPSRC_ADC_SEQA ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQA_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ADC_SEQB ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_SEQB_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ADC_THCMP_OVR ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ADC_THCMP_OVR_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_DMIC ((uint64_t)LOWPOWER_WAKEUPSRCINT1_DMIC_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_HWVAD ((uint64_t)LOWPOWER_WAKEUPSRCINT1_HWVAD_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_BLE_DP ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_BLE_DP0 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP0_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_BLE_DP1 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP1_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_BLE_DP2 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_DP2_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_BLE_LL_ALL ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_LL_ALL_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ZIGBEE_MAC ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MAC_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ZIGBEE_MODEM ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MODEM_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_RFP_TMU ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_TMU_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_RFP_AGC ((uint64_t)LOWPOWER_WAKEUPSRCINT1_RFP_AGC_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ISO7816 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ISO7816_IRQ << 32) |
| [DEEP SLEEP]
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#define | POWER_WAKEUPSRC_ANA_COMP ((uint64_t)LOWPOWER_WAKEUPSRCINT1_ANA_COMP_IRQ << 32) |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_WAKE_UP_TIMER0 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER0_IRQ << 32) |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_WAKE_UP_TIMER1 ((uint64_t)LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER1_IRQ << 32) |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_BLE_WAKE_TIMER ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_WAKE_TIMER_IRQ << 32) |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_BLE_OSC_EN ((uint64_t)LOWPOWER_WAKEUPSRCINT1_BLE_OSC_EN_IRQ << 32) |
| [DEEP SLEEP, POWER DOWN]
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#define | POWER_WAKEUPSRC_IO ((uint64_t)LOWPOWER_WAKEUPSRCINT1_IO_IRQ << 32) |
| [POWER DOWN, DEEP DOWN]
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#define | WAKEUP_NONE (0) |
| Programmed sources list for wakeup from POWER_DOWN Modes and DEEP_SLEEP Modes Note : PAD RESET works with All programmed wakeup sources below including WAKEUP_NONE. More...
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#define | WAKEUP_USART1 (1<<9) |
| Programmed sources list for wakeup from DEEP_SLEEP Modes only !
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In PM_SLEEP power mode, the application shall program the wakeup sources except for WAKE TIMER0/1 , RTC1KHz, RTC1Hz (field in config->wk_source) sources. Interrupt for these last wake up sources are cleared on resume. On later release, this exception will be removed and application will be responsible to program the wakeup timers. Other wake up sources interrupt are not cleared and will fire if not masked.
In power down and deep down modes, The API handles the programming of the wakeup sources. On wake up, the wakeup source becomes pending and will turn to active if unmasked. Knowing the source of interrupt can be achieved by reading the interrupt status registers in the NVIC.
In Deep sleep, power down, and deep power down modes, the API switches the CPU clock frequency to 12MHz. Application shall turn it back to the desired frequency on wake up from sleep
If RTC1KHz or RTC1Hz is the source of wakeup, the application shall switch OFF the RTC clock if it is no longer used on wakeup : CLOCK_SetClkDiv(clk, 0, false); with clk = kCLOCK_DivRtc1HzClk or kCLOCK_DivRtcClk
- Parameters
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mode | : power mode to switch the chip into |
config | : configuration structure for wakeup source setting |
- Returns
- false if chip could not go to sleep. Configuration structure is incorrect