Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Modules
	Multipurpose Clock Generator (MCG)

Files
file	fsl_clock.h

Data Structures
struct	sim_clock_config_t
	SIM configuration structure for clock setting. More...

struct	oscer_config_t
	OSC configuration for OSCERCLK. More...

struct	osc_config_t
	OSC Initialization Configuration Structure. More...

struct	mcg_pll_config_t
	MCG PLL configuration. More...

struct	mcg_config_t
	MCG mode change configuration structure. More...

Macros
#define	MCG_CONFIG_CHECK_PARAM 0U
	Configures whether to check a parameter in a function. More...

#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	MCG_INTERNAL_IRC_48M 48000000U
	IRC48M clock frequency in Hz. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX. More...

#define	RTC_CLOCKS
	Clock ip name array for RTC. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	PORT_CLOCKS
	Clock ip name array for PORT. More...

#define	FLEXBUS_CLOCKS
	Clock ip name array for FLEXBUS. More...

#define	EWM_CLOCKS
	Clock ip name array for EWM. More...

#define	PIT_CLOCKS
	Clock ip name array for PIT. More...

#define	DSPI_CLOCKS
	Clock ip name array for DSPI. More...

#define	LPTMR_CLOCKS
	Clock ip name array for LPTMR. More...

#define	FTM_CLOCKS
	Clock ip name array for FTM. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	ADC16_CLOCKS
	Clock ip name array for ADC16. More...

#define	VREF_CLOCKS
	Clock ip name array for VREF. More...

#define	UART_CLOCKS
	Clock ip name array for UART. More...

#define	RNGA_CLOCKS
	Clock ip name array for RNGA. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	I2C_CLOCKS
	Clock ip name array for I2C. More...

#define	FTF_CLOCKS
	Clock ip name array for FTF. More...

#define	PDB_CLOCKS
	Clock ip name array for PDB. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	LPO_CLK_FREQ 1000U
	LPO clock frequency.

#define	SYS_CLK kCLOCK_CoreSysClk
	Peripherals clock source definition. More...

Enumerations
enum	clock_name_t { kCLOCK_CoreSysClk, kCLOCK_PlatClk, kCLOCK_BusClk, kCLOCK_FlexBusClk, kCLOCK_FlashClk, kCLOCK_FastPeriphClk, kCLOCK_PllFllSelClk, kCLOCK_Er32kClk, kCLOCK_Osc0ErClk, kCLOCK_Osc1ErClk, kCLOCK_Osc0ErClkUndiv, kCLOCK_McgFixedFreqClk, kCLOCK_McgInternalRefClk, kCLOCK_McgFllClk, kCLOCK_McgPll0Clk, kCLOCK_McgPll1Clk, kCLOCK_McgExtPllClk, kCLOCK_McgPeriphClk, kCLOCK_McgIrc48MClk, kCLOCK_LpoClk }
	Clock name used to get clock frequency. More...

enum	clock_usb_src_t { kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(1U), kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(3U), kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) }
	USB clock source definition. More...

enum	clock_ip_name_t
	Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...

enum	osc_mode_t { kOSC_ModeExt = 0U, kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, kOSC_ModeOscHighGain }
	OSC work mode. More...

enum	_osc_cap_load { kOSC_Cap2P = OSC_CR_SC2P_MASK, kOSC_Cap4P = OSC_CR_SC4P_MASK, kOSC_Cap8P = OSC_CR_SC8P_MASK, kOSC_Cap16P = OSC_CR_SC16P_MASK }
	Oscillator capacitor load setting. More...

enum	_oscer_enable_mode { kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK }
	OSCERCLK enable mode. More...

enum	mcg_fll_src_t { kMCG_FllSrcExternal, kMCG_FllSrcInternal }
	MCG FLL reference clock source select. More...

enum	mcg_irc_mode_t { kMCG_IrcSlow, kMCG_IrcFast }
	MCG internal reference clock select. More...

enum	mcg_dmx32_t { kMCG_Dmx32Default, kMCG_Dmx32Fine }
	MCG DCO Maximum Frequency with 32.768 kHz Reference. More...

enum	mcg_drs_t { kMCG_DrsLow, kMCG_DrsMid, kMCG_DrsMidHigh, kMCG_DrsHigh }
	MCG DCO range select. More...

enum	mcg_pll_ref_src_t { kMCG_PllRefOsc0, kMCG_PllRefOsc1 }
	MCG PLL reference clock select. More...

enum	mcg_clkout_src_t { kMCG_ClkOutSrcOut, kMCG_ClkOutSrcInternal, kMCG_ClkOutSrcExternal }
	MCGOUT clock source. More...

enum	mcg_atm_select_t { kMCG_AtmSel32k, kMCG_AtmSel4m }
	MCG Automatic Trim Machine Select. More...

enum	mcg_oscsel_t { kMCG_OscselOsc, kMCG_OscselRtc, kMCG_OscselIrc }
	MCG OSC Clock Select. More...

enum	mcg_pll_clk_select_t { kMCG_PllClkSelPll0 }
	MCG PLLCS select. More...

enum	mcg_monitor_mode_t { kMCG_MonitorNone, kMCG_MonitorInt, kMCG_MonitorReset }
	MCG clock monitor mode. More...

enum	{ kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) }
	MCG status. More...

enum	{ kMCG_Osc0LostFlag = (1U << 0U), kMCG_Osc0InitFlag = (1U << 1U), kMCG_RtcOscLostFlag = (1U << 4U), kMCG_Pll0LostFlag = (1U << 5U), kMCG_Pll0LockFlag = (1U << 6U) }
	MCG status flags. More...

enum	{ kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK }
	MCG internal reference clock (MCGIRCLK) enable mode definition. More...

enum	{ kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK }
	MCG PLL clock enable mode definition. More...

enum	mcg_mode_t { kMCG_ModeFEI = 0U, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, kMCG_ModePEE, kMCG_ModeError }
	MCG mode definitions. More...

Functions
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static void	CLOCK_SetLpuartClock (uint32_t src)
	Set LPUART clock source. More...

static void	CLOCK_SetEr32kClock (uint32_t src)
	Set ERCLK32K source. More...

static void	CLOCK_SetTraceClock (uint32_t src)
	Set debug trace clock source. More...

static void	CLOCK_SetPllFllSelClock (uint32_t src)
	Set PLLFLLSEL clock source. More...

static void	CLOCK_SetClkOutClock (uint32_t src)
	Set CLKOUT source. More...

static void	CLOCK_SetRtcClkOutClock (uint32_t src)
	Set RTC_CLKOUT source. More...

bool	CLOCK_EnableUsbfs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB FS clock. More...

static void	CLOCK_DisableUsbfs0Clock (void)
	Disable USB FS clock. More...

static void	CLOCK_SetOutDiv (uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
	System clock divider. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Get the core clock or system clock frequency. More...

uint32_t	CLOCK_GetPlatClkFreq (void)
	Get the platform clock frequency. More...

uint32_t	CLOCK_GetBusClkFreq (void)
	Get the bus clock frequency. More...

uint32_t	CLOCK_GetFlexBusClkFreq (void)
	Get the flexbus clock frequency. More...

uint32_t	CLOCK_GetFlashClkFreq (void)
	Get the flash clock frequency. More...

uint32_t	CLOCK_GetPllFllSelClkFreq (void)
	Get the output clock frequency selected by SIM[PLLFLLSEL]. More...

uint32_t	CLOCK_GetEr32kClkFreq (void)
	Get the external reference 32K clock frequency (ERCLK32K). More...

uint32_t	CLOCK_GetOsc0ErClkUndivFreq (void)
	Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). More...

uint32_t	CLOCK_GetOsc0ErClkFreq (void)
	Get the OSC0 external reference clock frequency (OSC0ERCLK). More...

uint32_t	CLOCK_GetOsc0ErClkDivFreq (void)
	Get the OSC0 external reference divided clock frequency. More...

void	CLOCK_SetSimConfig (sim_clock_config_t const *config)
	Set the clock configure in SIM module. More...

static void	CLOCK_SetSimSafeDivs (void)
	Set the system clock dividers in SIM to safe value. More...

Variables
volatile uint32_t	g_xtal0Freq
	External XTAL0 (OSC0) clock frequency. More...

volatile uint32_t	g_xtal32Freq
	External XTAL32/EXTAL32/RTC_CLKIN clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
	CLOCK driver version 2.5.1. More...

MCG frequency functions.
uint32_t	CLOCK_GetOutClkFreq (void)
	Gets the MCG output clock (MCGOUTCLK) frequency. More...

uint32_t	CLOCK_GetFllFreq (void)
	Gets the MCG FLL clock (MCGFLLCLK) frequency. More...

uint32_t	CLOCK_GetInternalRefClkFreq (void)
	Gets the MCG internal reference clock (MCGIRCLK) frequency. More...

uint32_t	CLOCK_GetFixedFreqClkFreq (void)
	Gets the MCG fixed frequency clock (MCGFFCLK) frequency. More...

uint32_t	CLOCK_GetPll0Freq (void)
	Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. More...

MCG clock configuration.
static void	CLOCK_SetLowPowerEnable (bool enable)
	Enables or disables the MCG low power. More...

status_t	CLOCK_SetInternalRefClkConfig (uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
	Configures the Internal Reference clock (MCGIRCLK). More...

status_t	CLOCK_SetExternalRefClkConfig (mcg_oscsel_t oscsel)
	Selects the MCG external reference clock. More...

static void	CLOCK_SetFllExtRefDiv (uint8_t frdiv)
	Set the FLL external reference clock divider value. More...

void	CLOCK_EnablePll0 (mcg_pll_config_t const *config)
	Enables the PLL0 in FLL mode. More...

static void	CLOCK_DisablePll0 (void)
	Disables the PLL0 in FLL mode. More...

uint32_t	CLOCK_CalcPllDiv (uint32_t refFreq, uint32_t desireFreq, uint8_t prdiv, uint8_t vdiv)
	Calculates the PLL divider setting for a desired output frequency. More...

MCG clock lock monitor functions.
void	CLOCK_SetOsc0MonitorMode (mcg_monitor_mode_t mode)
	Sets the OSC0 clock monitor mode. More...

void	CLOCK_SetRtcOscMonitorMode (mcg_monitor_mode_t mode)
	Sets the RTC OSC clock monitor mode. More...

void	CLOCK_SetPll0MonitorMode (mcg_monitor_mode_t mode)
	Sets the PLL0 clock monitor mode. More...

uint32_t	CLOCK_GetStatusFlags (void)
	Gets the MCG status flags. More...

void	CLOCK_ClearStatusFlags (uint32_t mask)
	Clears the MCG status flags. More...

OSC configuration
static void	OSC_SetExtRefClkConfig (OSC_Type base, oscer_config_t const config)
	Configures the OSC external reference clock (OSCERCLK). More...

static void	OSC_SetCapLoad (OSC_Type *base, uint8_t capLoad)
	Sets the capacitor load configuration for the oscillator. More...

void	CLOCK_InitOsc0 (osc_config_t const *config)
	Initializes the OSC0. More...

void	CLOCK_DeinitOsc0 (void)
	Deinitializes the OSC0. More...

External clock frequency
static void	CLOCK_SetXtal0Freq (uint32_t freq)
	Sets the XTAL0 frequency based on board settings. More...

static void	CLOCK_SetXtal32Freq (uint32_t freq)
	Sets the XTAL32/RTC_CLKIN frequency based on board settings. More...

IRCs frequency
void	CLOCK_SetSlowIrcFreq (uint32_t freq)
	Set the Slow IRC frequency based on the trimmed value. More...

void	CLOCK_SetFastIrcFreq (uint32_t freq)
	Set the Fast IRC frequency based on the trimmed value. More...

MCG auto-trim machine.
status_t	CLOCK_TrimInternalRefClk (uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
	Auto trims the internal reference clock. More...

MCG mode functions.
mcg_mode_t	CLOCK_GetMode (void)
	Gets the current MCG mode. More...

status_t	CLOCK_SetFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FEI mode. More...

status_t	CLOCK_SetFeeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FEE mode. More...

status_t	CLOCK_SetFbiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FBI mode. More...

status_t	CLOCK_SetFbeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FBE mode. More...

status_t	CLOCK_SetBlpiMode (void)
	Sets the MCG to BLPI mode. More...

status_t	CLOCK_SetBlpeMode (void)
	Sets the MCG to BLPE mode. More...

status_t	CLOCK_SetPbeMode (mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
	Sets the MCG to PBE mode. More...

status_t	CLOCK_SetPeeMode (void)
	Sets the MCG to PEE mode. More...

status_t	CLOCK_ExternalModeToFbeModeQuick (void)
	Switches the MCG to FBE mode from the external mode. More...

status_t	CLOCK_InternalModeToFbiModeQuick (void)
	Switches the MCG to FBI mode from internal modes. More...

status_t	CLOCK_BootToFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FEI mode during system boot up. More...

status_t	CLOCK_BootToFeeMode (mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void))
	Sets the MCG to FEE mode during system bootup. More...

status_t	CLOCK_BootToBlpiMode (uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
	Sets the MCG to BLPI mode during system boot up. More...

status_t	CLOCK_BootToBlpeMode (mcg_oscsel_t oscsel)
	Sets the MCG to BLPE mode during system boot up. More...

status_t	CLOCK_BootToPeeMode (mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
	Sets the MCG to PEE mode during system boot up. More...

status_t	CLOCK_SetMcgConfig (mcg_config_t const *config)
	Sets the MCG to a target mode. More...

Data Structure Documentation

struct sim_clock_config_t

Data Fields
uint8_t	pllFllSel
	PLL/FLL/IRC48M selection. More...

uint8_t	er32kSrc
	ERCLK32K source selection. More...

uint32_t	clkdiv1
	SIM_CLKDIV1. More...

Field Documentation

uint8_t sim_clock_config_t::pllFllSel

uint8_t sim_clock_config_t::er32kSrc

uint32_t sim_clock_config_t::clkdiv1

struct oscer_config_t

Data Fields
uint8_t	enableMode
	OSCERCLK enable mode. More...

uint8_t	erclkDiv
	Divider for OSCERCLK. More...

Field Documentation

uint8_t oscer_config_t::enableMode

OR'ed value of _oscer_enable_mode.

uint8_t oscer_config_t::erclkDiv

struct osc_config_t

Defines the configuration data structure to initialize the OSC. When porting to a new board, set the following members according to the board setting:

freq: The external frequency.
workMode: The OSC module mode.

Data Fields
uint32_t	freq
	External clock frequency. More...

uint8_t	capLoad
	Capacitor load setting. More...

osc_mode_t	workMode
	OSC work mode setting. More...

oscer_config_t	oscerConfig
	Configuration for OSCERCLK. More...

Field Documentation

uint32_t osc_config_t::freq

uint8_t osc_config_t::capLoad

osc_mode_t osc_config_t::workMode

oscer_config_t osc_config_t::oscerConfig

struct mcg_pll_config_t

Data Fields
uint8_t	enableMode
	Enable mode. More...

uint8_t	prdiv
	Reference divider PRDIV. More...

uint8_t	vdiv
	VCO divider VDIV. More...

Field Documentation

uint8_t mcg_pll_config_t::enableMode

OR'ed value of enumeration _mcg_pll_enable_mode.

uint8_t mcg_pll_config_t::prdiv

uint8_t mcg_pll_config_t::vdiv

struct mcg_config_t

When porting to a new board, set the following members according to the board setting:

frdiv: If the FLL uses the external reference clock, set this value to ensure that the external reference clock divided by frdiv is in the 31.25 kHz to 39.0625 kHz range.
The PLL reference clock divider PRDIV: PLL reference clock frequency after PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to FSL_FEATURE_MCG_PLL_REF_MAX range.

Data Fields
mcg_mode_t	mcgMode
	MCG mode. More...

uint8_t	irclkEnableMode
	MCGIRCLK enable mode. More...

mcg_irc_mode_t	ircs
	Source, MCG_C2[IRCS]. More...

uint8_t	fcrdiv
	Divider, MCG_SC[FCRDIV]. More...

uint8_t	frdiv
	Divider MCG_C1[FRDIV]. More...

mcg_drs_t	drs
	DCO range MCG_C4[DRST_DRS]. More...

mcg_dmx32_t	dmx32
	MCG_C4[DMX32]. More...

mcg_oscsel_t	oscsel
	OSC select MCG_C7[OSCSEL]. More...

mcg_pll_config_t	pll0Config
	MCGPLL0CLK configuration. More...

Field Documentation

mcg_mode_t mcg_config_t::mcgMode

uint8_t mcg_config_t::irclkEnableMode

mcg_irc_mode_t mcg_config_t::ircs

uint8_t mcg_config_t::fcrdiv

uint8_t mcg_config_t::frdiv

mcg_drs_t mcg_config_t::drs

mcg_dmx32_t mcg_config_t::dmx32

mcg_oscsel_t mcg_config_t::oscsel

mcg_pll_config_t mcg_config_t::pll0Config

Macro Definition Documentation

#define MCG_CONFIG_CHECK_PARAM 0U

Some MCG settings must be changed with conditions, for example:

MCGIRCLK settings, such as the source, divider, and the trim value should not change when MCGIRCLK is used as a system clock source.
MCG_C7[OSCSEL] should not be changed when the external reference clock is used as a system clock source. For example, in FBE/BLPE/PBE modes.
The users should only switch between the supported clock modes.

MCG functions check the parameter and MCG status before setting, if not allowed to change, the functions return error. The parameter checking increases code size, if code size is a critical requirement, change MCG_CONFIG_CHECK_PARAM to 0 to disable parameter checking.

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))

#define MCG_INTERNAL_IRC_48M 48000000U

#define DMAMUX_CLOCKS

Value:

{                  \
        kCLOCK_Dmamux0 \
    }

#define RTC_CLOCKS

Value:

{               \
        kCLOCK_Rtc0 \
    }

#define SAI_CLOCKS

Value:

{               \
        kCLOCK_Sai0 \
    }

#define PORT_CLOCKS

Value:

{                                                                        \
        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
    }

#define FLEXBUS_CLOCKS

Value:

{                   \
        kCLOCK_Flexbus0 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define PIT_CLOCKS

Value:

{               \
        kCLOCK_Pit0 \
    }

#define DSPI_CLOCKS

Value:

{                            \
        kCLOCK_Spi0, kCLOCK_Spi1 \
    }

#define LPTMR_CLOCKS

Value:

{                 \
        kCLOCK_Lptmr0 \
    }

#define FTM_CLOCKS

Value:

{                                                      \
        kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
    }

#define EDMA_CLOCKS

Value:

{               \
        kCLOCK_Dma0 \
    }

#define LPUART_CLOCKS

Value:

{                  \
        kCLOCK_Lpuart0 \
    }

#define DAC_CLOCKS

Value:

{                            \
        kCLOCK_Dac0, kCLOCK_Dac1 \
    }

#define ADC16_CLOCKS

Value:

{                            \
        kCLOCK_Adc0, kCLOCK_Adc1 \
    }

#define VREF_CLOCKS

Value:

{                \
        kCLOCK_Vref0 \
    }

#define UART_CLOCKS

Value:

{                                            \
        kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
    }

#define RNGA_CLOCKS

Value:

{                \
        kCLOCK_Rnga0 \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define I2C_CLOCKS

Value:

{                            \
        kCLOCK_I2c0, kCLOCK_I2c1 \
    }

#define FTF_CLOCKS

Value:

{               \
        kCLOCK_Ftf0 \
    }

#define PDB_CLOCKS

Value:

{               \
        kCLOCK_Pdb0 \
    }

#define CMP_CLOCKS

Value:

{                            \
        kCLOCK_Cmp0, kCLOCK_Cmp1 \
    }

#define SYS_CLK kCLOCK_CoreSysClk

Enumeration Type Documentation

enum clock_name_t

Enumerator
kCLOCK_CoreSysClk	Core/system clock.
kCLOCK_PlatClk	Platform clock.
kCLOCK_BusClk	Bus clock.
kCLOCK_FlexBusClk	FlexBus clock.
kCLOCK_FlashClk	Flash clock.
kCLOCK_FastPeriphClk	Fast peripheral clock.
kCLOCK_PllFllSelClk	The clock after SIM[PLLFLLSEL].
kCLOCK_Er32kClk	External reference 32K clock (ERCLK32K)
kCLOCK_Osc0ErClk	OSC0 external reference clock (OSC0ERCLK)
kCLOCK_Osc1ErClk	OSC1 external reference clock (OSC1ERCLK)
kCLOCK_Osc0ErClkUndiv	OSC0 external reference undivided clock(OSC0ERCLK_UNDIV).
kCLOCK_McgFixedFreqClk	MCG fixed frequency clock (MCGFFCLK)
kCLOCK_McgInternalRefClk	MCG internal reference clock (MCGIRCLK)
kCLOCK_McgFllClk	MCGFLLCLK.
kCLOCK_McgPll0Clk	MCGPLL0CLK.
kCLOCK_McgPll1Clk	MCGPLL1CLK.
kCLOCK_McgExtPllClk	EXT_PLLCLK.
kCLOCK_McgPeriphClk	MCG peripheral clock (MCGPCLK)
kCLOCK_McgIrc48MClk	MCG IRC48M clock.
kCLOCK_LpoClk	LPO clock.

enum clock_usb_src_t

Enumerator
kCLOCK_UsbSrcPll0	Use PLL0.
kCLOCK_UsbSrcIrc48M	Use IRC48M.
kCLOCK_UsbSrcExt	Use USB_CLKIN.

enum clock_ip_name_t

enum osc_mode_t

Enumerator
kOSC_ModeExt	Use an external clock.
kOSC_ModeOscLowPower	Oscillator low power.
kOSC_ModeOscHighGain	Oscillator high gain.

enum _osc_cap_load

Enumerator
kOSC_Cap2P	2 pF capacitor load
kOSC_Cap4P	4 pF capacitor load
kOSC_Cap8P	8 pF capacitor load
kOSC_Cap16P	16 pF capacitor load

enum _oscer_enable_mode

Enumerator
kOSC_ErClkEnable	Enable.
kOSC_ErClkEnableInStop	Enable in stop mode.

enum mcg_fll_src_t

Enumerator
kMCG_FllSrcExternal	External reference clock is selected.
kMCG_FllSrcInternal	The slow internal reference clock is selected.

enum mcg_irc_mode_t

Enumerator
kMCG_IrcSlow	Slow internal reference clock selected.
kMCG_IrcFast	Fast internal reference clock selected.

enum mcg_dmx32_t

Enumerator
kMCG_Dmx32Default	DCO has a default range of 25%.
kMCG_Dmx32Fine	DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

enum mcg_drs_t

Enumerator
kMCG_DrsLow	Low frequency range.
kMCG_DrsMid	Mid frequency range.
kMCG_DrsMidHigh	Mid-High frequency range.
kMCG_DrsHigh	High frequency range.

enum mcg_pll_ref_src_t

Enumerator
kMCG_PllRefOsc0	Selects OSC0 as PLL reference clock.
kMCG_PllRefOsc1	Selects OSC1 as PLL reference clock.

enum mcg_clkout_src_t

Enumerator
kMCG_ClkOutSrcOut	Output of the FLL is selected (reset default)
kMCG_ClkOutSrcInternal	Internal reference clock is selected.
kMCG_ClkOutSrcExternal	External reference clock is selected.

enum mcg_atm_select_t

Enumerator
kMCG_AtmSel32k	32 kHz Internal Reference Clock selected
kMCG_AtmSel4m	4 MHz Internal Reference Clock selected

enum mcg_oscsel_t

Enumerator
kMCG_OscselOsc	Selects System Oscillator (OSCCLK)
kMCG_OscselRtc	Selects 32 kHz RTC Oscillator.
kMCG_OscselIrc	Selects 48 MHz IRC Oscillator.

enum mcg_pll_clk_select_t

Enumerator
kMCG_PllClkSelPll0	PLL0 output clock is selected.

enum mcg_monitor_mode_t

Enumerator
kMCG_MonitorNone	Clock monitor is disabled.
kMCG_MonitorInt	Trigger interrupt when clock lost.
kMCG_MonitorReset	System reset when clock lost.

anonymous enum

Enumeration _mcg_status

Enumerator
kStatus_MCG_ModeUnreachable	Can't switch to target mode.
kStatus_MCG_ModeInvalid	Current mode invalid for the specific function.
kStatus_MCG_AtmBusClockInvalid	Invalid bus clock for ATM.
kStatus_MCG_AtmDesiredFreqInvalid	Invalid desired frequency for ATM.
kStatus_MCG_AtmIrcUsed	IRC is used when using ATM.
kStatus_MCG_AtmHardwareFail	Hardware fail occurs during ATM.
kStatus_MCG_SourceUsed	Can't change the clock source because it is in use.

anonymous enum

Enumeration _mcg_status_flags_t

Enumerator
kMCG_Osc0LostFlag	OSC0 lost.
kMCG_Osc0InitFlag	OSC0 crystal initialized.
kMCG_RtcOscLostFlag	RTC OSC lost.
kMCG_Pll0LostFlag	PLL0 lost.
kMCG_Pll0LockFlag	PLL0 locked.

anonymous enum

Enumeration _mcg_irclk_enable_mode

Enumerator
kMCG_IrclkEnable	MCGIRCLK enable.
kMCG_IrclkEnableInStop	MCGIRCLK enable in stop mode.

anonymous enum

Enumeration _mcg_pll_enable_mode

Enumerator

kMCG_PllEnableIndependent

MCGPLLCLK enable independent of the MCG clock mode.

Generally, the PLL is disabled in FLL modes (FEI/FBI/FEE/FBE). Setting the PLL clock enable independent, enables the PLL in the FLL modes.

kMCG_PllEnableInStop

MCGPLLCLK enable in STOP mode.

enum mcg_mode_t

Enumerator
kMCG_ModeFEI	FEI - FLL Engaged Internal.
kMCG_ModeFBI	FBI - FLL Bypassed Internal.
kMCG_ModeBLPI	BLPI - Bypassed Low Power Internal.
kMCG_ModeFEE	FEE - FLL Engaged External.
kMCG_ModeFBE	FBE - FLL Bypassed External.
kMCG_ModeBLPE	BLPE - Bypassed Low Power External.
kMCG_ModePBE	PBE - PLL Bypassed External.
kMCG_ModePEE	PEE - PLL Engaged External.
kMCG_ModeError	Unknown mode.

Function Documentation

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

static void CLOCK_SetLpuartClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set LPUART clock source.

static void CLOCK_SetEr32kClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set ERCLK32K clock source.

static void CLOCK_SetTraceClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set debug trace clock source.

static void CLOCK_SetPllFllSelClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set PLLFLLSEL clock source.

static void CLOCK_SetClkOutClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set CLKOUT source.

static void CLOCK_SetRtcClkOutClock ( uint32_t src )

inlinestatic

Parameters

src	The value to set RTC_CLKOUT source.

bool CLOCK_EnableUsbfs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	USB FS clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB FS clock.

static void CLOCK_DisableUsbfs0Clock ( void )

inlinestatic

Disable USB FS clock.

static void CLOCK_SetOutDiv	(	uint32_t	outdiv1,
		uint32_t	outdiv2,
		uint32_t	outdiv3,
		uint32_t	outdiv4
	)

inlinestatic

Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].

Parameters

outdiv1	Clock 1 output divider value.
outdiv2	Clock 2 output divider value.
outdiv3	Clock 3 output divider value.
outdiv4	Clock 4 output divider value.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t. The MCG must be properly configured before using this function.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in Hertz

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetPlatClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetBusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFlexBusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFlashClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetPllFllSelClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetEr32kClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetOsc0ErClkUndivFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetOsc0ErClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetOsc0ErClkDivFreq ( void )

Returns: Clock frequency in Hz.

void CLOCK_SetSimConfig ( sim_clock_config_t const * config )

This function sets system layer clock settings in SIM module.

Parameters

config Pointer to the configure structure.

static void CLOCK_SetSimSafeDivs ( void )

inlinestatic

The system level clocks (core clock, bus clock, flexbus clock and flash clock) must be in allowed ranges. During MCG clock mode switch, the MCG output clock changes then the system level clocks may be out of range. This function could be used before MCG mode change, to make sure system level clocks are in allowed range.

uint32_t CLOCK_GetOutClkFreq ( void )

This function gets the MCG output clock frequency in Hz based on the current MCG register value.

Returns: The frequency of MCGOUTCLK.

uint32_t CLOCK_GetFllFreq ( void )

This function gets the MCG FLL clock frequency in Hz based on the current MCG register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and disabled in low power state in other modes.

Returns: The frequency of MCGFLLCLK.

uint32_t CLOCK_GetInternalRefClkFreq ( void )

This function gets the MCG internal reference clock frequency in Hz based on the current MCG register value.

Returns: The frequency of MCGIRCLK.

uint32_t CLOCK_GetFixedFreqClkFreq ( void )

This function gets the MCG fixed frequency clock frequency in Hz based on the current MCG register value.

Returns: The frequency of MCGFFCLK.

uint32_t CLOCK_GetPll0Freq ( void )

This function gets the MCG PLL0 clock frequency in Hz based on the current MCG register value.

Returns: The frequency of MCGPLL0CLK.

static void CLOCK_SetLowPowerEnable ( bool enable )

inlinestatic

Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and PBI modes, enabling low power sets the MCG to BLPI mode. When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.

Parameters

enable True to enable MCG low power, false to disable MCG low power.

status_t CLOCK_SetInternalRefClkConfig	(	uint8_t	enableMode,
		mcg_irc_mode_t	ircs,
		uint8_t	fcrdiv
	)

This function sets the MCGIRCLK base on parameters. It also selects the IRC source. If the fast IRC is used, this function sets the fast IRC divider. This function also sets whether the MCGIRCLK is enabled in stop mode. Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, using the function in these modes it is not allowed.

Parameters

enableMode	MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
ircs	MCGIRCLK clock source, choose fast or slow.
fcrdiv	Fast IRC divider setting (`FCRDIV`).

Return values

kStatus_MCG_SourceUsed	Because the internal reference clock is used as a clock source, the configuration should not be changed. Otherwise, a glitch occurs.
kStatus_Success	MCGIRCLK configuration finished successfully.

status_t CLOCK_SetExternalRefClkConfig ( mcg_oscsel_t oscsel )

Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], and waits for the clock source to be stable. Because the external reference clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.

Parameters

oscsel MCG external reference clock source, MCG_C7[OSCSEL].

Return values

kStatus_MCG_SourceUsed	Because the external reference clock is used as a clock source, the configuration should not be changed. Otherwise, a glitch occurs.
kStatus_Success	External reference clock set successfully.

static void CLOCK_SetFllExtRefDiv ( uint8_t frdiv )

inlinestatic

Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].

Parameters

frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].

void CLOCK_EnablePll0 ( mcg_pll_config_t const * config )

This function sets us the PLL0 in FLL mode and reconfigures the PLL0. Ensure that the PLL reference clock is enabled before calling this function and that the PLL0 is not used as a clock source. The function CLOCK_CalcPllDiv gets the correct PLL divider values.

Parameters

config Pointer to the configuration structure.

static void CLOCK_DisablePll0 ( void )

inlinestatic

This function disables the PLL0 in FLL mode. It should be used together with the CLOCK_EnablePll0.

uint32_t CLOCK_CalcPllDiv	(	uint32_t	refFreq,
		uint32_t	desireFreq,
		uint8_t *	prdiv,
		uint8_t *	vdiv
	)

This function calculates the correct reference clock divider (PRDIV) and VCO divider (VDIV) to generate a desired PLL output frequency. It returns the closest frequency match with the corresponding PRDIV/VDIV returned from parameters. If a desired frequency is not valid, this function returns 0.

Parameters

refFreq	PLL reference clock frequency.
desireFreq	Desired PLL output frequency.
prdiv	PRDIV value to generate desired PLL frequency.
vdiv	VDIV value to generate desired PLL frequency.

Returns: Closest frequency match that the PLL was able generate.

void CLOCK_SetOsc0MonitorMode ( mcg_monitor_mode_t mode )

This function sets the OSC0 clock monitor mode. See mcg_monitor_mode_t for details.

Parameters

mode	Monitor mode to set.

void CLOCK_SetRtcOscMonitorMode ( mcg_monitor_mode_t mode )

This function sets the RTC OSC clock monitor mode. See mcg_monitor_mode_t for details.

Parameters

mode	Monitor mode to set.

void CLOCK_SetPll0MonitorMode ( mcg_monitor_mode_t mode )

This function sets the PLL0 clock monitor mode. See mcg_monitor_mode_t for details.

Parameters

mode	Monitor mode to set.

uint32_t CLOCK_GetStatusFlags ( void )

This function gets the MCG clock status flags. All status flags are returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To check a specific flag, compare the return value with the flag.

Example:

* To check the clock lost lock status of OSC0 and PLL0.
* uint32_t mcgFlags;
*
* mcgFlags = CLOCK_GetStatusFlags();
*
* if (mcgFlags & kMCG_Osc0LostFlag)
* {
*     OSC0 clock lock lost. Do something.
* }
* if (mcgFlags & kMCG_Pll0LostFlag)
* {
*     PLL0 clock lock lost. Do something.
* }
* 

Returns: Logical OR value of the enumeration _mcg_status_flags_t.

void CLOCK_ClearStatusFlags ( uint32_t mask )

This function clears the MCG clock lock lost status. The parameter is a logical OR value of the flags to clear. See the enumeration _mcg_status_flags_t.

Example:

* To clear the clock lost lock status flags of OSC0 and PLL0.
*
* CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
* 

Parameters

mask	The status flags to clear. This is a logical OR of members of the enumeration _mcg_status_flags_t.

static void OSC_SetExtRefClkConfig	(	OSC_Type *	base,
		oscer_config_t const *	config
	)

inlinestatic

This function configures the OSC external reference clock (OSCERCLK). This is an example to enable the OSCERCLK in normal and stop modes and also set the output divider to 1:

oscer_config_t config =
{
    .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
    .erclkDiv   = 1U,
};
OSC_SetExtRefClkConfig(OSC, &config);

Parameters

base	OSC peripheral address.
config	Pointer to the configuration structure.

static void OSC_SetCapLoad	(	OSC_Type *	base,
		uint8_t	capLoad
	)

inlinestatic

This function sets the specified capacitors configuration for the oscillator. This should be done in the early system level initialization function call based on the system configuration.

Parameters

base	OSC peripheral address.
capLoad	OR'ed value for the capacitor load option, see _osc_cap_load.

Example:

To enable only 2 pF and 8 pF capacitor load, please use like this.

OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);

void CLOCK_InitOsc0 ( osc_config_t const * config )

This function initializes the OSC0 according to the board configuration.

Parameters

config Pointer to the OSC0 configuration structure.

void CLOCK_DeinitOsc0 ( void )

This function deinitializes the OSC0.

static void CLOCK_SetXtal0Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL0/EXTAL0 input clock frequency in Hz.

static void CLOCK_SetXtal32Freq ( uint32_t freq )

inlinestatic

Parameters

freq	The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.

void CLOCK_SetSlowIrcFreq ( uint32_t freq )

Parameters

freq	The Slow IRC frequency input clock frequency in Hz.

void CLOCK_SetFastIrcFreq ( uint32_t freq )

Parameters

freq	The Fast IRC frequency input clock frequency in Hz.

status_t CLOCK_TrimInternalRefClk	(	uint32_t	extFreq,
		uint32_t	desireFreq,
		uint32_t *	actualFreq,
		mcg_atm_select_t	atms
	)

This function trims the internal reference clock by using the external clock. If successful, it returns the kStatus_Success and the frequency after trimming is received in the parameter actualFreq. If an error occurs, the error code is returned.

Parameters

extFreq	External clock frequency, which should be a bus clock.
desireFreq	Frequency to trim to.
actualFreq	Actual frequency after trimming.
atms	Trim fast or slow internal reference clock.

Return values

kStatus_Success	ATM success.
kStatus_MCG_AtmBusClockInvalid	The bus clock is not in allowed range for the ATM.
kStatus_MCG_AtmDesiredFreqInvalid	MCGIRCLK could not be trimmed to the desired frequency.
kStatus_MCG_AtmIrcUsed	Could not trim because MCGIRCLK is used as a bus clock source.
kStatus_MCG_AtmHardwareFail	Hardware fails while trimming.

mcg_mode_t CLOCK_GetMode ( void )

This function checks the MCG registers and determines the current MCG mode.

Returns: Current MCG mode or error code; See mcg_mode_t.

status_t CLOCK_SetFeiMode	(	mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets the MCG to FEI mode. If setting to FEI mode fails from the current mode, this function returns an error.

Parameters

dmx32	DMX32 in FEI mode.
drs	The DCO range selection.
fllStableDelay	Delay function to ensure that the FLL is stable. Passing NULL does not cause a delay.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

Note: If dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to a frequency above 32768 Hz.

status_t CLOCK_SetFeeMode	(	uint8_t	frdiv,
		mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets the MCG to FEE mode. If setting to FEE mode fails from the current mode, this function returns an error.

Parameters

frdiv	FLL reference clock divider setting, FRDIV.
dmx32	DMX32 in FEE mode.
drs	The DCO range selection.
fllStableDelay	Delay function to make sure FLL is stable. Passing NULL does not cause a delay.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_SetFbiMode	(	mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets the MCG to FBI mode. If setting to FBI mode fails from the current mode, this function returns an error.

Parameters

dmx32	DMX32 in FBI mode.
drs	The DCO range selection.
fllStableDelay	Delay function to make sure FLL is stable. If the FLL is not used in FBI mode, this parameter can be NULL. Passing NULL does not cause a delay.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

Note: If dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz.

status_t CLOCK_SetFbeMode	(	uint8_t	frdiv,
		mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets the MCG to FBE mode. If setting to FBE mode fails from the current mode, this function returns an error.

Parameters

frdiv	FLL reference clock divider setting, FRDIV.
dmx32	DMX32 in FBE mode.
drs	The DCO range selection.
fllStableDelay	Delay function to make sure FLL is stable. If the FLL is not used in FBE mode, this parameter can be NULL. Passing NULL does not cause a delay.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_SetBlpiMode ( void )

This function sets the MCG to BLPI mode. If setting to BLPI mode fails from the current mode, this function returns an error.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_SetBlpeMode ( void )

This function sets the MCG to BLPE mode. If setting to BLPE mode fails from the current mode, this function returns an error.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_SetPbeMode	(	mcg_pll_clk_select_t	pllcs,
		mcg_pll_config_t const *	config
	)

This function sets the MCG to PBE mode. If setting to PBE mode fails from the current mode, this function returns an error.

Parameters

pllcs	The PLL selection, PLLCS.
config	Pointer to the PLL configuration.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

Note

The parameter pllcs selects the PLL. For platforms with only one PLL, the parameter pllcs is kept for interface compatibility.
The parameter config is the PLL configuration structure. On some platforms, it is possible to choose the external PLL directly, which renders the configuration structure not necessary. In this case, pass in NULL. For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);

status_t CLOCK_SetPeeMode ( void )

This function sets the MCG to PEE mode.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

Note: This function only changes the CLKS to use the PLL/FLL output. If the PRDIV/VDIV are different than in the PBE mode, set them up in PBE mode and wait. When the clock is stable, switch to PEE mode.

status_t CLOCK_ExternalModeToFbeModeQuick ( void )

This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. The external clock is used as the system clock source and PLL is disabled. However, the FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEE mode to FEI mode:

* CLOCK_ExternalModeToFbeModeQuick();
* CLOCK_SetFeiMode(...);
* 

Return values

kStatus_Success	Switched successfully.
kStatus_MCG_ModeInvalid	If the current mode is not an external mode, do not call this function.

status_t CLOCK_InternalModeToFbiModeQuick ( void )

This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. The MCGIRCLK is used as the system clock source and PLL is disabled. However, FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEI mode to FEE mode:

* CLOCK_InternalModeToFbiModeQuick();
* CLOCK_SetFeeMode(...);
* 

Return values

kStatus_Success	Switched successfully.
kStatus_MCG_ModeInvalid	If the current mode is not an internal mode, do not call this function.

status_t CLOCK_BootToFeiMode	(	mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets the MCG to FEI mode from the reset mode. It can also be used to set up MCG during system boot up.

Parameters

dmx32	DMX32 in FEI mode.
drs	The DCO range selection.
fllStableDelay	Delay function to ensure that the FLL is stable.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

Note: If dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz.

status_t CLOCK_BootToFeeMode	(	mcg_oscsel_t	oscsel,
		uint8_t	frdiv,
		mcg_dmx32_t	dmx32,
		mcg_drs_t	drs,
		void(*)(void)	fllStableDelay
	)

This function sets MCG to FEE mode from the reset mode. It can also be used to set up the MCG during system boot up.

Parameters

oscsel	OSC clock select, OSCSEL.
frdiv	FLL reference clock divider setting, FRDIV.
dmx32	DMX32 in FEE mode.
drs	The DCO range selection.
fllStableDelay	Delay function to ensure that the FLL is stable.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_BootToBlpiMode	(	uint8_t	fcrdiv,
		mcg_irc_mode_t	ircs,
		uint8_t	ircEnableMode
	)

This function sets the MCG to BLPI mode from the reset mode. It can also be used to set up the MCG during system boot up.

Parameters

fcrdiv	Fast IRC divider, FCRDIV.
ircs	The internal reference clock to select, IRCS.
ircEnableMode	The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.

Return values

kStatus_MCG_SourceUsed	Could not change MCGIRCLK setting.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_BootToBlpeMode ( mcg_oscsel_t oscsel )

This function sets the MCG to BLPE mode from the reset mode. It can also be used to set up the MCG during system boot up.

Parameters

oscsel OSC clock select, MCG_C7[OSCSEL].

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_BootToPeeMode	(	mcg_oscsel_t	oscsel,
		mcg_pll_clk_select_t	pllcs,
		mcg_pll_config_t const *	config
	)

This function sets the MCG to PEE mode from reset mode. It can also be used to set up the MCG during system boot up.

Parameters

oscsel	OSC clock select, MCG_C7[OSCSEL].
pllcs	The PLL selection, PLLCS.
config	Pointer to the PLL configuration.

Return values

kStatus_MCG_ModeUnreachable	Could not switch to the target mode.
kStatus_Success	Switched to the target mode successfully.

status_t CLOCK_SetMcgConfig ( mcg_config_t const * config )

This function sets MCG to a target mode defined by the configuration structure. If switching to the target mode fails, this function chooses the correct path.

Parameters

config Pointer to the target MCG mode configuration structure.

Returns: Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.

Note: If the external clock is used in the target mode, ensure that it is enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this function.

Variable Documentation

volatile uint32_t g_xtal0Freq

The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:

* Set up the OSC0
* CLOCK_InitOsc0(...);
* Set the XTAL0 value to the clock driver.
* CLOCK_SetXtal0Freq(80000000);
* 

This is important for the multicore platforms where only one core needs to set up the OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.

volatile uint32_t g_xtal32Freq

The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.

Overview

Modules

Files

Data Structures

Macros

Enumerations

Functions

Variables

Driver version

MCG frequency functions.

MCG clock configuration.

MCG clock lock monitor functions.

OSC configuration

External clock frequency

IRCs frequency

MCG auto-trim machine.

MCG mode functions.

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation