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MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
The clock driver supports:
Modules | |
Multipurpose Clock Generator (MCG) | |
Files | |
file | fsl_clock.h |
Data Structures | |
struct | sim_clock_config_t |
SIM configuration structure for clock setting. More... | |
struct | oscer_config_t |
OSC configuration for OSCERCLK. More... | |
struct | osc_config_t |
OSC Initialization Configuration Structure. More... | |
struct | mcg_pll_config_t |
MCG PLL configuration. More... | |
struct | mcg_config_t |
MCG mode change configuration structure. More... | |
Macros | |
#define | MCG_CONFIG_CHECK_PARAM 0U |
Configures whether to check a parameter in a function. More... | |
#define | FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
Configure whether driver controls clock. More... | |
#define | MCG_INTERNAL_IRC_48M 48000000U |
IRC48M clock frequency in Hz. More... | |
#define | DMAMUX_CLOCKS |
Clock ip name array for DMAMUX. More... | |
#define | RTC_CLOCKS |
Clock ip name array for RTC. More... | |
#define | SAI_CLOCKS |
Clock ip name array for SAI. More... | |
#define | PORT_CLOCKS |
Clock ip name array for PORT. More... | |
#define | FLEXBUS_CLOCKS |
Clock ip name array for FLEXBUS. More... | |
#define | EWM_CLOCKS |
Clock ip name array for EWM. More... | |
#define | PIT_CLOCKS |
Clock ip name array for PIT. More... | |
#define | DSPI_CLOCKS |
Clock ip name array for DSPI. More... | |
#define | LPTMR_CLOCKS |
Clock ip name array for LPTMR. More... | |
#define | FTM_CLOCKS |
Clock ip name array for FTM. More... | |
#define | EDMA_CLOCKS |
Clock ip name array for EDMA. More... | |
#define | LPUART_CLOCKS |
Clock ip name array for LPUART. More... | |
#define | DAC_CLOCKS |
Clock ip name array for DAC. More... | |
#define | ADC16_CLOCKS |
Clock ip name array for ADC16. More... | |
#define | VREF_CLOCKS |
Clock ip name array for VREF. More... | |
#define | UART_CLOCKS |
Clock ip name array for UART. More... | |
#define | RNGA_CLOCKS |
Clock ip name array for RNGA. More... | |
#define | CRC_CLOCKS |
Clock ip name array for CRC. More... | |
#define | I2C_CLOCKS |
Clock ip name array for I2C. More... | |
#define | FTF_CLOCKS |
Clock ip name array for FTF. More... | |
#define | PDB_CLOCKS |
Clock ip name array for PDB. More... | |
#define | CMP_CLOCKS |
Clock ip name array for CMP. More... | |
#define | LPO_CLK_FREQ 1000U |
LPO clock frequency. | |
#define | SYS_CLK kCLOCK_CoreSysClk |
Peripherals clock source definition. More... | |
Functions | |
static void | CLOCK_EnableClock (clock_ip_name_t name) |
Enable the clock for specific IP. More... | |
static void | CLOCK_DisableClock (clock_ip_name_t name) |
Disable the clock for specific IP. More... | |
static void | CLOCK_SetLpuartClock (uint32_t src) |
Set LPUART clock source. More... | |
static void | CLOCK_SetEr32kClock (uint32_t src) |
Set ERCLK32K source. More... | |
static void | CLOCK_SetTraceClock (uint32_t src) |
Set debug trace clock source. More... | |
static void | CLOCK_SetPllFllSelClock (uint32_t src) |
Set PLLFLLSEL clock source. More... | |
static void | CLOCK_SetClkOutClock (uint32_t src) |
Set CLKOUT source. More... | |
static void | CLOCK_SetRtcClkOutClock (uint32_t src) |
Set RTC_CLKOUT source. More... | |
bool | CLOCK_EnableUsbfs0Clock (clock_usb_src_t src, uint32_t freq) |
Enable USB FS clock. More... | |
static void | CLOCK_DisableUsbfs0Clock (void) |
Disable USB FS clock. More... | |
static void | CLOCK_SetOutDiv (uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) |
System clock divider. More... | |
uint32_t | CLOCK_GetFreq (clock_name_t clockName) |
Gets the clock frequency for a specific clock name. More... | |
uint32_t | CLOCK_GetCoreSysClkFreq (void) |
Get the core clock or system clock frequency. More... | |
uint32_t | CLOCK_GetPlatClkFreq (void) |
Get the platform clock frequency. More... | |
uint32_t | CLOCK_GetBusClkFreq (void) |
Get the bus clock frequency. More... | |
uint32_t | CLOCK_GetFlexBusClkFreq (void) |
Get the flexbus clock frequency. More... | |
uint32_t | CLOCK_GetFlashClkFreq (void) |
Get the flash clock frequency. More... | |
uint32_t | CLOCK_GetPllFllSelClkFreq (void) |
Get the output clock frequency selected by SIM[PLLFLLSEL]. More... | |
uint32_t | CLOCK_GetEr32kClkFreq (void) |
Get the external reference 32K clock frequency (ERCLK32K). More... | |
uint32_t | CLOCK_GetOsc0ErClkUndivFreq (void) |
Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). More... | |
uint32_t | CLOCK_GetOsc0ErClkFreq (void) |
Get the OSC0 external reference clock frequency (OSC0ERCLK). More... | |
uint32_t | CLOCK_GetOsc0ErClkDivFreq (void) |
Get the OSC0 external reference divided clock frequency. More... | |
void | CLOCK_SetSimConfig (sim_clock_config_t const *config) |
Set the clock configure in SIM module. More... | |
static void | CLOCK_SetSimSafeDivs (void) |
Set the system clock dividers in SIM to safe value. More... | |
Variables | |
volatile uint32_t | g_xtal0Freq |
External XTAL0 (OSC0) clock frequency. More... | |
volatile uint32_t | g_xtal32Freq |
External XTAL32/EXTAL32/RTC_CLKIN clock frequency. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) |
CLOCK driver version 2.5.1. More... | |
MCG frequency functions. | |
uint32_t | CLOCK_GetOutClkFreq (void) |
Gets the MCG output clock (MCGOUTCLK) frequency. More... | |
uint32_t | CLOCK_GetFllFreq (void) |
Gets the MCG FLL clock (MCGFLLCLK) frequency. More... | |
uint32_t | CLOCK_GetInternalRefClkFreq (void) |
Gets the MCG internal reference clock (MCGIRCLK) frequency. More... | |
uint32_t | CLOCK_GetFixedFreqClkFreq (void) |
Gets the MCG fixed frequency clock (MCGFFCLK) frequency. More... | |
uint32_t | CLOCK_GetPll0Freq (void) |
Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. More... | |
MCG clock configuration. | |
static void | CLOCK_SetLowPowerEnable (bool enable) |
Enables or disables the MCG low power. More... | |
status_t | CLOCK_SetInternalRefClkConfig (uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) |
Configures the Internal Reference clock (MCGIRCLK). More... | |
status_t | CLOCK_SetExternalRefClkConfig (mcg_oscsel_t oscsel) |
Selects the MCG external reference clock. More... | |
static void | CLOCK_SetFllExtRefDiv (uint8_t frdiv) |
Set the FLL external reference clock divider value. More... | |
void | CLOCK_EnablePll0 (mcg_pll_config_t const *config) |
Enables the PLL0 in FLL mode. More... | |
static void | CLOCK_DisablePll0 (void) |
Disables the PLL0 in FLL mode. More... | |
uint32_t | CLOCK_CalcPllDiv (uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) |
Calculates the PLL divider setting for a desired output frequency. More... | |
MCG clock lock monitor functions. | |
void | CLOCK_SetOsc0MonitorMode (mcg_monitor_mode_t mode) |
Sets the OSC0 clock monitor mode. More... | |
void | CLOCK_SetRtcOscMonitorMode (mcg_monitor_mode_t mode) |
Sets the RTC OSC clock monitor mode. More... | |
void | CLOCK_SetPll0MonitorMode (mcg_monitor_mode_t mode) |
Sets the PLL0 clock monitor mode. More... | |
uint32_t | CLOCK_GetStatusFlags (void) |
Gets the MCG status flags. More... | |
void | CLOCK_ClearStatusFlags (uint32_t mask) |
Clears the MCG status flags. More... | |
OSC configuration | |
static void | OSC_SetExtRefClkConfig (OSC_Type *base, oscer_config_t const *config) |
Configures the OSC external reference clock (OSCERCLK). More... | |
static void | OSC_SetCapLoad (OSC_Type *base, uint8_t capLoad) |
Sets the capacitor load configuration for the oscillator. More... | |
void | CLOCK_InitOsc0 (osc_config_t const *config) |
Initializes the OSC0. More... | |
void | CLOCK_DeinitOsc0 (void) |
Deinitializes the OSC0. More... | |
External clock frequency | |
static void | CLOCK_SetXtal0Freq (uint32_t freq) |
Sets the XTAL0 frequency based on board settings. More... | |
static void | CLOCK_SetXtal32Freq (uint32_t freq) |
Sets the XTAL32/RTC_CLKIN frequency based on board settings. More... | |
IRCs frequency | |
void | CLOCK_SetSlowIrcFreq (uint32_t freq) |
Set the Slow IRC frequency based on the trimmed value. More... | |
void | CLOCK_SetFastIrcFreq (uint32_t freq) |
Set the Fast IRC frequency based on the trimmed value. More... | |
MCG auto-trim machine. | |
status_t | CLOCK_TrimInternalRefClk (uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) |
Auto trims the internal reference clock. More... | |
MCG mode functions. | |
mcg_mode_t | CLOCK_GetMode (void) |
Gets the current MCG mode. More... | |
status_t | CLOCK_SetFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FEI mode. More... | |
status_t | CLOCK_SetFeeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FEE mode. More... | |
status_t | CLOCK_SetFbiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FBI mode. More... | |
status_t | CLOCK_SetFbeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FBE mode. More... | |
status_t | CLOCK_SetBlpiMode (void) |
Sets the MCG to BLPI mode. More... | |
status_t | CLOCK_SetBlpeMode (void) |
Sets the MCG to BLPE mode. More... | |
status_t | CLOCK_SetPbeMode (mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
Sets the MCG to PBE mode. More... | |
status_t | CLOCK_SetPeeMode (void) |
Sets the MCG to PEE mode. More... | |
status_t | CLOCK_ExternalModeToFbeModeQuick (void) |
Switches the MCG to FBE mode from the external mode. More... | |
status_t | CLOCK_InternalModeToFbiModeQuick (void) |
Switches the MCG to FBI mode from internal modes. More... | |
status_t | CLOCK_BootToFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FEI mode during system boot up. More... | |
status_t | CLOCK_BootToFeeMode (mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
Sets the MCG to FEE mode during system bootup. More... | |
status_t | CLOCK_BootToBlpiMode (uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) |
Sets the MCG to BLPI mode during system boot up. More... | |
status_t | CLOCK_BootToBlpeMode (mcg_oscsel_t oscsel) |
Sets the MCG to BLPE mode during system boot up. More... | |
status_t | CLOCK_BootToPeeMode (mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
Sets the MCG to PEE mode during system boot up. More... | |
status_t | CLOCK_SetMcgConfig (mcg_config_t const *config) |
Sets the MCG to a target mode. More... | |
struct sim_clock_config_t |
struct oscer_config_t |
Data Fields | |
uint8_t | enableMode |
OSCERCLK enable mode. More... | |
uint8_t | erclkDiv |
Divider for OSCERCLK. More... | |
uint8_t oscer_config_t::enableMode |
OR'ed value of _oscer_enable_mode.
uint8_t oscer_config_t::erclkDiv |
struct osc_config_t |
Defines the configuration data structure to initialize the OSC. When porting to a new board, set the following members according to the board setting:
Data Fields | |
uint32_t | freq |
External clock frequency. More... | |
uint8_t | capLoad |
Capacitor load setting. More... | |
osc_mode_t | workMode |
OSC work mode setting. More... | |
oscer_config_t | oscerConfig |
Configuration for OSCERCLK. More... | |
uint32_t osc_config_t::freq |
uint8_t osc_config_t::capLoad |
osc_mode_t osc_config_t::workMode |
oscer_config_t osc_config_t::oscerConfig |
struct mcg_pll_config_t |
Data Fields | |
uint8_t | enableMode |
Enable mode. More... | |
uint8_t | prdiv |
Reference divider PRDIV. More... | |
uint8_t | vdiv |
VCO divider VDIV. More... | |
uint8_t mcg_pll_config_t::enableMode |
OR'ed value of enumeration _mcg_pll_enable_mode.
uint8_t mcg_pll_config_t::prdiv |
uint8_t mcg_pll_config_t::vdiv |
struct mcg_config_t |
When porting to a new board, set the following members according to the board setting:
Data Fields | |
mcg_mode_t | mcgMode |
MCG mode. More... | |
uint8_t | irclkEnableMode |
MCGIRCLK enable mode. More... | |
mcg_irc_mode_t | ircs |
Source, MCG_C2[IRCS]. More... | |
uint8_t | fcrdiv |
Divider, MCG_SC[FCRDIV]. More... | |
uint8_t | frdiv |
Divider MCG_C1[FRDIV]. More... | |
mcg_drs_t | drs |
DCO range MCG_C4[DRST_DRS]. More... | |
mcg_dmx32_t | dmx32 |
MCG_C4[DMX32]. More... | |
mcg_oscsel_t | oscsel |
OSC select MCG_C7[OSCSEL]. More... | |
mcg_pll_config_t | pll0Config |
MCGPLL0CLK configuration. More... | |
mcg_mode_t mcg_config_t::mcgMode |
uint8_t mcg_config_t::irclkEnableMode |
mcg_irc_mode_t mcg_config_t::ircs |
uint8_t mcg_config_t::fcrdiv |
uint8_t mcg_config_t::frdiv |
mcg_drs_t mcg_config_t::drs |
mcg_dmx32_t mcg_config_t::dmx32 |
mcg_oscsel_t mcg_config_t::oscsel |
mcg_pll_config_t mcg_config_t::pll0Config |
#define MCG_CONFIG_CHECK_PARAM 0U |
Some MCG settings must be changed with conditions, for example:
MCG functions check the parameter and MCG status before setting, if not allowed to change, the functions return error. The parameter checking increases code size, if code size is a critical requirement, change MCG_CONFIG_CHECK_PARAM to 0 to disable parameter checking.
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) |
#define MCG_INTERNAL_IRC_48M 48000000U |
#define DMAMUX_CLOCKS |
#define RTC_CLOCKS |
#define SAI_CLOCKS |
#define PORT_CLOCKS |
#define FLEXBUS_CLOCKS |
#define EWM_CLOCKS |
#define PIT_CLOCKS |
#define DSPI_CLOCKS |
#define LPTMR_CLOCKS |
#define FTM_CLOCKS |
#define EDMA_CLOCKS |
#define LPUART_CLOCKS |
#define DAC_CLOCKS |
#define ADC16_CLOCKS |
#define VREF_CLOCKS |
#define UART_CLOCKS |
#define RNGA_CLOCKS |
#define CRC_CLOCKS |
#define I2C_CLOCKS |
#define FTF_CLOCKS |
#define PDB_CLOCKS |
#define CMP_CLOCKS |
#define SYS_CLK kCLOCK_CoreSysClk |
enum clock_name_t |
enum clock_usb_src_t |
enum clock_ip_name_t |
enum osc_mode_t |
enum _osc_cap_load |
enum _oscer_enable_mode |
enum mcg_fll_src_t |
enum mcg_irc_mode_t |
enum mcg_dmx32_t |
enum mcg_drs_t |
enum mcg_pll_ref_src_t |
enum mcg_clkout_src_t |
enum mcg_atm_select_t |
enum mcg_oscsel_t |
enum mcg_pll_clk_select_t |
enum mcg_monitor_mode_t |
anonymous enum |
Enumeration _mcg_status
anonymous enum |
anonymous enum |
anonymous enum |
Enumeration _mcg_pll_enable_mode
enum mcg_mode_t |
|
inlinestatic |
name | Which clock to enable, see clock_ip_name_t. |
|
inlinestatic |
name | Which clock to disable, see clock_ip_name_t. |
|
inlinestatic |
src | The value to set LPUART clock source. |
|
inlinestatic |
src | The value to set ERCLK32K clock source. |
|
inlinestatic |
src | The value to set debug trace clock source. |
|
inlinestatic |
src | The value to set PLLFLLSEL clock source. |
|
inlinestatic |
src | The value to set CLKOUT source. |
|
inlinestatic |
src | The value to set RTC_CLKOUT source. |
bool CLOCK_EnableUsbfs0Clock | ( | clock_usb_src_t | src, |
uint32_t | freq | ||
) |
src | USB FS clock source. |
freq | The frequency specified by src. |
true | The clock is set successfully. |
false | The clock source is invalid to get proper USB FS clock. |
|
inlinestatic |
Disable USB FS clock.
|
inlinestatic |
Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
outdiv1 | Clock 1 output divider value. |
outdiv2 | Clock 2 output divider value. |
outdiv3 | Clock 3 output divider value. |
outdiv4 | Clock 4 output divider value. |
uint32_t CLOCK_GetFreq | ( | clock_name_t | clockName | ) |
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t. The MCG must be properly configured before using this function.
clockName | Clock names defined in clock_name_t |
uint32_t CLOCK_GetCoreSysClkFreq | ( | void | ) |
uint32_t CLOCK_GetPlatClkFreq | ( | void | ) |
uint32_t CLOCK_GetBusClkFreq | ( | void | ) |
uint32_t CLOCK_GetFlexBusClkFreq | ( | void | ) |
uint32_t CLOCK_GetFlashClkFreq | ( | void | ) |
uint32_t CLOCK_GetPllFllSelClkFreq | ( | void | ) |
uint32_t CLOCK_GetEr32kClkFreq | ( | void | ) |
uint32_t CLOCK_GetOsc0ErClkUndivFreq | ( | void | ) |
uint32_t CLOCK_GetOsc0ErClkFreq | ( | void | ) |
uint32_t CLOCK_GetOsc0ErClkDivFreq | ( | void | ) |
void CLOCK_SetSimConfig | ( | sim_clock_config_t const * | config | ) |
This function sets system layer clock settings in SIM module.
config | Pointer to the configure structure. |
|
inlinestatic |
The system level clocks (core clock, bus clock, flexbus clock and flash clock) must be in allowed ranges. During MCG clock mode switch, the MCG output clock changes then the system level clocks may be out of range. This function could be used before MCG mode change, to make sure system level clocks are in allowed range.
uint32_t CLOCK_GetOutClkFreq | ( | void | ) |
This function gets the MCG output clock frequency in Hz based on the current MCG register value.
uint32_t CLOCK_GetFllFreq | ( | void | ) |
This function gets the MCG FLL clock frequency in Hz based on the current MCG register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and disabled in low power state in other modes.
uint32_t CLOCK_GetInternalRefClkFreq | ( | void | ) |
This function gets the MCG internal reference clock frequency in Hz based on the current MCG register value.
uint32_t CLOCK_GetFixedFreqClkFreq | ( | void | ) |
This function gets the MCG fixed frequency clock frequency in Hz based on the current MCG register value.
uint32_t CLOCK_GetPll0Freq | ( | void | ) |
This function gets the MCG PLL0 clock frequency in Hz based on the current MCG register value.
|
inlinestatic |
Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and PBI modes, enabling low power sets the MCG to BLPI mode. When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
enable | True to enable MCG low power, false to disable MCG low power. |
status_t CLOCK_SetInternalRefClkConfig | ( | uint8_t | enableMode, |
mcg_irc_mode_t | ircs, | ||
uint8_t | fcrdiv | ||
) |
This function sets the MCGIRCLK
base on parameters. It also selects the IRC source. If the fast IRC is used, this function sets the fast IRC divider. This function also sets whether the MCGIRCLK
is enabled in stop mode. Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, using the function in these modes it is not allowed.
enableMode | MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode. |
ircs | MCGIRCLK clock source, choose fast or slow. |
fcrdiv | Fast IRC divider setting (FCRDIV ). |
kStatus_MCG_SourceUsed | Because the internal reference clock is used as a clock source, the configuration should not be changed. Otherwise, a glitch occurs. |
kStatus_Success | MCGIRCLK configuration finished successfully. |
status_t CLOCK_SetExternalRefClkConfig | ( | mcg_oscsel_t | oscsel | ) |
Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], and waits for the clock source to be stable. Because the external reference clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
oscsel | MCG external reference clock source, MCG_C7[OSCSEL]. |
kStatus_MCG_SourceUsed | Because the external reference clock is used as a clock source, the configuration should not be changed. Otherwise, a glitch occurs. |
kStatus_Success | External reference clock set successfully. |
|
inlinestatic |
Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
frdiv | The FLL external reference clock divider value, MCG_C1[FRDIV]. |
void CLOCK_EnablePll0 | ( | mcg_pll_config_t const * | config | ) |
This function sets us the PLL0 in FLL mode and reconfigures the PLL0. Ensure that the PLL reference clock is enabled before calling this function and that the PLL0 is not used as a clock source. The function CLOCK_CalcPllDiv gets the correct PLL divider values.
config | Pointer to the configuration structure. |
|
inlinestatic |
This function disables the PLL0 in FLL mode. It should be used together with the CLOCK_EnablePll0.
uint32_t CLOCK_CalcPllDiv | ( | uint32_t | refFreq, |
uint32_t | desireFreq, | ||
uint8_t * | prdiv, | ||
uint8_t * | vdiv | ||
) |
This function calculates the correct reference clock divider (PRDIV
) and VCO divider (VDIV
) to generate a desired PLL output frequency. It returns the closest frequency match with the corresponding PRDIV/VDIV
returned from parameters. If a desired frequency is not valid, this function returns 0.
refFreq | PLL reference clock frequency. |
desireFreq | Desired PLL output frequency. |
prdiv | PRDIV value to generate desired PLL frequency. |
vdiv | VDIV value to generate desired PLL frequency. |
void CLOCK_SetOsc0MonitorMode | ( | mcg_monitor_mode_t | mode | ) |
This function sets the OSC0 clock monitor mode. See mcg_monitor_mode_t for details.
mode | Monitor mode to set. |
void CLOCK_SetRtcOscMonitorMode | ( | mcg_monitor_mode_t | mode | ) |
This function sets the RTC OSC clock monitor mode. See mcg_monitor_mode_t for details.
mode | Monitor mode to set. |
void CLOCK_SetPll0MonitorMode | ( | mcg_monitor_mode_t | mode | ) |
This function sets the PLL0 clock monitor mode. See mcg_monitor_mode_t for details.
mode | Monitor mode to set. |
uint32_t CLOCK_GetStatusFlags | ( | void | ) |
This function gets the MCG clock status flags. All status flags are returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To check a specific flag, compare the return value with the flag.
Example:
void CLOCK_ClearStatusFlags | ( | uint32_t | mask | ) |
This function clears the MCG clock lock lost status. The parameter is a logical OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
Example:
mask | The status flags to clear. This is a logical OR of members of the enumeration _mcg_status_flags_t. |
|
inlinestatic |
This function configures the OSC external reference clock (OSCERCLK). This is an example to enable the OSCERCLK in normal and stop modes and also set the output divider to 1:
base | OSC peripheral address. |
config | Pointer to the configuration structure. |
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inlinestatic |
This function sets the specified capacitors configuration for the oscillator. This should be done in the early system level initialization function call based on the system configuration.
base | OSC peripheral address. |
capLoad | OR'ed value for the capacitor load option, see _osc_cap_load. |
Example:
void CLOCK_InitOsc0 | ( | osc_config_t const * | config | ) |
This function initializes the OSC0 according to the board configuration.
config | Pointer to the OSC0 configuration structure. |
void CLOCK_DeinitOsc0 | ( | void | ) |
This function deinitializes the OSC0.
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inlinestatic |
freq | The XTAL0/EXTAL0 input clock frequency in Hz. |
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inlinestatic |
freq | The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. |
void CLOCK_SetSlowIrcFreq | ( | uint32_t | freq | ) |
freq | The Slow IRC frequency input clock frequency in Hz. |
void CLOCK_SetFastIrcFreq | ( | uint32_t | freq | ) |
freq | The Fast IRC frequency input clock frequency in Hz. |
status_t CLOCK_TrimInternalRefClk | ( | uint32_t | extFreq, |
uint32_t | desireFreq, | ||
uint32_t * | actualFreq, | ||
mcg_atm_select_t | atms | ||
) |
This function trims the internal reference clock by using the external clock. If successful, it returns the kStatus_Success and the frequency after trimming is received in the parameter actualFreq
. If an error occurs, the error code is returned.
extFreq | External clock frequency, which should be a bus clock. |
desireFreq | Frequency to trim to. |
actualFreq | Actual frequency after trimming. |
atms | Trim fast or slow internal reference clock. |
kStatus_Success | ATM success. |
kStatus_MCG_AtmBusClockInvalid | The bus clock is not in allowed range for the ATM. |
kStatus_MCG_AtmDesiredFreqInvalid | MCGIRCLK could not be trimmed to the desired frequency. |
kStatus_MCG_AtmIrcUsed | Could not trim because MCGIRCLK is used as a bus clock source. |
kStatus_MCG_AtmHardwareFail | Hardware fails while trimming. |
mcg_mode_t CLOCK_GetMode | ( | void | ) |
This function checks the MCG registers and determines the current MCG mode.
status_t CLOCK_SetFeiMode | ( | mcg_dmx32_t | dmx32, |
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets the MCG to FEI mode. If setting to FEI mode fails from the current mode, this function returns an error.
dmx32 | DMX32 in FEI mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to ensure that the FLL is stable. Passing NULL does not cause a delay. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
dmx32
is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to a frequency above 32768 Hz. status_t CLOCK_SetFeeMode | ( | uint8_t | frdiv, |
mcg_dmx32_t | dmx32, | ||
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets the MCG to FEE mode. If setting to FEE mode fails from the current mode, this function returns an error.
frdiv | FLL reference clock divider setting, FRDIV. |
dmx32 | DMX32 in FEE mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to make sure FLL is stable. Passing NULL does not cause a delay. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_SetFbiMode | ( | mcg_dmx32_t | dmx32, |
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets the MCG to FBI mode. If setting to FBI mode fails from the current mode, this function returns an error.
dmx32 | DMX32 in FBI mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to make sure FLL is stable. If the FLL is not used in FBI mode, this parameter can be NULL. Passing NULL does not cause a delay. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
dmx32
is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz. status_t CLOCK_SetFbeMode | ( | uint8_t | frdiv, |
mcg_dmx32_t | dmx32, | ||
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets the MCG to FBE mode. If setting to FBE mode fails from the current mode, this function returns an error.
frdiv | FLL reference clock divider setting, FRDIV. |
dmx32 | DMX32 in FBE mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to make sure FLL is stable. If the FLL is not used in FBE mode, this parameter can be NULL. Passing NULL does not cause a delay. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_SetBlpiMode | ( | void | ) |
This function sets the MCG to BLPI mode. If setting to BLPI mode fails from the current mode, this function returns an error.
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_SetBlpeMode | ( | void | ) |
This function sets the MCG to BLPE mode. If setting to BLPE mode fails from the current mode, this function returns an error.
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_SetPbeMode | ( | mcg_pll_clk_select_t | pllcs, |
mcg_pll_config_t const * | config | ||
) |
This function sets the MCG to PBE mode. If setting to PBE mode fails from the current mode, this function returns an error.
pllcs | The PLL selection, PLLCS. |
config | Pointer to the PLL configuration. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
pllcs
selects the PLL. For platforms with only one PLL, the parameter pllcs is kept for interface compatibility.config
is the PLL configuration structure. On some platforms, it is possible to choose the external PLL directly, which renders the configuration structure not necessary. In this case, pass in NULL. For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); status_t CLOCK_SetPeeMode | ( | void | ) |
This function sets the MCG to PEE mode.
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_ExternalModeToFbeModeQuick | ( | void | ) |
This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. The external clock is used as the system clock source and PLL is disabled. However, the FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEE mode to FEI mode:
kStatus_Success | Switched successfully. |
kStatus_MCG_ModeInvalid | If the current mode is not an external mode, do not call this function. |
status_t CLOCK_InternalModeToFbiModeQuick | ( | void | ) |
This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. The MCGIRCLK is used as the system clock source and PLL is disabled. However, FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEI mode to FEE mode:
kStatus_Success | Switched successfully. |
kStatus_MCG_ModeInvalid | If the current mode is not an internal mode, do not call this function. |
status_t CLOCK_BootToFeiMode | ( | mcg_dmx32_t | dmx32, |
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets the MCG to FEI mode from the reset mode. It can also be used to set up MCG during system boot up.
dmx32 | DMX32 in FEI mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to ensure that the FLL is stable. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
dmx32
is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz. status_t CLOCK_BootToFeeMode | ( | mcg_oscsel_t | oscsel, |
uint8_t | frdiv, | ||
mcg_dmx32_t | dmx32, | ||
mcg_drs_t | drs, | ||
void(*)(void) | fllStableDelay | ||
) |
This function sets MCG to FEE mode from the reset mode. It can also be used to set up the MCG during system boot up.
oscsel | OSC clock select, OSCSEL. |
frdiv | FLL reference clock divider setting, FRDIV. |
dmx32 | DMX32 in FEE mode. |
drs | The DCO range selection. |
fllStableDelay | Delay function to ensure that the FLL is stable. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_BootToBlpiMode | ( | uint8_t | fcrdiv, |
mcg_irc_mode_t | ircs, | ||
uint8_t | ircEnableMode | ||
) |
This function sets the MCG to BLPI mode from the reset mode. It can also be used to set up the MCG during system boot up.
fcrdiv | Fast IRC divider, FCRDIV. |
ircs | The internal reference clock to select, IRCS. |
ircEnableMode | The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode. |
kStatus_MCG_SourceUsed | Could not change MCGIRCLK setting. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_BootToBlpeMode | ( | mcg_oscsel_t | oscsel | ) |
This function sets the MCG to BLPE mode from the reset mode. It can also be used to set up the MCG during system boot up.
oscsel | OSC clock select, MCG_C7[OSCSEL]. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_BootToPeeMode | ( | mcg_oscsel_t | oscsel, |
mcg_pll_clk_select_t | pllcs, | ||
mcg_pll_config_t const * | config | ||
) |
This function sets the MCG to PEE mode from reset mode. It can also be used to set up the MCG during system boot up.
oscsel | OSC clock select, MCG_C7[OSCSEL]. |
pllcs | The PLL selection, PLLCS. |
config | Pointer to the PLL configuration. |
kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
kStatus_Success | Switched to the target mode successfully. |
status_t CLOCK_SetMcgConfig | ( | mcg_config_t const * | config | ) |
This function sets MCG to a target mode defined by the configuration structure. If switching to the target mode fails, this function chooses the correct path.
config | Pointer to the target MCG mode configuration structure. |
volatile uint32_t g_xtal0Freq |
The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:
This is important for the multicore platforms where only one core needs to set up the OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.
volatile uint32_t g_xtal32Freq |
The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.
This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.