Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Modules
	System Clock Generator (SCG)

Files
file	fsl_clock.h

Data Structures
struct	scg_sys_clk_config_t
	SCG system clock configuration. More...

struct	scg_sirc_config_t
	SCG slow IRC clock configuration. More...

struct	scg_firc_trim_config_t
	SCG fast IRC clock trim configuration. More...

struct	scg_firc_config_t
	SCG fast IRC clock configuration. More...

struct	scg_lpfll_trim_config_t
	SCG LPFLL clock trim configuration. More...

struct	scg_lpfll_config_t
	SCG low power FLL configuration. More...

struct	scg_rosc_config_t
	SCG RTC OSC configuration. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	MAX_CLOCKS
	Clock ip name array for MAX. More...

#define	EDMA_CLOCKS
	Clock ip name array for EDMA. More...

#define	FLEXBUS_CLOCKS
	Clock ip name array for FLEXBUS. More...

#define	FSL_CLOCK_XRDC_GATE_COUNT (5U)
	XRDC clock gate number. More...

#define	XRDC_CLOCKS
	Clock ip name array for XRDC. More...

#define	SEMA42_CLOCKS
	Clock ip name array for SEMA42. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX. More...

#define	MU_CLOCKS
	Clock ip name array for MU. More...

#define	CRC_CLOCKS
	Clock ip name array for CRC. More...

#define	LPIT_CLOCKS
	Clock ip name array for LPIT. More...

#define	TPM_CLOCKS
	Clock ip name array for TPM. More...

#define	TRNG_CLOCKS
	Clock ip name array for TRNG. More...

#define	EMVSIM_CLOCKS
	Clock ip name array for SMVSIM. More...

#define	EWM_CLOCKS
	Clock ip name array for EWM. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C0. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	USDHC_CLOCKS
	Clock ip name array for SDHC. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	USB_CLOCKS
	Clock ip name array for USB. More...

#define	PORT_CLOCKS
	Clock ip name array for PORT. More...

#define	LPADC_CLOCKS
	Clock ip name array for LPADC. More...

#define	LPDAC_CLOCKS
	Clock ip name array for DAC. More...

#define	INTMUX_CLOCKS
	Clock ip name array for INTMUX. More...

#define	EXT_CLOCKS
	Clock ip name array for EXT. More...

#define	VREF_CLOCKS
	Clock ip name array for VREF. More...

#define	FGPIO_CLOCKS
	Clock ip name array for FGPIO. More...

#define	MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. More...

Enumerations
enum	clock_name_t { kCLOCK_CoreSysClk, kCLOCK_SlowClk, kCLOCK_PlatClk, kCLOCK_SysClk, kCLOCK_BusClk, kCLOCK_ExtClk, kCLOCK_ScgSysLpFllAsyncDiv1Clk, kCLOCK_ScgSysLpFllAsyncDiv2Clk, kCLOCK_ScgSysLpFllAsyncDiv3Clk, kCLOCK_ScgSircAsyncDiv1Clk, kCLOCK_ScgSircAsyncDiv2Clk, kCLOCK_ScgSircAsyncDiv3Clk, kCLOCK_ScgFircAsyncDiv1Clk, kCLOCK_ScgFircAsyncDiv2Clk, kCLOCK_ScgFircAsyncDiv3Clk, kCLOCK_ScgSircClk, kCLOCK_ScgFircClk, kCLOCK_RtcOscClk, kCLOCK_ScgLpFllClk, kCLOCK_LpoClk, kCLOCK_Osc32kClk }
	Clock name used to get clock frequency. More...

enum	clock_ip_src_t { kCLOCK_IpSrcNoneOrExt = 0U, kCLOCK_IpSrcSircAsync = 2U, kCLOCK_IpSrcFircAsync = 3U, kCLOCK_IpSrcLpFllAsync = 6U }
	Clock source for peripherals that support various clock selections. More...

enum	clock_usb_src_t { kCLOCK_UsbSrcIrc48M = 1, kCLOCK_UsbSrcUnused = 0xFFFFFFFU }
	USB clock source definition. More...

enum	{ kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) }
	SCG status return codes. More...

enum	scg_sys_clk_t { kSCG_SysClkSlow, kSCG_SysClkBus, kSCG_SysClkExt, kSCG_SysClkCore }
	SCG system clock type. More...

enum	scg_sys_clk_src_t { kSCG_SysClkSrcSirc = 2U, kSCG_SysClkSrcFirc = 3U, kSCG_SysClkSrcRosc = 4U, kSCG_SysClkSrcLpFll = 5U }
	SCG system clock source. More...

enum	scg_sys_clk_div_t { kSCG_SysClkDivBy1 = 0U, kSCG_SysClkDivBy2 = 1U, kSCG_SysClkDivBy3 = 2U, kSCG_SysClkDivBy4 = 3U, kSCG_SysClkDivBy5 = 4U, kSCG_SysClkDivBy6 = 5U, kSCG_SysClkDivBy7 = 6U, kSCG_SysClkDivBy8 = 7U, kSCG_SysClkDivBy9 = 8U, kSCG_SysClkDivBy10 = 9U, kSCG_SysClkDivBy11 = 10U, kSCG_SysClkDivBy12 = 11U, kSCG_SysClkDivBy13 = 12U, kSCG_SysClkDivBy14 = 13U, kSCG_SysClkDivBy15 = 14U, kSCG_SysClkDivBy16 = 15U }
	SCG system clock divider value. More...

enum	clock_clkout_src_t { kClockClkoutSelScgExt = 0U, kClockClkoutSelSirc = 2U, kClockClkoutSelFirc = 3U, kClockClkoutSelScgRtcOsc = 4U, kClockClkoutSelLpFll = 5U }
	SCG clock out configuration (CLKOUTSEL). More...

enum	scg_async_clk_t { kSCG_AsyncDiv1Clk, kSCG_AsyncDiv2Clk, kSCG_AsyncDiv3Clk }
	SCG asynchronous clock type. More...

enum	scg_async_clk_div_t { kSCG_AsyncClkDisable = 0U, kSCG_AsyncClkDivBy1 = 1U, kSCG_AsyncClkDivBy2 = 2U, kSCG_AsyncClkDivBy4 = 3U, kSCG_AsyncClkDivBy8 = 4U, kSCG_AsyncClkDivBy16 = 5U, kSCG_AsyncClkDivBy32 = 6U, kSCG_AsyncClkDivBy64 = 7U }
	SCG asynchronous clock divider value. More...

enum	scg_sirc_range_t { kSCG_SircRangeLow, kSCG_SircRangeHigh }
	SCG slow IRC clock frequency range. More...

enum	_scg_sirc_enable_mode { kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK, kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK, kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK }
	SIRC enable mode. More...

enum	scg_firc_trim_mode_t { kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK \| SCG_FIRCCSR_FIRCTRUP_MASK }
	SCG fast IRC trim mode. More...

enum	scg_firc_trim_div_t { kSCG_FircTrimDivBy1, kSCG_FircTrimDivBy128, kSCG_FircTrimDivBy256, kSCG_FircTrimDivBy512, kSCG_FircTrimDivBy1024, kSCG_FircTrimDivBy2048 }
	SCG fast IRC trim predivided value for system OSC. More...

enum	scg_firc_trim_src_t { kSCG_FircTrimSrcSysOsc = 2U, kSCG_FircTrimSrcRtcOsc = 3U }
	SCG fast IRC trim source. More...

enum	scg_firc_range_t { kSCG_FircRange48M, kSCG_FircRange52M, kSCG_FircRange56M, kSCG_FircRange60M }
	SCG fast IRC clock frequency range. More...

enum	_scg_firc_enable_mode { kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK, kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK, kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK, kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK }
	FIRC enable mode. More...

enum	_scg_lpfll_enable_mode { kSCG_LpFllEnable = SCG_LPFLLCSR_LPFLLEN_MASK }
	LPFLL enable mode. More...

enum	scg_lpfll_range_t { kSCG_LpFllRange48M, kSCG_LpFllRange72M, kSCG_LpFllRange96M, kSCG_LpFllRange120M }
	SCG LPFLL clock frequency range. More...

enum	scg_lpfll_trim_mode_t { kSCG_LpFllTrimNonUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK, kSCG_LpFllTrimUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK \| SCG_LPFLLCSR_LPFLLTRUP_MASK }
	SCG LPFLL trim mode. More...

enum	scg_lpfll_trim_src_t { kSCG_LpFllTrimSrcSirc = 0U, kSCG_LpFllTrimSrcFirc = 1U, kSCG_LpFllTrimSrcSysOsc = 2U, kSCG_LpFllTrimSrcRtcOsc = 3U }
	SCG LPFLL trim source. More...

enum	scg_lpfll_lock_mode_t { kSCG_LpFllLock1Lsb = 0U, kSCG_LpFllLock2Lsb = 1U }
	SCG LPFLL lock mode. More...

enum	scg_rosc_monitor_mode_t { kSCG_rtcOscMonitorDisable = 0U, kSCG_rtcOscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, kSCG_rtcOscMonitorReset }
	SCG RTC OSC monitor mode. More...

Functions
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

static bool	CLOCK_IsEnabledByOtherCore (clock_ip_name_t name)
	Check whether the clock is already enabled and configured by any other core. More...

static void	CLOCK_SetIpSrc (clock_ip_name_t name, clock_ip_src_t src)
	Set the clock source for specific IP module. More...

static void	CLOCK_SetIpSrcDiv (clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue)
	Set the clock source and divider for specific IP module. More...

uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name. More...

uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Get the core clock or system clock frequency. More...

uint32_t	CLOCK_GetPlatClkFreq (void)
	Get the platform clock frequency. More...

uint32_t	CLOCK_GetBusClkFreq (void)
	Get the bus clock frequency. More...

uint32_t	CLOCK_GetFlashClkFreq (void)
	Get the flash clock frequency. More...

uint32_t	CLOCK_GetOsc32kClkFreq (void)
	Get the OSC 32K clock frequency (OSC32KCLK). More...

uint32_t	CLOCK_GetExtClkFreq (void)
	Get the external clock frequency (EXTCLK). More...

static uint32_t	CLOCK_GetLpoClkFreq (void)
	Get the LPO clock frequency. More...

uint32_t	CLOCK_GetIpFreq (clock_ip_name_t name)
	Gets the functional clock frequency for a specific IP module. More...

static void	CLOCK_EnableRtcOsc (bool enable)
	Enable the RTC Oscillator. More...

bool	CLOCK_EnableUsbfs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB FS clock. More...

static void	CLOCK_DisableUsbfs0Clock (void)
	Disable USB FS clock. More...

uint32_t	CLOCK_GetRtcOscFreq (void)
	Gets the SCG RTC OSC clock frequency. More...

static bool	CLOCK_IsRtcOscErr (void)
	Checks whether the RTC OSC clock error occurs. More...

static void	CLOCK_ClearRtcOscErr (void)
	Clears the RTC OSC clock error.

static void	CLOCK_SetRtcOscMonitorMode (scg_rosc_monitor_mode_t mode)
	Sets the RTC OSC monitor mode. More...

static bool	CLOCK_IsRtcOscValid (void)
	Checks whether the RTC OSC clock is valid. More...

Variables
volatile uint32_t	g_xtal0Freq
	External XTAL0 (OSC0/SYSOSC) clock frequency. More...

volatile uint32_t	g_xtal32Freq
	External XTAL32/EXTAL32 clock frequency. More...

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
	CLOCK driver version 2.2.1. More...

MCU System Clock.
uint32_t	CLOCK_GetSysClkFreq (scg_sys_clk_t type)
	Gets the SCG system clock frequency. More...

static void	CLOCK_SetVlprModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for VLPR mode. More...

static void	CLOCK_SetRunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for RUN mode. More...

static void	CLOCK_SetHsrunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for HSRUN mode. More...

static void	CLOCK_GetCurSysClkConfig (scg_sys_clk_config_t *config)
	Gets the system clock configuration in the current power mode. More...

static void	CLOCK_SetClkOutSel (clock_clkout_src_t setting)
	Sets the clock out selection. More...

SCG Slow IRC Clock.
status_t	CLOCK_InitSirc (const scg_sirc_config_t *config)
	Initializes the SCG slow IRC clock. More...

status_t	CLOCK_DeinitSirc (void)
	De-initializes the SCG slow IRC. More...

static void	CLOCK_SetSircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetSircFreq (void)
	Gets the SCG SIRC clock frequency. More...

uint32_t	CLOCK_GetSircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the SIRC. More...

static bool	CLOCK_IsSircValid (void)
	Checks whether the SIRC clock is valid. More...

SCG Fast IRC Clock.
status_t	CLOCK_InitFirc (const scg_firc_config_t *config)
	Initializes the SCG fast IRC clock. More...

status_t	CLOCK_DeinitFirc (void)
	De-initializes the SCG fast IRC. More...

static void	CLOCK_SetFircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider. More...

uint32_t	CLOCK_GetFircFreq (void)
	Gets the SCG FIRC clock frequency. More...

uint32_t	CLOCK_GetFircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the FIRC. More...

static bool	CLOCK_IsFircErr (void)
	Checks whether the FIRC clock error occurs. More...

static void	CLOCK_ClearFircErr (void)
	Clears the FIRC clock error.

static bool	CLOCK_IsFircValid (void)
	Checks whether the FIRC clock is valid. More...

Data Structure Documentation

struct scg_sys_clk_config_t

Data Fields
uint32_t	divSlow: 4
	Slow clock divider, see scg_sys_clk_div_t. More...

uint32_t	divBus: 4
	Bus clock divider, see scg_sys_clk_div_t. More...

uint32_t	divExt: 4
	External clock divider, see scg_sys_clk_div_t. More...

uint32_t	__pad0__: 4
	Reserved. More...

uint32_t	divCore: 4
	Core clock divider, see scg_sys_clk_div_t. More...

uint32_t	__pad1__: 4
	Reserved. More...

uint32_t	src: 4
	System clock source, see scg_sys_clk_src_t. More...

uint32_t	__pad2__: 4
	reserved. More...

Field Documentation

uint32_t scg_sys_clk_config_t::divSlow

uint32_t scg_sys_clk_config_t::divBus

uint32_t scg_sys_clk_config_t::divExt

uint32_t scg_sys_clk_config_t::__pad0__

uint32_t scg_sys_clk_config_t::divCore

uint32_t scg_sys_clk_config_t::__pad1__

uint32_t scg_sys_clk_config_t::src

uint32_t scg_sys_clk_config_t::__pad2__

struct scg_sirc_config_t

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _scg_sirc_enable_mode. More...

scg_async_clk_div_t	div1
	SIRCDIV1 value. More...

scg_async_clk_div_t	div2
	SIRCDIV2 value. More...

scg_async_clk_div_t	div3
	SIRCDIV3 value. More...

scg_sirc_range_t	range
	Slow IRC frequency range. More...

Field Documentation

uint32_t scg_sirc_config_t::enableMode

scg_async_clk_div_t scg_sirc_config_t::div1

scg_async_clk_div_t scg_sirc_config_t::div2

scg_async_clk_div_t scg_sirc_config_t::div3

scg_sirc_range_t scg_sirc_config_t::range

struct scg_firc_trim_config_t

Data Fields
scg_firc_trim_mode_t	trimMode
	FIRC trim mode. More...

scg_firc_trim_src_t	trimSrc
	Trim source. More...

uint8_t	trimCoar
	Trim coarse value; Irrelevant if trimMode is kSCG_FircTrimUpdate. More...

uint8_t	trimFine
	Trim fine value; Irrelevant if trimMode is kSCG_FircTrimUpdate. More...

Field Documentation

scg_firc_trim_mode_t scg_firc_trim_config_t::trimMode

scg_firc_trim_src_t scg_firc_trim_config_t::trimSrc

uint8_t scg_firc_trim_config_t::trimCoar

uint8_t scg_firc_trim_config_t::trimFine

struct scg_firc_config_t

Data Fields
uint32_t	enableMode
	Enable mode, OR'ed value of _scg_firc_enable_mode. More...

scg_async_clk_div_t	div1
	FIRCDIV1 value. More...

scg_async_clk_div_t	div2
	FIRCDIV2 value. More...

scg_async_clk_div_t	div3
	FIRCDIV3 value. More...

scg_firc_range_t	range
	Fast IRC frequency range. More...

const scg_firc_trim_config_t *	trimConfig
	Pointer to the FIRC trim configuration; set NULL to disable trim. More...

Field Documentation

uint32_t scg_firc_config_t::enableMode

scg_async_clk_div_t scg_firc_config_t::div1

scg_async_clk_div_t scg_firc_config_t::div2

scg_async_clk_div_t scg_firc_config_t::div3

scg_firc_range_t scg_firc_config_t::range

const scg_firc_trim_config_t* scg_firc_config_t::trimConfig

struct scg_lpfll_trim_config_t

Data Fields
scg_lpfll_trim_mode_t	trimMode
	Trim mode. More...

scg_lpfll_lock_mode_t	lockMode
	Lock mode; Irrelevant if the trimMode is kSCG_LpFllTrimNonUpdate. More...

scg_lpfll_trim_src_t	trimSrc
	Trim source. More...

uint8_t	trimDiv
	Trim predivideds value, which can be 0 ~ 31. More...

uint8_t	trimValue
	Trim value; Irrelevant if trimMode is the kSCG_LpFllTrimUpdate. More...

Field Documentation

scg_lpfll_trim_mode_t scg_lpfll_trim_config_t::trimMode

scg_lpfll_lock_mode_t scg_lpfll_trim_config_t::lockMode

scg_lpfll_trim_src_t scg_lpfll_trim_config_t::trimSrc

uint8_t scg_lpfll_trim_config_t::trimDiv

[ Trim source frequency / (trimDiv + 1) ] must be 2 MHz or 32768 Hz.

uint8_t scg_lpfll_trim_config_t::trimValue

struct scg_lpfll_config_t

Data Fields
uint8_t	enableMode
	Enable mode, OR'ed value of _scg_lpfll_enable_mode.

scg_async_clk_div_t	div1
	LPFLLDIV1 value. More...

scg_async_clk_div_t	div2
	LPFLLDIV2 value. More...

scg_async_clk_div_t	div3
	LPFLLDIV3 value. More...

scg_lpfll_range_t	range
	LPFLL frequency range. More...

const scg_lpfll_trim_config_t *	trimConfig
	Trim configuration; set NULL to disable trim. More...

Field Documentation

scg_async_clk_div_t scg_lpfll_config_t::div1

scg_async_clk_div_t scg_lpfll_config_t::div2

scg_async_clk_div_t scg_lpfll_config_t::div3

scg_lpfll_range_t scg_lpfll_config_t::range

const scg_lpfll_trim_config_t* scg_lpfll_config_t::trimConfig

struct scg_rosc_config_t

Data Fields
scg_rosc_monitor_mode_t	monitorMode
	Clock monitor mode selected. More...

Field Documentation

scg_rosc_monitor_mode_t scg_rosc_config_t::monitorMode

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))

#define MAX_CLOCKS

Value:

{               \
        kCLOCK_Max0 \
    }

#define EDMA_CLOCKS

Value:

{                              \
        kCLOCK_Edma0, kCLOCK_Edma1 \
    }

#define FLEXBUS_CLOCKS

Value:

{                  \
        kCLOCK_Flexbus \
    }

#define FSL_CLOCK_XRDC_GATE_COUNT (5U)

#define XRDC_CLOCKS

Value:

{                                                                                         \
        kCLOCK_Xrdc0Mgr, kCLOCK_Xrdc0Pac, kCLOCK_Xrdc0Mrc, kCLOCK_Xrdc0PacB, kCLOCK_Xrdc0MrcB \
    }

#define SEMA42_CLOCKS

Value:

{                                  \
        kCLOCK_Sema420, kCLOCK_Sema421 \
    }

#define DMAMUX_CLOCKS

Value:

{                                  \
        kCLOCK_Dmamux0, kCLOCK_Dmamux1 \
    }

#define MU_CLOCKS

Value:

{              \
        kCLOCK_MuA \
    }

#define CRC_CLOCKS

Value:

{               \
        kCLOCK_Crc0 \
    }

#define LPIT_CLOCKS

Value:

{                              \
        kCLOCK_Lpit0, kCLOCK_Lpit1 \
    }

#define TPM_CLOCKS

Value:

{                                                      \
        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3 \
    }

#define TRNG_CLOCKS

Value:

{               \
        kCLOCK_Trng \
    }

#define EMVSIM_CLOCKS

Value:

{                  \
        kCLOCK_Emvsim0 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define FLEXIO_CLOCKS

Value:

{                  \
        kCLOCK_Flexio0 \
    }

#define LPI2C_CLOCKS

Value:

{                                                              \
        kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3 \
    }

#define SAI_CLOCKS

Value:

{               \
        kCLOCK_Sai0 \
    }

#define USDHC_CLOCKS

Value:

{                \
        kCLOCK_Sdhc0 \
    }

#define LPSPI_CLOCKS

Value:

{                                                              \
        kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3 \
    }

#define LPUART_CLOCKS

Value:

{                                                                  \
        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3 \
    }

#define USB_CLOCKS

Value:

{               \
        kCLOCK_Usb0 \
    }

#define PORT_CLOCKS

Value:

{                                                                        \
        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
    }

#define LPADC_CLOCKS

Value:

{                 \
        kCLOCK_Lpadc0 \
    }

#define LPDAC_CLOCKS

Value:

{                \
        kCLOCK_Dac0  \
    }

#define INTMUX_CLOCKS

Value:

{                                    \
        kCLOCK_IpInvalid, kCLOCK_Intmux0 \
    }

#define EXT_CLOCKS

Value:

{                            \
        kCLOCK_Ext0, kCLOCK_Ext1 \
    }

#define VREF_CLOCKS

Value:

{               \
        kCLOCK_Vref \
    }

#define FGPIO_CLOCKS

Value:

{                                                                                         \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Rgpio1 \
    }

#define MAKE_PCC_REGADDR	(	base,
		offset
	)	((base) + (offset))

It is defined as the corresponding register address.

Enumeration Type Documentation

enum clock_name_t

These clocks source would be generated from SCG module.

Enumerator
kCLOCK_CoreSysClk	Core 0/1 clock.
kCLOCK_SlowClk	SLOW_CLK with DIVSLOW.
kCLOCK_PlatClk	PLAT_CLK.
kCLOCK_SysClk	SYS_CLK.
kCLOCK_BusClk	BUS_CLK with DIVBUS.
kCLOCK_ExtClk	One clock selection of CLKOUT from main clock after DIVCORE and DIVEXT divider.
kCLOCK_ScgSysLpFllAsyncDiv1Clk	LPFLL_DIV1_CLK.
kCLOCK_ScgSysLpFllAsyncDiv2Clk	LPFLL_DIV1_CLK.
kCLOCK_ScgSysLpFllAsyncDiv3Clk	LPFLL_DIV1_CLK.
kCLOCK_ScgSircAsyncDiv1Clk	SIRCDIV1_CLK.
kCLOCK_ScgSircAsyncDiv2Clk	SIRCDIV2_CLK.
kCLOCK_ScgSircAsyncDiv3Clk	SIRCDIV3_CLK.
kCLOCK_ScgFircAsyncDiv1Clk	FIRCDIV1_CLK.
kCLOCK_ScgFircAsyncDiv2Clk	FIRCDIV2_CLK.
kCLOCK_ScgFircAsyncDiv3Clk	FIRCDIV3_CLK.
kCLOCK_ScgSircClk	SCG SIRC clock.
kCLOCK_ScgFircClk	SCG FIRC clock.
kCLOCK_RtcOscClk	RTC OSC clock.
kCLOCK_ScgLpFllClk	SCG Low-power FLL clock. (LPFLL)
kCLOCK_LpoClk	LPO clock.
kCLOCK_Osc32kClk	External OSC 32K clock (OSC32KCLK)

enum clock_ip_src_t

These options are for PCC->CLKCFG[PCS].

Enumerator
kCLOCK_IpSrcNoneOrExt	Clock is off or external clock is used.
kCLOCK_IpSrcSircAsync	Slow IRC async clock.
kCLOCK_IpSrcFircAsync	Fast IRC async clock.
kCLOCK_IpSrcLpFllAsync	System LPFLL async clock.

enum clock_usb_src_t

Enumerator
kCLOCK_UsbSrcIrc48M	Use IRC48M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

anonymous enum

Enumerator
kStatus_SCG_Busy	Clock is busy.
kStatus_SCG_InvalidSrc	Invalid source.

enum scg_sys_clk_t

Enumerator
kSCG_SysClkSlow	System slow clock.
kSCG_SysClkBus	Bus clock.
kSCG_SysClkExt	External clock.
kSCG_SysClkCore	Core clock.

enum scg_sys_clk_src_t

Enumerator
kSCG_SysClkSrcSirc	Slow IRC.
kSCG_SysClkSrcFirc	Fast IRC.
kSCG_SysClkSrcRosc	RTC OSC.
kSCG_SysClkSrcLpFll	Low power FLL.

enum scg_sys_clk_div_t

Enumerator
kSCG_SysClkDivBy1	Divided by 1.
kSCG_SysClkDivBy2	Divided by 2.
kSCG_SysClkDivBy3	Divided by 3.
kSCG_SysClkDivBy4	Divided by 4.
kSCG_SysClkDivBy5	Divided by 5.
kSCG_SysClkDivBy6	Divided by 6.
kSCG_SysClkDivBy7	Divided by 7.
kSCG_SysClkDivBy8	Divided by 8.
kSCG_SysClkDivBy9	Divided by 9.
kSCG_SysClkDivBy10	Divided by 10.
kSCG_SysClkDivBy11	Divided by 11.
kSCG_SysClkDivBy12	Divided by 12.
kSCG_SysClkDivBy13	Divided by 13.
kSCG_SysClkDivBy14	Divided by 14.
kSCG_SysClkDivBy15	Divided by 15.
kSCG_SysClkDivBy16	Divided by 16.

enum clock_clkout_src_t

Enumerator
kClockClkoutSelScgExt	SCG external clock.
kClockClkoutSelSirc	Slow IRC.
kClockClkoutSelFirc	Fast IRC.
kClockClkoutSelScgRtcOsc	SCG RTC OSC clock.
kClockClkoutSelLpFll	Low power FLL.

enum scg_async_clk_t

Enumerator

kSCG_AsyncDiv1Clk

The async clock by DIV1, e.g.

SOSCDIV1_CLK, SIRCDIV1_CLK.

kSCG_AsyncDiv2Clk

The async clock by DIV2, e.g.

SOSCDIV2_CLK, SIRCDIV2_CLK.

kSCG_AsyncDiv3Clk

The async clock by DIV3, e.g.

SOSCDIV3_CLK, SIRCDIV3_CLK.

enum scg_async_clk_div_t

Enumerator
kSCG_AsyncClkDisable	Clock output is disabled.
kSCG_AsyncClkDivBy1	Divided by 1.
kSCG_AsyncClkDivBy2	Divided by 2.
kSCG_AsyncClkDivBy4	Divided by 4.
kSCG_AsyncClkDivBy8	Divided by 8.
kSCG_AsyncClkDivBy16	Divided by 16.
kSCG_AsyncClkDivBy32	Divided by 32.
kSCG_AsyncClkDivBy64	Divided by 64.

enum scg_sirc_range_t

Enumerator
kSCG_SircRangeLow	Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP).
kSCG_SircRangeHigh	Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP).

enum _scg_sirc_enable_mode

Enumerator
kSCG_SircEnable	Enable SIRC clock.
kSCG_SircEnableInStop	Enable SIRC in stop mode.
kSCG_SircEnableInLowPower	Enable SIRC in low power mode.

enum scg_firc_trim_mode_t

Enumerator

kSCG_FircTrimNonUpdate

FIRC trim enable but not enable trim value update.

In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure scg_firc_trim_config_t.

kSCG_FircTrimUpdate

FIRC trim enable and trim value update enable.

In this mode, the trim value is auto update.

enum scg_firc_trim_div_t

Enumerator
kSCG_FircTrimDivBy1	Divided by 1.
kSCG_FircTrimDivBy128	Divided by 128.
kSCG_FircTrimDivBy256	Divided by 256.
kSCG_FircTrimDivBy512	Divided by 512.
kSCG_FircTrimDivBy1024	Divided by 1024.
kSCG_FircTrimDivBy2048	Divided by 2048.

enum scg_firc_trim_src_t

Enumerator
kSCG_FircTrimSrcSysOsc	System OSC.
kSCG_FircTrimSrcRtcOsc	RTC OSC (32.768 kHz).

enum scg_firc_range_t

Enumerator
kSCG_FircRange48M	Fast IRC is trimmed to 48 MHz.
kSCG_FircRange52M	Fast IRC is trimmed to 52 MHz.
kSCG_FircRange56M	Fast IRC is trimmed to 56 MHz.
kSCG_FircRange60M	Fast IRC is trimmed to 60 MHz.

enum _scg_firc_enable_mode

Enumerator
kSCG_FircEnable	Enable FIRC clock.
kSCG_FircEnableInStop	Enable FIRC in stop mode.
kSCG_FircEnableInLowPower	Enable FIRC in low power mode.
kSCG_FircDisableRegulator	Disable regulator.

enum _scg_lpfll_enable_mode

Enumerator
kSCG_LpFllEnable	Enable LPFLL clock.

enum scg_lpfll_range_t

Enumerator
kSCG_LpFllRange48M	LPFLL is trimmed to 48MHz.
kSCG_LpFllRange72M	LPFLL is trimmed to 72MHz.
kSCG_LpFllRange96M	LPFLL is trimmed to 96MHz.
kSCG_LpFllRange120M	LPFLL is trimmed to 120MHz.

enum scg_lpfll_trim_mode_t

Enumerator

kSCG_LpFllTrimNonUpdate

LPFLL trim is enabled but the trim value update is not enabled.

In this mode, the trim value is fixed to the initialized value, which is defined by the trimValue in the structure scg_lpfll_trim_config_t.

kSCG_LpFllTrimUpdate

FIRC trim is enabled and trim value update is enabled.

In this mode, the trim value is automatically updated.

enum scg_lpfll_trim_src_t

Enumerator
kSCG_LpFllTrimSrcSirc	SIRC.
kSCG_LpFllTrimSrcFirc	FIRC.
kSCG_LpFllTrimSrcSysOsc	System OSC.
kSCG_LpFllTrimSrcRtcOsc	RTC OSC (32.768 kHz).

enum scg_lpfll_lock_mode_t

Enumerator
kSCG_LpFllLock1Lsb	Lock with 1 LSB.
kSCG_LpFllLock2Lsb	Lock with 2 LSB.

enum scg_rosc_monitor_mode_t

Enumerator
kSCG_rtcOscMonitorDisable	Monitor disable.
kSCG_rtcOscMonitorInt	Interrupt when the RTC OSC error is detected.
kSCG_rtcOscMonitorReset	Reset when the RTC OSC error is detected.

Function Documentation

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see enumeration clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see enumeration clock_ip_name_t.

static bool CLOCK_IsEnabledByOtherCore ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which peripheral to check, see enumeration clock_ip_name_t.

Returns: True if clock is already enabled, otherwise false.

static void CLOCK_SetIpSrc	(	clock_ip_name_t	name,
		clock_ip_src_t	src
	)

inlinestatic

Set the clock source for specific IP, not all modules need to set the clock source, should only use this function for the modules need source setting.

Parameters

name	Which peripheral to check, see enumeration clock_ip_name_t.
src	Clock source to set.

static void CLOCK_SetIpSrcDiv	(	clock_ip_name_t	name,
		clock_ip_src_t	src,
		uint8_t	divValue,
		uint8_t	fracValue
	)

inlinestatic

Set the clock source and divider for specific IP, not all modules need to set the clock source and divider, should only use this function for the modules need source and divider setting.

Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]).

Parameters

name	Which peripheral to check, see enumeration clock_ip_name_t.
src	Clock source to set.
divValue	The divider value.
fracValue	The fraction multiply value.

uint32_t CLOCK_GetFreq ( clock_name_t clockName )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

uint32_t CLOCK_GetCoreSysClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetPlatClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetBusClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetFlashClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetOsc32kClkFreq ( void )

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetExtClkFreq ( void )

Returns: Clock frequency in Hz.

static uint32_t CLOCK_GetLpoClkFreq ( void )

inlinestatic

Returns: Clock frequency in Hz.

uint32_t CLOCK_GetIpFreq ( clock_ip_name_t name )

This function gets the IP module's functional clock frequency based on PCC registers. It is only used for the IP modules which could select clock source by PCC[PCS].

Parameters

name	Which peripheral to get, see enumeration clock_ip_name_t.

Returns: Clock frequency value in Hz

static void CLOCK_EnableRtcOsc ( bool enable )

inlinestatic

This function enables the Oscillator for RTC external crystal.

Parameters

enable Enable the Oscillator or not.

bool CLOCK_EnableUsbfs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

Parameters

src	USB FS clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB FS clock.

static void CLOCK_DisableUsbfs0Clock ( void )

inlinestatic

Disable USB FS clock.

uint32_t CLOCK_GetSysClkFreq ( scg_sys_clk_t type )

This function gets the SCG system clock frequency. These clocks are used for core, platform, external, and bus clock domains.

Parameters

type	Which type of clock to get, core clock or slow clock.

Returns: Clock frequency.

static void CLOCK_SetVlprModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for VLPR mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetRunModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for RUN mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetHsrunModeSysClkConfig ( const scg_sys_clk_config_t * config )

inlinestatic

This function sets the system clock configuration for HSRUN mode.

Parameters

config Pointer to the configuration.

static void CLOCK_GetCurSysClkConfig ( scg_sys_clk_config_t * config )

inlinestatic

This function gets the system configuration in the current power mode.

Parameters

config Pointer to the configuration.

static void CLOCK_SetClkOutSel ( clock_clkout_src_t setting )

inlinestatic

This function sets the clock out selection (CLKOUTSEL).

Parameters

setting The selection to set.

Returns: The current clock out selection.

status_t CLOCK_InitSirc ( const scg_sirc_config_t * config )

This function enables the SCG slow IRC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	SIRC is initialized.
kStatus_SCG_Busy	SIRC has been enabled and is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note: This function can't detect whether the system OSC has been enabled and used by an IP.

status_t CLOCK_DeinitSirc ( void )

This function disables the SCG slow IRC.

Return values

kStatus_Success	SIRC is deinitialized.
kStatus_SCG_Busy	SIRC is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note: This function can't detect whether the SIRC is used by an IP.

static void CLOCK_SetSircAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetSircFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetSircAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsSircValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

status_t CLOCK_InitFirc ( const scg_firc_config_t * config )

This function enables the SCG fast IRC clock according to the configuration.

Parameters

config Pointer to the configuration structure.

Return values

kStatus_Success	FIRC is initialized.
kStatus_SCG_Busy	FIRC has been enabled and is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note: This function can't detect whether the FIRC has been enabled and used by an IP.

status_t CLOCK_DeinitFirc ( void )

This function disables the SCG fast IRC.

Return values

kStatus_Success	FIRC is deinitialized.
kStatus_SCG_Busy	FIRC is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note: This function can't detect whether the FIRC is used by an IP.

static void CLOCK_SetFircAsyncClkDiv	(	scg_async_clk_t	asyncClk,
		scg_async_clk_div_t	divider
	)

inlinestatic

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note: There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

uint32_t CLOCK_GetFircFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetFircAsyncFreq ( scg_async_clk_t type )

Parameters

type	The asynchronous clock type.

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsFircErr ( void )

inlinestatic

Returns: True if the error occurs, false if not.

static bool CLOCK_IsFircValid ( void )

inlinestatic

Returns: True if clock is valid, false if not.

uint32_t CLOCK_GetRtcOscFreq ( void )

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsRtcOscErr ( void )

inlinestatic

Returns: True if error occurs, false if not.

static void CLOCK_SetRtcOscMonitorMode ( scg_rosc_monitor_mode_t mode )

inlinestatic

This function sets the RTC OSC monitor mode. The mode can be disabled. It can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

static bool CLOCK_IsRtcOscValid ( void )

inlinestatic

Returns: True if the clock is valid, false if not.

Variable Documentation

volatile uint32_t g_xtal0Freq

The XTAL0/EXTAL0 (OSC0/SYSOSC) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:

* CLOCK_InitSysOsc(...);
* CLOCK_SetXtal0Freq(80000000);
* 

This is important for the multicore platforms where only one core needs to set up the OSC0/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.

volatile uint32_t g_xtal32Freq

The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.

Overview

Modules

Files

Data Structures

Macros

Enumerations

Functions

Variables

Driver version

MCU System Clock.

SCG Slow IRC Clock.

SCG Fast IRC Clock.

Data Structure Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Data Fields

Field Documentation

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation