Overview

Macros
#define	L1CODEBUSCACHE_LINESIZE_BYTE FSL_FEATURE_L1ICACHE_LINESIZE_BYTE
	code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. More...

#define	L1SYSTEMBUSCACHE_LINESIZE_BYTE L1CODEBUSCACHE_LINESIZE_BYTE
	The system bus CACHE line size is 16B = 128b. More...

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
	cache driver version. More...

cache control for L1 cache (local memory controller for code/system bus cache)
void	L1CACHE_EnableCodeCache (void)
	Enables the processor code bus cache.

void	L1CACHE_DisableCodeCache (void)
	Disables the processor code bus cache.

void	L1CACHE_InvalidateCodeCache (void)
	Invalidates the processor code bus cache.

void	L1CACHE_InvalidateCodeCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates processor code bus cache by range. More...

void	L1CACHE_CleanCodeCache (void)
	Cleans the processor code bus cache.

void	L1CACHE_CleanCodeCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans processor code bus cache by range. More...

void	L1CACHE_CleanInvalidateCodeCache (void)
	Cleans and invalidates the processor code bus cache.

void	L1CACHE_CleanInvalidateCodeCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and invalidate processor code bus cache by range. More...

static void	L1CACHE_EnableCodeCacheWriteBuffer (bool enable)
	Enables/disables the processor code bus write buffer. More...

void	L1CACHE_EnableSystemCache (void)
	Enables the processor system bus cache.

void	L1CACHE_DisableSystemCache (void)
	Disables the processor system bus cache.

void	L1CACHE_InvalidateSystemCache (void)
	Invalidates the processor system bus cache.

void	L1CACHE_InvalidateSystemCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates processor system bus cache by range. More...

void	L1CACHE_CleanSystemCache (void)
	Cleans the processor system bus cache.

void	L1CACHE_CleanSystemCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans processor system bus cache by range. More...

void	L1CACHE_CleanInvalidateSystemCache (void)
	Cleans and invalidates the processor system bus cache.

void	L1CACHE_CleanInvalidateSystemCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates processor system bus cache by range. More...

static void	L1CACHE_EnableSystemCacheWriteBuffer (bool enable)
	Enables/disables the processor system bus write buffer. More...

cache control for unified L1 cache driver
void	L1CACHE_InvalidateICacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates cortex-m4 L1 instrument cache by range. More...

static void	L1CACHE_InvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Invalidates cortex-m4 L1 data cache by range. More...

void	L1CACHE_CleanDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans cortex-m4 L1 data cache by range. More...

void	L1CACHE_CleanInvalidateDCacheByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates cortex-m4 L1 data cache by range. More...

Unified Cache Control for all caches
static void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates instruction cache by range. More...

static void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates data cache by range. More...

static void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Clean data cache by range. More...

static void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates data cache by range. More...

Macro Definition Documentation

#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))

#define L1CODEBUSCACHE_LINESIZE_BYTE FSL_FEATURE_L1ICACHE_LINESIZE_BYTE

The code bus CACHE line size is 16B = 128b.

#define L1SYSTEMBUSCACHE_LINESIZE_BYTE L1CODEBUSCACHE_LINESIZE_BYTE

Function Documentation

void L1CACHE_InvalidateCodeCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be invalidated.

Note: Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void L1CACHE_CleanCodeCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be cleaned.

Note: Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void L1CACHE_CleanInvalidateCodeCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be Cleaned and Invalidated.

Note: Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void L1CACHE_EnableCodeCacheWriteBuffer ( bool enable )

inlinestatic

Parameters

enable The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_InvalidateSystemCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be invalidated.

Note: Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void L1CACHE_CleanSystemCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be cleaned.

Note: Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

void L1CACHE_CleanInvalidateSystemCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The physical address of cache.
size_byte	size of the memory to be Clean and Invalidated.

Note: Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void L1CACHE_EnableSystemCacheWriteBuffer ( bool enable )

inlinestatic

Parameters

enable The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_InvalidateICacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.

static void L1CACHE_InvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

void L1CACHE_CleanDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The start address of the memory to be cleaned.
size_byte	The memory size.

Note: The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

void L1CACHE_CleanInvalidateDCacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Parameters

address	The start address of the memory to be clean and invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

static void ICACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note: Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

static void DCACHE_CleanInvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

inlinestatic

Parameters

address	The physical address.
size_byte	size of the memory to be Cleaned and Invalidated.

Note: Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Overview

Macros

Driver version

cache control for L1 cache (local memory controller for code/system bus cache)

cache control for unified L1 cache driver

Unified Cache Control for all caches

Macro Definition Documentation

Function Documentation