Overview

The MCUXpresso SDK provides a driver for the FLEXRAM module of MCUXpresso SDK devices.

The FLEXRAM module intergrates the ITCM, DTCM, and OCRAM controllers, and supports parameterized RAM array and RAM array portioning.

This example code shows how to allocate RAM using the FLEXRAM driver.

Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/flexram.

Data Structures
struct	flexram_allocate_ram_t
	FLEXRAM allocate ocram, itcm, dtcm size. More...

Macros
#define	FLEXRAM_ECC_ERROR_DETAILED_INFO 0U /* Define to zero means get raw ECC error information, which needs parse it by user. */
	Get ECC error detailed information. More...

Enumerations
enum	{ kFLEXRAM_BankNotUsed = 0U, kFLEXRAM_BankOCRAM = 1U, kFLEXRAM_BankDTCM = 2U, kFLEXRAM_BankITCM = 3U }
	FLEXRAM bank type. More...

enum	flexram_bank_allocate_src_t { kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, kFLEXRAM_BankAllocateThroughBankCfg = 1U }
	FLEXRAM bank allocate source. More...

enum	{ kFLEXRAM_Read = 0U, kFLEXRAM_Write = 1U }
	Flexram write/read selection. More...

enum	{ kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK }
	Interrupt status flag mask. More...

enum	flexram_tcm_access_mode_t { kFLEXRAM_TCMAccessFastMode = 0U, kFLEXRAM_TCMAccessWaitMode = 1U }
	FLEXRAM TCM access mode. More...

enum	{ kFLEXRAM_TCMSize32KB = 32 * 1024U, kFLEXRAM_TCMSize64KB = 64 * 1024U, kFLEXRAM_TCMSize128KB = 128 * 1024U, kFLEXRAM_TCMSize256KB = 256 * 1024U, kFLEXRAM_TCMSize512KB = 512 * 1024U }
	FLEXRAM TCM support size. More...

Functions
status_t	FLEXRAM_AllocateRam (flexram_allocate_ram_t *config)
	FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate is needed. More...

static void	FLEXRAM_SetAllocateRamSrc (flexram_bank_allocate_src_t src)
	FLEXRAM set allocate on-chip ram source. More...

void	FLEXRAM_SetTCMSize (uint8_t itcmBankNum, uint8_t dtcmBankNum)
	FLEXRAM configure TCM size This function is used to set the TCM to the target size. More...

static void	FLEXRAM_SetTCMReadAccessMode (FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
	FLEXRAM module sets TCM read access mode. More...

static void	FLEXRAM_SetTCMWriteAccessMode (FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
	FLEXRAM module set TCM write access mode. More...

static void	FLEXRAM_EnableForceRamClockOn (FLEXRAM_Type *base, bool enable)
	FLEXRAM module force ram clock on. More...

static void	FLEXRAM_SetOCRAMMagicAddr (FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
	FLEXRAM OCRAM magic addr configuration. More...

static void	FLEXRAM_SetDTCMMagicAddr (FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
	FLEXRAM DTCM magic addr configuration. More...

static void	FLEXRAM_SetITCMMagicAddr (FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
	FLEXRAM ITCM magic addr configuration. More...

Driver version
#define	FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
	SOC_FLEXRAM_ALLOCATE driver version 2.0.1. More...

Driver version
#define	FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
	Driver version 2.1.0. More...

Initialization and de-initialization
void	FLEXRAM_Init (FLEXRAM_Type *base)
	FLEXRAM module initialization function. More...

void	FLEXRAM_Deinit (FLEXRAM_Type *base)
	De-initializes the FLEXRAM.

Status
static uint32_t	FLEXRAM_GetInterruptStatus (FLEXRAM_Type *base)
	FLEXRAM module gets interrupt status. More...

static void	FLEXRAM_ClearInterruptStatus (FLEXRAM_Type *base, uint32_t status)
	FLEXRAM module clears interrupt status. More...

static void	FLEXRAM_EnableInterruptStatus (FLEXRAM_Type *base, uint32_t status)
	FLEXRAM module enables interrupt status. More...

static void	FLEXRAM_DisableInterruptStatus (FLEXRAM_Type *base, uint32_t status)
	FLEXRAM module disable interrupt status. More...

Interrupts
static void	FLEXRAM_EnableInterruptSignal (FLEXRAM_Type *base, uint32_t status)
	FLEXRAM module enables interrupt. More...

static void	FLEXRAM_DisableInterruptSignal (FLEXRAM_Type *base, uint32_t status)
	FLEXRAM module disables interrupt. More...

Data Structure Documentation

struct flexram_allocate_ram_t

Data Fields
const uint8_t	ocramBankNum
	ocram banknumber which the SOC support

const uint8_t	dtcmBankNum
	dtcm bank number to allocate, the number should be power of 2

const uint8_t	itcmBankNum
	itcm bank number to allocate, the number should be power of 2

Macro Definition Documentation

#define FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))

#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))

#define FLEXRAM_ECC_ERROR_DETAILED_INFO 0U /* Define to zero means get raw ECC error information, which needs parse it by user. */

Enumeration Type Documentation

anonymous enum

Enumerator
kFLEXRAM_BankNotUsed	bank is not used
kFLEXRAM_BankOCRAM	bank is OCRAM
kFLEXRAM_BankDTCM	bank is DTCM
kFLEXRAM_BankITCM	bank is ITCM

enum flexram_bank_allocate_src_t

Enumerator
kFLEXRAM_BankAllocateThroughHardwareFuse	allocate ram through hardware fuse value
kFLEXRAM_BankAllocateThroughBankCfg	allocate ram through FLEXRAM_BANK_CFG

anonymous enum

Enumerator
kFLEXRAM_Read	read
kFLEXRAM_Write	write

anonymous enum

Enumerator
kFLEXRAM_OCRAMAccessError	OCRAM accesses unallocated address.
kFLEXRAM_DTCMAccessError	DTCM accesses unallocated address.
kFLEXRAM_ITCMAccessError	ITCM accesses unallocated address.
kFLEXRAM_OCRAMMagicAddrMatch	OCRAM magic address match.
kFLEXRAM_DTCMMagicAddrMatch	DTCM magic address match.
kFLEXRAM_ITCMMagicAddrMatch	ITCM magic address match.

enum flexram_tcm_access_mode_t

Fast access mode expected to be finished in 1-cycle; Wait access mode expected to be finished in 2-cycle. Wait access mode is a feature of the flexram and it should be used when the CPU clock is too fast to finish TCM access in 1-cycle. Normally, fast mode is the default mode, the efficiency of the TCM access will better.

Enumerator
kFLEXRAM_TCMAccessFastMode	fast access mode
kFLEXRAM_TCMAccessWaitMode	wait access mode

anonymous enum

Enumerator
kFLEXRAM_TCMSize32KB	TCM total size be 32KB.
kFLEXRAM_TCMSize64KB	TCM total size be 64KB.
kFLEXRAM_TCMSize128KB	TCM total size be 128KB.
kFLEXRAM_TCMSize256KB	TCM total size be 256KB.
kFLEXRAM_TCMSize512KB	TCM total size be 512KB.

Function Documentation

status_t FLEXRAM_AllocateRam ( flexram_allocate_ram_t * config )

Parameters

config allocate configuration.

Return values

kStatus_InvalidArgument the argument is invalid kStatus_Success allocate success

static void FLEXRAM_SetAllocateRamSrc ( flexram_bank_allocate_src_t src )

inlinestatic

Parameters

src	bank config source select value.

void FLEXRAM_SetTCMSize	(	uint8_t	itcmBankNum,
		uint8_t	dtcmBankNum
	)

If a odd bank number is used, a new banknumber will be used which is bigger than target value, application can set tcm size to the biggest bank number always, then boundary access error can be captured by flexram only. When access to the TCM memory boundary ,hardfault will raised by core.

Parameters

itcmBankNum	itcm bank number to allocate
dtcmBankNum	dtcm bank number to allocate

void FLEXRAM_Init ( FLEXRAM_Type * base )

Parameters

base	FLEXRAM base address.

static uint32_t FLEXRAM_GetInterruptStatus ( FLEXRAM_Type * base )

inlinestatic

Parameters

base	FLEXRAM base address.

static void FLEXRAM_ClearInterruptStatus	(	FLEXRAM_Type *	base,
		uint32_t	status
	)

inlinestatic

Parameters

base	FLEXRAM base address.
status	Status to be cleared.

static void FLEXRAM_EnableInterruptStatus	(	FLEXRAM_Type *	base,
		uint32_t	status
	)

inlinestatic

Parameters

base	FLEXRAM base address.
status	Status to be enabled.

static void FLEXRAM_DisableInterruptStatus	(	FLEXRAM_Type *	base,
		uint32_t	status
	)

inlinestatic

Parameters

base	FLEXRAM base address.
status	Status to be disabled.

static void FLEXRAM_EnableInterruptSignal	(	FLEXRAM_Type *	base,
		uint32_t	status
	)

inlinestatic

Parameters

base	FLEXRAM base address.
status	Status interrupt to be enabled.

static void FLEXRAM_DisableInterruptSignal	(	FLEXRAM_Type *	base,
		uint32_t	status
	)

inlinestatic

Parameters

base	FLEXRAM base address.
status	Status interrupt to be disabled.

static void FLEXRAM_SetTCMReadAccessMode	(	FLEXRAM_Type *	base,
		flexram_tcm_access_mode_t	mode
	)

inlinestatic

Parameters

base	FLEXRAM base address.
mode	Access mode.

static void FLEXRAM_SetTCMWriteAccessMode	(	FLEXRAM_Type *	base,
		flexram_tcm_access_mode_t	mode
	)

inlinestatic

Parameters

base	FLEXRAM base address.
mode	Access mode.

static void FLEXRAM_EnableForceRamClockOn	(	FLEXRAM_Type *	base,
		bool	enable
	)

inlinestatic

Parameters

base	FLEXRAM base address.
enable	Enable or disable clock force on.

static void FLEXRAM_SetOCRAMMagicAddr	(	FLEXRAM_Type *	base,
		uint16_t	magicAddr,
		uint32_t	rwSel
	)

inlinestatic

When read/write access hit magic address, it will generate interrupt.

Parameters

base	FLEXRAM base address.
magicAddr	Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
rwSel	Read/write selection. 0 for read access while 1 for write access.

static void FLEXRAM_SetDTCMMagicAddr	(	FLEXRAM_Type *	base,
		uint16_t	magicAddr,
		uint32_t	rwSel
	)

inlinestatic

When read/write access hits magic address, it will generate interrupt.

Parameters

base	FLEXRAM base address.
magicAddr	Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
rwSel	Read/write selection. 0 for read access while 1 write access.

static void FLEXRAM_SetITCMMagicAddr	(	FLEXRAM_Type *	base,
		uint16_t	magicAddr,
		uint32_t	rwSel
	)

inlinestatic

When read/write access hits magic address, it will generate interrupt.

Parameters

base	FLEXRAM base address.
magicAddr	Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
rwSel	Read/write selection. 0 for read access while 1 for write access.

Overview

Data Structures

Macros

Enumerations

Functions

Driver version

Driver version

Initialization and de-initialization

Status

Interrupts

Data Structure Documentation

Data Fields

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation