MCUXpresso SDK API Reference Manual  Rev. 0
NXP Semiconductors
 All Data Structures Functions Variables Typedefs Enumerations Enumerator Groups Pages
Common Driver

Read Guidance

The MCUXpresso SDK provides a driver for the common module of MCUXpresso SDK devices.

Driver Overview

 Driver Change Log
 The current COMMON driver version is 2.0.0.
 

Macros

#define MAKE_STATUS(group, code)   ((((group)*100UL) + (code)))
 Construct a status code value from a group and code number. More...
 
#define MAKE_VERSION(major, minor, bugfix)   (((major) << 16) | ((minor) << 8) | (bugfix))
 Construct the version number for drivers. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE   0U
 No debug console. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_UART   1U
 Debug console based on UART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART   2U
 Debug console based on LPUART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI   3U
 Debug console based on LPSCI. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC   4U
 Debug console based on USBCDC. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U
 Debug console based on FLEXCOMM. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART   6U
 Debug console based on i.MX UART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART   7U
 Debug console based on LPC_VUSART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART   8U
 Debug console based on LPC_USART. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO   9U
 Debug console based on SWO. More...
 
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI   10U
 Debug console based on QSCI. More...
 
#define ARRAY_SIZE(x)   (sizeof(x) / sizeof((x)[0]))
 Computes the number of elements in an array. More...
 
#define SDK_DSC_DEFAULT_INT_PRIO   1U
 Default DSC interrupt priority number. More...
 
#define SetIRQBasePriority(x)   __EI##x()
 Set base core IRQ priority, that core will response the interrupt request with priority >= base IRQ priority. More...
 
#define PeriphReadReg(reg)   (reg)
 Read register value. More...
 
#define PeriphWriteReg(reg, data)   (reg) = (data)
 Write data to register. More...
 
#define PeriphSetBits(reg, bitMask)   (reg) |= (bitMask)
 Set specified bits in register. More...
 
#define PeriphClearBits(reg, bitMask)   (reg) &= (~(bitMask))
 Clear specified bits in register. More...
 
#define PeriphInvertBits(reg, bitMask)   (reg) ^= (bitMask)
 Invert specified bits in register. More...
 
#define PeriphGetBits(reg, bitMask)   ( (reg) & (bitMask) )
 Get specified bits in register. More...
 
#define PeriphWriteBitGroup(reg, bitMask, bitValue)   (reg) = ((reg) & ~(bitMask)) | ((bitValue) & (bitMask))
 Write group of bits to register. More...
 
#define PeriphSafeClearFlags(reg, allFlagsMask, flagMask)   (reg) = ((reg) & (~(allFlagsMask))) | ((flagMask) & (allFlagsMask))
 Clear (acknowledge) flags which are active-high and are cleared-by-write-one. More...
 
#define PeriphSafeClearBits(reg, allFlagsMask, bitMask)   (reg) = ((reg) & (~((allFlagsMask) | (bitMask))))
 Clear selected bits without modifying (acknowledge) bit flags which are active-high and are cleared-by-write-one. More...
 
#define PeriphSafeSetBits(reg, allFlagsMask, bitMask)   (reg) = ((reg) & (~(allFlagsMask))) | ((bitMask) & (~(allFlagsMask)))
 Set selected bits without modifying (acknowledge) bit flags which are active-high and are cleared-by-write-one. More...
 
#define PeriphSafeWriteBitGroup(reg, allFlagsMask, bitMask, bitValue)   (reg) = ((reg) & (~((allFlagsMask)|(bitMask)))) | ((bitValue) & (bitMask) & (~(allFlagsMask)))
 Write group of bits without modifying (acknowledge) bit flags which are active-high and are cleared-by-write-one. More...
 

Typedefs

typedef int32_t status_t
 Type used for all status and error return values. More...
 

Enumerations

enum  _status_groups {
  kStatusGroup_Generic = 0,
  kStatusGroup_FLASH = 1,
  kStatusGroup_LPSPI = 4,
  kStatusGroup_FLEXIO_SPI = 5,
  kStatusGroup_DSPI = 6,
  kStatusGroup_FLEXIO_UART = 7,
  kStatusGroup_FLEXIO_I2C = 8,
  kStatusGroup_LPI2C = 9,
  kStatusGroup_UART = 10,
  kStatusGroup_I2C = 11,
  kStatusGroup_LPSCI = 12,
  kStatusGroup_LPUART = 13,
  kStatusGroup_SPI = 14,
  kStatusGroup_XRDC = 15,
  kStatusGroup_SEMA42 = 16,
  kStatusGroup_SDHC = 17,
  kStatusGroup_SDMMC = 18,
  kStatusGroup_SAI = 19,
  kStatusGroup_MCG = 20,
  kStatusGroup_SCG = 21,
  kStatusGroup_SDSPI = 22,
  kStatusGroup_FLEXIO_I2S = 23,
  kStatusGroup_FLEXIO_MCULCD = 24,
  kStatusGroup_FLASHIAP = 25,
  kStatusGroup_FLEXCOMM_I2C = 26,
  kStatusGroup_I2S = 27,
  kStatusGroup_IUART = 28,
  kStatusGroup_CSI = 29,
  kStatusGroup_MIPI_DSI = 30,
  kStatusGroup_SDRAMC = 35,
  kStatusGroup_POWER = 39,
  kStatusGroup_ENET = 40,
  kStatusGroup_PHY = 41,
  kStatusGroup_TRGMUX = 42,
  kStatusGroup_SMARTCARD = 43,
  kStatusGroup_LMEM = 44,
  kStatusGroup_QSPI = 45,
  kStatusGroup_DMA = 50,
  kStatusGroup_EDMA = 51,
  kStatusGroup_DMAMGR = 52,
  kStatusGroup_FLEXCAN = 53,
  kStatusGroup_LTC = 54,
  kStatusGroup_FLEXIO_CAMERA = 55,
  kStatusGroup_LPC_SPI = 56,
  kStatusGroup_LPC_USART = 57,
  kStatusGroup_DMIC = 58,
  kStatusGroup_SDIF = 59,
  kStatusGroup_SPIFI = 60,
  kStatusGroup_OTP = 61,
  kStatusGroup_MCAN = 62,
  kStatusGroup_CAAM = 63,
  kStatusGroup_ECSPI = 64,
  kStatusGroup_USDHC = 65,
  kStatusGroup_LPC_I2C = 66,
  kStatusGroup_DCP = 67,
  kStatusGroup_MSCAN = 68,
  kStatusGroup_ESAI = 69,
  kStatusGroup_FLEXSPI = 70,
  kStatusGroup_MMDC = 71,
  kStatusGroup_PDM = 72,
  kStatusGroup_SDMA = 73,
  kStatusGroup_ICS = 74,
  kStatusGroup_SPDIF = 75,
  kStatusGroup_LPC_MINISPI = 76,
  kStatusGroup_HASHCRYPT = 77,
  kStatusGroup_LPC_SPI_SSP = 78,
  kStatusGroup_I3C = 79,
  kStatusGroup_LPC_I2C_1 = 97,
  kStatusGroup_NOTIFIER = 98,
  kStatusGroup_DebugConsole = 99,
  kStatusGroup_SEMC = 100,
  kStatusGroup_ApplicationRangeStart = 101,
  kStatusGroup_IAP = 102,
  kStatusGroup_SFA = 103,
  kStatusGroup_SPC = 104,
  kStatusGroup_PUF = 105,
  kStatusGroup_QUEUEDSPI = 106,
  kStatusGroup_HAL_GPIO = 121,
  kStatusGroup_HAL_UART = 122,
  kStatusGroup_HAL_TIMER = 123,
  kStatusGroup_HAL_SPI = 124,
  kStatusGroup_HAL_I2C = 125,
  kStatusGroup_HAL_FLASH = 126,
  kStatusGroup_HAL_PWM = 127,
  kStatusGroup_HAL_RNG = 128,
  kStatusGroup_TIMERMANAGER = 135,
  kStatusGroup_SERIALMANAGER = 136,
  kStatusGroup_LED = 137,
  kStatusGroup_BUTTON = 138,
  kStatusGroup_EXTERN_EEPROM = 139,
  kStatusGroup_SHELL = 140,
  kStatusGroup_MEM_MANAGER = 141,
  kStatusGroup_LIST = 142,
  kStatusGroup_OSA = 143,
  kStatusGroup_COMMON_TASK = 144,
  kStatusGroup_MSG = 145,
  kStatusGroup_SDK_OCOTP = 146,
  kStatusGroup_SDK_FLEXSPINOR = 147,
  kStatusGroup_CODEC = 148,
  kStatusGroup_ASRC = 149,
  kStatusGroup_OTFAD = 150,
  kStatusGroup_SDIOSLV = 151
}
 Status group numbers. More...
 
enum  
 Generic status return codes. More...
 

Functions

void * SDK_Malloc (size_t size, size_t alignbytes)
 Allocate memory with given alignment and aligned size. More...
 
void SDK_Free (void *ptr)
 Free memory. More...
 
void SDK_DelayCoreCycles (uint32_t u32Num)
 Delay core cycles. More...
 
void SDK_DelayAtLeastUs (uint32_t delay_us, uint32_t coreClock_Hz)
 Delay at least for some time. More...
 

Driver version

#define FSL_COMMON_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))
 common driver version 2.2.2. More...
 

Min/max macros

#define MIN(a, b)   (((a) < (b)) ? (a) : (b))
 
#define MAX(a, b)   (((a) > (b)) ? (a) : (b))
 

UINT16_MAX/UINT32_MAX value

#define UINT16_MAX   ((uint16_t)-1)
 
#define UINT32_MAX   ((uint32_t)-1)
 

Timer utilities

#define USEC_TO_COUNT(us, clockFreqInHz)   (uint32_t)(((float)clockFreqInHz / 1000000U) * us)
 Macro to convert a microsecond period to raw count value.
 
#define COUNT_TO_USEC(count, clockFreqInHz)   (uint32_t)(((float)count / clockFreqInHz) * 1000000U)
 Macro to convert a raw count value to microsecond.
 
#define MSEC_TO_COUNT(ms, clockFreqInHz)   (uint32_t)(((float)clockFreqInHz / 1000U) * ms)
 Macro to convert a millisecond period to raw count value.
 
#define COUNT_TO_MSEC(count, clockFreqInHz)   (uint32_t)(((float)count / clockFreqInHz) * 1000U)
 Macro to convert a raw count value to millisecond.
 

Alignment variable definition macros

#define SDK_ALIGN(var, alignbytes)   var __attribute__((aligned(alignbytes)))
 Macro to define a variable with alignbytes alignment.
 
#define SDK_SIZEALIGN(var, alignbytes)   ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
 Macro to change a value to a given size aligned value.
 
#define AT_NONCACHEABLE_SECTION(var)   var
 
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)   var __attribute__((aligned(alignbytes)))
 
#define AT_NONCACHEABLE_SECTION_INIT(var)   var
 
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)   var __attribute__((aligned(alignbytes)))
 

Interrupt

DSC interrupt controller uses the same bit-filed to control interrupt enable status and priority, to provide compatible APIs, SDK uses a interrupt priority table, thus application could control the interrupt enable/disable, and interrupt priority independently.

Also, the API EnableIRQWithPriority could be used to enable the interrupt and set the priority at the same time.

API implementation:

  1. When calling EnableIRQ, if the interrupt priority in priority table is valid, then set the interrupt priority level to the value in priority table If interrupt priority in priority table is invalid, then set the interrupt priority level to SDK_DSC_DEFAULT_INT_PRIO.
  2. When calling IRQ_SetPriority, if the interrupt is already enabled, new priority is set to interrupt controller, meanwhile the priority table is updated accordingly. If the interrupt is not enabled, new priority value is saved to priority table , and takes effect when calling EnableIRQ.

The interrupt functions configure INTC module, application could call the INTC driver directly for the same purpose.

status_t EnableIRQWithPriority (IRQn_Type irq, uint8_t priNum)
 Enable the IRQ, and also set the interrupt priority. More...
 
status_t DisableIRQ (IRQn_Type irq)
 Disable specific interrupt. More...
 
status_t EnableIRQ (IRQn_Type irq)
 Enable specific interrupt. More...
 
status_t IRQ_SetPriority (IRQn_Type irq, uint8_t priNum)
 Set the IRQ priority. More...
 
static uint32_t DisableGlobalIRQ (void)
 Disable the global IRQ.
 
static void EnableGlobalIRQ (uint32_t irqSts)
 Enable the global IRQ.
 
static bool isIRQAllowed (void)
 Check if currently core is able to response IRQ.
 

Macro Definition Documentation

#define MAKE_STATUS (   group,
  code 
)    ((((group)*100UL) + (code)))
#define MAKE_VERSION (   major,
  minor,
  bugfix 
)    (((major) << 16) | ((minor) << 8) | (bugfix))
#define FSL_COMMON_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE   0U
#define DEBUG_CONSOLE_DEVICE_TYPE_UART   1U
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART   2U
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI   3U
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC   4U
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART   6U
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART   7U
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART   8U
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO   9U
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI   10U
#define ARRAY_SIZE (   x)    (sizeof(x) / sizeof((x)[0]))
#define SDK_DSC_DEFAULT_INT_PRIO   1U
#define SetIRQBasePriority (   x)    __EI##x()
#define PeriphReadReg (   reg)    (reg)

Example: val = PeriphReadReg(OCCS->OSCTL2);

Parameters
regRegister name.
Returns
The value of register.
#define PeriphWriteReg (   reg,
  data 
)    (reg) = (data)

Example: PeriphWriteReg(OCCS->OSCTL2, 0x278U);

Parameters
regRegister name.
dataData wrote to register.
#define PeriphSetBits (   reg,
  bitMask 
)    (reg) |= (bitMask)

Example: PeriphSetBits(OCCS->OSCTL2, 0x12U);

Parameters
regRegister name.
bitMaskBits mask, set bits will be set in the register.
#define PeriphClearBits (   reg,
  bitMask 
)    (reg) &= (~(bitMask))

Example: PeriphClearBits(OCCS->OSCTL2, 0x12U);

Parameters
regRegister name.
bitMaskBits mask, set bits will be cleared in the register.
#define PeriphInvertBits (   reg,
  bitMask 
)    (reg) ^= (bitMask)

Example: PeriphInvertBits(OCCS->OSCTL2, 0x12U);

Parameters
regRegister name.
bitMaskBits mask, set bits will be inverted in the register.
#define PeriphGetBits (   reg,
  bitMask 
)    ( (reg) & (bitMask) )

Example: val = PeriphGetBits(OCCS->OSCTL2, 0x23U);

Parameters
regRegister name.
bitMaskBits mask, specify the getting bits.
Returns
The value of specified bits.
#define PeriphWriteBitGroup (   reg,
  bitMask,
  bitValue 
)    (reg) = ((reg) & ~(bitMask)) | ((bitValue) & (bitMask))

Example: PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK, OCCS_DIVBY_COD(23U)); PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK | OCCS_DIVBY_PLLDB_MASK, \ OCCS_DIVBY_COD(23U) | OCCS_DIVBY_PLLDB(49U));

Parameters
regRegister name.
bitMaskBits mask, mask of the group of bits.
bitValueThis value will be written into the bit group specified by parameter bitMask.
#define PeriphSafeClearFlags (   reg,
  allFlagsMask,
  flagMask 
)    (reg) = ((reg) & (~(allFlagsMask))) | ((flagMask) & (allFlagsMask))

This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. Example: PeriphSafeClearFlags(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FFLAG(2));

Parameters
regRegister name.
allFlagsMaskMask for all flags which are active-high and are cleared-by-write-one.
flagMaskThe selected flags(cleared-by-write-one) which are supposed to be cleared.
#define PeriphSafeClearBits (   reg,
  allFlagsMask,
  bitMask 
)    (reg) = ((reg) & (~((allFlagsMask) | (bitMask))))

This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. Example: PeriphSafeClearBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2));

Parameters
regRegister name.
allFlagsMaskMask for all flags which are active-high and are cleared-by-write-one.
bitMaskThe selected bits which are supposed to be cleared.
#define PeriphSafeSetBits (   reg,
  allFlagsMask,
  bitMask 
)    (reg) = ((reg) & (~(allFlagsMask))) | ((bitMask) & (~(allFlagsMask)))

This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. Example: PeriphSafeSetBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2));

Parameters
regRegister name.
allFlagsMaskMask for all flags which are active-high and are cleared-by-write-one.
bitMaskThe selected bits which are supposed to be set.
#define PeriphSafeWriteBitGroup (   reg,
  allFlagsMask,
  bitMask,
  bitValue 
)    (reg) = ((reg) & (~((allFlagsMask)|(bitMask)))) | ((bitValue) & (bitMask) & (~(allFlagsMask)))

This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. Example: PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK, PWM_FSTS_FHALF(3U)); PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK | PWM_FSTS_FFULL_MASK, \ PWM_FSTS_FHALF(3U) | PWM_FSTS_FFULL(2U));

Parameters
regRegister name.
allFlagsMaskMask for all flags which are active-high and are cleared-by-write-one.
bitMaskBits mask, mask of the group of bits.
bitValueThis value will be written into the bit group specified by parameter bitMask.

Typedef Documentation

typedef int32_t status_t

Enumeration Type Documentation

Enumerator
kStatusGroup_Generic 

Group number for generic status codes.

kStatusGroup_FLASH 

Group number for FLASH status codes.

kStatusGroup_LPSPI 

Group number for LPSPI status codes.

kStatusGroup_FLEXIO_SPI 

Group number for FLEXIO SPI status codes.

kStatusGroup_DSPI 

Group number for DSPI status codes.

kStatusGroup_FLEXIO_UART 

Group number for FLEXIO UART status codes.

kStatusGroup_FLEXIO_I2C 

Group number for FLEXIO I2C status codes.

kStatusGroup_LPI2C 

Group number for LPI2C status codes.

kStatusGroup_UART 

Group number for UART status codes.

kStatusGroup_I2C 

Group number for UART status codes.

kStatusGroup_LPSCI 

Group number for LPSCI status codes.

kStatusGroup_LPUART 

Group number for LPUART status codes.

kStatusGroup_SPI 

Group number for SPI status code.

kStatusGroup_XRDC 

Group number for XRDC status code.

kStatusGroup_SEMA42 

Group number for SEMA42 status code.

kStatusGroup_SDHC 

Group number for SDHC status code.

kStatusGroup_SDMMC 

Group number for SDMMC status code.

kStatusGroup_SAI 

Group number for SAI status code.

kStatusGroup_MCG 

Group number for MCG status codes.

kStatusGroup_SCG 

Group number for SCG status codes.

kStatusGroup_SDSPI 

Group number for SDSPI status codes.

kStatusGroup_FLEXIO_I2S 

Group number for FLEXIO I2S status codes.

kStatusGroup_FLEXIO_MCULCD 

Group number for FLEXIO LCD status codes.

kStatusGroup_FLASHIAP 

Group number for FLASHIAP status codes.

kStatusGroup_FLEXCOMM_I2C 

Group number for FLEXCOMM I2C status codes.

kStatusGroup_I2S 

Group number for I2S status codes.

kStatusGroup_IUART 

Group number for IUART status codes.

kStatusGroup_CSI 

Group number for CSI status codes.

kStatusGroup_MIPI_DSI 

Group number for MIPI DSI status codes.

kStatusGroup_SDRAMC 

Group number for SDRAMC status codes.

kStatusGroup_POWER 

Group number for POWER status codes.

kStatusGroup_ENET 

Group number for ENET status codes.

kStatusGroup_PHY 

Group number for PHY status codes.

kStatusGroup_TRGMUX 

Group number for TRGMUX status codes.

kStatusGroup_SMARTCARD 

Group number for SMARTCARD status codes.

kStatusGroup_LMEM 

Group number for LMEM status codes.

kStatusGroup_QSPI 

Group number for QSPI status codes.

kStatusGroup_DMA 

Group number for DMA status codes.

kStatusGroup_EDMA 

Group number for EDMA status codes.

kStatusGroup_DMAMGR 

Group number for DMAMGR status codes.

kStatusGroup_FLEXCAN 

Group number for FlexCAN status codes.

kStatusGroup_LTC 

Group number for LTC status codes.

kStatusGroup_FLEXIO_CAMERA 

Group number for FLEXIO CAMERA status codes.

kStatusGroup_LPC_SPI 

Group number for LPC_SPI status codes.

kStatusGroup_LPC_USART 

Group number for LPC_USART status codes.

kStatusGroup_DMIC 

Group number for DMIC status codes.

kStatusGroup_SDIF 

Group number for SDIF status codes.

kStatusGroup_SPIFI 

Group number for SPIFI status codes.

kStatusGroup_OTP 

Group number for OTP status codes.

kStatusGroup_MCAN 

Group number for MCAN status codes.

kStatusGroup_CAAM 

Group number for CAAM status codes.

kStatusGroup_ECSPI 

Group number for ECSPI status codes.

kStatusGroup_USDHC 

Group number for USDHC status codes.

kStatusGroup_LPC_I2C 

Group number for LPC_I2C status codes.

kStatusGroup_DCP 

Group number for DCP status codes.

kStatusGroup_MSCAN 

Group number for MSCAN status codes.

kStatusGroup_ESAI 

Group number for ESAI status codes.

kStatusGroup_FLEXSPI 

Group number for FLEXSPI status codes.

kStatusGroup_MMDC 

Group number for MMDC status codes.

kStatusGroup_PDM 

Group number for MIC status codes.

kStatusGroup_SDMA 

Group number for SDMA status codes.

kStatusGroup_ICS 

Group number for ICS status codes.

kStatusGroup_SPDIF 

Group number for SPDIF status codes.

kStatusGroup_LPC_MINISPI 

Group number for LPC_MINISPI status codes.

kStatusGroup_HASHCRYPT 

Group number for Hashcrypt status codes.

kStatusGroup_LPC_SPI_SSP 

Group number for LPC_SPI_SSP status codes.

kStatusGroup_I3C 

Group number for I3C status codes.

kStatusGroup_LPC_I2C_1 

Group number for LPC_I2C_1 status codes.

kStatusGroup_NOTIFIER 

Group number for NOTIFIER status codes.

kStatusGroup_DebugConsole 

Group number for debug console status codes.

kStatusGroup_SEMC 

Group number for SEMC status codes.

kStatusGroup_ApplicationRangeStart 

Starting number for application groups.

kStatusGroup_IAP 

Group number for IAP status codes.

kStatusGroup_SFA 

Group number for SFA status codes.

kStatusGroup_SPC 

Group number for SPC status codes.

kStatusGroup_PUF 

Group number for PUF status codes.

kStatusGroup_QUEUEDSPI 

Group number for QUEUEDSPI status codes.

kStatusGroup_HAL_GPIO 

Group number for HAL GPIO status codes.

kStatusGroup_HAL_UART 

Group number for HAL UART status codes.

kStatusGroup_HAL_TIMER 

Group number for HAL TIMER status codes.

kStatusGroup_HAL_SPI 

Group number for HAL SPI status codes.

kStatusGroup_HAL_I2C 

Group number for HAL I2C status codes.

kStatusGroup_HAL_FLASH 

Group number for HAL FLASH status codes.

kStatusGroup_HAL_PWM 

Group number for HAL PWM status codes.

kStatusGroup_HAL_RNG 

Group number for HAL RNG status codes.

kStatusGroup_TIMERMANAGER 

Group number for TiMER MANAGER status codes.

kStatusGroup_SERIALMANAGER 

Group number for SERIAL MANAGER status codes.

kStatusGroup_LED 

Group number for LED status codes.

kStatusGroup_BUTTON 

Group number for BUTTON status codes.

kStatusGroup_EXTERN_EEPROM 

Group number for EXTERN EEPROM status codes.

kStatusGroup_SHELL 

Group number for SHELL status codes.

kStatusGroup_MEM_MANAGER 

Group number for MEM MANAGER status codes.

kStatusGroup_LIST 

Group number for List status codes.

kStatusGroup_OSA 

Group number for OSA status codes.

kStatusGroup_COMMON_TASK 

Group number for Common task status codes.

kStatusGroup_MSG 

Group number for messaging status codes.

kStatusGroup_SDK_OCOTP 

Group number for OCOTP status codes.

kStatusGroup_SDK_FLEXSPINOR 

Group number for FLEXSPINOR status codes.

kStatusGroup_CODEC 

Group number for codec status codes.

kStatusGroup_ASRC 

Group number for codec status ASRC.

kStatusGroup_OTFAD 

Group number for codec status codes.

kStatusGroup_SDIOSLV 

Group number for SDIOSLV status codes.

anonymous enum

Function Documentation

status_t EnableIRQWithPriority ( IRQn_Type  irq,
uint8_t  priNum 
)
Note
The parameter priNum is range in 1~3, and its value is NOT directly map to interrupt priority.
  • Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3
  • Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2

User should check chip's RM to get its corresponding interrupt priority.

When priNum set as 0, then SDK_DSC_DEFAULT_INT_PRIO is set instead. When priNum set as number larger than 3, then only the 2 LSB take effect, for example, setting priNum to 5 is the same with setting it to 1.

This function configures INTC module, application could call the INTC driver directly for the same purpose.

Parameters
irqThe IRQ to enable.
priNumPriority number set to interrupt controller register. Larger number means higher priority. The allowed range is 1~3, and its value is NOT directly map to interrupt priority. In other words, the same priority number means different interrupt priority levels for different IRQ, please check reference manual for the relationship. When pass in 0, then SDK_DSC_DEFAULT_INT_PRIO is set to priority register.
Returns
Currently only returns kStatus_Success, will enhance in the future.
status_t DisableIRQ ( IRQn_Type  irq)

This function configures INTC module, application could call the INTC driver directly for the same purpose.

Parameters
irqThe IRQ to disable.
Returns
Currently only returns kStatus_Success, will enhance in the future.
status_t EnableIRQ ( IRQn_Type  irq)

The recommended workflow is calling IRQ_SetPriority first, then call EnableIRQ. If IRQ_SetPriority is not called first, then the interrupt is enabled with default priority value SDK_DSC_DEFAULT_INT_PRIO.

Another recommended workflow is calling EnableIRQWithPriority directly, it is the same with calling IRQ_SetPriority + EnableIRQ.

This function configures INTC module, application could call the INTC driver directly for the same purpose.

Parameters
irqThe IRQ to enable.
Returns
Currently only returns kStatus_Success, will enhance in the future.
status_t IRQ_SetPriority ( IRQn_Type  irq,
uint8_t  priNum 
)
Note
The parameter priNum is range in 1~3, and its value is NOT directly map to interrupt priority.
  • Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3
  • Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2

User should check chip's RM to get its corresponding interrupt priority

When priNum set as 0, then SDK_DSC_DEFAULT_INT_PRIO is set instead. When priNum set as number larger than 3, then only the 2 LSB take effect, for example, setting priNum to 5 is the same with setting it to 1.

This function configures INTC module, application could call the INTC driver directly for the same purpose.

Parameters
irqThe IRQ to set.
priNumPriority number set to interrupt controller register. Larger number means higher priority, 0 means disable the interrupt. The allowed range is 0~3, and its value is NOT directly map to interrupt priority. In other words, the same priority number means different interrupt priority levels for different IRQ, please check reference manual for the relationship.
Returns
Currently only returns kStatus_Success, will enhance in the future.
void* SDK_Malloc ( size_t  size,
size_t  alignbytes 
)

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters
sizeThe length required to malloc.
alignbytesThe alignment size.
Return values
Theallocated memory.
void SDK_Free ( void *  ptr)
Parameters
ptrThe memory to be release.
void SDK_DelayCoreCycles ( uint32_t  u32Num)

Please note that, this API uses software loop for delay, the actual delayed time depends on core clock frequency, where the function is located (ram or flash), flash clock, possible interrupt.

Parameters
u32NumNumber of core clock cycle which needs to be delayed.
void SDK_DelayAtLeastUs ( uint32_t  delay_us,
uint32_t  coreClock_Hz 
)

Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters
delay_usDelay time in unit of microsecond.
coreClock_HzCore clock frequency with Hz.