Peripheral features and how this peripheral works
The 12-bit Cyclic Analog-to-Digital converter(CADC) is a dual converter 12-bit ADC in which each ADC converter has its own voltage reference and control block. The two converters are converterA and converterB.
Features
- Supports up to 16 analog input channels.
- The total 16 analog input channels are subdivided into two sets of eight(ANA[0:7] and ANB[0:7]), each with their own Sample/Hold unit and converter
- Support single-end or fully differential inputs(So platform also support unipolar differential inputs).
- Single-end
- The analog input directed to the plus terminal of the A/D core, and the minus terminal of the A/D core is connected to the Vrefl reference. The ADC measures the voltage of the selected analog input and compares it against the (Vrefh - Vrefl) reference voltage range. Calculation formula: SingleEndedValue = round(((Vin - Vrefl)/(Vrefh - Vrefl)) * 4096) * 8
- Differential The ADC measures the voltage difference between two analog inputs and compares that value against the (Vrefh - Vrefl) voltage range.
- Fully differential Fully differential conversions can swing both positive and negative. Calculation formula: FullyDifferentialValue = round((((Vin1 - Vin2) / (Vrefh - Vrefl)) * 2048) + 2048) * 8
- Unipolar differential(Chip specific) Unipolar differential conversions are only positive but uses the full code range of the ADC. Calculation formula: UnipolarDifferentialValue = round(((Vin1 - Vin2) / (Vrefh - Vrefl)) * 4096) * 8
- For some platforms, some channels can also be alternated as internal signal.
- Supports 16 sample slots basically.(There are 4 additional sample slots for some platforms.)
- Sample slot is a virtual concept to describe ADC scan mode. Normally, in sequential scan mode, ADC converts the channel assigned to sample slot0 firstly, and then the channel assigned to sample slot 1,..., and finally the channel assigned to sample slot 15. In parallel scan mode, channels assigned to sample slot 0~7 are converted in order by converterA; meanwhile, channels assigned to sample slot 8~15 are converted in order by converterB(The details of scan mode will be provided in the following sections).
- Users need to assign ADC channels to each sample slot. Same channel can be assigned to different sample slots.
- Each sample slot has its own result register, offset register. The offset register value is subtracted from the converted raw result and stored in its corresponding result register.
- Each sample slot has its own high limit and low limit registers. The converted raw result is compared with this high and low limits, and store the compare results in high and low limit status registers.
- For each sample slot, zero-crossing of the value in result register can be captured and stored in zero-crossing status register.
- Consists of two separate ADC converters.
- Dual converters can work sequentially or parallel. When work sequentially, the converterA's control setting is used to control dual converters. When work parallel, based on executing dual converters independently or not, the control setting for each converter is different. Please read the simultaneous parallel scan mode and independent parallel scan mode in the next section for details.
- ConverterA converters sample slot0-7, converterB converters sample slot8-15. (If 4 additional sample slots exist, sample slot16 and sample slot17 added to converterA, sample slot18 and sample slot19 added to converterB)
- Supports different scan modes and different scan types. A scan is the process of stepping through a subset of all sample slots, converting the channel indicated by a sample slot, and storing the result. This CADC supports 3 scan modes, and each scan mode falls into 3 types based on how they repeat.
- Scan mode:
- Sequential scan mode Upon start or when armed with an enabled SYNC signal, the scan executes all sample slots in order. It means the scan starts from sample slot0, stops at the first disabled sample slot. If no disabled sample is encountered, conversion shall be concluded after the last sample slot which is sample slot 15. If the device also supports additional 4 sample slots, after executing the sample slot 15 the scan will continue until the first disabled sample slot is encountered or when all 4 additional sample slots are completed.
- Simultaneous parallel scan mode Upon start or when armed with an enabled SYNC signal, the converterA scans from sample slot0 to sample slot7(if the device supports additional 4 sample slots, sample slot 16 and sample slot17 are added to end of this sequence) and converter B scans from sample slot8 to sample 15(if the device supports additional 4 sample slots, sample slot 18 and sample slot19 are added to end of this sequence) at the same time. The control signal of the scan (E.g. Start signal, Stop signal, Sync signal) is the signal of converterA. The scans in both converters terminate when either of the converters encounters a disabled sample slot or the last sample slot.
- Independent parallel scan mode. In this scan mode, each converter has independent control setting(E.g. Start signal, Stop signal, Sync signal). The scan for two converters can be executed independently. Upon start or when armed with an enabled SYNC signal, the converterA scans from sample slot0 to sample slot7(if the device supports additional 4 sample slots, sample slot16 and sample slot17 are added to the end of this sequence), the scan of converterA terminates when either encounters a disabled sample slot or the last sample slot. Upon start or when armed with an enabled SYNC signal, the converterB scans from sample slot8 to sample slot15(if the device supports additional 4 sample slots, sample slot18 and sample slot19 are added to the end of this sequence), the scan of converterB terminates when either encounters a disabled sample slot or the last sample slot.
- Scan type:
- Once(Single) scan In this scan type, the module executes a scan only once each time it is started.
- Loopig scan Automatically restarts a scan, as soon as the previous scan completes. If the scan mode is selected as independent parallel mode, then the converterA scan restarts as soon as the converter A scan sequence completes and the converter B scan restarts as soon as the converterB scan sequence completes. All subsequent start and sync pulses are ignored after the scan begins unless the scan is set as "Delay
sample until a new sync input occurs". The scan in this type can only be terminated by setting the STOP signal.
- Triggered scan In this scan type, if external sync is enabled, new scans start at each SYNC pulse that does not overlap with a current scan in progress.
- Supports DMA.
- DMA trigger source can be selected as trigger from end of scan interrupt or sample slot result ready bit.
- Each converter can generate DMA trigger signal.
- Supports Interrupts.
- Threshold interrupts: High limit interrupt, Low limit interrupt, zero crossing interrupt.
- Conversion complete interrupt
- Scan interrupts which are generated when a sample slot is converted.
How this peripheral works
- Connects signals to CADC's input channels pin on the board.
- Sets the scan mode of the cadc.
- Assigns the channels to sample slots.
- Upon a software start or external sync trigger, ADC starts to convert from sample slot 0. The conversion result of each sample slot is placed into the corresponding result register.
- The scan shall complete upon a disabled sample slot or otherwise upon the last sample slot.
How this driver is designed to make this peripheral works.
The cadc driver provides a structure cadc_config_t which contains major options of cadc features. The CADC_Init() function takes the argument in type of cadc_config_t, and this function can be used to configure major features of the CADC module except the high limit value, low limit value, offset value and zero crossing mode of each sample slots. After Invoking the CADC_Init() function with the related converters being powered up, upon software starting or being armed by the Sync signal, the scan will start based on the options configured. Based on the behaviour of the cadc module, the cadc driver also is divided into multiple function groups.
- Initialization and deinitialization Interfaces. The APIs in the function group can be used to initialize or de-initialize the cadc module.
- Scan related Interfaces. The APIs in this funcion group can be used to configure scan related options, including scan mode and scan control.
- Channel Control Interfaces. The APIs in this function group can be used to configure channel related options, including channel mode and channel gain.
- Sample Slot Control Interfaces. The APIs in this function group can be used to configure options of sample slots, including zero crossing mode, high limit value, low limit value and connected channel. The APIs in this function group take "eSampleIndex" as the parameter, those APIs are designed to set options for each specific sample slot.
- Converters Control Interfaces. The APIs in this function group can be used to configure converters related options, such as clock divisor, reference voltage source, converters' power, and so on. All APIs in this function group take "eConverterId" as the parameter.
- Power Control Interfaces. The APIs in this function group can be used to configure the power options of the cadc module.
- DMA Control Interfaces. The APIs in this function group can be used to set DMA features. Such as select DMA trigger source, enable/disable DMA.
- Interrupt Control Interfaces. The APIs in this function group can be used to enable/disable interrupts.
- ADC Status Flag Interfaces. The APIs in this function group can be used to get or clear the status flag of the cadc module or each sample slot.
How to use this driver
- Sets the Cyclic ADC resources by invoking CADC_Init()
- Defines the variable in type of cadc_config_t. This variable takes 80 Byte space.
- [Optional] Invokes CADC_GetDefaultConfig() function with the pointer of variable which is type of cadc_config_t to get the default options.
- Sets the member of the variable which is in type of cadc_config_t. Some members that must be configured to realize a scan are listed below.
- eScanMode: Used to set the scan mode of the converters scan. E.g. If users want to set scan mode as sequential scan mode and only scan one time. This member can be set as kCADC_ScanModeOnceSequential.
- uDisabledSampleSlot: Used to set the disabled sample slot in the scan. E.g. If users set the scan mode as once sequential mode and want to scan sample slot 0~2 only, this member can be configured as the following code shows.
* {INITSTRUCT_NAME}.uDisabledSampleSlot.eSequentialModeDisSample =
*
- u32ChannelModeMask: The mask of the channel mode, the default value is all channels are set as single-end mode. E.g. If users want to set ANA0 and ANA2 as fully differential mode and ANB0 and ANB1 as single-end mode. This member can be set as
- eSampleSlot[]: The channel that is routed to each sample slot. E.g. If the users want to route ANA0 to sample slot0, this member can be set as
- sConverterA.bPowerUp: Used to power up/down the converterA. When converterA is used, it must be powered up.
- sConverterA.u16ClockDivisor: ConverterA clock divisor for the clock source. The Available setting range is 0-63. When the clockDivisor is 0, the divisor is 2. For all other clockDivisor values, the divisor is 1 more than the decimal value of clockDivisor: clockDivisor + 1.
- sConverterB.bPowerUp: Used to power up/down the converterB. When converterB is used, it must be powered up.
- sConverterB.u16ClockDivisor: ConverterB clock divisor for the clock source. The Available setting range is 0-63. When the clockDivisor is 0, the divisor is 2. For all other clockDivisor values, the divisor is 1 more than the decimal value of clockDivisor: clockDivisor + 1
- Invokes CADC_Init() function to set CADC resources.
- [Optional] Sets sample slots data process related options
- Starts the scan
- Sends start command via CADC_DoSoftwareTriggerConverter() or armed the Sync signal to the specific converter, if the related converter is powered up, then the scan sequence will start from the converter's first sample slot and the scan sequence will complete at the disabled sample slot or the last sample slot.
- Gets the conversion result
- In case of enabled sample slot scan interrupts The interrupt will be generated when the related sample slot's ready flag is set, in the ISR use CADC_GetSampleResultValue() to get the result.
- In case of enabled DMA and the DMA trigger source selected as Sample Ready Trigger The DMA is triggered when the related sample slot's ready flag is asserted.
- In case of polling sample slot ready flag. Use the CADC_GetSampleSlotReadyStatusFlags() to poll the ready status flag. If the specific sample slot's READY flag is asserted, use CADC_GetSampleResultValue() to get the result.
- In case of enabled end of scan interupts The interrupt will be generated when the scan sequence is terminated, in the ISR use CADC_GetSampleResultValue() to get all converted sample slots' result.
Typical Use Case
- Dual converters scan sample slots sequentially. In this type of use case, dual converters use the control setting of converterA. The scan mode must be selected as sequential mode, so dual converters can be executed sequentially. In this type of use case, do remember to power up the converter which contains the channels to be sampled. If the application wants to use interrupts, please remember to enable related interrupts except that kCADC_ConversionCompleteInterrupt1Enable is useless. After started, the scan will execute from sample slot0 and will stop at the first disabled sample slot. The prototype of this type of use case is shown below.
- Dual converters scan sample slots parallel independently. In this type of use case each converter has its own control setting. The scan mode must be selected as parallel independent mode, so dual converters can work independently. The converter must be powered up if it is used to convert sample slots. If the application wants to use interrupt, please remember to enable interrupts. If converterA is started, the scan of converterA will start from sample slot0 and will stop at the first disabled sample slot. If converterB is started, the scan of converterB will start from sample slot8 and will stop at the first disabled sample slot. The prototype of this type of use case is shown below.
kCADC_convASample2Disabled;
kCADC_convBSample10Disabled;
- Dual converters scan sample slots parallel simultaneously. In this type of use case, dual converters use the control setting of converterA. The scan mode must be selected as parallel simultaneous mode, so dual converters can work simultaneously. In this type of use case do power up both the converters. If the application wants to use interrupt, please remember to enable related interrupts but please note that kCADC_ConverterBEndOfScanFlag is useless in this type of use case. If started, the scan of converterA and converterB will start from converters' first sample slot at the same time, and the scan will stop when any converter encounters the first disabled sample slot. The prototype of this type of use case is shown below.
