DAC Peripheral and Driver Overview

Peripheral features and how this peripheral works

The 12-bit digital-to-analog converter(DAC) provides a voltage reference to on-chip modules or a package pin. It can also be used as a waveform generator to generate triangle and sawtooth waveforms. The DAC module has two different operation modes, they are Normal Mode and Automatic mode. In the Normal mode, the DAC is used to convert the digital value to analog voltage, the input data is held in a data FIFO(8 words depth), the value in data FIFO is pushed to DAC analog portion for conversion on a selected edge of an input SYNC signal. In the Automatic mode, the DAC is used to generate different types of waveforms, data FIFO is disconnected from DAC analog portion in this mode, DAC output is determined by buffered STEP, MIN and MAX value registers. The SYNC signal is used to updated STEP, MIN and MAX registers from their buffers and reset the output wavefrom as well. A fast refresh signals(generated within DAC) is used to update DAC output based on STEP, MIN and MAX. The details of those operation modes will be provided in the following sections.

Features

• Supports two different types of SYNC signals. The SYNC signal is used to push the data in data FIFO to analog portion of DAC for conversion in normal mode, or update STEP, MIN, MAX registers from their buffers and reset output waveform in automatic mode. The SYNC signal can be selected from internal CLOCK signal(bus clock) or SYNC_IN signal. The SYNC_IN signal is the signal that comes from other peripherals(timers, comparators, pins, or other peripherals).
  • Clock Signal selected as SYNC signal SYNC signal is set as clock signal, so the SYNC_IN signal is useless. The value in DATA FIFO is pushed to DAC output on the next clock cycle, which means DAC output is updated almost immediately after DATA FIFO is written into. It is not recommended to use clock signal as SYNC signal in automatic mode, because it is too fast.
  • External SYNC_IN signal selected as SYNC signal SYNC_IN signal usually comes from crossbar output, which means it can be from various peripheral outputs or even pin through crossbar. SYNC_IN is often used in automatic mode, where the selected edge of SYNC_IN updates STEP, MIN and MAX registers from their buffers and also reset the output waveform to its start point defined by the new minimum and maximum value.
• Data FIFO Data written to DATA register is held in a FIFO. Based on the SYNC signal, upon the active edge of the signal(clock signal or SYNC_IN signal), the digital data contained in the FIFO is presented to the analog DAC for conversion. Reading this register returns the value of data presented to the analog DAC at that time.
• Buffered step size/minimum value/maximum value register STEP, MIN and MAX registers are buffered, and only useful in the automatic operation mode. The values written to these three registers are stored in their buffers, and the buffer values are updated to their registers at the active edge of the SYNC signal.
• Supports two different operation modes.
  • Normal operation mode to generate a voltage output In normal operation mode, the DAC receives data words via software writes or via DMA writes. The DMA is only useful in this mode.
  • Automatic operation mode to generate triangle, and sawtooth waveforms In automatic operation mode, the internal waveform generation logic will be used to generate sawtooth, triangle waveforms. In this operation mode, all waveform related options are programmable.
    1. Maximum Value The MAX register defines the upper range limit of the waveform. If the DAC input data is greater than the maximum value, the DAC's output is limited to the maximum value during automatic waveform generation.
    2. Minimum Value The MIN register defines the lower range limit of the waveform. If the DAC input data is less than the minimum value, the DAC's output is limited to the minimum value during automatic waveform generation.
    3. Step Size The STEP register value will be added or subtracted from the DAC's current data value at the rising edge of the REFRESH signal, which is to create the next value presented to the DAC inputs.
    4. REFRESH signal The REFRESH signal is used to update the internal Automatic waveform generation logic. The STEP value is added to/subtracted from the current output value every REFRESH cycle. The compare register can be used to set the frequency of REFERSH signal. If the compare value is 0, then the REFRESH signal's frequency is equal to clock's frequency which is the bus clock and the generated waveform will be updated every clock cycle. If the compare value is N, then the REFRESH signal's frequency is equal to clock's frequency divided by N+1 and the generated waveform will be updated every N+1 clock cycles.

Sawtooth waveform generation. To generate the sawtooth waveform which likes kDAC_RepeatSawtoothWaveform0, the CTRL0[UP] should be set with the CTRL0[DOWN] be cleared. To generate the sawtooth waveform which likes kDAC_RepeatSawtoothWaveform1, the CTRL0[DOWN] should be set with the CTRL0[UP] be cleared. To generate the sawtooth waveform which likes kDAC_OneShotSawtoothWaveform0, the CTRL0[UP] should be set with the CTRL0[DOWN] be cleared. CTRL0[ONESHOT] should be set. To generate the sawtooth waveform which likes kDAC_OneShotSawtoothWaveform1, the CTRL0[DOWN] should be set with the CTRL0[UP] be cleared. CTRL0[ONESHOT] should be set. Usually, SYNC signal defines the period of this waveform, while REFRESH signal defines the slope of the waveform. When oneshot is enabled, the output waveform holds the value when it reaches MAX or MIN value before the occurrence of the next SYNC signal.

1. Triangle waveform generation. To generate the triangle waveform which likes kDAC_RepeatTriangleWaveform0, the CTRL0[DOWN] should be set firstly then the CTRL0[UP] should be set. In this way, the generated waveform will rise from the starting value firstly then drop down upon reaching the maximum value. To generate the triangle waveform which likes kDAC_RepeatTriangleWaveform1, the CTRL[UP] should be set firstly then the CTRL[DOWN] should be set. In this way, the generated waveform will drop down from the starting value firstly then rise up upon reaching the minimum value.
2. Starting value The starting value of the generated waveform is programmable. Before entering Automatic operation mode, set the DAC module as Normal mode and set SYNC as clock signal, choose the active edge of SYNC signal, write the starting value to DATA register, then enter automatic mode. All the above options can be realized by invoking the DAC_Init() function.

LDOK feature STEP, MIN, and MAX registers are updated when LDOK bit equals to 1 upon the active edge of SYNC signal, and then LDOK bit is cleared automatically. This is to make sure these 3 registers are updated simultaneously.

• Supports DMA
  • When the level of FIFO is less than or equal to the watermark level value, the DMA request will be sent(if the DMA feature is enabled). And please note that the DMA is only useful when the operation mode is selected as Normal mode.

How this peripheral works

• Normal operation mode In this mode, the DAC is used to convert the digital value to analog voltage, the input data is held in a data FIFO(8 words depth), the value in data FIFO is pushed to DAC analog portion for conversion on a selected edge of an input SYNC signal.
• Automatic operation mode In this mode the internal waveform generator logic is used. The Triangle waveform example is shown below:

           Triangle Waveform:
  
                                 ____                          ____
                            ____|    |____                ____|    |____
                       ____|              |____      ____|              |
                   ___|                        |____|
  
                       _    _    _    _    _    _    _    _    _    _    _
           REFRESH:  _| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__|

  As shown above, at the rising edge of REFRESH signal, the step size is added to the current value till the maximum value is reached, then the step size is substracted from the current value till the minimum value is reached.

How this driver is designed to make this peripheral works.

This driver is designed with one DAC_Init() function and multiple register access level APIs. DAC_Init() can realize all the possible DAC configurations. Users need to invoke DAC_Init() firstly and then use other functions such as DAC_WriteDataFIFO() in the runtime.

How to use this driver

For initialization:

• Set the pin mux of the DAC output pin.
• [Optional] On some platforms the macro FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL may be defined as 1, so the DAC clock gate will not be handled in the driver. The users must make sure to enable the clock of DAC instance before using this DAC driver.
• Define a cadc_config_t type variable, such as

  dac_config_t sDacConfig;

• Invoke DAC_GetDefaultConfig(&sDacConfig) to set some default value to sDacConfig, where normal mode is enabled, SYNC signal is set as bus clock, data FIFO is set as 0.
• Configure the members in sDacConfig as desired.
• Invoke DAC_Init(DAC_BASE, &sDacConfig) to make the configuration take effect.

For runtime DAC update:

• Update DAC output.
  • Normal operation mode
    • Update the DAC output by invoking DAC_WriteDataFIFO().
  • Automatic operation mode
    • [Optional] Update the step size by invoking DAC_WriteStepSize().
    • [Optional] Update the minimum value by invoking DAC_WriteMinValue().
    • [Optional] Update the maximum value by invoking DAC_WriteMaxValue().
    • If any of these 3 registers are modified, invoke DAC_SetLDOK() to make sure buffered values of STEP/MIN/MAX are updated and used at the next active edge of SYNC signal.

Typical Use Case

1. Normal operation mode + Clock selected as SYNC signal. In this type of use case, the DAC is used to generate voltage output, and when the data is written to the DAC's DATA FIFO, the data can be almost immediately presented to the DAC output. The template of this type of use case is shown below.

   dac_config_t sDacConfig;
   DAC_GetDefaultConfig(&sDacConfig);
   sDacConfig.eOperationMode = kDAC_NormalMode;
   sDacConfig.uOperationConfig.sNormalModeConfig.u16DataFIFO = 4095;   (Each DAC LSB represent 0.806mV)
   sDacConfig.eSyncSignal = kDAC_InternalClockSignal;
   sDacConfig.bEnableAnalogPortion = true;
   DAC_Init(DACA, &sDacConfig);

   In this template, the 3.3V voltage will be generated on the DAC output pin. During runtime, invoke DAC_WriteDataFIFO() to change DAC output, such as DAC_WriteDataFIFO(DAC_BASE, 2048), where DAC outputs 1.65V.
2. Automatic operation mode + External SYNC_IN signal selected as SYNC signal. In this type of use case, the DAC is used to generate a waveform, and the SYNC_IN signal controls when the values of the buffered registers are updated. The update occurs on the active edge of the SYNC_IN signal if DAC_SetLDOK() function is invoked. The active edge of SYNC_IN will also cause the automatic waveform to be reset to its start point as defined by the new minimum value and maximum value. The SYNC_IN signal can come from a timer, comparator, pins, or other sources through the crossbar. The template of this type of use case is shown below.
   1. Initialize the DAC module with automatic operation mode and SYNC_IN signal.

      dac_config_t sDacConfig;
      DAC_GetDefaultConfig(&sDacConfig);
      sDacConfig.eOperationMode = kDAC_AutomaticOperationMode;
      sDacConfig.eSyncSignal = kDAC_ExternalSyncInSignal;
      sDacConfig.eSyncInputEdge = kDAC_RisingEdge;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.eWaveformType = kDAC_OneShotSawtoothWaveform1;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.u16MaxValue = 3000;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.u16MinValue = 1000;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.u16StepSize = 50;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.u16StartValue = 3000;
      sDacConfig.uOperationConfig.sAutomaticModeConfig.u16CompareValue = 200U;
      sDacConfig.bEnableAnalogPortion = true;
      DAC_Init(DACA, &sDacConfig);

      After this initialization, a ramping down sawtooth waveform will be generated on the DAC output pin. Supposes SYNC_IN signal is 10kHz, because REFERSH signal is configured as 500kHz(bus clock is 100MHz), the sawtooth waveform will be similar as the one shown in kDAC_OneShotSawtoothWaveform1.
   2. Update waveform(maximum value/minimum value/step size)during runtime.

      DAC_WriteStepSize(DACA, 10);
      DAC_WriteMinValue(DACA, 800);
      DAC_WriteMaxValue(DACA, 2000);
      DAC_SetLDOK(DACA);

      When the active edge of SYNC_IN signal occurs, a new sawtooth waveform will be generated on the DAC output pin.