Overview

The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.

The clock driver supports:

Clock generator (PLL, FLL, and so on) configuration
Clock mux and divider configuration
Getting clock frequency

Files
file	fsl_clock.h

Data Structures
struct	clock_arm_pll_config_t
	PLL configuration for ARM. More...

struct	clock_usb_pll_config_t
	PLL configuration for USB. More...

struct	clock_pll_ss_config_t
	Spread specturm configure Pll. More...

struct	clock_sys_pll2_config_t
	PLL configure for Sys Pll2. More...

struct	clock_sys_pll1_config_t
	PLL configure for Sys Pll1. More...

struct	clock_video_pll_config_t
	PLL configuration for AUDIO and VIDEO. More...

struct	clock_sys_pll1_gpc_config_t
	PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. More...

struct	clock_enet_pll_config_t
	PLL configuration for ENET. More...

struct	clock_root_config_t
	Clock root configuration. More...

struct	clock_root_setpoint_config_t
	Clock root configuration in SetPoint Mode. More...

Macros
#define	FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
	Configure whether driver controls clock. More...

#define	CCSR_OFFSET 0x0C
	CCM registers offset.

#define	ARM_PLL_OFFSET 0x00
	CCM Analog registers offset.

#define	CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) \| (shift))
	CCM ANALOG tuple macros to map corresponding registers and bit fields.

#define	SYS_PLL1_FREQ (1000000000U)
	SYS_PLL_FREQ frequency in Hz.

#define	LPADC_CLOCKS
	Clock gate name array for ADC. More...

#define	ADC_ETC_CLOCKS
	Clock gate name array for ADC. More...

#define	AOI_CLOCKS
	Clock gate name array for AOI. More...

#define	DCDC_CLOCKS
	Clock gate name array for DCDC. More...

#define	DCDC_CLOCKS
	Clock gate name array for DCDC. More...

#define	SRC_CLOCKS
	Clock gate name array for SRC. More...

#define	GPC_CLOCKS
	Clock gate name array for GPC. More...

#define	SSARC_CLOCKS
	Clock gate name array for SSARC. More...

#define	WDOG_CLOCKS
	Clock gate name array for WDOG. More...

#define	EWM_CLOCKS
	Clock gate name array for EWM. More...

#define	SEMA_CLOCKS
	Clock gate name array for Sema. More...

#define	MU_CLOCKS
	Clock gate name array for MU. More...

#define	EDMA_CLOCKS
	Clock gate name array for EDMA. More...

#define	FLEXRAM_CLOCKS
	Clock gate name array for FLEXRAM. More...

#define	LMEM_CLOCKS
	Clock gate name array for LMEM. More...

#define	FLEXSPI_CLOCKS
	Clock gate name array for FLEXSPI. More...

#define	RDC_CLOCKS
	Clock gate name array for RDC. More...

#define	SEMC_CLOCKS
	Clock ip name array for SEMC. More...

#define	XECC_CLOCKS
	Clock ip name array for XECC. More...

#define	IEE_CLOCKS
	Clock ip name array for IEE. More...

#define	KEYMANAGER_CLOCKS
	Clock ip name array for KEY_MANAGER. More...

#define	PUF_CLOCKS
	Clock ip name array for PUF. More...

#define	OCOTP_CLOCKS
	Clock ip name array for OCOTP. More...

#define	CAAM_CLOCKS
	Clock ip name array for CAAM. More...

#define	XBAR_CLOCKS
	Clock ip name array for XBAR. More...

#define	IOMUXC_CLOCKS
	Clock ip name array for IOMUXC. More...

#define	GPIO_CLOCKS
	Clock ip name array for GPIO. More...

#define	KPP_CLOCKS
	Clock ip name array for KPP. More...

#define	FLEXIO_CLOCKS
	Clock ip name array for FLEXIO. More...

#define	DAC_CLOCKS
	Clock ip name array for DAC. More...

#define	CMP_CLOCKS
	Clock ip name array for CMP. More...

#define	PIT_CLOCKS
	Clock ip name array for PIT. More...

#define	GPT_CLOCKS
	Clock ip name array for GPT. More...

#define	TMR_CLOCKS
	Clock ip name array for QTIMER. More...

#define	ENC_CLOCKS
	Clock ip name array for ENC. More...

#define	PWM_CLOCKS
	Clock ip name array for PWM. More...

#define	FLEXCAN_CLOCKS
	Clock ip name array for FLEXCAN. More...

#define	LPUART_CLOCKS
	Clock ip name array for LPUART. More...

#define	LPI2C_CLOCKS
	Clock ip name array for LPI2C. More...

#define	LPSPI_CLOCKS
	Clock ip name array for LPSPI. More...

#define	EMVSIM_CLOCKS
	Clock ip name array for EMVSIM. More...

#define	ENET_CLOCKS
	Clock ip name array for ENET. More...

#define	ENETQOS_CLOCKS
	Clock ip name array for ENET_QOS. More...

#define	USB_CLOCKS
	Clock ip name array for USB. More...

#define	CDOG_CLOCKS
	Clock ip name array for CDOG. More...

#define	USDHC_CLOCKS
	Clock ip name array for USDHC. More...

#define	ASRC_CLOCKS
	Clock ip name array for ASRC. More...

#define	MQS_CLOCKS
	Clock ip name array for MQS. More...

#define	PDM_CLOCKS
	Clock ip name array for PDM. More...

#define	SPDIF_CLOCKS
	Clock ip name array for SPDIF. More...

#define	SAI_CLOCKS
	Clock ip name array for SAI. More...

#define	PXP_CLOCKS
	Clock ip name array for PXP. More...

#define	GPU2D_CLOCKS
	Clock ip name array for GPU2d. More...

#define	LCDIF_CLOCKS
	Clock ip name array for LCDIF. More...

#define	LCDIFV2_CLOCKS
	Clock ip name array for LCDIFV2. More...

#define	MIPI_DSI_HOST_CLOCKS
	Clock ip name array for MIPI_DSI. More...

#define	MIPI_CSI2RX_CLOCKS
	Clock ip name array for MIPI_CSI. More...

#define	CSI_CLOCKS
	Clock ip name array for CSI. More...

#define	DCIC_CLOCKS
	Clock ip name array for DCIC. More...

#define	DMAMUX_CLOCKS
	Clock ip name array for DMAMUX_CLOCKS. More...

#define	XBARA_CLOCKS
	Clock ip name array for XBARA. More...

#define	XBARB_CLOCKS
	Clock ip name array for XBARB. More...

#define	CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq
	For compatible with other platforms without CCM. More...

Enumerations
enum	clock_root_mux_source_t
	The enumerator of clock roots' clock source mux value.

enum	clock_osc_t { kCLOCK_RcOsc = 0U, kCLOCK_XtalOsc = 1U }
	OSC 24M sorce select. More...

enum	clock_gate_value_t { kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK }
	Clock gate value. More...

enum	clock_mode_t { kCLOCK_ModeRun = 0U, kCLOCK_ModeWait = 1U, kCLOCK_ModeStop = 2U }
	System clock mode. More...

enum	clock_usb_src_t { kCLOCK_Usb480M = 0, kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
	USB clock source definition. More...

enum	clock_usb_phy_src_t { kCLOCK_Usbphy480M = 0 }
	Source of the USB HS PHY. More...

enum	_clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, kCLOCK_PllSrcClkPN = 1U }
	PLL clock source, bypass cloco source also. More...

enum	clock_pll_post_div_t { kCLOCK_PllPostDiv2 = 0U, kCLOCK_PllPostDiv4 = 1U, kCLOCK_PllPostDiv8 = 2U, kCLOCK_PllPostDiv1 = 3U }

enum	clock_pll_t
	PLL name.

enum	clock_pfd_t { kCLOCK_Pfd0 = 0U, kCLOCK_Pfd1 = 1U, kCLOCK_Pfd2 = 2U, kCLOCK_Pfd3 = 3U }
	PLL PFD name. More...

enum	clock_control_mode_t { kCLOCK_SoftwareMode = 0U, kCLOCK_GpcMode }
	The enumeration of control mode. More...

enum	clock_24MOsc_mode_t { kCLOCK_24MOscHighGainMode = 0U, kCLOCK_24MOscBypassMode = 1U, kCLOCK_24MOscLowPowerMode = 2U }
	The enumeration of 24MHz crystal oscillator mode. More...

enum	clock_16MOsc_source_t { kCLOCK_16MOscSourceFrom16MOsc = 0U, kCLOCK_16MOscSourceFrom24MOsc = 1U }
	The enumeration of 16MHz RC oscillator clock source. More...

enum	clock_1MHzOut_behavior_t { kCLOCK_1MHzOutDisable = 0U, kCLOCK_1MHzOutEnableLocked1Mhz = 1U, kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U }
	The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. More...

enum	clock_level_t { kCLOCK_Level0 = 0x0UL, kCLOCK_Level1 = 0x1UL, kCLOCK_Level2 = 0x2UL, kCLOCK_Level3 = 0x3UL, kCLOCK_Level4 = 0x4UL }
	The clock dependence level. More...

Functions
static void	CLOCK_SetRootClockMux (clock_root_t root, uint8_t src)
	Set CCM Root Clock MUX node to certain value. More...

static uint32_t	CLOCK_GetRootClockMux (clock_root_t root)
	Get CCM Root Clock MUX value. More...

static clock_name_t	CLOCK_GetRootClockSource (clock_root_t root, uint32_t src)
	Get CCM Root Clock Source. More...

static void	CLOCK_SetRootClockDiv (clock_root_t root, uint8_t div)
	Set CCM Root Clock DIV certain value. More...

static uint32_t	CLOCK_GetRootClockDiv (clock_root_t root)
	Get CCM DIV node value. More...

static void	CLOCK_PowerOffRootClock (clock_root_t root)
	Power Off Root Clock. More...

static void	CLOCK_PowerOnRootClock (clock_root_t root)
	Power On Root Clock. More...

static void	CLOCK_SetRootClock (clock_root_t root, const clock_root_config_t *config)
	Configure Root Clock. More...

static void	CLOCK_ControlGate (clock_ip_name_t name, clock_gate_value_t value)
	Control the clock gate for specific IP. More...

static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP. More...

static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP. More...

void	CLOCK_SetGroupConfig (clock_group_t group, const clock_group_config_t *config)
	Set the clock group configuration. More...

uint32_t	CLOCK_GetFreq (clock_name_t name)
	Gets the clock frequency for a specific clock name. More...

static uint32_t	CLOCK_GetRootClockFreq (clock_root_t root)
	Gets the clock frequency for a specific root clock name. More...

static uint32_t	CLOCK_GetM7Freq (void)
	Get the CCM CPU/core/system frequency. More...

static uint32_t	CLOCK_GetM4Freq (void)
	Get the CCM CPU/core/system frequency. More...

static bool	CLOCK_IsPllBypassed (clock_pll_t pll)
	Check if PLL is bypassed. More...

static bool	CLOCK_IsPllEnabled (clock_pll_t pll)
	Check if PLL is enabled. More...

void	CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
	Initialize the ARM PLL. More...

status_t	CLOCK_CalcArmPllFreq (clock_arm_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitArmPllWithFreq (uint32_t freqInMhz)
	Initializes the Arm PLL with Specific Frequency (in Mhz). More...

void	CLOCK_DeinitArmPll (void)
	De-initialize the ARM PLL.

void	CLOCK_CalcPllSpreadSpectrum (uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
	Calculate spread spectrum step and stop. More...

void	CLOCK_InitSysPll1 (const clock_sys_pll1_config_t *config)
	Initialize the System PLL1. More...

void	CLOCK_DeinitSysPll1 (void)
	De-initialize the System PLL1.

void	CLOCK_GPC_SetSysPll1OutputFreq (const clock_sys_pll1_gpc_config_t *config)
	Set System PLL1 output frequency in GPC mode. More...

void	CLOCK_InitSysPll2 (const clock_sys_pll2_config_t *config)
	Initialize the System PLL2. More...

void	CLOCK_DeinitSysPll2 (void)
	De-initialize the System PLL2.

void	CLOCK_InitSysPll3 (void)
	Initialize the System PLL3. More...

void	CLOCK_DeinitSysPll3 (void)
	De-initialize the System PLL3.

Driver version
#define	FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
	CLOCK driver version. More...

#define	SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)

OSC operations
void	CLOCK_InitExternalClk (bool bypassXtalOsc)
	Initialize the external 24MHz clock. More...

void	CLOCK_DeinitExternalClk (void)
	Deinitialize the external 24MHz clock. More...

void	CLOCK_SwitchOsc (clock_osc_t osc)
	Switch the OSC. More...

static uint32_t	CLOCK_GetRtcFreq (void)
	Gets the RTC clock frequency. More...

static void	CLOCK_OSC_SetOsc48MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 48MHz RC oscillator. More...

static void	CLOCK_OSC_EnableOsc48M (bool enable)
	Enable/disable 48MHz RC oscillator. More...

static void	CLOCK_OSC_SetOsc48MDiv2ControlMode (clock_control_mode_t controlMode)
	Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator. More...

static void	CLOCK_OSC_EnableOsc48MDiv2 (bool enable)
	Enable/disable the 24MHz clock sourced from 48MHz RC oscillator. More...

static void	CLOCK_OSC_SetOsc24MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 24MHz crystal oscillator. More...

void	CLOCK_OSC_EnableOsc24M (void)
	Enable OSC 24Mhz. More...

static void	CLOCK_OSC_GateOsc24M (bool enableGate)
	Gate/ungate the 24MHz crystal oscillator output. More...

void	CLOCK_OSC_SetOsc24MWorkMode (clock_24MOsc_mode_t workMode)
	Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode. More...

static void	CLOCK_OSC_SetOscRc400MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 400MHz RC oscillator. More...

void	CLOCK_OSC_EnableOscRc400M (void)
	Enable OSC RC 400Mhz. More...

static void	CLOCK_OSC_GateOscRc400M (bool enableGate)
	Gate/ungate 400MHz RC oscillator. More...

void	CLOCK_OSC_TrimOscRc400M (bool enable, bool bypass, uint16_t trim)
	Trims OSC RC 400MHz. More...

void	CLOCK_OSC_SetOscRc400MRefClkDiv (uint8_t divValue)
	Set the divide value for ref_clk to generate slow clock. More...

void	CLOCK_OSC_SetOscRc400MFastClkCount (uint16_t targetCount)
	Set the target count for the fast clock. More...

void	CLOCK_OSC_SetOscRc400MHysteresisValue (uint8_t negHysteresis, uint8_t posHysteresis)
	Set the negative and positive hysteresis value for the tuned clock. More...

void	CLOCK_OSC_BypassOscRc400MTuneLogic (bool enableBypass)
	Bypass/un-bypass the tune logic. More...

void	CLOCK_OSC_EnableOscRc400MTuneLogic (bool enable)
	Start/Stop the tune logic. More...

void	CLOCK_OSC_FreezeOscRc400MTuneValue (bool enableFreeze)
	Freeze/Unfreeze the tuning value. More...

void	CLOCK_OSC_SetOscRc400MTuneValue (uint8_t tuneValue)
	Set the 400MHz RC oscillator tune value when the tune logic is disabled. More...

void	CLOCK_OSC_Set1MHzOutputBehavior (clock_1MHzOut_behavior_t behavior)
	Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output. More...

void	CLOCK_OSC_SetLocked1MHzCount (uint16_t count)
	Set the count for the locked 1MHz clock out. More...

bool	CLOCK_OSC_CheckLocked1MHzErrorFlag (void)
	Check the error flag for locked 1MHz clock out. More...

void	CLOCK_OSC_ClearLocked1MHzErrorFlag (void)
	Clear the error flag for locked 1MHz clock out.

uint16_t	CLOCK_OSC_GetCurrentOscRc400MFastClockCount (void)
	Get current count for the fast clock during the tune process. More...

uint8_t	CLOCK_OSC_GetCurrentOscRc400MTuneValue (void)
	Get current tune value used by oscillator during tune process. More...

static void	CLOCK_OSC_SetOsc16MControlMode (clock_control_mode_t controlMode)
	Set the control mode of 16MHz crystal oscillator. More...

void	CLOCK_OSC_SetOsc16MConfig (clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)
	Configure the 16MHz oscillator. More...

PLL/PFD operations
void	CLOCK_SetPllBypass (clock_pll_t pll, bool bypass)
	PLL bypass setting. More...

status_t	CLOCK_CalcAvPllFreq (clock_av_pll_config_t *config, uint32_t freqInMhz)
	Calculate corresponding config values per given frequency. More...

status_t	CLOCK_InitAudioPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Audio PLL with Specific Frequency (in Mhz). More...

void	CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
	Initializes the Audio PLL. More...

void	CLOCK_DeinitAudioPll (void)
	De-initialize the Audio PLL.

void	CLOCK_GPC_SetAudioPllOutputFreq (const clock_audio_pll_gpc_config_t *config)
	Set Audio PLL output frequency in GPC mode. More...

status_t	CLOCK_InitVideoPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
	Initializes the Video PLL with Specific Frequency (in Mhz). More...

void	CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
	Initialize the video PLL. More...

void	CLOCK_DeinitVideoPll (void)
	De-initialize the Video PLL.

void	CLOCK_GPC_SetVideoPllOutputFreq (const clock_video_pll_gpc_config_t *config)
	Set Video PLL output frequency in GPC mode. More...

uint32_t	CLOCK_GetPllFreq (clock_pll_t pll)
	Get current PLL output frequency. More...

void	CLOCK_InitPfd (clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
	Initialize PLL PFD. More...

uint32_t	CLOCK_GetPfdFreq (clock_pll_t pll, clock_pfd_t pfd)
	Get current PFD output frequency. More...

uint32_t	CLOCK_GetFreqFromObs (uint32_t obsSigIndex, uint32_t obsIndex)

bool	CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
	Enable USB HS clock. More...

bool	CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs0PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

bool	CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
	Enable USB HS PHY PLL clock. More...

void	CLOCK_DisableUsbhs1PhyPllClock (void)
	Disable USB HS PHY PLL clock. More...

static void	CLOCK_OSCPLL_LockControlMode (clock_name_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_OSCPLL_LockWhiteList (clock_name_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_OSCPLL_SetWhiteList (clock_name_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_OSCPLL_IsSetPointImplemented (clock_name_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_OSCPLL_ControlByUnassignedMode (clock_name_t name)
	Set this clock works in Unassigned Mode. More...

void	CLOCK_OSCPLL_ControlBySetPointMode (clock_name_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode. More...

void	CLOCK_OSCPLL_ControlByCpuLowPowerMode (clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_OSCPLL_SetCurrentClockLevel (clock_name_t name, clock_level_t level)
	Set clock depend level for current accessing domain. More...

static void	CLOCK_OSCPLL_ControlByDomainMode (clock_name_t name, uint8_t domainId)
	Set this clock works in Domain Mode. More...

static void	CLOCK_ROOT_LockControlMode (clock_root_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_ROOT_LockWhiteList (clock_root_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_ROOT_SetWhiteList (clock_root_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_ROOT_IsSetPointImplemented (clock_root_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_ROOT_ControlByUnassignedMode (clock_root_t name)
	Set this clock works in Unassigned Mode. More...

static void	CLOCK_ROOT_ConfigSetPoint (clock_root_t name, uint16_t spIndex, const clock_root_setpoint_config_t *config)
	Configure one SetPoint for this clock. More...

static void	CLOCK_ROOT_EnableSetPointControl (clock_root_t name)
	Enable SetPoint control for this clock root. More...

void	CLOCK_ROOT_ControlBySetPointMode (clock_root_t name, const clock_root_setpoint_config_t *spTable)
	Set this clock works in SetPoint controlled Mode. More...

static void	CLOCK_ROOT_ControlByDomainMode (clock_root_t name, uint8_t domainId)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_LPCG_LockControlMode (clock_lpcg_t name)
	Lock low power and access control mode for this clock. More...

static void	CLOCK_LPCG_LockWhiteList (clock_lpcg_t name)
	Lock the value of Domain ID white list for this clock. More...

static void	CLOCK_LPCG_SetWhiteList (clock_lpcg_t name, uint8_t domainId)
	Set domain ID that can change this clock. More...

static bool	CLOCK_LPCG_IsSetPointImplemented (clock_lpcg_t name)
	Check whether this clock implement SetPoint control scheme. More...

static void	CLOCK_LPCG_ControlByUnassignedMode (clock_lpcg_t name)
	Set this clock works in Unassigned Mode. More...

void	CLOCK_LPCG_ControlBySetPointMode (clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)
	Set this clock works in SetPoint control Mode. More...

void	CLOCK_LPCG_ControlByCpuLowPowerMode (clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
	Set this clock works in CPU Low Power Mode. More...

static void	CLOCK_LPCG_SetCurrentClockLevel (clock_lpcg_t name, clock_level_t level)
	Set clock depend level for current accessing domain. More...

static void	CLOCK_LPCG_ControlByDomainMode (clock_lpcg_t name, uint8_t domainId)
	Set this clock works in Domain Mode. More...

Data Structure Documentation

struct clock_arm_pll_config_t

The output clock frequency is:

Fout=Fin*loopDivider /(2 * postDivider).

Fin is always 24MHz.

Data Fields
clock_pll_post_div_t	postDivider
	Post divider. More...

uint32_t	loopDivider
	PLL loop divider. More...

Field Documentation

clock_pll_post_div_t clock_arm_pll_config_t::postDivider

uint32_t clock_arm_pll_config_t::loopDivider

Valid range: 104-208.

struct clock_usb_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

Field Documentation

uint8_t clock_usb_pll_config_t::loopDivider

0 - Fout=Fref*20; 1 - Fout=Fref*22

struct clock_pll_ss_config_t

Data Fields
uint16_t	stop
	Spread spectrum stop value to get frequency change. More...

uint16_t	step
	Spread spectrum step value to get frequency change step. More...

Field Documentation

uint16_t clock_pll_ss_config_t::stop

uint16_t clock_pll_ss_config_t::step

struct clock_sys_pll2_config_t

Data Fields
uint32_t	mfd
	Denominator of spread spectrum.

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

struct clock_sys_pll1_config_t

Data Fields
bool	pllDiv2En
	Enable Sys Pll1 divide-by-2 clock or not. More...

bool	pllDiv5En
	Enable Sys Pll1 divide-by-5 clock or not. More...

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

bool clock_sys_pll1_config_t::pllDiv2En

bool clock_sys_pll1_config_t::pllDiv5En

struct clock_video_pll_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint8_t	postDivider
	Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

uint8_t clock_video_pll_config_t::loopDivider

Valid range for DIV_SELECT divider value: 27~54.

uint8_t clock_video_pll_config_t::postDivider

uint32_t clock_video_pll_config_t::numerator

struct clock_sys_pll1_gpc_config_t

Data Fields
uint8_t	loopDivider
	PLL loop divider. More...

uint32_t	numerator
	30 bit numerator of fractional loop divider. More...

uint32_t	denominator
	30 bit denominator of fractional loop divider

clock_pll_ss_config_t *	ss
	Spread spectrum parameter, it can be NULL, if ssEnable is set to false.

bool	ssEnable
	Enable spread spectrum flag.

Field Documentation

uint8_t clock_sys_pll1_gpc_config_t::loopDivider

uint32_t clock_sys_pll1_gpc_config_t::numerator

struct clock_enet_pll_config_t

Data Fields
bool	enableClkOutput
	Power on and enable PLL clock output for ENET0 (ref_enetpll0). More...

bool	enableClkOutput25M
	Power on and enable PLL clock output for ENET2 (ref_enetpll2). More...

uint8_t	loopDivider
	Controls the frequency of the ENET0 reference clock. More...

uint8_t	src
	Pll clock source, reference _clock_pll_clk_src.

bool	enableClkOutput1
	Power on and enable PLL clock output for ENET1 (ref_enetpll1). More...

uint8_t	loopDivider1
	Controls the frequency of the ENET1 reference clock. More...

Field Documentation

bool clock_enet_pll_config_t::enableClkOutput

bool clock_enet_pll_config_t::enableClkOutput25M

uint8_t clock_enet_pll_config_t::loopDivider

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

bool clock_enet_pll_config_t::enableClkOutput1

uint8_t clock_enet_pll_config_t::loopDivider1

b00 25MHz b01 50MHz b10 100MHz (not 50% duty cycle) b11 125MHz

struct clock_root_config_t

Data Fields
uint8_t	mux
	See clock_root_mux_source_t for details. More...

uint8_t	div
	it's the actual divider

Field Documentation

uint8_t clock_root_config_t::mux

struct clock_root_setpoint_config_t

Data Fields
uint8_t	grade
	Indicate speed grade for each SetPoint.

uint8_t	mux
	See clock_root_mux_source_t for details. More...

uint8_t	div
	it's the actual divider

Field Documentation

uint8_t clock_root_setpoint_config_t::mux

Macro Definition Documentation

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note: All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))

#define LPADC_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
    }

#define ADC_ETC_CLOCKS

Value:

{                  \
        kCLOCK_Adc_Etc \
    }

#define AOI_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
    }

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

#define DCDC_CLOCKS

Value:

{               \
        kCLOCK_Dcdc \
    }

Clock ip name array for DCDC.

#define SRC_CLOCKS

Value:

{              \
        kCLOCK_Src \
    }

#define GPC_CLOCKS

Value:

{              \
        kCLOCK_Gpc \
    }

#define SSARC_CLOCKS

Value:

{                \
        kCLOCK_Ssarc \
    }

#define WDOG_CLOCKS

Value:

{                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
    }

#define EWM_CLOCKS

Value:

{               \
        kCLOCK_Ewm0 \
    }

#define SEMA_CLOCKS

Value:

{               \
        kCLOCK_Sema \
    }

#define MU_CLOCKS

Value:

{               \
        kCLOCK_Mu_B \
    }

#define EDMA_CLOCKS

Value:

{                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

#define FLEXRAM_CLOCKS

Value:

{                  \
        kCLOCK_Flexram \
    }

#define LMEM_CLOCKS

Value:

{               \
        kCLOCK_Lmem \
    }

#define FLEXSPI_CLOCKS

Value:

{                                                      \
        kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
    }

#define RDC_CLOCKS

Value:

{                                              \
        kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
    }

#define SEMC_CLOCKS

Value:

{               \
        kCLOCK_Semc \
    }

#define XECC_CLOCKS

Value:

{               \
        kCLOCK_Xecc \
    }

#define IEE_CLOCKS

Value:

{              \
        kCLOCK_Iee \
    }

#define KEYMANAGER_CLOCKS

Value:

{                      \
        kCLOCK_Key_Manager \
    }

#define PUF_CLOCKS

Value:

{              \
        kCLOCK_Puf \
    }

#define OCOTP_CLOCKS

Value:

{                \
        kCLOCK_Ocotp \
    }

#define CAAM_CLOCKS

Value:

{               \
        kCLOCK_Caam \
    }

#define XBAR_CLOCKS

Value:

{                                                              \
        kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

#define IOMUXC_CLOCKS

Value:

{                                     \
        kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
    }

#define GPIO_CLOCKS

Value:

{                                                                                                                \
        kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
            kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio,                            \
    }

#define KPP_CLOCKS

Value:

{              \
        kCLOCK_Kpp \
    }

#define FLEXIO_CLOCKS

Value:

{                                                    \
        kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
    }

#define DAC_CLOCKS

Value:

{              \
        kCLOCK_Dac \
    }

#define CMP_CLOCKS

Value:

{                                                                            \
        kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
    }

#define PIT_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
    }

#define GPT_CLOCKS

Value:

{                                                                                                  \
        kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
    }

#define TMR_CLOCKS

Value:

{                                                                                    \
        kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
    }

#define ENC_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
    }

#define PWM_CLOCKS

Value:

{                                                                             \
        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
        {                                                                         \
            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
        }                                                                         \
    }

#define FLEXCAN_CLOCKS

Value:

{                                                           \
        kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
    }

#define LPUART_CLOCKS

Value:

{                                                                                                         \
        kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
            kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
            kCLOCK_Lpuart12                                                                                   \
    }

#define LPI2C_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
    }

#define LPSPI_CLOCKS

Value:

{                                                                                                              \
        kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
    }

#define EMVSIM_CLOCKS

Value:

{                                              \
        kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
    }

#define ENET_CLOCKS

Value:

{                               \
        kCLOCK_Enet, kCLOCK_Enet_1g \
    }

#define ENETQOS_CLOCKS

Value:

{                   \
        kCLOCK_Enet_Qos \
    }

#define USB_CLOCKS

Value:

{              \
        kCLOCK_Usb \
    }

#define CDOG_CLOCKS

Value:

{               \
        kCLOCK_Cdog \
    }

#define USDHC_CLOCKS

Value:

{                                                  \
        kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
    }

#define ASRC_CLOCKS

Value:

{               \
        kCLOCK_Asrc \
    }

#define MQS_CLOCKS

Value:

{              \
        kCLOCK_Mqs \
    }

#define PDM_CLOCKS

Value:

{              \
        kCLOCK_Pdm \
    }

#define SPDIF_CLOCKS

Value:

{                \
        kCLOCK_Spdif \
    }

#define SAI_CLOCKS

Value:

{                                                                        \
        kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
    }

#define PXP_CLOCKS

Value:

{              \
        kCLOCK_Pxp \
    }

#define GPU2D_CLOCKS

Value:

{                \
        kCLOCK_Gpu2d \
    }

#define LCDIF_CLOCKS

Value:

{                \
        kCLOCK_Lcdif \
    }

#define LCDIFV2_CLOCKS

Value:

{                  \
        kCLOCK_Lcdifv2 \
    }

#define MIPI_DSI_HOST_CLOCKS

Value:

{                        \
        kCLOCK_Mipi_Dsi      \
    }

#define MIPI_CSI2RX_CLOCKS

Value:

{                      \
        kCLOCK_Mipi_Csi    \
    }

#define CSI_CLOCKS

Value:

{              \
        kCLOCK_Csi \
    }

#define DCIC_CLOCKS

Value:

{                                                       \
        kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
    }

#define DMAMUX_CLOCKS

Value:

{                                 \
        kCLOCK_Edma, kCLOCK_Edma_Lpsr \
    }

#define XBARA_CLOCKS

Value:

{                \
        kCLOCK_Xbar1 \
    }

#define XBARB_CLOCKS

Value:

{                                                                  \
        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
    }

#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq

Enumeration Type Documentation

enum clock_osc_t

Enumerator
kCLOCK_RcOsc	On chip OSC.
kCLOCK_XtalOsc	24M Xtal OSC

enum clock_gate_value_t

Enumerator
kCLOCK_Off	Clock is off.
kCLOCK_On	Clock is on.

enum clock_mode_t

Enumerator
kCLOCK_ModeRun	Remain in run mode.
kCLOCK_ModeWait	Transfer to wait mode.
kCLOCK_ModeStop	Transfer to stop mode.

enum clock_usb_src_t

Enumerator
kCLOCK_Usb480M	Use 480M.
kCLOCK_UsbSrcUnused	Used when the function does not care the clock source.

enum clock_usb_phy_src_t

Enumerator
kCLOCK_Usbphy480M	Use 480M.

enum _clock_pll_clk_src

Enumerator
kCLOCK_PllClkSrc24M	Pll clock source 24M.
kCLOCK_PllSrcClkPN	Pll clock source CLK1_P and CLK1_N.

enum clock_pll_post_div_t

Enumerator
kCLOCK_PllPostDiv2	Divide by 2.
kCLOCK_PllPostDiv4	Divide by 4.
kCLOCK_PllPostDiv8	Divide by 8.
kCLOCK_PllPostDiv1	Divide by 1.

enum clock_pfd_t

Enumerator
kCLOCK_Pfd0	PLL PFD0.
kCLOCK_Pfd1	PLL PFD1.
kCLOCK_Pfd2	PLL PFD2.
kCLOCK_Pfd3	PLL PFD3.

enum clock_control_mode_t

Enumerator
kCLOCK_SoftwareMode	Software control mode.
kCLOCK_GpcMode	GPC control mode.

enum clock_24MOsc_mode_t

Enumerator
kCLOCK_24MOscHighGainMode	24MHz crystal oscillator work as high gain mode.
kCLOCK_24MOscBypassMode	24MHz crystal oscillator work as bypass mode.
kCLOCK_24MOscLowPowerMode	24MHz crystal oscillator work as low power mode.

enum clock_16MOsc_source_t

Enumerator
kCLOCK_16MOscSourceFrom16MOsc	Source from 16MHz RC oscialltor.
kCLOCK_16MOscSourceFrom24MOsc	Source from 24MHz crystal oscillator.

enum clock_1MHzOut_behavior_t

Enumerator
kCLOCK_1MHzOutDisable	Disable 1MHz output clock.
kCLOCK_1MHzOutEnableLocked1Mhz	Enable 1MHz output clock, and select locked 1MHz to output.
kCLOCK_1MHzOutEnableFreeRunning1Mhz	Enable 1MHZ output clock, and select free-running 1MHz to output.

enum clock_level_t

Enumerator
kCLOCK_Level0	Not needed in any mode.
kCLOCK_Level1	Needed in RUN mode.
kCLOCK_Level2	Needed in RUN and WAIT mode.
kCLOCK_Level3	Needed in RUN, WAIT and STOP mode.
kCLOCK_Level4	Always on in any mode.

Function Documentation

static void CLOCK_SetRootClockMux	(	clock_root_t	root,
		uint8_t	src
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
src	Clock mux value to set, different mux has different value range. See clock_root_mux_source_t.

static uint32_t CLOCK_GetRootClockMux ( clock_root_t root )

inlinestatic

Parameters

mux	Which mux node to get, see clock_mux_t.

Returns: Clock mux value.

static clock_name_t CLOCK_GetRootClockSource	(	clock_root_t	root,
		uint32_t	src
	)

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.
src	Clock mux value to get, see clock_root_mux_source_t.

Returns: Clock source

static void CLOCK_SetRootClockDiv	(	clock_root_t	root,
		uint8_t	div
	)

inlinestatic

Parameters

root	Which root clock to set, see clock_root_t.
div	Clock div value to set, different divider has different value range.

static uint32_t CLOCK_GetRootClockDiv ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to get, see clock_root_t.

Returns: divider set for this root

static void CLOCK_PowerOffRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_PowerOnRootClock ( clock_root_t root )

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.

static void CLOCK_SetRootClock	(	clock_root_t	root,
		const clock_root_config_t *	config
	)

inlinestatic

Parameters

root	Which root clock node to set, see clock_root_t.
config	root clock config, see clock_root_config_t

static void CLOCK_ControlGate	(	clock_ip_name_t	name,
		clock_gate_value_t	value
	)

inlinestatic

Note: This API will not have any effect when this clock is in CPULPM or SetPoint Mode

Parameters

name	Which clock to enable, see clock_ip_name_t.
value	Clock gate value to set, see clock_gate_value_t.

static void CLOCK_EnableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to enable, see clock_ip_name_t.

static void CLOCK_DisableClock ( clock_ip_name_t name )

inlinestatic

Parameters

name	Which clock to disable, see clock_ip_name_t.

void CLOCK_SetGroupConfig	(	clock_group_t	group,
		const clock_group_config_t *	config
	)

Parameters

group	Which group to configure, see clock_group_t.
config	Configuration to set.

uint32_t CLOCK_GetFreq ( clock_name_t name )

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName Clock names defined in clock_name_t

Returns: Clock frequency value in hertz

static uint32_t CLOCK_GetRootClockFreq ( clock_root_t root )

inlinestatic

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_root_t.

Parameters

clockName Clock names defined in clock_root_t

Returns: Clock frequency value in hertz

static uint32_t CLOCK_GetM7Freq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static uint32_t CLOCK_GetM4Freq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static bool CLOCK_IsPllBypassed ( clock_pll_t pll )

inlinestatic

Parameters

base	CCM_ANALOG base pointer.
pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is bypassed.
false: The PLL is not bypassed.

static bool CLOCK_IsPllEnabled ( clock_pll_t pll )

inlinestatic

Parameters

pll	PLL control name (see clock_pll_t enumeration)

Returns

PLL bypass status.

true: The PLL is enabled.
false: The PLL is not enabled.

void CLOCK_InitExternalClk ( bool bypassXtalOsc )

This function supports two modes:

Use external crystal oscillator.
Bypass the external crystal oscillator, using input source clock directly.

After this function, please call CLOCK_SetXtal0Freq to inform clock driver the external clock frequency.

Parameters

bypassXtalOsc Pass in true to bypass the external crystal oscillator.

Note: This device does not support bypass external crystal oscillator, so the input parameter should always be false.

void CLOCK_DeinitExternalClk ( void )

This function disables the external 24MHz clock.

After this function, please call CLOCK_SetXtal0Freq to set external clock frequency to 0.

void CLOCK_SwitchOsc ( clock_osc_t osc )

This function switches the OSC source for SoC.

Parameters

osc	OSC source to switch to.

static uint32_t CLOCK_GetRtcFreq ( void )

inlinestatic

Returns: Clock frequency; If the clock is invalid, returns 0.

static void CLOCK_OSC_SetOsc48MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

static void CLOCK_OSC_EnableOsc48M ( bool enable )

inlinestatic

Parameters

enable

Used to enable or disable the 48MHz RC oscillator.

true Enable the 48MHz RC oscillator.
false Dissable the 48MHz RC oscillator.

static void CLOCK_OSC_SetOsc48MDiv2ControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

static void CLOCK_OSC_EnableOsc48MDiv2 ( bool enable )

inlinestatic

Note: The 48MHz RC oscillator must be enabled before enabling this 24MHz clock.

Parameters

enable

Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator.

true Enable the 24MHz clock sourced from 48MHz.
false Disable the 24MHz clock sourced from 48MHz.

static void CLOCK_OSC_SetOsc24MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOsc24M ( void )

This function enables OSC 24Mhz.

static void CLOCK_OSC_GateOsc24M ( bool enableGate )

inlinestatic

Note: Gating the 24MHz crystal oscillator can save power.

Parameters

enableGate

Used to gate/ungate the 24MHz crystal oscillator.

true Gate the 24MHz crystal oscillator to save power.
false Ungate the 24MHz crystal oscillator.

void CLOCK_OSC_SetOsc24MWorkMode ( clock_24MOsc_mode_t workMode )

Parameters

workMode The work mode of 24MHz crystal oscillator, please refer to clock_24MOsc_mode_t for details.

static void CLOCK_OSC_SetOscRc400MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_EnableOscRc400M ( void )

This function enables OSC RC 400Mhz.

static void CLOCK_OSC_GateOscRc400M ( bool enableGate )

inlinestatic

Parameters

enableGate

Used to gate/ungate 400MHz RC oscillator.

true Gate the 400MHz RC oscillator.
false Ungate the 400MHz RC oscillator.

void CLOCK_OSC_TrimOscRc400M	(	bool	enable,
		bool	bypass,
		uint16_t	trim
	)

Parameters

enable	Used to enable trim function.
bypass	Bypass the trim function.
trim	Trim value.

void CLOCK_OSC_SetOscRc400MRefClkDiv ( uint8_t divValue )

Note: slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.

Parameters

divValue The divide value to be set, the available range is 0~63.

void CLOCK_OSC_SetOscRc400MFastClkCount ( uint16_t targetCount )

Parameters

targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per divided ref_clk.

void CLOCK_OSC_SetOscRc400MHysteresisValue	(	uint8_t	negHysteresis,
		uint8_t	posHysteresis
	)

Note: The hysteresis value should be set after the clock is tuned.

Parameters

negHysteresis	The negative hysteresis value for the turned clock, this value in number of clock cycles of the fast clock
posHysteresis	The positive hysteresis value for the turned clock, this value in number of clock cycles of the fast clock

void CLOCK_OSC_BypassOscRc400MTuneLogic ( bool enableBypass )

Parameters

enableBypass

Used to control whether to bypass the turn logic.

true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
false Use the output of tune logic to run the oscillator.

void CLOCK_OSC_EnableOscRc400MTuneLogic ( bool enable )

Parameters

enable

Used to start or stop the tune logic.

true Start tuning
false Stop tuning and reset the tuning logic.

void CLOCK_OSC_FreezeOscRc400MTuneValue ( bool enableFreeze )

Parameters

enableFreeze

Used to control whether to freeze the tune value.

true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
false Unfreezes and continues the tune operation.

void CLOCK_OSC_SetOscRc400MTuneValue ( uint8_t tuneValue )

Parameters

tuneValue The tune value to determine the frequency of Oscillator.

void CLOCK_OSC_Set1MHzOutputBehavior ( clock_1MHzOut_behavior_t behavior )

Note: The 1MHz clock is divided from 400M RC Oscillator.

Parameters

behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details.

void CLOCK_OSC_SetLocked1MHzCount ( uint16_t count )

Parameters

count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the fast clock per divided ref_clk.

bool CLOCK_OSC_CheckLocked1MHzErrorFlag ( void )

Returns

The error flag for locked 1MHz clock out.

true The count value has been reached within one diviced ref clock period
false No effect.

uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount ( void )

Returns: The current count for the fast clock.

uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue ( void )

Returns: The current tune value.

static void CLOCK_OSC_SetOsc16MControlMode ( clock_control_mode_t controlMode )

inlinestatic

Parameters

controlMode The control mode to be set, please refer to clock_control_mode_t.

void CLOCK_OSC_SetOsc16MConfig	(	clock_16MOsc_source_t	source,
		bool	enablePowerSave,
		bool	enableClockOut
	)

Parameters

source	Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t.
enablePowerSave	Enable/disable power save mode function at 16MHz OSC. true Enable power save mode function at 16MHz osc. false Disable power save mode function at 16MHz osc.
enableClockOut	Enable/Disable clock output for 16MHz RCOSC. true Enable clock output for 16MHz RCOSC. false Disable clock output for 16MHz RCOSC.

void CLOCK_InitArmPll ( const clock_arm_pll_config_t * config )

This function initialize the ARM PLL with specific settings

Parameters

config configuration to set to PLL.

status_t CLOCK_CalcArmPllFreq	(	clock_arm_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Arm PLL

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitArmPllWithFreq ( uint32_t freqInMhz )

This function initializes the Arm PLL with specific frequency

Parameters

freqInMhz target frequency

void CLOCK_CalcPllSpreadSpectrum	(	uint32_t	factor,
		uint32_t	range,
		uint32_t	mod,
		clock_pll_ss_config_t *	ss
	)

This function calculate spread spectrum step and stop according to given parameters. For integer PLL (syspll2) the factor is mfd, while for other fractional PLLs (audio/video/syspll1), the factor is denominator.

Parameters

factor	factor to calculate step/stop
range	spread spectrum range
mod	spread spectrum modulation frequency
ss	calculated spread spectrum values

void CLOCK_InitSysPll1 ( const clock_sys_pll1_config_t * config )

This function initializes the System PLL1 with specific settings

Parameters

config Configuration to set to PLL1.

void CLOCK_GPC_SetSysPll1OutputFreq ( const clock_sys_pll1_gpc_config_t * config )

Parameters

config Pointer to clock_sys_pll1_gpc_config_t.

void CLOCK_InitSysPll2 ( const clock_sys_pll2_config_t * config )

This function initializes the System PLL2 with specific settings

Parameters

config Configuration to configure spread spectrum. This parameter can be NULL, if no need to enabled spread spectrum

void CLOCK_InitSysPll3 ( void )

This function initializes the System PLL3 with specific settings

void CLOCK_SetPllBypass	(	clock_pll_t	pll,
		bool	bypass
	)

Parameters

pll	PLL control name (see clock_pll_t enumeration)
bypass	Bypass the PLL. true: Bypass the PLL. false:Not bypass the PLL.

status_t CLOCK_CalcAvPllFreq	(	clock_av_pll_config_t *	config,
		uint32_t	freqInMhz
	)

This function calculates config valudes per given frequency for Audio/Video PLL.

Parameters

config	pll config structure
freqInMhz	target frequency

status_t CLOCK_InitAudioPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

This function initializes the Audio PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

void CLOCK_InitAudioPll ( const clock_audio_pll_config_t * config )

This function initializes the Audio PLL with specific settings

Parameters

config	Configuration to set to PLL.
ss	Configuration to set spread spectrum

void CLOCK_GPC_SetAudioPllOutputFreq ( const clock_audio_pll_gpc_config_t * config )

Parameters

config Pointer to clock_audio_pll_gpc_config_t.

status_t CLOCK_InitVideoPllWithFreq	(	uint32_t	freqInMhz,
		bool	ssEnable,
		uint32_t	ssRange,
		uint32_t	ssMod
	)

This function initializes the Video PLL with specific frequency

Parameters

freqInMhz	target frequency
ssEnable	enable spread spectrum or not
ssRange	range spread spectrum range
ssMod	spread spectrum modulation frequency

void CLOCK_InitVideoPll ( const clock_video_pll_config_t * config )

This function configures the Video PLL with specific settings

Parameters

config configuration to set to PLL.

void CLOCK_GPC_SetVideoPllOutputFreq ( const clock_video_pll_gpc_config_t * config )

Parameters

config Pointer to clock_audio_pll_gpc_config_t.

uint32_t CLOCK_GetPllFreq ( clock_pll_t pll )

This function get current output frequency of specific PLL

Parameters

pll	pll name to get frequency.

Returns: The PLL output frequency in hertz.

void CLOCK_InitPfd	(	clock_pll_t	pll,
		clock_pfd_t	pfd,
		uint8_t	frac
	)

This function initializes the System PLL PFD. During new value setting, the clock output is disabled to prevent glitch.

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	Which PFD clock to enable.
pfdFrac	The PFD FRAC value.

Note: It is recommended that PFD settings are kept between 12-35.

uint32_t CLOCK_GetPfdFreq	(	clock_pll_t	pll,
		clock_pfd_t	pfd
	)

This function get current output frequency of specific System PLL PFD

Parameters

pll	Which PLL of targeting PFD to be operated.
pfd	pfd name to get frequency.

Returns: The PFD output frequency in hertz.

bool CLOCK_EnableUsbhs0Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs1Clock	(	clock_usb_src_t	src,
		uint32_t	freq
	)

This function only enables the access to USB HS prepheral, upper layer should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY clock to use USB HS.

Parameters

src	USB HS does not care about the clock source, here must be kCLOCK_UsbSrcUnused.
freq	USB HS does not care about the clock source, so this parameter is ignored.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

bool CLOCK_EnableUsbhs0PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs0PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

bool CLOCK_EnableUsbhs1PhyPllClock	(	clock_usb_phy_src_t	src,
		uint32_t	freq
	)

This function enables the internal 480MHz USB PHY PLL clock.

Parameters

src	USB HS PHY PLL clock source.
freq	The frequency specified by src.

Return values

true	The clock is set successfully.
false	The clock source is invalid to get proper USB HS clock.

void CLOCK_DisableUsbhs1PhyPllClock ( void )

This function disables USB HS PHY PLL clock.

static void CLOCK_OSCPLL_LockControlMode ( clock_name_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

static void CLOCK_OSCPLL_LockWhiteList ( clock_name_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

static void CLOCK_OSCPLL_SetWhiteList	(	clock_name_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_OSCPLL_IsSetPointImplemented ( clock_name_t name )

inlinestatic

Parameters

name	Clock source name, see clock_name_t.

Returns

Clock source SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_OSCPLL_ControlByUnassignedMode ( clock_name_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.

void CLOCK_OSCPLL_ControlBySetPointMode	(	clock_name_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_OSCPLL_ControlByCpuLowPowerMode	(	clock_name_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

static void CLOCK_OSCPLL_SetCurrentClockLevel	(	clock_name_t	name,
		clock_level_t	level
	)

inlinestatic

Note: This setting only take effects in CPU Low Power Mode.

Parameters

name	Clock source name, see clock_name_t.
level	Depend level of this clock.

static void CLOCK_OSCPLL_ControlByDomainMode	(	clock_name_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock source name, see clock_name_t.
domainId	Domains that on the whitelist can change this clock.

static void CLOCK_ROOT_LockControlMode ( clock_root_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_LockWhiteList ( clock_root_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_SetWhiteList	(	clock_root_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_ROOT_IsSetPointImplemented ( clock_root_t name )

inlinestatic

Parameters

name	Clock root name, see clock_root_t.

Returns

Clock root SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_ROOT_ControlByUnassignedMode ( clock_root_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

static void CLOCK_ROOT_ConfigSetPoint	(	clock_root_t	name,
		uint16_t	spIndex,
		const clock_root_setpoint_config_t *	config
	)

inlinestatic

Note: SetPoint value could only be changed in Unassigend Mode.

Parameters

name	Which clock root to set, see clock_root_t.
spIndex	Which SetPoint of this clock root to set.
config	SetPoint config, see clock_root_setpoint_config_t

static void CLOCK_ROOT_EnableSetPointControl ( clock_root_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.

void CLOCK_ROOT_ControlBySetPointMode	(	clock_root_t	name,
		const clock_root_setpoint_config_t *	spTable
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
spTable	Point to the array that stores clock root settings for each setpoint. Note that the pointed array must have 16 elements.

static void CLOCK_ROOT_ControlByDomainMode	(	clock_root_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock root name, see clock_root_t.
domainId	Domains that on the whitelist can change this clock.

static void CLOCK_LPCG_LockControlMode ( clock_lpcg_t name )

inlinestatic

Note: When this bit is set, bits 16-20 can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

static void CLOCK_LPCG_LockWhiteList ( clock_lpcg_t name )

inlinestatic

Note: Once locked, this bit and domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

static void CLOCK_LPCG_SetWhiteList	(	clock_lpcg_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.

static bool CLOCK_LPCG_IsSetPointImplemented ( clock_lpcg_t name )

inlinestatic

Parameters

name	Clock gate name, see clock_lpcg_t.

Returns

Clock gate SetPoint implement status.

true: SetPoint is implemented.
false: SetPoint is not implemented.

static void CLOCK_LPCG_ControlByUnassignedMode ( clock_lpcg_t name )

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.

void CLOCK_LPCG_ControlBySetPointMode	(	clock_lpcg_t	name,
		uint16_t	spValue,
		uint16_t	stbyValue
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
spValue	Bit0~Bit15 hold value for Setpoint 0~16 respectively. A bitfield value of 0 implies clock will be shutdown in this Setpoint. A bitfield value of 1 implies clock will be turn on in this Setpoint.
stbyValue	Bit0~Bit15 hold value for Setpoint 0~16 standby. A bitfield value of 0 implies clock will be shutdown during standby. A bitfield value of 1 represent clock will keep Setpoint setting during standby.

void CLOCK_LPCG_ControlByCpuLowPowerMode	(	clock_lpcg_t	name,
		uint8_t	domainId,
		clock_level_t	level0,
		clock_level_t	level1
	)

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.
level0,level1	Depend level of this clock.

static void CLOCK_LPCG_SetCurrentClockLevel	(	clock_lpcg_t	name,
		clock_level_t	level
	)

inlinestatic

Note: This setting only take effects in CPU Low Power Mode.

Parameters

name	Clock gate name, see clock_lpcg_t.
level	Depend level of this clock.

static void CLOCK_LPCG_ControlByDomainMode	(	clock_lpcg_t	name,
		uint8_t	domainId
	)

inlinestatic

Note: When LOCK_MODE bit is set, control mode can not be changed until next system reset.

Parameters

name	Clock gate name, see clock_lpcg_t.
domainId	Domains that on the whitelist can change this clock.

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