MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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The MCUXpresso SDK provides a driver for the MECC module of MCUXpresso SDK devices.
The MECC64 module supports Single Error Correction and Double Error Detection(SECDED) ECC function to provide reliability for 4 banks On-Chip RAM(OCRAM) access.
This example code shows how to correct single error and detect multiple error using the MECC driver.
Refer to the driver examples codes located at <SDK_ROOT>/boards/<BOARD>/driver_examples/mecc
Data Structures | |
struct | mecc_config_t |
MECC user configuration. More... | |
struct | mecc_single_error_info_t |
MECC ocram single error information, including single error address, ECC code, error data and error bit position. More... | |
struct | mecc_multi_error_info_t |
MECC ocram multiple error information, including multiple error address, ECC code, error data. More... | |
Variables | |
bool | mecc_config_t::enableMecc |
Enable the MECC function. More... | |
uint32_t | mecc_config_t::Ocram1StartAddress |
Ocram 1 start address. More... | |
uint32_t | mecc_config_t::Ocram1EndAddress |
Ocram 1 end address. More... | |
uint32_t | mecc_config_t::Ocram2StartAddress |
Ocram 2 start address. More... | |
uint32_t | mecc_config_t::Ocram2EndAddress |
Ocram 2 end address. More... | |
uint32_t | mecc_single_error_info_t::singleErrorAddress |
Single error address on Ocram bank n. | |
uint32_t | mecc_single_error_info_t::singleErrorDataLow |
Single error low 32 bits uncorrected read data on Ocram bank n. | |
uint32_t | mecc_single_error_info_t::singleErrorDataHigh |
Single error high 32 bits uncorrected read data on Ocram bank n. | |
uint32_t | mecc_single_error_info_t::singleErrorPosLow |
Single error bit postion of low 32 bits read data on Ocram bank n. | |
uint32_t | mecc_single_error_info_t::singleErrorPosHigh |
Single error bit postion of high 32 bits read data on Ocram bank n. | |
uint8_t | mecc_single_error_info_t::singleErrorEccCode |
Single error ECC code on Ocram bank n. | |
uint32_t | mecc_multi_error_info_t::multiErrorAddress |
Multiple error address on Ocram bank n. | |
uint32_t | mecc_multi_error_info_t::multiErrorDataLow |
Multiple error low 32 bits read data on Ocram bank n. | |
uint32_t | mecc_multi_error_info_t::multiErrorDataHigh |
Multiple error high 32 bits read data on Ocram bank n. | |
uint8_t | mecc_multi_error_info_t::multiErrorEccCode |
Multiple error ECC code on Ocram bank n. | |
Driver version | |
#define | FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) |
Driver version 2.0.1. More... | |
Initialization and deinitialization | |
void | MECC_Init (MECC_Type *base, mecc_config_t *config) |
MECC module initialization function. More... | |
void | MECC_Deinit (MECC_Type *base) |
Deinitializes the MECC. More... | |
void | MECC_GetDefaultConfig (mecc_config_t *config) |
Sets the MECC configuration structure to default values. More... | |
Status | |
static uint32_t | MECC_GetStatusFlags (MECC_Type *base) |
Gets MECC status flags. More... | |
static void | MECC_ClearStatusFlags (MECC_Type *base, uint32_t mask) |
MECC module clear interrupt status. More... | |
static void | MECC_EnableInterruptStatus (MECC_Type *base, uint32_t mask) |
MECC module enable interrupt status. More... | |
static void | MECC_DisableInterruptStatus (MECC_Type *base, uint32_t mask) |
MECC module disable interrupt status. More... | |
Interrupts | |
static void | MECC_EnableInterrupts (MECC_Type *base, uint32_t mask) |
MECC module enable interrupt. More... | |
static void | MECC_DisableInterrupts (MECC_Type *base, uint32_t mask) |
MECC module disable interrupt. More... | |
functional | |
status_t | MECC_ErrorInjection (MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber) |
MECC module error injection. More... | |
status_t | MECC_GetSingleErrorInfo (MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber) |
MECC module get single error information. More... | |
status_t | MECC_GetMultiErrorInfo (MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber) |
MECC module get multiple error information. More... | |
struct mecc_config_t |
Data Fields | |
bool | enableMecc |
Enable the MECC function. More... | |
uint32_t | Ocram1StartAddress |
Ocram 1 start address. More... | |
uint32_t | Ocram1EndAddress |
Ocram 1 end address. More... | |
uint32_t | Ocram2StartAddress |
Ocram 2 start address. More... | |
uint32_t | Ocram2EndAddress |
Ocram 2 end address. More... | |
struct mecc_single_error_info_t |
Data Fields | |
uint32_t | singleErrorAddress |
Single error address on Ocram bank n. | |
uint32_t | singleErrorDataLow |
Single error low 32 bits uncorrected read data on Ocram bank n. | |
uint32_t | singleErrorDataHigh |
Single error high 32 bits uncorrected read data on Ocram bank n. | |
uint32_t | singleErrorPosLow |
Single error bit postion of low 32 bits read data on Ocram bank n. | |
uint32_t | singleErrorPosHigh |
Single error bit postion of high 32 bits read data on Ocram bank n. | |
uint8_t | singleErrorEccCode |
Single error ECC code on Ocram bank n. | |
struct mecc_multi_error_info_t |
Data Fields | |
uint32_t | multiErrorAddress |
Multiple error address on Ocram bank n. | |
uint32_t | multiErrorDataLow |
Multiple error low 32 bits read data on Ocram bank n. | |
uint32_t | multiErrorDataHigh |
Multiple error high 32 bits read data on Ocram bank n. | |
uint8_t | multiErrorEccCode |
Multiple error ECC code on Ocram bank n. | |
#define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) |
anonymous enum |
This structure contains the settings for all of the MECC interrupt configurations.
anonymous enum |
This structure contains the settings for all of the MECC interrupt status configurations.
anonymous enum |
This provides constants for the MECC status flags for use in the MECC functions.
anonymous enum |
anonymous enum |
void MECC_Init | ( | MECC_Type * | base, |
mecc_config_t * | config | ||
) |
base | MECC base address. |
config | pointer to the MECC configuration structure. |
void MECC_Deinit | ( | MECC_Type * | base | ) |
base | MECC base address. |
void MECC_GetDefaultConfig | ( | mecc_config_t * | config | ) |
config | pointer to the MECC configuration structure. |
|
inlinestatic |
base | MECC peripheral base address. |
|
inlinestatic |
base | MECC base address. |
mask | status to clear. |
|
inlinestatic |
base | MECC base address. |
mask | status to enable. |
|
inlinestatic |
base | MECC base address. |
mask | status to disable. |
|
inlinestatic |
base | MECC base address. |
mask | The interrupts to enable. |
|
inlinestatic |
base | MECC base address. |
mask | The interrupts to disable. |
status_t MECC_ErrorInjection | ( | MECC_Type * | base, |
uint32_t | lowerrordata, | ||
uint32_t | higherrordata, | ||
uint8_t | eccdata, | ||
uint8_t | banknumber | ||
) |
base | MECC base address. |
lowerrordata | low 32 bits data. |
higherrordata | high 32 bits data. |
eccdata | ecc code. |
banknumber | ocram bank number. |
kStatus_Success. | Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4..... |
status_t MECC_GetSingleErrorInfo | ( | MECC_Type * | base, |
mecc_single_error_info_t * | info, | ||
uint8_t | banknumber | ||
) |
base | MECC base address. |
info | single error information. |
banknumber | ocram bank number. |
kStatus_Success. | |
kStatus_MECC_BankMiss. | Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4..... |
status_t MECC_GetMultiErrorInfo | ( | MECC_Type * | base, |
mecc_multi_error_info_t * | info, | ||
uint8_t | banknumber | ||
) |
base | MECC base address. |
info | multiple error information. |
banknumber | ocram bank number. |
kStatus_Success. | |
kStatus_MECC_BankMiss. | Bank0: ocram_base_address+0x20*i Bank1: ocram_base_address+0x20*i+0x8 Bank2: ocram_base_address+0x20*i+0x10 Bank3: ocram_base_address+0x20*i+0x18 i = 0,1,2,3,4..... |
bool mecc_config_t::enableMecc |
uint32_t mecc_config_t::Ocram1StartAddress |
uint32_t mecc_config_t::Ocram1EndAddress |
uint32_t mecc_config_t::Ocram2StartAddress |
uint32_t mecc_config_t::Ocram2EndAddress |