MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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LINREG_STAT - LinReg status bits LinReg status bits. More...
CTRL0 - CTRL0 Register | |
#define | AI_PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK) |
#define | AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) |
#define | AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) |
#define | AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK) |
LINREG_EN - LinReg master enable LinReg master enable. More... | |
#define | AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U) |
#define | AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U) |
#define | AI_PHY_LDO_CTRL0_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK) |
LINREG_PWRUPLOAD_DIS - LinReg power-up load disable 0b0..Internal pull-down enabled 0b1..Internal pull-down disabled. | |
#define | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U) |
#define | AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U) |
#define | AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK) |
LINREG_LIMIT_EN - LinReg current limit enable LinReg current-limit enable. More... | |
#define | AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U) |
#define | AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U) |
#define | AI_PHY_LDO_CTRL0_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK) |
LINREG_OUTPUT_TRG - LinReg output voltage target setting 0b00000..Set output voltage to x.xV 0b10000..Set output voltage to 1.0V 0b11111..Set output voltage to x.xV. | |
#define | AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U) |
#define | AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U) |
#define | AI_BANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK) |
#define | AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) |
#define | AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) |
#define | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) |
REFTOP_PWD - This bit fully powers down the bandgap module. More... | |
#define | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) |
#define | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) |
#define | AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) |
REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap. More... | |
#define | AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) |
#define | AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) |
#define | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) |
REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap without affecting any additional functionality. | |
#define | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) |
#define | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) |
#define | AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) |
REFTOP_LOWPOWER - This bit enables the low-power operation of the bandgap by cutting the bias currents in half to the main amplifiers. More... | |
#define | AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) |
#define | AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) |
#define | AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK) |
REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap. More... | |
#define | AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) |
#define | AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U) |
#define | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK) |
REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed 000 : nominal 001 : +10mV 010 : +20mV 011 : +30mV 100 : -10mV 101 : -20mV 110 : -30mV 111 : -40mV. | |
#define | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) |
#define | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) |
#define | AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) |
#define | AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) |
#define | AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U) |
#define | AI_PLL1G_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK) |
#define | AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) |
#define | AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | AI_PLL1G_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK) |
#define | AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL) |
#define | AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U) |
#define | AI_PLL1G_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK) |
#define | AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL) |
#define | AI_PLL1G_CTRL0_ENABLE_SHIFT (15U) |
#define | AI_PLL1G_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK) |
#define | AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL) |
#define | AI_PLL1G_CTRL0_BYPASS_SHIFT (16U) |
#define | AI_PLL1G_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK) |
#define | AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL) |
#define | AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U) |
#define | AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK) |
#define | AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) |
#define | AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | AI_PLLAUDIO_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK) |
#define | AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL) |
#define | AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U) |
#define | AI_PLLAUDIO_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK) |
#define | AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL) |
#define | AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U) |
#define | AI_PLLAUDIO_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK) |
#define | AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL) |
#define | AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U) |
#define | AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK) |
#define | AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL) |
#define | AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U) |
#define | AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK) |
#define | AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) |
#define | AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | AI_PLLVIDEO_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK) |
#define | AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL) |
#define | AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U) |
#define | AI_PLLVIDEO_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK) |
#define | AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL) |
#define | AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U) |
#define | AI_PLLVIDEO_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK) |
#define | AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL) |
#define | AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U) |
#define | AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK) |
#define | AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL) |
#define | AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U) |
STAT2 - STAT2 Register | |
#define | AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) |
#define | AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) |
#define | AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) |
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK) |
Setting this bit will enable the regular
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK) |
Setting this bit will enable the current-limiter in the regulator
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD | ( | x | ) |
Setting this bit high will disable reference output currents and voltages from the bandgap and will affect functionality and validity of the voltage detectors.
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) |
Setting this bit high will affect functionality and validity of the voltage detectors.
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF | ( | x | ) |
This will save power but could affect the accuracy of the output voltages and currents.
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK) |
The self-bias circuit is used by the bandgap during startup. This bit should be set high after the bandgap has stabilized and is necessary for best noise performance of modules using the outputs of the bandgap. It is expected that this control bit be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed.