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MCUXpresso SDK API Reference Manual
Rev. 0
NXP Semiconductors
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The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
The clock driver supports:
Files | |
file | fsl_clock.h |
Data Structures | |
struct | clock_sfll_config_t |
SFLL configuration. More... | |
struct | clock_aupll_config_t |
AUPLL configuration. More... | |
Macros | |
#define | FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
Configure whether driver controls clock. More... | |
#define | GPIO_CLOCKS |
Clock ip name array for GPIO. More... | |
#define | I2C_CLOCKS |
Clock ip name array for I2C. More... | |
#define | QSPI_CLOCKS |
Clock ip name array for QSPI. More... | |
#define | UART_CLOCKS |
Clock ip name array for UART. More... | |
#define | SSP_CLOCKS |
Clock ip name array for SSP. More... | |
#define | GPT_CLOCKS |
Clock ip name array for GPT. More... | |
#define | WDT_CLOCKS |
Clock ip name array for WDT. More... | |
#define | RTC_CLOCKS |
Clock ip name array for RTC. More... | |
#define | ACOMP_CLOCKS |
Clock ip name array for ACOMP. More... | |
#define | ADC_CLOCKS |
Clock ip name array for ADC. More... | |
#define | DAC_CLOCKS |
Clock ip name array for DAC. More... | |
#define | DMAC_CLOCKS |
Clock ip name array for DMAC. More... | |
#define | CLK_OP_CODE_DEFINE(regOff, bitPos, bitWid, val) (((regOff) << 16U) | ((bitPos) << 11U) | ((bitWid) << 8U) | (val)) |
Clock operation code. More... | |
Enumerations | |
enum | clock_ip_name_t |
Peripheral clock name difinition used for clock gate. | |
enum | clock_attach_id_t |
Peripheral clock source selection definition. | |
enum | clock_div_name_t |
Clock divider definition. | |
enum | clock_sys_clk_src_t { kCLOCK_SysClkSrcSFll = 0U, kCLOCK_SysClkSrcRC32M_1 = 1U, kCLOCK_SysClkSrcMainXtal = 2U, kCLOCK_SysClkSrcRC32M_3 = 3U } |
CLOCK system clock source. More... | |
enum | clock_refclk_t { kCLOCK_RefClk_SYS = (1U << PMU_WLAN_CTRL_REFCLK_SYS_REQ_SHIFT), kCLOCK_RefClk_AUD = (1U << PMU_WLAN_CTRL_REFCLK_AUD_REQ_SHIFT), kCLOCK_RefClk_USB = (1U << PMU_WLAN_CTRL_REFCLK_USB_REQ_SHIFT) } |
System reference clock option. More... | |
enum | clock_osc32k_mode_t { kCLOCK_Osc32k_Internal = 0, kCLOCK_Osc32k_External = 1 } |
XTAL32K mode option. More... | |
enum | clock_sfll_src_t { kCLOCK_SFllSrcRC32M = 0U, kCLOCK_SFllSrcMainXtal = 1U } |
SFLL Reference Input Clock Source. More... | |
enum | clock_aupll_src_t { kCLOCK_AuPllSrcRC32M = 0U, kCLOCK_AuPllSrcRefClk = 1U } |
AUPLL Reference Input Clock Source. More... | |
Functions | |
void | CLOCK_EnableClock (clock_ip_name_t name) |
Enable the clock for specific IP. More... | |
void | CLOCK_DisableClock (clock_ip_name_t name) |
Disable the clock for specific IP. More... | |
void | CLOCK_AttachClk (clock_attach_id_t connection) |
Configure the clock selection muxes. More... | |
void | CLOCK_SetClkDiv (clock_div_name_t name, uint32_t divider) |
Setup clock dividers. More... | |
void | CLOCK_SetUartClkDiv (clock_div_name_t name, uint32_t nom, uint32_t denom) |
Setup UART clock dividers. More... | |
uint32_t | CLOCK_GetSysClkFreq (void) |
Get the system clock frequency. More... | |
void | CLOCK_SetSysClkSource (clock_sys_clk_src_t src) |
Set the system clock source. More... | |
void | CLOCK_EnableXtal32K (clock_osc32k_mode_t mode) |
Enable the 32K XTAL. More... | |
void | CLOCK_DisableXtal32K (void) |
Disable the 32K XTAL output. | |
void | CLOCK_EnableRC32M (bool halfDiv) |
Enable the RC32M OSC. More... | |
void | CLOCK_DisableRC32M (void) |
Disable the RC32M OSC. | |
int32_t | CLOCK_CalibrateRC32M (bool autoCal, uint32_t manCalCode) |
RC32M clock calibration function. More... | |
void | CLOCK_EnableRC32K (void) |
Enable the RC32K OSC. | |
void | CLOCK_DisableRC32K (void) |
Disable the RC32K OSC. | |
int32_t | CLOCK_CalibrateRC32K (bool autoCal, uint32_t manCalCode) |
RC32K clock calibration function. More... | |
void | CLOCK_EnableRefClk (uint32_t refclks) |
Enable the REFCLK for SYS/AUD/USB reference. More... | |
void | CLOCK_DisableRefClk (uint32_t refclks) |
Disable the REFCLK for SYS/AUD/USB reference. More... | |
void | CLOCK_InitSFll (const clock_sfll_config_t *config) |
Initialize the SFLL. More... | |
void | CLOCK_DeinitSFll (void) |
Deinit the SFLL. | |
void | CLOCK_InitAuPll (const clock_aupll_config_t *config) |
Initialize the AUPLL. More... | |
void | CLOCK_DeinitAuPll (void) |
Deinit the AUPLL. | |
void | CLOCK_UpdateAupllPostDiv (uint8_t postDivPattern, uint8_t postDivModulo) |
Update the AUPLL post divider. | |
__STATIC_INLINE void | CLOCK_SetMainXtalFreq (uint32_t freq) |
Set the MAIN XTAL frequency based on board setting. More... | |
uint32_t | CLOCK_GetMainXtalFreq (void) |
Return Frequency of MAIN XTAL Clock. More... | |
uint32_t | CLOCK_GetRefClkAudFreq (void) |
Return Frequency of REFCLK_AUD Clock. More... | |
uint32_t | CLOCK_GetRC32MFreq (void) |
Return Frequency of RC32M Clock. More... | |
uint32_t | CLOCK_GetXtal32KFreq (void) |
Return Frequency of XTAL32K Clock. More... | |
uint32_t | CLOCK_GetRC32KFreq (void) |
Return Frequency of RC32K Clock. More... | |
uint32_t | CLOCK_GetSFllFreq (void) |
Return Frequency of SFLL Clock. More... | |
uint32_t | CLOCK_GetAuPllFreq (void) |
Return Frequency of AUPLL Clock. More... | |
uint32_t | CLOCK_GetCoreBusFreq (void) |
Return Frequency of M4/AHB Clock. More... | |
uint32_t | CLOCK_GetApbFreq (uint32_t instance) |
Return Frequency of APB Clock. More... | |
uint32_t | CLOCK_GetUartClkFreq (uint32_t instance) |
Return Frequency of UART Clock. More... | |
uint32_t | CLOCK_GetGptClkFreq (uint32_t instance) |
Return Frequency of GPT Clock. More... | |
uint32_t | CLOCK_GetGptSampleClkFreq (void) |
Return Frequency of GPT Sample Clock. More... | |
uint32_t | CLOCK_GetSspClkFreq (uint32_t instance) |
Return Frequency of SSP Clock. More... | |
uint32_t | CLOCK_GetGauClkFreq (void) |
Return Frequency of GAU Clock. More... | |
uint32_t | CLOCK_GetRtcClkFreq (void) |
Return Frequency of RTC Clock. More... | |
uint32_t | CLOCK_GetI2cClkFreq (void) |
Return Frequency of I2C Clock. More... | |
uint32_t | CLOCK_GetQspiClkFreq (void) |
Return Frequency of QSPI Clock. More... | |
uint32_t | CLOCK_GetFlashCClkFreq (void) |
Return Frequency of FlashC Clock. More... | |
uint32_t | CLOCK_GetWdtClkFreq (void) |
Return Frequency of WDT Clock. More... | |
uint32_t | CLOCK_GetSdioClkFreq (void) |
Return Frequency of SDIO Clock. More... | |
Variables | |
volatile uint32_t | g_mainXtalFreq |
External crystal MAINXTAL clock frequency. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) |
CLOCK driver version 2.0.1. More... | |
struct clock_sfll_config_t |
Data Fields | |
clock_sfll_src_t | sfllSrc |
Reference Input Clock Source. | |
uint16_t | refDiv |
Divider for reference clock, 9-bit. More... | |
uint16_t | fbDiv |
Divider for feedback clock, 9-bit. | |
uint8_t | kvco |
VCO setting, 2-bit. More... | |
uint8_t | postDiv |
Post divider, 2-bit. More... | |
uint16_t clock_sfll_config_t::refDiv |
0.2 MHz <= Fref (frequency of Reference clock / refDiv) <= 0.4 MHz
uint8_t clock_sfll_config_t::kvco |
Select KVCO per VCO target frequency
uint8_t clock_sfll_config_t::postDiv |
2'b01, Fout = Fvco/2 2'b10, Fout = Fvco/4 2'b11, Fout = Fvco/8
struct clock_aupll_config_t |
Data Fields | |
clock_aupll_src_t | aupllSrc |
Reference Input Clock Source. | |
uint8_t | refDiv |
Divider for reference clock, 4-bit, range: 3 ~ 10. | |
uint8_t | fbDiv |
Divider for feedback clock, 6-bit, range: 27, 29, 31 ~ 36, 38, 39, 42, 46. | |
uint8_t | icp |
charge pump current control, 2-bit, reserved now More... | |
uint8_t | postDivPattern |
Pattern divider for ouput clock, 2-bit, range: 0 ~ 2. More... | |
uint8_t | postDivModulo |
Modulo divider for ouput clock, 3-bit, range: 0 ~ 2, 4, 7. More... | |
bool | enaVcoClkX2 |
< 1'b0, Integration only More... | |
uint32_t | fract |
< 1'b0, Disable VCOCLK_X2 More... | |
uint8_t clock_aupll_config_t::icp |
2'b00, 2.5 uA 2'b01, 5 uA 2'b10, 7.5 uA 2'b11, 10 uA
uint8_t clock_aupll_config_t::postDivPattern |
2'b00, pattern = 4.0 2'b01, pattern = 3.0 2'b10, pattern = 4.5
uint8_t clock_aupll_config_t::postDivModulo |
3'b000, modulo = 1 3'b001, modulo = 2 3'b010, modulo = 4 3'b100, modulo = 8 3'b111, modulo = 16
bool clock_aupll_config_t::enaVcoClkX2 |
< 1'b1, Integration + MASH
uint32_t clock_aupll_config_t::fract |
< 1'b1, Enable VCOCLK_X2 Fractional PLL feedback divider 20-bits, range: 0 ~ 0x10000
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) |
#define GPIO_CLOCKS |
#define I2C_CLOCKS |
#define QSPI_CLOCKS |
#define UART_CLOCKS |
#define SSP_CLOCKS |
#define GPT_CLOCKS |
#define WDT_CLOCKS |
#define RTC_CLOCKS |
#define ACOMP_CLOCKS |
#define ADC_CLOCKS |
#define DAC_CLOCKS |
#define DMAC_CLOCKS |
#define CLK_OP_CODE_DEFINE | ( | regOff, | |
bitPos, | |||
bitWid, | |||
val | |||
) | (((regOff) << 16U) | ((bitPos) << 11U) | ((bitWid) << 8U) | (val)) |
[31:16] Register offset from PMU base. [15:11] Register bit position. [10: 8] Register bits width to operate. [ 7: 0] Value to set to the bits.
enum clock_sys_clk_src_t |
enum clock_refclk_t |
enum clock_osc32k_mode_t |
enum clock_sfll_src_t |
enum clock_aupll_src_t |
void CLOCK_EnableClock | ( | clock_ip_name_t | name | ) |
name | Which clock to enable, see clock_ip_name_t. |
void CLOCK_DisableClock | ( | clock_ip_name_t | name | ) |
name | Which clock to disable, see clock_ip_name_t. |
void CLOCK_AttachClk | ( | clock_attach_id_t | connection | ) |
connection | : Clock to be configured. |
void CLOCK_SetClkDiv | ( | clock_div_name_t | name, |
uint32_t | divider | ||
) |
name | : Clock divider name |
divider | : Value to be divided. |
void CLOCK_SetUartClkDiv | ( | clock_div_name_t | name, |
uint32_t | nom, | ||
uint32_t | denom | ||
) |
name | : Clock divider name |
nom | : Nominator for fraction divider. |
denom | : Denominator for fraction divider. |
uint32_t CLOCK_GetSysClkFreq | ( | void | ) |
void CLOCK_SetSysClkSource | ( | clock_sys_clk_src_t | src | ) |
This function sets the system clock source.
src | System clock source to set. |
void CLOCK_EnableXtal32K | ( | clock_osc32k_mode_t | mode | ) |
mode | Internal or external OSC selection. |
void CLOCK_EnableRC32M | ( | bool | halfDiv | ) |
halfDiv | half-divided reference clock. True for 16MHz and false for original 32MHz output. |
int32_t CLOCK_CalibrateRC32M | ( | bool | autoCal, |
uint32_t | manCalCode | ||
) |
autoCal | Calibration option, true for auto and false for manual |
manCalCode | Select manual way, need input the calibration code |
int32_t CLOCK_CalibrateRC32K | ( | bool | autoCal, |
uint32_t | manCalCode | ||
) |
autoCal | Calibration option, true for auto and false for manual |
manCalCode | Select manual way, need input the calibration code |
void CLOCK_EnableRefClk | ( | uint32_t | refclks | ) |
refclks | Or'ed value to select SYS/AUD/USB REFCLK to disable. See clock_refclk_t. |
void CLOCK_DisableRefClk | ( | uint32_t | refclks | ) |
refclks | Or'ed value to select SYS/AUD/USB REFCLK to disable. See clock_refclk_t. |
void CLOCK_InitSFll | ( | const clock_sfll_config_t * | config | ) |
config | : Configuration to set to SFLL. |
void CLOCK_InitAuPll | ( | const clock_aupll_config_t * | config | ) |
config | : Configuration to set to AUPLL. |
__STATIC_INLINE void CLOCK_SetMainXtalFreq | ( | uint32_t | freq | ) |
freq | : The XTAL input clock frequency in Hz. |
uint32_t CLOCK_GetMainXtalFreq | ( | void | ) |
uint32_t CLOCK_GetRefClkAudFreq | ( | void | ) |
uint32_t CLOCK_GetRC32MFreq | ( | void | ) |
uint32_t CLOCK_GetXtal32KFreq | ( | void | ) |
uint32_t CLOCK_GetRC32KFreq | ( | void | ) |
uint32_t CLOCK_GetSFllFreq | ( | void | ) |
uint32_t CLOCK_GetAuPllFreq | ( | void | ) |
uint32_t CLOCK_GetCoreBusFreq | ( | void | ) |
uint32_t CLOCK_GetApbFreq | ( | uint32_t | instance | ) |
instance | APB instance 0-1. |
uint32_t CLOCK_GetUartClkFreq | ( | uint32_t | instance | ) |
instance | UART instance 0-2. |
uint32_t CLOCK_GetGptClkFreq | ( | uint32_t | instance | ) |
instance | GPT instance 0-3. |
uint32_t CLOCK_GetGptSampleClkFreq | ( | void | ) |
uint32_t CLOCK_GetSspClkFreq | ( | uint32_t | instance | ) |
instance | SSP instance 0-2. |
uint32_t CLOCK_GetGauClkFreq | ( | void | ) |
uint32_t CLOCK_GetRtcClkFreq | ( | void | ) |
uint32_t CLOCK_GetI2cClkFreq | ( | void | ) |
uint32_t CLOCK_GetQspiClkFreq | ( | void | ) |
uint32_t CLOCK_GetFlashCClkFreq | ( | void | ) |
uint32_t CLOCK_GetWdtClkFreq | ( | void | ) |
uint32_t CLOCK_GetSdioClkFreq | ( | void | ) |
volatile uint32_t g_mainXtalFreq |
The MAINXTAL clock frequency in Hz. When the clock is set up, use the function CLOCK_SetMainXtalFreq to set the value in the clock driver. For example, if MAINXTAL is 38.4 MHz: