|
|
#define | AES_INB_FSEL(n) ((n) << 16) |
| | n->1=Input Text, n->2=Holding, n->3=Input Text XOR Holding
|
| |
|
#define | AES_HOLD_FSEL(n) ((n) << 20) |
| | n->0=Counter, n->1=Input Text, n->2=Output Block, n->3=Input Text XOR Output Block
|
| |
|
#define | AES_OUTT_FSEL(n) ((n) << 24) |
| | n->0=OUTT, n->1=Output Block XOR Input Text, n->2=Output Block XOR Holding
|
| |
|
#define | ISP_INVALID_EXTENSION (0) |
| | Each ISP extension function invalid : 0 corresponds to a NULL pointer.
|
| |
| #define | ISP_FLAG_HAS_CRC32 (1 << 0) |
| | Each ISP command is preceded by a 'flag' byte that tell how to verify the command. More...
|
| |
|
#define | ISP_FLAG_SIGNED (1 << 1) |
| | tells that command is RSA signed and authentication is checked, if unset, the SHA256 is computed and compared against the one held in the message, which guarantees integrity
|
| |
|
#define | ISP_FLAG_HAS_NEXT_HASH (1 << 2) |
| | tells to hold the computed hash
|
| |
|
#define | LOWPOWER_CFG_MODE_ACTIVE 0 |
| | ACTIVE mode.
|
| |
|
#define | LOWPOWER_CFG_MODE_DEEPSLEEP 1 |
| | DEEP SLEEP mode.
|
| |
|
#define | LOWPOWER_CFG_MODE_POWERDOWN 2 |
| | POWER DOWN mode.
|
| |
|
#define | LOWPOWER_CFG_MODE_DEEPPOWERDOWN 3 |
| | DEEP POWER DOWN mode.
|
| |
|
#define | LOWPOWER_CFG_XTAL32MSTART_DISABLE 0 |
| | Disable Crystal 32 MHz automatic start when waking up from POWER DOWN and DEEP POWER DOWN modes.
|
| |
|
#define | LOWPOWER_CFG_XTAL32MSTART_ENABLE 1 |
| | Enable Crystal 32 MHz automatic start when waking up from POWER DOWN and DEEP POWER DOWN modes.
|
| |
| #define | LOWPOWER_CFG_FLASHPWDNMODE_FLASHPWND 0 |
| | Power down the Flash only (send CMD_POWERDOWN to Flash controller). More...
|
| |
|
#define | LOWPOWER_CFG_FLASHPWDNMODE_LDOSHUTOFF 1 |
| | Power down the Flash ((send CMD_POWERDOWN to Flash controller) and shutoff both Flash LDOs (Core and NV) \ \ (only valid in DEEP SLEEP mode)
|
| |
| #define | LOWPOWER_PMUPWDN_DCDC (1UL << 0) |
| | Analog Power Domains (analog components in Power Management Unit) Low Power Modes control. More...
|
| |
|
#define | LOWPOWER_PMUPWDN_BIAS (1UL << 1) |
| | Power Down all Bias and references.
|
| |
|
#define | LOWPOWER_PMUPWDN_LDOMEM (1UL << 2) |
| | Power Down Memories LDO.
|
| |
|
#define | LOWPOWER_PMUPWDN_BODVBAT (1UL << 3) |
| | Power Down VBAT Brown Out Detector.
|
| |
|
#define | LOWPOWER_PMUPWDN_FRO192M (1UL << 4) |
| | Power Down FRO 192 MHz.
|
| |
|
#define | LOWPOWER_PMUPWDN_FRO1M (1UL << 5) |
| | Power Down FRO 1 MHz.
|
| |
|
#define | LOWPOWER_PMUPWDN_GPADC (1UL << 22) |
| | Power Down General Purpose ADC.
|
| |
|
#define | LOWPOWER_PMUPWDN_BODMEM (1UL << 23) |
| | Power Down Memories Brown Out Detector.
|
| |
|
#define | LOWPOWER_PMUPWDN_BODCORE (1UL << 24) |
| | Power Down Core Logic Brown Out Detector.
|
| |
|
#define | LOWPOWER_PMUPWDN_FRO32K (1UL << 25) |
| | Power Down FRO 32 KHz.
|
| |
|
#define | LOWPOWER_PMUPWDN_XTAL32K (1UL << 26) |
| | Power Down Crystal 32 KHz.
|
| |
|
#define | LOWPOWER_PMUPWDN_ANACOMP (1UL << 27) |
| | Power Down Analog Comparator.
|
| |
|
#define | LOWPOWER_PMUPWDN_XTAL32M (1UL << 28) |
| | Power Down Crystal 32 MHz.
|
| |
|
#define | LOWPOWER_PMUPWDN_TEMPSENSOR (1UL << 29) |
| | Power Down Temperature Sensor.
|
| |
| #define | LOWPOWER_DIGPWDN_FLASH (1UL << 6) |
| | Digital Power Domains Low Power Modes control. More...
|
| |
|
#define | LOWPOWER_DIGPWDN_COMM0 (1UL << 7) |
| | Power Down Digital COMM0 power domain (USART0, I2C0 and SPI0)
|
| |
|
#define | LOWPOWER_DIGPWDN_MCU_RET (1UL << 8) |
| | Power Down MCU Retention Power Domain (Disable Zigbee IP retention, ES1:Disable CPU retention \ \ flip-flops)
|
| |
|
#define | LOWPOWER_DIGPWDN_ZIGBLE_RET (1UL << 9) |
| | Power Down ZIGBEE/BLE retention Power Domain (Disable ZIGBEE/BLE retention flip-flops)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM0 (1UL << LOWPOWER_DIGPWDN_SRAM0_INDEX) |
| | Power Down SRAM 0 instance [Bank 0, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM1 (1UL << 11) |
| | Power Down SRAM 1 instance [Bank 0, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM2 (1UL << 12) |
| | Power Down SRAM 2 instance [Bank 0, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM3 (1UL << 13) |
| | Power Down SRAM 3 instance [Bank 0, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM4 (1UL << 14) |
| | Power Down SRAM 4 instance [Bank 0, 8 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM5 (1UL << 15) |
| | Power Down SRAM 5 instance [Bank 0, 8 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM6 (1UL << 16) |
| | Power Down SRAM 6 instance [Bank 0, 4 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM7 (1UL << 17) |
| | Power Down SRAM 7 instance [Bank 0, 4 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM8 (1UL << 18) |
| | Power Down SRAM 8 instance [Bank 1, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM9 (1UL << 19) |
| | Power Down SRAM 9 instance [Bank 1, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM10 (1UL << 20) |
| | Power Down SRAM 10 instance [Bank 1, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_SRAM11 (1UL << 21) |
| | Power Down SRAM 11 instance [Bank 1, 16 KB], (no retention)
|
| |
|
#define | LOWPOWER_DIGPWDN_IO (1UL << LOWPOWER_DIGPWDN_IO_INDEX) |
| | Power Down.
|
| |
|
#define | LOWPOWER_DIGPWDN_NTAG_FD (1UL << LOWPOWER_DIGPWDN_NTAG_FD_INDEX) |
| | NTAG FD field detect Disable - need the IO source to be set too.
|
| |
|
#define | LOWPOWER_SRAM_LPMODE_MASK (0xFUL) |
| | LDO Voltage control in Low Power Modes.
|
| |
|
#define | LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 |
| | LDO Voltage control in Low Power Modes.
|
| |
| #define | LOWPOWER_WAKEUPSRCINT0_SYSTEM_IRQ (1UL << 0) |
| | Low Power Modes Wake up Interrupt sources. More...
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_DMA_IRQ (1UL << 1) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_GINT_IRQ (1UL << 2) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_IRBLASTER_IRQ (1UL << 3) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PINT0_IRQ (1UL << 4) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PINT1_IRQ (1UL << 5) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PINT2_IRQ (1UL << 6) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PINT3_IRQ (1UL << 7) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_SPIFI_IRQ (1UL << 8) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_TIMER0_IRQ (1UL << 9) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_TIMER1_IRQ (1UL << 10) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_USART0_IRQ (1UL << 11) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_USART1_IRQ (1UL << 12) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_I2C0_IRQ (1UL << 13) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_I2C1_IRQ (1UL << 14) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_SPI0_IRQ (1UL << 15) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_SPI1_IRQ (1UL << 16) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM0_IRQ (1UL << 17) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM1_IRQ (1UL << 18) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM2_IRQ (1UL << 19) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM3_IRQ (1UL << 20) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM4_IRQ (1UL << 21) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM5_IRQ (1UL << 22) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM6_IRQ (1UL << 23) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM7_IRQ (1UL << 24) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM8_IRQ (1UL << 25) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM9_IRQ (1UL << 26) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_PWM10_IRQ (1UL << 27) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_I2C2_IRQ (1UL << 28) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_RTC_IRQ (1UL << 29) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_NFCTAG_IRQ (1UL << 30) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT0_MAILBOX_IRQ (1UL << 31) |
| | Mailbox, Wake-up from DEEP SLEEP and POWER DOWN low power mode [DEEP SLEEP, POWER DOWN].
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ADC_SEQA_IRQ (1UL << 0) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ADC_SEQB_IRQ (1UL << 1) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ADC_THCMP_OVR_IRQ (1UL << 2) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_DMIC_IRQ (1UL << 3) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_HWVAD_IRQ (1UL << 4) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_DP_IRQ (1UL << 5) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_DP0_IRQ (1UL << 6) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_DP1_IRQ (1UL << 7) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_DP2_IRQ (1UL << 8) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_LL_ALL_IRQ (1UL << 9) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MAC_IRQ (1UL << 10) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ZIGBEE_MODEM_IRQ (1UL << 11) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_RFP_TMU_IRQ (1UL << 12) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_RFP_AGC_IRQ (1UL << 13) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ISO7816_IRQ (1UL << 14) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_ANA_COMP_IRQ (1UL << 15) |
| | [DEEP SLEEP]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER0_IRQ (1UL << 16) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_WAKE_UP_TIMER1_IRQ (1UL << 17) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_WAKE_TIMER_IRQ (1UL << 22) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_BLE_OSC_EN_IRQ (1UL << 23) |
| | [DEEP SLEEP, POWER DOWN]
|
| |
|
#define | LOWPOWER_WAKEUPSRCINT1_IO_IRQ (1UL << 31) |
| | [POWER DOWN, DEEP DOWN]
|
| |
| #define | LOWPOWER_SLEEPPOSTPONE_FORCED (1UL << 0) |
| | Sleep Postpone. More...
|
| |
|
#define | LOWPOWER_SLEEPPOSTPONE_PERIPHERALS (1UL << 1) |
| | USART0, USART1, SPI0, SPI1, I2C0, I2C1, I2C2 interrupts can postpone power down modes in case an \ \ interrupt is pending when the processor request low power mode.
|
| |
|
#define | LOWPOWER_SLEEPPOSTPONE_DMIC (1UL << 0) |
| | DMIC interrupt can postpone power down modes in case an interrupt is pending when the processor \ \ request low power mode.
|
| |
|
#define | LOWPOWER_SLEEPPOSTPONE_SDMA (1UL << 1) |
| | System DMA interrupt can postpone power down modes in case an interrupt is pending when the \ \ processor request low power mode.
|
| |
|
#define | LOWPOWER_SLEEPPOSTPONE_NFCTAG (1UL << 0) |
| | NFC Tag interrupt can postpone power down modes in case an interrupt is pending when the \ \ processor request low power mode.
|
| |
|
#define | LOWPOWER_SLEEPPOSTPONE_BLEOSC (1UL << 1) |
| | BLE_OSC_EN interrupt can postpone power down modes in case an interrupt is pending when the \ \ processor request low power mode.
|
| |
|
#define | LOWPOWER_WAKEUPIOSRC_PIO0 (1UL << 0) |
| | Wake up I/O sources.
|
| |
|
#define | LOWPOWER_GPIOLATCH_PIO0 (1UL << 0) |
| | I/O whose state must be kept in Power Down mode.
|
| |
|
#define | LOWPOWER_TIMERCFG_ENABLE_INDEX 0 |
| | Wake up timers configuration in Low Power Modes.
|
| |
|
#define | LOWPOWER_TIMERCFG_TIMER_ENABLE 1 |
| | Wake Timer Enable.
|
| |
| #define | LOWPOWER_TIMERCFG_TIMER_WAKEUPTIMER0 0 |
| | Primary Wake up timers configuration in Low Power Modes. More...
|
| |
|
#define | LOWPOWER_TIMERCFG_TIMER_WAKEUPTIMER1 1 |
| | Zigbee Wake up Counter 1 used as wake up source.
|
| |
|
#define | LOWPOWER_TIMERCFG_TIMER_BLEWAKEUPTIMER 2 |
| | BLE Wake up Counter used as wake up source.
|
| |
|
#define | LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 3 |
| | 1 KHz Real Time Counter (RTC) used as wake up source
|
| |
|
#define | LOWPOWER_TIMERCFG_TIMER_RTC1HZ 4 |
| | 1 Hz Real Time Counter (RTC) used as wake up source
|
| |
| #define | LOWPOWER_TIMERCFG_2ND_TIMER_WAKEUPTIMER0 0 |
| | Secondary Wake up timers configuration in Low Power Modes. More...
|
| |
|
#define | LOWPOWER_TIMERCFG_2ND_TIMER_WAKEUPTIMER1 1 |
| | Zigbee Wake up Counter 1 used as secondary wake up source.
|
| |
|
#define | LOWPOWER_TIMERCFG_2ND_TIMER_BLEWAKEUPTIMER 2 |
| | BLE Wake up Counter used as secondary wake up source.
|
| |
|
#define | LOWPOWER_TIMERCFG_2ND_TIMER_RTC1KHZ 3 |
| | 1 KHz Real Time Counter (RTC) used as secondary wake up source
|
| |
|
#define | LOWPOWER_TIMERCFG_2ND_TIMER_RTC1HZ 4 |
| | 1 Hz Real Time Counter (RTC) used as secondary wake up source
|
| |
|
#define | LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 |
| | Wake up Timers uses FRO 32 KHz as clock source.
|
| |
|
#define | LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 |
| | Wake up Timers uses Chrystal 32 KHz as clock source.
|
| |
|
#define | LOWPOWER_TIMERBLECFG_RADIOEN_INDEX 0 |
| | BLE Wake up timers configuration in Low Power Modes.
|
| |
|
#define | RD_RIGHT (1<<0) |
| | bits for access right
|
| |
| #define | PSECTOR_PAGE_WORDS 30 |
| | PSECTOR_PAGE_WORDS number of 16 byte words available in page A page is 512 bytes in size. More...
|
| |
|
#define | PSECTOR_PAGE0_MAGIC 0xc51d8ca9 |
| | PSECTOR_PAGE0_MAGIC magic word to identify PAGE0 page in header.
|
| |
|
#define | PSECTOR_PFLASH_MAGIC 0xa7b4353d |
| | PSECTOR_PFLASH_MAGIC magic word to identify PFLASH page in header.
|
| |
|
#define | IMG_DIRECTORY_MAX_SIZE 8 |
| | IMG_DIRECTORY_MAX_SIZE max number of entries in image directory Concerns Secondary Stage Bootloader only.
|
| |
|
#define | CERTIFICATE_MARKER (0xCE27CE27) |
| | CERTIFICATE_MARKER magic value identifying certificate.
|
| |
|
| static ErrorCode_t | aesInit (void) |
| | Initialize the AES. More...
|
| |
| static void | aesWriteByte (uint32_t offset, uint8_t val8) |
| | AES control function, byte write (useful for writing configuration register) More...
|
| |
| static void | aesWrite (uint32_t offset, uint32_t val32) |
| | AES control function, word write. More...
|
| |
| static void | aesRead (uint32_t offset, uint32_t *pVal32) |
| | AES control function, word read. More...
|
| |
| static void | aesWriteBlock (uint32_t offset, uint32_t *pVal32, uint32_t numBytes) |
| | AES control function, block write (used for multi-register block writes) More...
|
| |
| static void | aesReadBlock (uint32_t offset, uint32_t *pVal32, uint32_t numBytes) |
| | AES control function, block read (used for multi-register block read) More...
|
| |
| static ErrorCode_t | aesMode (AES_MODE_T modeVal, uint32_t flags) |
| | Sets up the AES mode. More...
|
| |
| static ErrorCode_t | aesAbort (int wipe) |
| | Aborts optional AES operation and wipes AES engine. More...
|
| |
| static ErrorCode_t | aesLoadCounter (uint32_t counter) |
| | Loads the increment that is used when in counter modes in the AES block. More...
|
| |
| static ErrorCode_t | aesLoadKeyFromSW (AES_KEY_SIZE_T keySize, uint32_t *key) |
| | Loads the passed (software) key into the AES block. More...
|
| |
| static ErrorCode_t | aesLoadIV (uint32_t *pIv) |
| | Loads the Initialization Vector (IV) into the AES block. More...
|
| |
| static ErrorCode_t | aesProcess (uint32_t *pBlockIn, uint32_t *pBlockOut, uint32_t numBlocks) |
| | Process AES blocks (descrypt or encrypt) More...
|
| |
| static ErrorCode_t | aesWriteYInputGf128 (uint32_t *pYGf128) |
| | Sets the Y input of the GF128 hash used in GCM mode. More...
|
| |
| static ErrorCode_t | aesReadGf128Hash (uint32_t *pGf128Hash) |
| | Reads the results of the GF128(Z) hash used in GCM mode. More...
|
| |
| static ErrorCode_t | aesReadGcmTag (uint32_t *pGcmTag) |
| | Reads the GCM tag. More...
|
| |
| static uint32_t | aesGetDriverVersion (void) |
| | Returns the version of the AES driver in ROM. More...
|
| |
| static ErrorCode_t | aesIsSupported (void) |
| | Returns status of AES IP block (supported or not) More...
|
| |
| static uint32_t | BOOT_RemapAddress (uint32_t address) |
| | Convert logical address into physical address, based on SYSCOM MEMORYREMAP register. More...
|
| |
| static uint32_t | boot_Verify_eScoreImageList (IMAGE_DATA_T *list_head) |
| | Parse the image chained list and select the first valid entry. More...
|
| |
| static uint32_t | BOOT_FindImage (uint32_t start_addr, uint32_t end_addr, uint32_t signature, IMAGE_VERIFY_T verify) |
| | Search for a valid executable image between boundaries in internal flash. More...
|
| |
| static uint32_t | BOOT_GetStartPowerMode (void) |
| | Retrieve LPMode value that has been saved previously in retained RAM bank. More...
|
| |
| static void | BOOT_SetResumeStackPointer (uint32_t stack_pointer) |
| | Sets the value of stack pointer to be restored on warm boot. More...
|
| |
| static void | ROM_GetFlash (uint32_t *address, uint32_t *size) |
| | Retrieve Internal flash address and size. More...
|
| |
| static void | ROM_GetSRAM0 (uint32_t *address, uint32_t *size) |
| | Retrieve SRAM0 address and size. More...
|
| |
| static void | ROM_GetSRAM1 (uint32_t *address, uint32_t *size) |
| | Retrieve SRAM1 address and size. More...
|
| |
| static int | ISP_Entry (ISP_EXTENSION_T isp_extension) |
| | This function is invoked when ISP mode is requested. More...
|
| |
| static void | Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer (LPC_LOWPOWER_T *p_lowpower_cfg) |
| | Configure Wake or RTC timers. used for testing only. More...
|
| |
| static int | Chip_LOWPOWER_SetSystemFrequency (uint32_t frequency) |
| | Configure CPU and System Bus clock frequency. More...
|
| |
| static int | Chip_LOWPOWER_SetMemoryLowPowerMode (uint32_t p_sram_instance, uint32_t p_sram_lp_mode) |
| | Configure Memory instances Low Power Mode. More...
|
| |
| static void | Chip_LOWPOWER_GetSystemVoltages (LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage) |
| | Get System Voltages. More...
|
| |
| static void | Chip_LOWPOWER_SetSystemVoltages (LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage) |
| | Configure System Voltages. More...
|
| |
| static void | Chip_LOWPOWER_SetLowPowerMode (LPC_LOWPOWER_T *p_lowpower_cfg) |
| | Configure and enters in low power mode. More...
|
| |
| static void | Chip_LOWPOWER_ChipSoftwareReset (void) |
| | Perform a Full chip reset using Software reset bit in PMC. More...
|
| |
| static void | Chip_LOWPOWER_ArmSoftwareReset (void) |
| | Perform a digital System reset. More...
|
| |
| static int | MPU_pSectorGrantAccessRights (uint32_t addr, size_t sz, MPU_reg_settings_t *save_rule) |
| | This function is used to grant access to the pSector region. More...
|
| |
| static int | MPU_pSectorWithdrawAccessRights (MPU_reg_settings_t *save_rule) |
| | This function is used to withdraw access to the pSector region. More...
|
| |
| static void | MPU_GetCurrentSettings (MPU_Settings_t *settings) |
| | This function is used to read the MPU settings into a RAM structure. More...
|
| |
| static int | MPU_AllocateRegionDesc (void) |
| | This function is used to select the first available rule. More...
|
| |
| static uint32_t | pmc_reset_get_cause (void) |
| | Get the cause of the reset. More...
|
| |
| static void | pmc_reset_clear_cause (uint32_t mask) |
| | Clear the cause of the reset. More...
|
| |
| static psector_write_status_t | psector_WriteUpdatePage (psector_partition_id_t part_index, psector_page_t *page) |
| | This function is used to validate a page content and write it to the update page. More...
|
| |
| static void | psector_EraseUpdate (void) |
| | This function is used to validate a page content and write it to the update page. More...
|
| |
| static psector_page_state_t | psector_ReadData (psector_partition_id_t part_index, int page_number, uint32_t offset, uint32_t size, void *data) |
| | This function is used to read data from a psector partition. More...
|
| |
| static uint32_t | psector_CalculateChecksum (psector_page_t *psector_page) |
| | This function is used to calculate a page checksum. More...
|
| |
| static uint64_t | psector_Read_CustomerId (void) |
| | This function returns the CustomerId field. More...
|
| |
| static int | psector_Read_RomPatchInfo (uint32_t *patch_region_sz, uint32_t *patch_region_addr, uint32_t *patch_checksum, uint32_t *patch_checksum_valid) |
| | This function returns the ROM patch information read from the PFLASH. More...
|
| |
| static uint16_t | psector_Read_ImgAuthLevel (void) |
| | This function returns the image authentication level from the PFLASH. More...
|
| |
| static uint32_t | psector_Read_AppSearchGranularity (void) |
| | This function returns the app search granularity value from the PFLASH. More...
|
| |
| static uint32_t | psector_Read_QspiAppSearchGranularity (void) |
| | This function returns the Qspi app search granularity value from the PFLASH. More...
|
| |
| static uint64_t | psector_Read_DeviceId (void) |
| | This function returns the DeviceId value from the PFLASH. More...
|
| |
| static int | psector_Read_UnlockKey (int *valid, uint8_t key[256], bool raw) |
| | This function returns the unlock key value from the PFLASH. More...
|
| |
| static int | psector_Read_ISP_protocol_key (uint8_t key[16]) |
| | This function returns the ISP protocol AES key from PFLASH. More...
|
| |
| static uint64_t | psector_ReadIeee802_15_4_MacId1 (void) |
| | This function returns the IEEE-802.15.4 Mac address first instance from PFLASH. More...
|
| |
| static uint64_t | psector_ReadIeee802_15_4_MacId2 (void) |
| | This function returns the IEEE-802.15.4 Mac address second instance from PFLASH. More...
|
| |
| static uint64_t | psector_Read_MinDeviceId (void) |
| | This function returns the Min Device id from PFLASH. More...
|
| |
| static uint64_t | psector_Read_MaxDeviceId (void) |
| | This function returns the Max Device id from PFLASH. More...
|
| |
| static uint32_t | psector_Read_MinVersion (void) |
| | This function returns the Min Version from PAGE0. More...
|
| |
| static psector_write_status_t | psector_SetEscoreImageData (uint32_t image_addr, uint32_t min_version) |
| | This function is used to set the selected image address and MinVersion into PAGE0. More...
|
| |
| static psector_page_state_t | psector_ReadEscoreImageData (uint32_t *image_addr, uint32_t *min_version) |
| | This function returns the image address and min version value from PAGE0. More...
|
| |
| static int | psector_Read_ImagePubKey (int *valid, uint8_t key[256], bool raw) |
| | This function returns the unlock key value from PAGE0. More...
|
| |
| static uint32_t | secure_VerifySignature (uint8_t *hash, const uint8_t *signature, const uint32_t *key) |
| | This function performs an RSA 2048 signature verification. More...
|
| |
| static uint32_t | secure_VerifyBlock (uint8_t *start, uint32_t length, const uint32_t *key, const uint8_t *signature) |
| | This function performs an RSA 2048 signature verification over specified data block. More...
|
| |
| static uint32_t | secure_VerifyCertificate (const IMAGE_CERT_T *certificate, const uint32_t *key, const uint8_t *cert_signature) |
| | This function performs an RSA 2048 signature verification. More...
|
| |
| static uint32_t | secure_VerifyImage (uint32_t image_addr, const IMAGE_CERT_T *root_cert) |
| | This function verifies image authenticity. More...
|
| |
|
|
uint32_t | IMAGE_DATA_T::version |
| | version number found in image
|
| |
|
uint32_t | IMAGE_DATA_T::address |
| | start address of image
|
| |
|
struct _image_data_t * | IMAGE_DATA_T::next |
| | pointer on next IMAGE_DATA_T in list
|
| |
|
uint32_t | ISP_MEM_INFO_T::base_address |
| | base address of memory bank
|
| |
|
uint32_t | ISP_MEM_INFO_T::length |
| | total size
|
| |
|
uint32_t | ISP_MEM_INFO_T::block_size |
| | block size : flash page size
|
| |
|
uint16_t | ISP_MEM_INFO_T::flags |
| | unused
|
| |
|
ISP_MEMORY_TYPE_E | ISP_MEM_INFO_T::type |
| | memory type : note that EFUSE bank is not a memory as such - SPIFI is unimplemented
|
| |
| uint8_t | ISP_MEM_INFO_T::access |
| | bitfield of access rights: More...
|
| |
|
uint8_t | ISP_MEM_INFO_T::auth_access |
| | similar to access for authenticated commands
|
| |
|
ISP_MEM_FUNC_T * | ISP_MEM_INFO_T::func |
| | set of function pointers of this memory type see @ ISP_MEM_FUNC_T
|
| |
|
const char * | ISP_MEM_INFO_T::name |
| | name of memory bank
|
| |
|
uint32_t | ISP_ENC_STATE_T::mode |
| | 0: none - 1: AES CTR
|
| |
|
uint32_t | ISP_ENC_STATE_T::start |
| | start address of cipher/decipher operation
|
| |
|
uint32_t | ISP_ENC_STATE_T::end |
| | end address of cipher/decipher operation
|
| |
|
uint32_t | ISP_ENC_STATE_T::iv [4] |
| | Initialization vector IV : 16 bytes.
|
| |
|
uint32_t | ISP_ENC_STATE_T::key [8] |
| | AES Key - key[4..7] unused.
|
| |
|
ISP_GET_MEMORY_T | ISP_STATE_T::get_memory |
| | Function pointer to get_memory.
|
| |
|
ISP_EXTENSION_T | ISP_STATE_T::extension |
| | Function pointer to extension.
|
| |
|
uint32_t * | ISP_STATE_T::buffer |
| | buffer holding command (in stack)
|
| |
|
ISP_ENC_STATE_T | ISP_STATE_T::enc_state |
| | Embedded ciphering structure see @ ISP_ENC_STATE_T.
|
| |
|
IMAGE_CERT_T | ISP_STATE_T::certificate |
| | Certificate used to authenticate ISP commands it is composed of the custumer identifier and the unlock public key found in PFLASH.
|
| |
|
uint8_t | ISP_STATE_T::stored_hash [32] |
| | SHA=256 hash storage.
|
| |
| uint8_t | ISP_STATE_T::mode |
| | mode 0x00: inactive More...
|
| |
|
uint8_t | ISP_STATE_T::isp_level |
| | ISP level as restrained by EFUSE configuation and PFLASH parameter.
|
| |
|
uint16_t | ISP_STATE_T::buffer_size |
| | size of buffer : normally 1024
|
| |
|
uint8_t | ISP_STATE_T::unlock_disable |
| | unlock forbidden by EFUSE
|
| |
|
uint8_t | ISP_STATE_T::SWD_disable |
| | SWD Debug interface disabled.
|
| |
|
uint32_t | MPU_Settings_t::ctrl |
| | MPU Ctrl register.
|
| |
|
uint32_t | MPU_Settings_t::rbar [8] |
| | MPU RBAR array for the 8 rules.
|
| |
|
uint32_t | MPU_Settings_t::rasr [8] |
| | MPU RASR array for the 8 rules.
|
| |
|
uint32_t | image_directory_entry_t::img_base_addr |
| | image start address in internal Flash or QSPI flash
|
| |
|
uint16_t | image_directory_entry_t::img_nb_pages |
| | image number of 512 byte pages
|
| |
|
uint8_t | image_directory_entry_t::flags |
| | IMG_FLAG_BOOTABLE : bit 0, other TBD.
|
| |
|
uint8_t | image_directory_entry_t::img_type |
| | image type
|
| |
|
uint32_t | psector_header_t::checksum |
| | page checksum
|
| |
|
uint32_t | psector_header_t::magic |
| | magic: PSECTOR_PAGE0_MAGIC or PSECTOR_PFLASH_MAGIC
|
| |
|
uint16_t | psector_header_t::page_number |
| | should be 0 because both partitions contain a single page
|
| |
| struct { |
| } psector_page_data_t::page0_v2 |
| | Deprecated form kept for backward compatibility.
|
| |
| uint32_t psector_page_data_t::SelectedImageAddress |
| | Address of image to be loaded by boot ROM offset 0x20.
|
| |
| uint32_t psector_page_data_t::preferred_app_index |
| | for use with SSBL: index of application to select from image directory value 0..8 offset 0x24
|
| |
| image_directory_entry_t psector_page_data_t::ota_entry |
| | New image written by OTA : SSBL to check validity and authentication offset 0x28.
|
| |
| uint32_t psector_page_data_t::MinVersion |
| | Minimum version accepted : application's version number must be greater than this one to be accepted. More...
|
| |
| uint32_t psector_page_data_t::img_pk_valid |
| | Image public key valid offset 0x34.
|
| |
| uint32_t psector_page_data_t::flash_audit_done |
| | Flash audit done: already sought for wrongly initialized pages offset 0x38.
|
| |
| uint32_t psector_page_data_t::RESERVED1 |
| | padding reserved word
|
| |
| uint8_t psector_page_data_t::image_pubkey [256] |
| | RSA Public Key to be used to verify authenticity offset 0x40.
|
| |
| uint8_t psector_page_data_t::zigbee_install_code [36] |
| | Zigbee install code offset 0x140.
|
| |
| uint32_t psector_page_data_t::RESERVED3 [3] |
| | padding reserved wordes
|
| |
| uint8_t psector_page_data_t::zigbee_password [16] |
| | Zigbee password offset 0x170.
|
| |
| image_directory_entry_t psector_page_data_t::img_directory [IMG_DIRECTORY_MAX_SIZE] |
| | < Image directory entries array, used by OTA process to locate images and/or blobs offset 0x180
|
| |
| uint32_t psector_page_data_t::rom_patch_region_addr |
| | ROM patch entry point address. More...
|
| |
| uint32_t psector_page_data_t::rom_patch_checksum_valid |
| | ROM patch checksum valid: 0 means invalid Any other value means valid.
|
| |
| uint32_t psector_page_data_t::ISP_access_level |
| | ISP access level: 0 means full access, unsecure 0x01010101 means full access, secure 0x02020202 means write only, unsecure 0x03030303 means write only, secure 0x04040404 means locked Any other value means disabled.
|
| |
| uint16_t psector_page_data_t::application_flash_sz |
| | Application flash size, in kilobytes. More...
|
| |
| uint16_t psector_page_data_t::image_authentication_level |
| | Image authentication level: 0 means check only header validity 1 means check signature of whole image if image has changed 2 means check signature of whole image on every cold start.
|
| |
| uint16_t psector_page_data_t::unlock_key_valid |
| | 0: unlock key is not valid, >= 1: is present
|
| |
| uint16_t psector_page_data_t::ram1_bank_sz |
| | RAM bank 1 size, in kilobytes. More...
|
| |
| uint32_t psector_page_data_t::app_search_granularity |
| | Application search granularity (increment), in bytes. More...
|
| |
| uint8_t psector_page_data_t::ISP_protocol_key [16] |
| | ISP protocol key: key used to encrypt messages over ISP UART with secure access level.
|
| |
| uint64_t psector_page_data_t::ieee_mac_id1 |
| | IEEE_MAC_ID_1 (Used to over-ride MAC ID_1 in N-2 page)
|
| |
| uint64_t psector_page_data_t::ieee_mac_id2 |
| | IEEE_MAC_ID_2 if second MAC iID is required.
|
| |
| uint64_t psector_page_data_t::ble_mac_id |
| | BLE device address : only 6 LSB bytes are significant.
|
| |
| uint8_t psector_page_data_t::reserved2 [104] |
| | Reserved for future use.
|
| |
| uint64_t psector_page_data_t::customer_id |
| | Customer ID, used for secure handshake.
|
| |
| uint64_t psector_page_data_t::min_device_id |
| | Min Device ID, used for secure handshake - Certificate compatibility.
|
| |
| uint64_t psector_page_data_t::device_id |
| | Device ID, used for secure handshake.
|
| |
| uint64_t psector_page_data_t::max_device_id |
| | Max Device ID, used for secure handshake - Certificate compatibility.
|
| |
| uint8_t psector_page_data_t::unlock_key [256] |
| | 2048-bit public key for secure handshake (equivalent to ‘unlock’ key). More...
|
| |
|
uint32_t | IMAGE_CERT_T::certificate_marker |
| | Certificate marker: magic see @ CERTIFICATE_MARKER.
|
| |
|
uint32_t | IMAGE_CERT_T::certificate_id |
| | Certificate id.
|
| |
|
uint32_t | IMAGE_CERT_T::usage_flags |
| | Usage flags: mostly used in the unlocking procedure.
|
| |
|
uint64_t | IMAGE_CERT_T::customer_id |
| | Customer Id: customer chosen identifier.
|
| |
|
uint64_t | IMAGE_CERT_T::min_device_id |
| | Min device id: min device version from which certificate applies.
|
| |
|
uint64_t | IMAGE_CERT_T::max_device_id |
| | Max device id: max device version up to which certificate applies.
|
| |
|
uint32_t | IMAGE_CERT_T::public_key [SIGNATURE_LEN/4] |
| | RSA-2048 public key.
|
| |
|
IMAGE_CERT_T | ImageAuthTrailer_t::certificate |
| | The certificate see @ IMAGE_CERT_T.
|
| |
|
uint8_t | ImageAuthTrailer_t::cert_signature [SIGNATURE_LEN] |
| | The signature of the certificate.
|
| |
|
uint8_t | ImageAuthTrailer_t::img_signature [SIGNATURE_LEN] |
| | The image siganture.
|
| |
