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Kinetis SDK v.2.0 API Reference Manual
Rev. 0
NXP Semiconductors
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The MCUXpresso SDK provides a clock driver for MCUXpresso SDK devices.
Clock driver provides these functions:
SYSCON clock module provides clocks, such as ADCCLK, DMICCLK, FXCOMCLK,WDTOSC, RTCOSC and SYSPLL. The functions CLOCK_EnableClock() and CLOCK_DisableClock() enables and disables the various clocks. The SYSCON clock driver provides functions to get the frequency of clocks, such as CLOCK_GetFreq(),
The SYSCON clock driver provides the function to configure the clock selected. The function CLOCK_AttachClk() is implemented for this. The function selects the clock source for a particular peripheral like MAINCLK, DMIC, FLEXCOMM, USB, ADC and PLL.
The SYSCON clock module provides the function to setup the peripheral clock dividers. The function CLOCK_SetClkDiv() configures the CLKDIV registers for various periperals like USB, DMIC, I2S, SYSTICK, AHB, ADC and also for CLKOUT and TRACE functions.
Files | |
file | fsl_clock.h |
Data Structures | |
struct | ClockCapacitanceCompensation_t |
Board specific constant capacitance characteristics Should be supplied by board manufacturer for best performance. More... | |
Macros | |
#define | FLEXCOMM_CLOCKS |
Clock ip name array for FLEXCOMM. More... | |
#define | CTIMER_CLOCKS |
Clock ip name array for CTIMER. More... | |
#define | GINT_CLOCKS |
Clock ip name array for GINT. More... | |
#define | WWDT_CLOCKS |
Clock ip name array for WWDT. More... | |
#define | DMIC_CLOCKS |
Clock ip name array for DMIC. More... | |
#define | ADC_CLOCKS |
Clock ip name array for ADC. More... | |
#define | SPIFI_CLOCKS |
Clock ip name array for SPIFI. More... | |
#define | GPIO_CLOCKS |
Clock ip name array for GPIO. More... | |
#define | DMA_CLOCKS |
Clock ip name array for DMA. More... | |
Enumerations | |
enum | CHIP_SYSCON_MAINCLKSRC_T { SYSCON_MAINCLKSRC_FRO12M, SYSCON_MAINCLKSRC_OSC32K, SYSCON_MAINCLKSRC_XTAL32M, SYSCON_MAINCLKSRC_FRO32M, SYSCON_MAINCLKSRC_FRO48M, SYSCON_MAINCLKSRC_EXT, SYSCON_MAINCLKSRC_FRO1M } |
Clock sources for main system clock. More... | |
enum | CHIP_SYSCON_FRGCLKSRC_T { SYSCON_FRGCLKSRC_MAINCLK, SYSCON_FRGCLKSRC_OSC32M, SYSCON_FRGCLKSRC_FRO48MHZ, SYSCON_FRGCLKSRC_NONE } |
Fractional Divider clock sources. More... | |
enum | clock_name_t { kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ROM_SHIFT), kCLOCK_Sram0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT), kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT), kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_FLASH_SHIFT), kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SPIFI_SHIFT), kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_MUX_SHIFT), kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_IOCON_SHIFT), kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_GPIO_SHIFT), kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_PINT_SHIFT) , kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_DMA_SHIFT), kCLOCK_Iso7816 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ISO7816_SHIFT), kCLOCK_WdtOsc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WWDT_SHIFT), kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_RTC_SHIFT), kCLOCK_AnaInt, kCLOCK_WakeTmr, kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ADC_SHIFT), kCLOCK_Efuse = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_EFUSE_SHIFT), kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT), kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C1_SHIFT), kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI0_SHIFT), kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI1_SHIFT), kCLOCK_Ir = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_IR_SHIFT), kCLOCK_Pwm = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_PWM_SHIFT), kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_RNG_SHIFT), kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C2_SHIFT), kCLOCK_Usart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), kCLOCK_Usart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), kCLOCK_I2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT), kCLOCK_I2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C1_SHIFT), kCLOCK_Spi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI0_SHIFT), kCLOCK_Spi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI1_SHIFT), kCLOCK_I2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C2_SHIFT), kCLOCK_BLE = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_BLE_SHIFT), kCLOCK_Modem = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_MODEM_MASTER_SHIFT), kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_AES_SHIFT), kCLOCK_Rfp = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_RFP_SHIFT), kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_DMIC_SHIFT), kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_HASH_SHIFT), kCLOCK_Timer0 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 1), kCLOCK_Timer1 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 2), kCLOCK_MainClk = (1 << 16), kCLOCK_CoreSysClk, kCLOCK_BusClk, kCLOCK_Xtal32k, kCLOCK_Xtal32M, kCLOCK_Fro32k, kCLOCK_Fro1M, kCLOCK_Fro12M, kCLOCK_Fro32M, kCLOCK_Fro48M, kCLOCK_Fro64M, kCLOCK_ExtClk, kCLOCK_WdtClk, kCLOCK_Frg, kCLOCK_ClkOut, kCLOCK_Fmeas, kCLOCK_Sha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_HASH_SHIFT) } |
Clock name definition. More... | |
enum | clock_sel_ofst_t { CM_MAINCLKSEL = REG_OFST(SYSCON, MAINCLKSEL), CM_OSC32CLKSEL = REG_OFST(SYSCON, OSC32CLKSEL), CM_CLKOUTCLKSEL = REG_OFST(SYSCON, CLKOUTSEL), CM_SPIFICLKSEL = REG_OFST(SYSCON, SPIFICLKSEL), CM_ADCCLKSEL = REG_OFST(SYSCON, ADCCLKSEL), CM_USARTCLKSEL = REG_OFST(SYSCON, USARTCLKSEL), CM_I2CCLKSEL = REG_OFST(SYSCON, I2CCLKSEL), CM_SPICLKSEL = REG_OFST(SYSCON, SPICLKSEL), CM_IRCLKSEL = REG_OFST(SYSCON, IRCLKSEL), CM_PWMCLKSEL = REG_OFST(SYSCON, PWMCLKSEL), CM_WDTCLKSEL = REG_OFST(SYSCON, WDTCLKSEL), CM_MODEMCLKSEL = REG_OFST(SYSCON, MODEMCLKSEL), CM_FRGCLKSEL = REG_OFST(SYSCON, FRGCLKSEL), CM_DMICLKSEL = REG_OFST(SYSCON, DMICCLKSEL), CM_WKTCLKSEL = REG_OFST(SYSCON, WKTCLKSEL) } |
Clock source selector definition. More... | |
enum | clock_attach_id_t { kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 0), kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 1), kXTAL32M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 2), kFRO32M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 3), kFRO48M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 4), kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 5), kFROM1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSEL, 6), kFRO32M_to_OSC32M_CLK = MUX_A(CM_OSC32CLKSEL, 0), kXTAL32M_to_OSC32M_CLK = MUX_A(CM_OSC32CLKSEL, 1), kFRO32K_to_OSC32K_CLK = MUX_A(CM_OSC32CLKSEL, 2), kXTAL32K_to_OSC32K_CLK = MUX_A(CM_OSC32CLKSEL, 3), kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), kXTAL32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), kFRO32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), kXTAL32M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), kDCDC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), kFRO48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), kMAIN_CLK_to_SPIFI = MUX_A(CM_SPIFICLKSEL, 0), kXTAL32M_to_SPIFI = MUX_A(CM_SPIFICLKSEL, 1), kFRO64M_to_SPIFI = MUX_A(CM_SPIFICLKSEL, 2), kFRO48M_to_SPIFI = MUX_A(CM_SPIFICLKSEL, 3), kXTAL32M_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 0), kFRO12M_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 1), kNONE_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 2), kOSC32M_to_USART_CLK = MUX_A(CM_USARTCLKSEL, 0), kFRO48M_to_USART_CLK = MUX_A(CM_USARTCLKSEL, 1), kFRG_CLK_to_USART_CLK = MUX_A(CM_USARTCLKSEL, 2), kNONE_to_USART_CLK = MUX_A(CM_USARTCLKSEL, 3), kOSC32M_to_I2C_CLK = MUX_A(CM_I2CCLKSEL, 0), kFRO48M_to_I2C_CLK = MUX_A(CM_I2CCLKSEL, 1), kNONE_to_I2C_CLK = MUX_A(CM_I2CCLKSEL, 2), kOSC32M_to_SPI_CLK = MUX_A(CM_SPICLKSEL, 0), kFRO48M_to_SPI_CLK = MUX_A(CM_SPICLKSEL, 1), kNONE_to_SPI_CLK = MUX_A(CM_SPICLKSEL, 2), kOSC32M_to_IR_CLK = MUX_A(CM_IRCLKSEL, 0), kFRO48M_to_IR_CLK = MUX_A(CM_IRCLKSEL, 1), kNONE_to_IR_CLK = MUX_A(CM_IRCLKSEL, 2), kOSC32M_to_PWM_CLK = MUX_A(CM_PWMCLKSEL, 0), kFRO48M_to_PWM_CLK = MUX_A(CM_PWMCLKSEL, 1), kNONE_to_PWM_CLK = MUX_A(CM_PWMCLKSEL, 2), kOSC32M_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 0), kOSC32K_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 1), kFRO1M_to_WDT_CLK = MUX_A(CM_WDTCLKSEL, 2), kMAIN_CLK_to_FRG_CLK = MUX_A(CM_FRGCLKSEL, 0), kOSC32M_to_FRG_CLK = MUX_A(CM_FRGCLKSEL, 1), kFRO48M_to_FRG_CLK = MUX_A(CM_FRGCLKSEL, 2), kNONE_to_FRG_CLK = MUX_A(CM_FRGCLKSEL, 3), kMAIN_CLK_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 0), kOSC32K_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 1), kFRO48M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 2), kMCLK_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 3), kFRO1M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 4), kFRO12M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 5), kNONE_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 6), kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0), kNONE_to_WKT_CLK = MUX_A(CM_DMICLKSEL, 3), kXTAL32M_to_BLE_CLK = MUX_A(CM_MODEMCLKSEL, 3), kNONE_to_BLE_CLK = MUX_A(CM_MODEMCLKSEL, 1), kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), kXTAL32M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), kFRO32M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), kFRO48M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3) } |
Clock attach definition. More... | |
enum | clock_div_name_t { , kCLOCK_DivSystickClk = (offsetof(SYSCON_Type, SYSTICKCLKDIV) / sizeof(uint32_t)), kCLOCK_DivTraceClk = (offsetof(SYSCON_Type, TRACECLKDIV) / sizeof(uint32_t)), kCLOCK_DivWdtClk = (offsetof(SYSCON_Type, WDTCLKDIV) / sizeof(uint32_t)), kCLOCK_DivIrClk = (offsetof(SYSCON_Type, IRCLKDIV) / sizeof(uint32_t)), kCLOCK_DivAhbClk = (offsetof(SYSCON_Type, AHBCLKDIV) / sizeof(uint32_t)), kCLOCK_DivClkout = (offsetof(SYSCON_Type, CLKOUTDIV) / sizeof(uint32_t)), kCLOCK_DivSpifiClk = (offsetof(SYSCON_Type, SPIFICLKDIV) / sizeof(uint32_t)), kCLOCK_DivAdcClk = (offsetof(SYSCON_Type, ADCCLKDIV) / sizeof(uint32_t)), kCLOCK_DivRtcClk = (offsetof(SYSCON_Type, RTCCLKDIV) / sizeof(uint32_t)), kCLOCK_DivDmicClk = (offsetof(SYSCON_Type, DMICCLKDIV) / sizeof(uint32_t)), kCLOCK_DivRtc1HzClk = (offsetof(SYSCON_Type, RTC1HZCLKDIV) / sizeof(uint32_t)), kCLOCK_DivFrg = (offsetof(SYSCON_Type, FRGCTRL) / sizeof(uint32_t)) } |
Clock divider definition. More... | |
enum | main_clock_src_t { kCLOCK_MainFro12M = 0, kCLOCK_MainOsc32k = 1, kCLOCK_MainXtal32M = 2, kCLOCK_MainFro32M = 3, kCLOCK_MainFro48M = 4, kCLOCK_MainExtClk = 5, kCLOCK_MainFro1M = 6 } |
Clock source selections for the Main Clock. More... | |
enum | clkout_clock_src_t { kCLOCK_ClkoutMainClk = 0, kCLOCK_ClkoutXtal32k = 1, kCLOCK_ClkoutFro32k = 2, kCLOCK_ClkoutXtal32M = 3, kCLOCK_ClkoutDcDcTest = 4, kCLOCK_ClkoutFro48M = 5, kCLOCK_ClkoutFro1M = 6, kCLOCK_ClkoutNoClock = 7 } |
Clock source selections for CLKOUT. More... | |
enum | wdt_clock_src_t { kCLOCK_WdtOsc32MClk = 0, kCLOCK_WdtOsc32kClk = 1, kCLOCK_WdtFro1M = 2, kCLOCK_WdtNoClock = 3 } |
Clock source definition for Watchdog timer. More... | |
enum | frg_clock_src_t { kCLOCK_FrgMainClk = 0, kCLOCK_FrgOsc32MClk = 1, kCLOCK_FrgFro48M = 2, kCLOCK_FrgNoClock = 3 } |
Clock source definition for fractional divider. More... | |
enum | apb_clock_src_t { kCLOCK_ApbMainClk = 0, kCLOCK_ApbXtal32M = 1, kCLOCK_ApbFro32M = 2, kCLOCK_ApbFro48M = 3 } |
Clock source definition for the APB. More... | |
enum | fmeas_clock_src_t { kCLOCK_fmeasClkIn = 0, kCLOCK_fmeasXtal32Mhz = 1, kCLOCK_fmeasFRO1Mhz = 2, kCLOCK_fmeasXtal32kHz = 3, kCLOCK_fmeasMainClock = 4, kCLOCK_fmeasGPIO_0_4 = 5, kCLOCK_fmeasGPIO_0_20 = 6, kCLOCK_fmeasGPIO_0_16 = 7, kCLOCK_fmeasGPIO_0_15 = 8 } |
Clock source definition for frequency measure. More... | |
enum | spifi_clock_src_t { kCLOCK_SpifiMainClk = 0, kCLOCK_SpifiXtal32M = 1, kCLOCK_SpifiFro64M = 2, kCLOCK_SpifiFro48M = 3, kCLOCK_SpifiNoClock = 4 } |
Clock source selection for SPIFI. More... | |
enum | adc_clock_src_t { kCLOCK_AdcXtal32M = 0, kCLOCK_AdcFro12M = 1, kCLOCK_AdcNoClock = 2 } |
Clock definition for ADC. More... | |
enum | pwm_clock_source_t { kCLOCK_PWMOsc32Mclk = 0x0, kCLOCK_PWMFro48Mclk = 0x1, kCLOCK_PWMNoClkSel = 0x2, kCLOCK_PWMTestClk = 0x3 } |
PWM Clock source selection values. More... | |
enum | Fro_ClkSel_t { FRO12M_ENA = (1 << 0), FRO32M_ENA = (1 << 1), FRO48M_ENA = (1 << 2), FRO64M_ENA = (1 << 3), FRO96M_ENA = (1 << 4) } |
FRO clock selection values. More... | |
Functions | |
uint32_t | CLOCK_GetFreq (clock_name_t clock) |
Obtains frequency of specified clock. More... | |
void | CLOCK_AttachClk (clock_attach_id_t connection) |
Selects clock source using <name>SEL register in syscon. More... | |
void | CLOCK_SetClkDiv (clock_div_name_t div_name, uint32_t divided_by_value, bool reset) |
Selects clock divider using <name>DIV register in syscon. More... | |
void | CLOCK_EnableClock (clock_ip_name_t clk) |
Enables specific AHB clock channel. More... | |
void | CLOCK_DisableClock (clock_ip_name_t clk) |
Disables specific AHB clock channel. More... | |
bool | CLOCK_IsClockEnable (clock_ip_name_t clk) |
Check if clock is enabled. More... | |
uint32_t | CLOCK_GetApbCLkFreq (void) |
Obtains frequency of APB Bus clock. More... | |
uint32_t | CLOCK_GetSpifiClkFreq (void) |
Return Frequency of Spifi Clock. More... | |
void | CLOCK_uDelay (uint32_t delayUs) |
Delay execution by busy waiting. More... | |
void | CLOCK_XtalBasicTrim (void) |
Sets default trim values for 32MHz XTAL. More... | |
void | CLOCK_Xtal32M_Trim (int32_t XO_32M_OSC_CAP_Delta_x1000, const ClockCapacitanceCompensation_t *capa_charac) |
Sets board-specific trim values for 32MHz XTAL. More... | |
void | CLOCK_Xtal32k_Trim (int32_t XO_32k_OSC_CAP_Delta_x1000, const ClockCapacitanceCompensation_t *capa_charac) |
Sets board-specific trim values for 32kHz XTAL. More... | |
void | CLOCK_SetXtal32M_LDO (void) |
Enables and sets LDO for 32MHz XTAL. More... | |
void | CLOCK_Xtal32M_WaitUntilStable (uint32_t u32AdditionalWait_us) |
Waits for 32MHz XTAL to stabilise. More... | |
Driver version | |
#define | FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) |
CLOCK driver version 2.1.0. More... | |
struct ClockCapacitanceCompensation_t |
Capacitances are expressed in hundreds of pF
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) |
#define FLEXCOMM_CLOCKS |
#define CTIMER_CLOCKS |
#define GINT_CLOCKS |
#define WWDT_CLOCKS |
#define DMIC_CLOCKS |
#define ADC_CLOCKS |
#define SPIFI_CLOCKS |
#define GPIO_CLOCKS |
#define DMA_CLOCKS |
enum clock_name_t |
enum clock_sel_ofst_t |
enum clock_attach_id_t |
enum clock_div_name_t |
enum main_clock_src_t |
enum clkout_clock_src_t |
enum wdt_clock_src_t |
enum frg_clock_src_t |
enum apb_clock_src_t |
enum fmeas_clock_src_t |
enum spifi_clock_src_t |
enum adc_clock_src_t |
enum pwm_clock_source_t |
enum Fro_ClkSel_t |
uint32_t CLOCK_GetFreq | ( | clock_name_t | clock | ) |
clock_name_t | specify clock to be read |
void CLOCK_AttachClk | ( | clock_attach_id_t | connection | ) |
clock_attach_id_t | specify clock mapping |
void CLOCK_SetClkDiv | ( | clock_div_name_t | div_name, |
uint32_t | divided_by_value, | ||
bool | reset | ||
) |
clock_div_name_t | specifies which DIV register we are accessing |
uint32_t | specifies divisor |
bool | true if a syscon clock reset should also be carried out |
void CLOCK_EnableClock | ( | clock_ip_name_t | clk | ) |
clock_ip_name_t | specifies which peripheral clock we are controlling |
void CLOCK_DisableClock | ( | clock_ip_name_t | clk | ) |
clock_ip_name_t | specifies which peripheral clock we are controlling |
bool CLOCK_IsClockEnable | ( | clock_ip_name_t | clk | ) |
clock_ip_name_t | specifies which peripheral clock we are controlling |
uint32_t CLOCK_GetApbCLkFreq | ( | void | ) |
none |
uint32_t CLOCK_GetSpifiClkFreq | ( | void | ) |
void CLOCK_uDelay | ( | uint32_t | delayUs | ) |
delayUs | delay duration in micro seconds |
void CLOCK_XtalBasicTrim | ( | void | ) |
none |
void CLOCK_Xtal32M_Trim | ( | int32_t | XO_32M_OSC_CAP_Delta_x1000, |
const ClockCapacitanceCompensation_t * | capa_charac | ||
) |
XO_32M_OSC_CAP_Delta_x1000 | capacitance correction in fF (femtoFarad) |
capa_charac | board 32M capacitance characteristics pointer |
void CLOCK_Xtal32k_Trim | ( | int32_t | XO_32k_OSC_CAP_Delta_x1000, |
const ClockCapacitanceCompensation_t * | capa_charac | ||
) |
XO_32k_OSC_CAP_Delta_x1000 | capacitance correction in fF |
capa_charac | board 32k capacitance characteristics pointer |
void CLOCK_SetXtal32M_LDO | ( | void | ) |
none |
void CLOCK_Xtal32M_WaitUntilStable | ( | uint32_t | u32AdditionalWait_us | ) |
u32AdditionalWait_us | Additional wait after hardware indicates that stability has been reached |