Power Driver

Overview

Power driver provides APIs to control peripherals power and control the system power mode.

Macros
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX0   (1UL << 0)
	SRAM instances retention control during low power modes. More...
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX1   (1UL << 1)
	Enable SRAMX_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX2   (1UL << 2)
	Enable SRAMX_2 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAMX3   (1UL << 3)
	Enable SRAMX_3 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM00   (1UL << 4)
	Enable SRAM0_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM01   (1UL << 5)
	Enable SRAM0_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM10   (1UL << 6)
	Enable SRAM1_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM20   (1UL << 7)
	Enable SRAM2_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM30   (1UL << 8)
	Enable SRAM3_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM31   (1UL << 9)
	Enable SRAM3_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM40   (1UL << 10)
	Enable SRAM4_0 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM41   (1UL << 11)
	Enable SRAM4_1 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM42   (1UL << 12)
	Enable SRAM4_2 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM43   (1UL << 13)
	Enable SRAM4_3 retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS   (1UL << 14)
	Enable SRAM USB HS retention when entering in Low power modes.
#define	LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF   (1UL << 15)
	Enable SRAM PUFF retention when entering in Low power modes.
#define	WAKEUP_SYS   (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
	Low Power Modes Wake up sources.
#define	WAKEUP_SDMA0   (1ULL << 1)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_GLOBALINT0   (1ULL << 2)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_GLOBALINT1   (1ULL << 3)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_INT0_0   (1ULL << 4)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_1   (1ULL << 5)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_2   (1ULL << 6)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_3   (1ULL << 7)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_UTICK   (1ULL << 8)
	[SLEEP, ]
#define	WAKEUP_MRT   (1ULL << 9)
	[SLEEP, ]
#define	WAKEUP_CTIMER0   (1ULL << 10)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER1   (1ULL << 11)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SCT   (1ULL << 12)
	[SLEEP, ]
#define	WAKEUP_CTIMER3   (1ULL << 13)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM0   (1ULL << 14)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM1   (1ULL << 15)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM2   (1ULL << 16)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM3   (1ULL << 17)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_FLEXCOMM4   (1ULL << 18)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM5   (1ULL << 19)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM6   (1ULL << 20)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_FLEXCOMM7   (1ULL << 21)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_ADC   (1ULL << 22)
	[SLEEP, ]
#define	WAKEUP_ACMP_CAPT   (1ULL << 24)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_USB0_NEEDCLK   (1ULL << 27)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_USB0   (1ULL << 28)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_RTC_LITE_ALARM_WAKEUP   (1ULL << 29)
	[SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN]
#define	WAKEUP_EZH_ARCH_B   (1ULL << 30)
	[SLEEP, ]
#define	WAKEUP_WAKEUP_MAILBOX   (1ULL << 31)
	[SLEEP, DEEP SLEEP, POWER DOWN ]
#define	WAKEUP_GPIO_INT0_4   (1ULL << 32)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_5   (1ULL << 33)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_6   (1ULL << 34)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_GPIO_INT0_7   (1ULL << 35)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER2   (1ULL << 36)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_CTIMER4   (1ULL << 37)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_OS_EVENT_TIMER   (1ULL << 38)
	[SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN]
#define	WAKEUP_SDIO   (1ULL << 42)
	[SLEEP, ]
#define	WAKEUP_USB1   (1ULL << 47)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_USB1_NEEDCLK   (1ULL << 48)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SEC_HYPERVISOR_CALL   (1ULL << 49)
	[SLEEP, ]
#define	WAKEUP_SEC_GPIO_INT0_0   (1ULL << 50)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SEC_GPIO_INT0_1   (1ULL << 51)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_PLU   (1ULL << 52)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_SHA   (1ULL << 54)
	[SLEEP, ]
#define	WAKEUP_CASPER   (1ULL << 55)
	[SLEEP, ]
#define	WAKEUP_PUFF   (1ULL << 56)
	[SLEEP, ]
#define	WAKEUP_PQ   (1ULL << 57)
	[SLEEP, ]
#define	WAKEUP_SDMA1   (1ULL << 58)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_LSPI_HS   (1ULL << 59)
	[SLEEP, DEEP SLEEP ]
#define	WAKEUP_ALLWAKEUPIOS   (1ULL << 63)
	[ , DEEP POWER DOWN]
#define	LOWPOWER_HWWAKE_FORCED   (1UL << 0)
	Sleep Postpone. More...
#define	LOWPOWER_HWWAKE_PERIPHERALS   (1UL << 1)
	Wake for Flexcomms. More...
#define	LOWPOWER_HWWAKE_SDMA0   (1UL << 3)
	Wake for DMA0. More...
#define	LOWPOWER_HWWAKE_SDMA1   (1UL << 5)
	Wake for DMA1. More...
#define	LOWPOWER_HWWAKE_ENABLE_FRO192M   (1UL << 31)
	Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set.
#define	LOWPOWER_CPURETCTRL_ENA_DISABLE   0
	In POWER DOWN mode, CPU Retention is disabled.
#define	LOWPOWER_CPURETCTRL_ENA_ENABLE   1
	In POWER DOWN mode, CPU Retention is enabled.
#define	LOWPOWER_WAKEUPIOSRC_PIO0_INDEX   0
	Wake up I/O sources. More...
#define	LOWPOWER_WAKEUPIOSRC_PIO1_INDEX   2
	Pin P0(28)
#define	LOWPOWER_WAKEUPIOSRC_PIO2_INDEX   4
	Pin P1(18)
#define	LOWPOWER_WAKEUPIOSRC_PIO3_INDEX   6
	Pin P1(30)
#define	LOWPOWER_WAKEUPIOSRC_DISABLE   0
	Wake up is disable.
#define	LOWPOWER_WAKEUPIOSRC_RISING   1
	Wake up on rising edge.
#define	LOWPOWER_WAKEUPIOSRC_FALLING   2
	Wake up on falling edge.
#define	LOWPOWER_WAKEUPIOSRC_RISING_FALLING   3
	Wake up on both rising or falling edges.
#define	LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX   8
	Wake-up I/O 0 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX   9
	Wake-up I/O 1 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX   10
	Wake-up I/O 2 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX   11
	Wake-up I/O 3 pull-up/down configuration index.
#define	LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX)
	Wake-up I/O 0 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX)
	Wake-up I/O 1 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX)
	Wake-up I/O 2 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX)
	Wake-up I/O 3 pull-up/down mask.
#define	LOWPOWER_WAKEUPIO_PULLDOWN   0
	Select pull-down.
#define	LOWPOWER_WAKEUPIO_PULLUP   1
	Select pull-up.
#define	LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX   12
	Wake-up I/O 0 pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX   13
	Wake-up I/O 1 pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX   14
	Wake-up I/O 2 pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX   15
	Wake-up I/O 3 pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX)
	Wake-up I/O 0 pull-up/down disable/enable mask.
#define	LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX)
	Wake-up I/O 1 pull-up/down disable/enable mask.
#define	LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX)
	Wake-up I/O 2 pull-up/down disable/enable mask.
#define	LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX)
	Wake-up I/O 3 pull-up/down disable/enable mask.
#define	LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX   (16)
	Wake-up I/O 0 use external pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX   (17)
	Wake-up I/O 1 use external pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX   (18)
	Wake-up I/O 2 use external pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX   (19)
	Wake-up I/O 3 use external pull-up/down disable/enable control index.
#define	LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX)
	Wake-up I/O 0 use external pull-up/down \ disable/enable mask, 0: disable, 1: enable.
#define	LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX)
	Wake-up I/O 1 use external pull-up/down \ disable/enable mask, 0: disable, 1: enable.
#define	LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX)
	Wake-up I/O 2 use external pull-up/down \ disable/enable mask, 0: disable, 1: enable.
#define	LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK   (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX)
	Wake-up I/O 3 use external pull-up/down \ disable/enable mask, 0: disable, 1: enable.

Enumerations
enum	pd_bit_t
	Analog components power modes control during low power modes.
enum	power_bod_vbat_level_t {   kPOWER_BodVbatLevel1000mv = 0,   kPOWER_BodVbatLevel1100mv = 1,   kPOWER_BodVbatLevel1200mv = 2,   kPOWER_BodVbatLevel1300mv = 3,   kPOWER_BodVbatLevel1400mv = 4,   kPOWER_BodVbatLevel1500mv = 5,   kPOWER_BodVbatLevel1600mv = 6,   kPOWER_BodVbatLevel1650mv = 7,   kPOWER_BodVbatLevel1700mv = 8,   kPOWER_BodVbatLevel1750mv = 9,   kPOWER_BodVbatLevel1800mv = 10,   kPOWER_BodVbatLevel1900mv = 11,   kPOWER_BodVbatLevel2000mv = 12,   kPOWER_BodVbatLevel2100mv = 13,   kPOWER_BodVbatLevel2200mv = 14,   kPOWER_BodVbatLevel2300mv = 15,   kPOWER_BodVbatLevel2400mv = 16,   kPOWER_BodVbatLevel2500mv = 17,   kPOWER_BodVbatLevel2600mv = 18,   kPOWER_BodVbatLevel2700mv = 19,   kPOWER_BodVbatLevel2806mv = 20,   kPOWER_BodVbatLevel2900mv = 21,   kPOWER_BodVbatLevel3000mv = 22,   kPOWER_BodVbatLevel3100mv = 23,   kPOWER_BodVbatLevel3200mv = 24,   kPOWER_BodVbatLevel3300mv = 25 }
	BOD VBAT level. More...
enum	power_bod_hyst_t {   kPOWER_BodHystLevel25mv = 0U,   kPOWER_BodHystLevel50mv = 1U,   kPOWER_BodHystLevel75mv = 2U,   kPOWER_BodHystLevel100mv = 3U }
	BOD Hysteresis control. More...
enum	power_bod_core_level_t {   kPOWER_BodCoreLevel600mv = 0,   kPOWER_BodCoreLevel650mv = 1,   kPOWER_BodCoreLevel700mv = 2,   kPOWER_BodCoreLevel750mv = 3,   kPOWER_BodCoreLevel800mv = 4,   kPOWER_BodCoreLevel850mv = 5,   kPOWER_BodCoreLevel900mv = 6,   kPOWER_BodCoreLevel950mv = 7 }
	BOD core level. More...
enum	power_device_reset_cause_t {   kRESET_CAUSE_POR = 0UL,   kRESET_CAUSE_PADRESET = 1UL,   kRESET_CAUSE_BODRESET = 2UL,   kRESET_CAUSE_ARMSYSTEMRESET = 3UL,   kRESET_CAUSE_WDTRESET = 4UL,   kRESET_CAUSE_SWRRESET = 5UL,   kRESET_CAUSE_CDOGRESET = 6UL,   kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL,   kRESET_CAUSE_DPDRESET_RTC = 8UL,   kRESET_CAUSE_DPDRESET_OSTIMER = 9UL,   kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL,   kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL,   kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL,   kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL,   kRESET_CAUSE_NOT_RELEVANT,   kRESET_CAUSE_NOT_DETERMINISTIC = 15UL }
	Device Reset Causes. More...
enum	power_device_boot_mode_t {   kBOOT_MODE_POWER_UP,   kBOOT_MODE_LP_DEEP_SLEEP = 1UL,   kBOOT_MODE_LP_POWER_DOWN = 2UL,   kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL }
	Device Boot Modes. More...

Functions
static void	POWER_EnablePD (pd_bit_t en)
	API to enable PDRUNCFG bit in the Syscon. More...
static void	POWER_DisablePD (pd_bit_t en)
	API to disable PDRUNCFG bit in the Syscon. More...
static void	POWER_SetBodVbatLevel (power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)
	set BOD VBAT level. More...
static void	POWER_EnableDeepSleep (void)
	API to enable deep sleep bit in the ARM Core. More...
static void	POWER_DisableDeepSleep (void)
	API to disable deep sleep bit in the ARM Core. More...
void	POWER_CycleCpuAndFlash (void)
	Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event This MUST BE EXECUTED outside the Flash: either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is preferable to have all functions defined in this file implemented in ROM. More...
void	POWER_EnterDeepSleep (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t hardware_wake_ctrl)
	Configures and enters in DEEP-SLEEP low power mode. More...
void	POWER_EnterPowerDown (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl)
	Configures and enters in POWERDOWN low power mode. More...
void	POWER_EnterDeepPowerDown (uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl)
	Configures and enters in DEEPPOWERDOWN low power mode. More...
void	POWER_EnterSleep (void)
	Configures and enters in SLEEP low power mode. More...
void	POWER_SetVoltageForFreq (uint32_t system_freq_hz)
	Power Library API to choose normal regulation and set the voltage for the desired operating frequency. More...
uint32_t	POWER_GetLibVersion (void)
	Power Library API to return the library version. More...
void	POWER_Xtal16mhzCapabankTrim (int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100)
	Sets board-specific trim values for 16MHz XTAL. More...
void	POWER_Xtal32khzCapabankTrim (int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100)
	Sets board-specific trim values for 32kHz XTAL. More...
void	POWER_SetXtal16mhzLdo (void)
	Enables and sets LDO for 16MHz XTAL. More...
void	POWER_SetXtal16mhzTrim (uint32_t amp, uint32_t gm)
	Set up 16-MHz XTAL Trimmings. More...
void	POWER_GetWakeUpCause (power_device_reset_cause_t *p_reset_cause, power_device_boot_mode_t *p_boot_mode, uint32_t *p_wakeupio_cause)
	Return some key information related to the device reset causes / wake-up sources, for all power modes. More...

Driver version
#define	FSL_POWER_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))
	power driver version 1.0.0. More...

Macro Definition Documentation

#define FSL_POWER_DRIVER_VERSION   (MAKE_VERSION(1, 0, 0))

#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0   (1UL << 0)

Enable SRAMX_0 retention when entering in Low power modes

#define LOWPOWER_HWWAKE_FORCED   (1UL << 0)

Force peripheral clocking to stay on during deep-sleep mode.

#define LOWPOWER_HWWAKE_PERIPHERALS   (1UL << 1)

Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ peripheral clocking to wake up temporarily while the related status is asserted

#define LOWPOWER_HWWAKE_SDMA0   (1UL << 3)

DMA0 being busy will cause peripheral clocking to remain running until DMA \ completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS

#define LOWPOWER_HWWAKE_SDMA1   (1UL << 5)

DMA0 being busy will cause peripheral clocking to remain running until DMA \ completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS

#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX   0

Pin P1( 1)

Enumeration Type Documentation

enum power_bod_vbat_level_t

Enumerator
kPOWER_BodVbatLevel1000mv	Brown out detector VBAT level 1V.
kPOWER_BodVbatLevel1100mv	Brown out detector VBAT level 1.1V.
kPOWER_BodVbatLevel1200mv	Brown out detector VBAT level 1.2V.
kPOWER_BodVbatLevel1300mv	Brown out detector VBAT level 1.3V.
kPOWER_BodVbatLevel1400mv	Brown out detector VBAT level 1.4V.
kPOWER_BodVbatLevel1500mv	Brown out detector VBAT level 1.5V.
kPOWER_BodVbatLevel1600mv	Brown out detector VBAT level 1.6V.
kPOWER_BodVbatLevel1650mv	Brown out detector VBAT level 1.65V.
kPOWER_BodVbatLevel1700mv	Brown out detector VBAT level 1.7V.
kPOWER_BodVbatLevel1750mv	Brown out detector VBAT level 1.75V.
kPOWER_BodVbatLevel1800mv	Brown out detector VBAT level 1.8V.
kPOWER_BodVbatLevel1900mv	Brown out detector VBAT level 1.9V.
kPOWER_BodVbatLevel2000mv	Brown out detector VBAT level 2V.
kPOWER_BodVbatLevel2100mv	Brown out detector VBAT level 2.1V.
kPOWER_BodVbatLevel2200mv	Brown out detector VBAT level 2.2V.
kPOWER_BodVbatLevel2300mv	Brown out detector VBAT level 2.3V.
kPOWER_BodVbatLevel2400mv	Brown out detector VBAT level 2.4V.
kPOWER_BodVbatLevel2500mv	Brown out detector VBAT level 2.5V.
kPOWER_BodVbatLevel2600mv	Brown out detector VBAT level 2.6V.
kPOWER_BodVbatLevel2700mv	Brown out detector VBAT level 2.7V.
kPOWER_BodVbatLevel2806mv	Brown out detector VBAT level 2.806V.
kPOWER_BodVbatLevel2900mv	Brown out detector VBAT level 2.9V.
kPOWER_BodVbatLevel3000mv	Brown out detector VBAT level 3.0V.
kPOWER_BodVbatLevel3100mv	Brown out detector VBAT level 3.1V.
kPOWER_BodVbatLevel3200mv	Brown out detector VBAT level 3.2V.
kPOWER_BodVbatLevel3300mv	Brown out detector VBAT level 3.3V.

enum power_bod_hyst_t

Enumerator
kPOWER_BodHystLevel25mv	BOD Hysteresis control level 25mv.
kPOWER_BodHystLevel50mv	BOD Hysteresis control level 50mv.
kPOWER_BodHystLevel75mv	BOD Hysteresis control level 75mv.
kPOWER_BodHystLevel100mv	BOD Hysteresis control level 100mv.

enum power_bod_core_level_t

Enumerator
kPOWER_BodCoreLevel600mv	Brown out detector core level 600mV.
kPOWER_BodCoreLevel650mv	Brown out detector core level 650mV.
kPOWER_BodCoreLevel700mv	Brown out detector core level 700mV.
kPOWER_BodCoreLevel750mv	Brown out detector core level 750mV.
kPOWER_BodCoreLevel800mv	Brown out detector core level 800mV.
kPOWER_BodCoreLevel850mv	Brown out detector core level 850mV.
kPOWER_BodCoreLevel900mv	Brown out detector core level 900mV.
kPOWER_BodCoreLevel950mv	Brown out detector core level 950mV.

enum power_device_reset_cause_t

Enumerator
kRESET_CAUSE_POR	Power On Reset.
kRESET_CAUSE_PADRESET	Hardware Pin Reset.
kRESET_CAUSE_BODRESET	Brown-out Detector reset (either BODVBAT or BODCORE)
kRESET_CAUSE_ARMSYSTEMRESET	ARM System Reset.
kRESET_CAUSE_WDTRESET	Watchdog Timer Reset.
kRESET_CAUSE_SWRRESET	Software Reset.
kRESET_CAUSE_CDOGRESET	Code Watchdog Reset.
kRESET_CAUSE_DPDRESET_WAKEUPIO	Any of the 4 wake-up pins.
kRESET_CAUSE_DPDRESET_RTC	Real Time Counter (RTC)
kRESET_CAUSE_DPDRESET_OSTIMER	OS Event Timer (OSTIMER)
kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC	Any of the 4 wake-up pins and RTC (it is not possible to distinguish which of these 2 events occured first)
kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER	Any of the 4 wake-up pins and OSTIMER (it is not possible to distinguish which of these 2 events occured first)
kRESET_CAUSE_DPDRESET_RTC_OSTIMER	Real Time Counter or OS Event Timer (it is not possible to distinguish which of these 2 events occured first)
kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER	Any of the 4 wake-up pins (it is not possible to distinguish which of these 3 events occured first)
kRESET_CAUSE_NOT_RELEVANT	No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode)
kRESET_CAUSE_NOT_DETERMINISTIC	Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an application point of view.

enum power_device_boot_mode_t

Enumerator
kBOOT_MODE_POWER_UP	All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... )
kBOOT_MODE_LP_DEEP_SLEEP	Wake up from DEEP-SLEEP Low Power mode.
kBOOT_MODE_LP_POWER_DOWN	Wake up from POWER-DOWN Low Power mode.
kBOOT_MODE_LP_DEEP_POWER_DOWN	Wake up from DEEP-POWER-DOWN Low Power mode.

Function Documentation

static void POWER_EnablePD ( pd_bit_t  en )

inlinestatic

Note that enabling the bit powers down the peripheral

Parameters

en	peripheral for which to enable the PDRUNCFG bit

Returns

none

static void POWER_DisablePD ( pd_bit_t  en )

inlinestatic

Note that disabling the bit powers up the peripheral

Parameters

en	peripheral for which to disable the PDRUNCFG bit

Returns

none

static void POWER_SetBodVbatLevel ( power_bod_vbat_level_t  level, power_bod_hyst_t  hyst, bool  enBodVbatReset  )

inlinestatic

Parameters

level	BOD detect level
hyst	BoD Hysteresis control
enBodVbatReset	VBAT brown out detect reset

static void POWER_EnableDeepSleep ( void  )

inlinestatic

Returns

none

static void POWER_DisableDeepSleep ( void  )

inlinestatic

Returns

none

void POWER_CycleCpuAndFlash

(

void

)

Returns

Nothing

void POWER_EnterDeepSleep	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	hardware_wake_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
hardware_wake_ctrl,:

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) reset)

void POWER_EnterPowerDown	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	cpu_retention_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
cpu_retention_ctrl,:	0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are RESERVED.

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl") 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) reset)

void POWER_EnterDeepPowerDown	(	uint32_t	exclude_from_pd,
		uint32_t	sram_retention_ctrl,
		uint64_t	wakeup_interrupts,
		uint32_t	wakeup_io_ctrl
	)

Parameters

exclude_from_pd,:
sram_retention_ctrl,:
wakeup_interrupts,:
wakeup_io_ctrl,:

Returns

Nothing

     !!! IMPORTANT NOTES :

0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)

void POWER_EnterSleep

(

void

)

Parameters

:

Returns

Nothing

void POWER_SetVoltageForFreq

(

uint32_t

system_freq_hz

)

Parameters

system_freq_hz

- The desired frequency (in Hertz) at which the part would like to operate, note that the voltage and flash wait states should be set before changing frequency

Returns

none

uint32_t POWER_GetLibVersion

(

void

)

Returns

version number of the power library

void POWER_Xtal16mhzCapabankTrim	(	int32_t	pi32_16MfXtalIecLoadpF_x100,
		int32_t	pi32_16MfXtalPPcbParCappF_x100,
		int32_t	pi32_16MfXtalNPcbParCappF_x100
	)

Parameters

pi32_16MfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_16MfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_16MfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns

none

Note

Following default Values can be used: pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void POWER_Xtal32khzCapabankTrim	(	int32_t	pi32_32kfXtalIecLoadpF_x100,
		int32_t	pi32_32kfXtalPPcbParCappF_x100,
		int32_t	pi32_32kfXtalNPcbParCappF_x100
	)

Parameters

pi32_32kfXtalIecLoadpF_x100	Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalPPcbParCappF_x100	PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
pi32_32kfXtalNPcbParCappF_x100	PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120

Returns

none

Note

Following default Values can be used: pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40

void POWER_SetXtal16mhzLdo

(

void

)

Returns

none

void POWER_SetXtal16mhzTrim	(	uint32_t	amp,
		uint32_t	gm
	)

Parameters

amp	Amplitude
gm	Transconductance

Returns

none

void POWER_GetWakeUpCause	(	power_device_reset_cause_t *	p_reset_cause,
		power_device_boot_mode_t *	p_boot_mode,
		uint32_t *	p_wakeupio_cause
	)

Parameters

p_reset_cause	: the device reset cause, according to the definition of power_device_reset_cause_t type.
p_boot_mode	: the device boot mode, according to the definition of power_device_boot_mode_t type.
p_wakeupio_cause,:	the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0].

Returns

Nothing

    !!!  IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA     !!!
    !!!   valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06)   !!!
    !!!   when FALLING EDGE DETECTION is enabled on wake-up pins:   !!!
    - 1. p_wakeupio_cause is NOT ACCURATE
    - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when
         several wake-up sources are enabled during DEEP-POWER-DOWN
         (like enabling wake-up on RTC and Falling edge wake-up pins)